2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/timer.h>
43 #include <linux/semaphore.h>
44 #include <linux/workqueue.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/driver.h>
48 #include <linux/mlx4/doorbell.h>
49 #include <linux/mlx4/cmd.h>
51 #define DRV_NAME "mlx4_core"
52 #define PFX DRV_NAME ": "
53 #define DRV_VERSION "1.1"
54 #define DRV_RELDATE "Dec, 2011"
58 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
59 #define MLX4_RATELIMIT_DEFAULT 0xffff
61 struct mlx4_set_port_prio2tc_context {
65 struct mlx4_port_scheduler_tc_cfg_be {
68 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
72 struct mlx4_set_port_scheduler_context {
73 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
77 MLX4_HCR_BASE = 0x80680,
78 MLX4_HCR_SIZE = 0x0001c,
79 MLX4_CLR_INT_SIZE = 0x00008,
80 MLX4_SLAVE_COMM_BASE = 0x0,
81 MLX4_COMM_PAGESIZE = 0x1000
85 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
86 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
87 MLX4_MTT_ENTRY_PER_SEG = 8,
91 MLX4_NUM_PDS = 1 << 15
95 MLX4_CMPT_TYPE_QP = 0,
96 MLX4_CMPT_TYPE_SRQ = 1,
97 MLX4_CMPT_TYPE_CQ = 2,
98 MLX4_CMPT_TYPE_EQ = 3,
103 MLX4_CMPT_SHIFT = 24,
104 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
108 MLX4_MR_DISABLED = 0,
113 #define MLX4_COMM_TIME 10000
119 MLX4_COMM_CMD_VHCR_EN,
120 MLX4_COMM_CMD_VHCR_POST,
121 MLX4_COMM_CMD_FLR = 254
124 /*The flag indicates that the slave should delay the RESET cmd*/
125 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
126 /*indicates how many retries will be done if we are in the middle of FLR*/
127 #define NUM_OF_RESET_RETRIES 10
128 #define SLEEP_TIME_IN_RESET (2 * 1000)
140 MLX4_NUM_OF_RESOURCE_TYPE
143 enum mlx4_alloc_mode {
145 RES_OP_RESERVE_AND_MAP,
149 enum mlx4_res_tracker_free_type {
151 RES_TR_FREE_SLAVES_ONLY,
152 RES_TR_FREE_STRUCTS_ONLY,
156 *Virtual HCR structures.
157 * mlx4_vhcr is the sw representation, in machine endianess
159 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
160 * to FW to go through communication channel.
161 * It is big endian, and has the same structure as the physical HCR
162 * used by command interface
175 struct mlx4_vhcr_cmd {
186 struct mlx4_cmd_info {
191 bool encode_slave_id;
192 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
193 struct mlx4_cmd_mailbox *inbox);
194 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
195 struct mlx4_cmd_mailbox *inbox,
196 struct mlx4_cmd_mailbox *outbox,
197 struct mlx4_cmd_info *cmd);
200 #ifdef CONFIG_MLX4_DEBUG
201 extern int mlx4_debug_level;
202 #else /* CONFIG_MLX4_DEBUG */
203 #define mlx4_debug_level (0)
204 #endif /* CONFIG_MLX4_DEBUG */
206 #define mlx4_dbg(mdev, format, arg...) \
208 if (mlx4_debug_level) \
209 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
212 #define mlx4_err(mdev, format, arg...) \
213 dev_err(&mdev->pdev->dev, format, ##arg)
214 #define mlx4_info(mdev, format, arg...) \
215 dev_info(&mdev->pdev->dev, format, ##arg)
216 #define mlx4_warn(mdev, format, arg...) \
217 dev_warn(&mdev->pdev->dev, format, ##arg)
219 extern int mlx4_log_num_mgm_entry_size;
220 extern int log_mtts_per_seg;
222 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
223 #define ALL_SLAVES 0xff
233 unsigned long *table;
237 unsigned long **bits;
238 unsigned int *num_free;
245 struct mlx4_icm_table {
253 struct mlx4_icm **icm;
257 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
259 struct mlx4_mpt_entry {
273 __be32 first_byte_offset;
277 * Must be packed because start is 64 bits but only aligned to 32 bits.
279 struct mlx4_eq_context {
293 __be32 mtt_base_addr_l;
295 __be32 consumer_index;
296 __be32 producer_index;
300 struct mlx4_cq_context {
304 __be32 logsize_usrpage;
312 __be32 mtt_base_addr_l;
313 __be32 last_notified_index;
314 __be32 solicit_producer_index;
315 __be32 consumer_index;
316 __be32 producer_index;
321 struct mlx4_srq_context {
322 __be32 state_logsize_srqn;
326 __be32 pg_offset_cqn;
331 __be32 mtt_base_addr_l;
333 __be16 limit_watermark;
374 } __packed port_change;
376 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
378 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
379 } __packed comm_channel_arm;
384 } __packed mac_update;
390 } __packed flr_event;
392 __be16 current_temperature;
393 __be16 warning_threshold;
402 struct mlx4_dev *dev;
403 void __iomem *doorbell;
409 struct mlx4_buf_list *page_list;
413 struct mlx4_slave_eqe {
419 struct mlx4_slave_event_eq_info {
424 struct mlx4_profile {
438 struct mlx4_icm *fw_icm;
439 struct mlx4_icm *aux_icm;
453 MLX4_MCAST_CONFIG = 0,
454 MLX4_MCAST_DISABLE = 1,
455 MLX4_MCAST_ENABLE = 2,
458 #define VLAN_FLTR_SIZE 128
460 struct mlx4_vlan_fltr {
461 __be32 entry[VLAN_FLTR_SIZE];
464 struct mlx4_mcast_entry {
465 struct list_head list;
469 struct mlx4_promisc_qp {
470 struct list_head list;
474 struct mlx4_steer_index {
475 struct list_head list;
477 struct list_head duplicates;
480 #define MLX4_EVENT_TYPES_NUM 64
482 struct mlx4_slave_state {
489 u16 mtu[MLX4_MAX_PORTS + 1];
490 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
491 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
492 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
493 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
494 /* event type to eq number lookup */
495 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
499 /*initialized via the kzalloc*/
500 u8 is_slave_going_down;
506 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
509 struct mlx4_resource_tracker {
511 /* tree for each resources */
512 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
513 /* num_of_slave's lists, one per slave */
514 struct slave_list *slave_list;
517 #define SLAVE_EVENT_EQ_SIZE 128
518 struct mlx4_slave_event_eq {
522 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
525 struct mlx4_master_qp0_state {
526 int proxy_qp0_active;
531 struct mlx4_mfunc_master_ctx {
532 struct mlx4_slave_state *slave_state;
533 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
534 int init_port_ref[MLX4_MAX_PORTS + 1];
535 u16 max_mtu[MLX4_MAX_PORTS + 1];
536 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
537 struct mlx4_resource_tracker res_tracker;
538 struct workqueue_struct *comm_wq;
539 struct work_struct comm_work;
540 struct work_struct slave_event_work;
541 struct work_struct slave_flr_event_work;
542 spinlock_t slave_state_lock;
543 __be32 comm_arm_bit_vector[4];
544 struct mlx4_eqe cmd_eqe;
545 struct mlx4_slave_event_eq slave_eq;
546 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
550 struct mlx4_comm __iomem *comm;
551 struct mlx4_vhcr_cmd *vhcr;
554 struct mlx4_mfunc_master_ctx master;
558 struct pci_pool *pool;
560 struct mutex hcr_mutex;
561 struct semaphore poll_sem;
562 struct semaphore event_sem;
563 struct semaphore slave_sem;
565 spinlock_t context_lock;
567 struct mlx4_cmd_context *context;
574 struct mlx4_uar_table {
575 struct mlx4_bitmap bitmap;
578 struct mlx4_mr_table {
579 struct mlx4_bitmap mpt_bitmap;
580 struct mlx4_buddy mtt_buddy;
583 struct mlx4_icm_table mtt_table;
584 struct mlx4_icm_table dmpt_table;
587 struct mlx4_cq_table {
588 struct mlx4_bitmap bitmap;
590 struct radix_tree_root tree;
591 struct mlx4_icm_table table;
592 struct mlx4_icm_table cmpt_table;
595 struct mlx4_eq_table {
596 struct mlx4_bitmap bitmap;
598 void __iomem *clr_int;
599 void __iomem **uar_map;
602 struct mlx4_icm_table table;
603 struct mlx4_icm_table cmpt_table;
608 struct mlx4_srq_table {
609 struct mlx4_bitmap bitmap;
611 struct radix_tree_root tree;
612 struct mlx4_icm_table table;
613 struct mlx4_icm_table cmpt_table;
616 struct mlx4_qp_table {
617 struct mlx4_bitmap bitmap;
621 struct mlx4_icm_table qp_table;
622 struct mlx4_icm_table auxc_table;
623 struct mlx4_icm_table altc_table;
624 struct mlx4_icm_table rdmarc_table;
625 struct mlx4_icm_table cmpt_table;
628 struct mlx4_mcg_table {
630 struct mlx4_bitmap bitmap;
631 struct mlx4_icm_table table;
634 struct mlx4_catas_err {
636 struct timer_list timer;
637 struct list_head list;
640 #define MLX4_MAX_MAC_NUM 128
641 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
643 struct mlx4_mac_table {
644 __be64 entries[MLX4_MAX_MAC_NUM];
645 int refs[MLX4_MAX_MAC_NUM];
651 #define MLX4_MAX_VLAN_NUM 128
652 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
654 struct mlx4_vlan_table {
655 __be32 entries[MLX4_MAX_VLAN_NUM];
656 int refs[MLX4_MAX_VLAN_NUM];
662 #define SET_PORT_GEN_ALL_VALID 0x7
663 #define SET_PORT_PROMISC_SHIFT 31
664 #define SET_PORT_MC_PROMISC_SHIFT 30
667 MCAST_DIRECT_ONLY = 0,
673 struct mlx4_set_port_general_context {
686 struct mlx4_set_port_rqp_calc_context {
704 struct mlx4_mac_entry {
708 struct mlx4_port_info {
709 struct mlx4_dev *dev;
712 struct device_attribute port_attr;
713 enum mlx4_port_type tmp_type;
714 char dev_mtu_name[16];
715 struct device_attribute port_mtu_attr;
716 struct mlx4_mac_table mac_table;
717 struct radix_tree_root mac_tree;
718 struct mlx4_vlan_table vlan_table;
723 struct mlx4_dev *dev;
724 u8 do_sense_port[MLX4_MAX_PORTS + 1];
725 u8 sense_allowed[MLX4_MAX_PORTS + 1];
726 struct delayed_work sense_poll;
729 struct mlx4_msix_ctl {
731 struct mutex pool_lock;
735 struct list_head promisc_qps[MLX4_NUM_STEERS];
736 struct list_head steer_entries[MLX4_NUM_STEERS];
742 struct list_head dev_list;
743 struct list_head ctx_list;
746 struct list_head pgdir_list;
747 struct mutex pgdir_mutex;
751 struct mlx4_mfunc mfunc;
753 struct mlx4_bitmap pd_bitmap;
754 struct mlx4_bitmap xrcd_bitmap;
755 struct mlx4_uar_table uar_table;
756 struct mlx4_mr_table mr_table;
757 struct mlx4_cq_table cq_table;
758 struct mlx4_eq_table eq_table;
759 struct mlx4_srq_table srq_table;
760 struct mlx4_qp_table qp_table;
761 struct mlx4_mcg_table mcg_table;
762 struct mlx4_bitmap counters_bitmap;
764 struct mlx4_catas_err catas_err;
766 void __iomem *clr_base;
768 struct mlx4_uar driver_uar;
770 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
771 struct mlx4_sense sense;
772 struct mutex port_mutex;
773 struct mlx4_msix_ctl msix_ctl;
774 struct mlx4_steer *steer;
775 struct list_head bf_list;
776 struct mutex bf_mutex;
777 struct io_mapping *bf_mapping;
781 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
783 return container_of(dev, struct mlx4_priv, dev);
786 #define MLX4_SENSE_RANGE (HZ * 3)
788 extern struct workqueue_struct *mlx4_wq;
790 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
791 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
792 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
793 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
794 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
795 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
796 u32 reserved_bot, u32 resetrved_top);
797 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
799 int mlx4_reset(struct mlx4_dev *dev);
801 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
802 void mlx4_free_eq_table(struct mlx4_dev *dev);
804 int mlx4_init_pd_table(struct mlx4_dev *dev);
805 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
806 int mlx4_init_uar_table(struct mlx4_dev *dev);
807 int mlx4_init_mr_table(struct mlx4_dev *dev);
808 int mlx4_init_eq_table(struct mlx4_dev *dev);
809 int mlx4_init_cq_table(struct mlx4_dev *dev);
810 int mlx4_init_qp_table(struct mlx4_dev *dev);
811 int mlx4_init_srq_table(struct mlx4_dev *dev);
812 int mlx4_init_mcg_table(struct mlx4_dev *dev);
814 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
815 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
816 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
817 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
818 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
819 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
820 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
821 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
822 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
823 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
824 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
825 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
826 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
827 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
828 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
829 int __mlx4_mr_reserve(struct mlx4_dev *dev);
830 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
831 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
832 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
833 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
834 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
836 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
837 struct mlx4_vhcr *vhcr,
838 struct mlx4_cmd_mailbox *inbox,
839 struct mlx4_cmd_mailbox *outbox,
840 struct mlx4_cmd_info *cmd);
841 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
842 struct mlx4_vhcr *vhcr,
843 struct mlx4_cmd_mailbox *inbox,
844 struct mlx4_cmd_mailbox *outbox,
845 struct mlx4_cmd_info *cmd);
846 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
847 struct mlx4_vhcr *vhcr,
848 struct mlx4_cmd_mailbox *inbox,
849 struct mlx4_cmd_mailbox *outbox,
850 struct mlx4_cmd_info *cmd);
851 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
852 struct mlx4_vhcr *vhcr,
853 struct mlx4_cmd_mailbox *inbox,
854 struct mlx4_cmd_mailbox *outbox,
855 struct mlx4_cmd_info *cmd);
856 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
857 struct mlx4_vhcr *vhcr,
858 struct mlx4_cmd_mailbox *inbox,
859 struct mlx4_cmd_mailbox *outbox,
860 struct mlx4_cmd_info *cmd);
861 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
862 struct mlx4_vhcr *vhcr,
863 struct mlx4_cmd_mailbox *inbox,
864 struct mlx4_cmd_mailbox *outbox,
865 struct mlx4_cmd_info *cmd);
866 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
867 struct mlx4_vhcr *vhcr,
868 struct mlx4_cmd_mailbox *inbox,
869 struct mlx4_cmd_mailbox *outbox,
870 struct mlx4_cmd_info *cmd);
871 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
873 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
874 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
875 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
876 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
877 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
878 int start_index, int npages, u64 *page_list);
879 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
880 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
881 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
882 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
884 void mlx4_start_catas_poll(struct mlx4_dev *dev);
885 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
886 void mlx4_catas_init(void);
887 int mlx4_restart_one(struct pci_dev *pdev);
888 int mlx4_register_device(struct mlx4_dev *dev);
889 void mlx4_unregister_device(struct mlx4_dev *dev);
890 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
893 struct mlx4_init_hca_param;
895 u64 mlx4_make_profile(struct mlx4_dev *dev,
896 struct mlx4_profile *request,
897 struct mlx4_dev_cap *dev_cap,
898 struct mlx4_init_hca_param *init_hca);
899 void mlx4_master_comm_channel(struct work_struct *work);
900 void mlx4_gen_slave_eqe(struct work_struct *work);
901 void mlx4_master_handle_slave_flr(struct work_struct *work);
903 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
904 struct mlx4_vhcr *vhcr,
905 struct mlx4_cmd_mailbox *inbox,
906 struct mlx4_cmd_mailbox *outbox,
907 struct mlx4_cmd_info *cmd);
908 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
909 struct mlx4_vhcr *vhcr,
910 struct mlx4_cmd_mailbox *inbox,
911 struct mlx4_cmd_mailbox *outbox,
912 struct mlx4_cmd_info *cmd);
913 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
914 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
915 struct mlx4_cmd_mailbox *outbox,
916 struct mlx4_cmd_info *cmd);
917 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
918 struct mlx4_vhcr *vhcr,
919 struct mlx4_cmd_mailbox *inbox,
920 struct mlx4_cmd_mailbox *outbox,
921 struct mlx4_cmd_info *cmd);
922 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
923 struct mlx4_vhcr *vhcr,
924 struct mlx4_cmd_mailbox *inbox,
925 struct mlx4_cmd_mailbox *outbox,
926 struct mlx4_cmd_info *cmd);
927 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
928 struct mlx4_vhcr *vhcr,
929 struct mlx4_cmd_mailbox *inbox,
930 struct mlx4_cmd_mailbox *outbox,
931 struct mlx4_cmd_info *cmd);
932 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
933 struct mlx4_vhcr *vhcr,
934 struct mlx4_cmd_mailbox *inbox,
935 struct mlx4_cmd_mailbox *outbox,
936 struct mlx4_cmd_info *cmd);
937 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
938 struct mlx4_vhcr *vhcr,
939 struct mlx4_cmd_mailbox *inbox,
940 struct mlx4_cmd_mailbox *outbox,
941 struct mlx4_cmd_info *cmd);
942 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
943 struct mlx4_vhcr *vhcr,
944 struct mlx4_cmd_mailbox *inbox,
945 struct mlx4_cmd_mailbox *outbox,
946 struct mlx4_cmd_info *cmd);
947 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
948 struct mlx4_vhcr *vhcr,
949 struct mlx4_cmd_mailbox *inbox,
950 struct mlx4_cmd_mailbox *outbox,
951 struct mlx4_cmd_info *cmd);
952 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd);
957 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
958 struct mlx4_vhcr *vhcr,
959 struct mlx4_cmd_mailbox *inbox,
960 struct mlx4_cmd_mailbox *outbox,
961 struct mlx4_cmd_info *cmd);
962 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
963 struct mlx4_vhcr *vhcr,
964 struct mlx4_cmd_mailbox *inbox,
965 struct mlx4_cmd_mailbox *outbox,
966 struct mlx4_cmd_info *cmd);
967 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
968 struct mlx4_vhcr *vhcr,
969 struct mlx4_cmd_mailbox *inbox,
970 struct mlx4_cmd_mailbox *outbox,
971 struct mlx4_cmd_info *cmd);
972 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
973 struct mlx4_vhcr *vhcr,
974 struct mlx4_cmd_mailbox *inbox,
975 struct mlx4_cmd_mailbox *outbox,
976 struct mlx4_cmd_info *cmd);
977 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
978 struct mlx4_vhcr *vhcr,
979 struct mlx4_cmd_mailbox *inbox,
980 struct mlx4_cmd_mailbox *outbox,
981 struct mlx4_cmd_info *cmd);
982 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
983 struct mlx4_vhcr *vhcr,
984 struct mlx4_cmd_mailbox *inbox,
985 struct mlx4_cmd_mailbox *outbox,
986 struct mlx4_cmd_info *cmd);
987 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
988 struct mlx4_vhcr *vhcr,
989 struct mlx4_cmd_mailbox *inbox,
990 struct mlx4_cmd_mailbox *outbox,
991 struct mlx4_cmd_info *cmd);
993 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
995 int mlx4_cmd_init(struct mlx4_dev *dev);
996 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
997 int mlx4_multi_func_init(struct mlx4_dev *dev);
998 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
999 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1000 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1001 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1003 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1004 unsigned long timeout);
1006 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1007 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1009 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1011 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1013 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1015 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1016 enum mlx4_port_type *type);
1017 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1018 enum mlx4_port_type *stype,
1019 enum mlx4_port_type *defaults);
1020 void mlx4_start_sense(struct mlx4_dev *dev);
1021 void mlx4_stop_sense(struct mlx4_dev *dev);
1022 void mlx4_sense_init(struct mlx4_dev *dev);
1023 int mlx4_check_port_params(struct mlx4_dev *dev,
1024 enum mlx4_port_type *port_type);
1025 int mlx4_change_port_types(struct mlx4_dev *dev,
1026 enum mlx4_port_type *port_types);
1028 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1029 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1031 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
1032 /* resource tracker functions*/
1033 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1034 enum mlx4_resource resource_type,
1035 int resource_id, int *slave);
1036 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1037 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1039 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1040 enum mlx4_res_tracker_free_type type);
1042 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1043 struct mlx4_vhcr *vhcr,
1044 struct mlx4_cmd_mailbox *inbox,
1045 struct mlx4_cmd_mailbox *outbox,
1046 struct mlx4_cmd_info *cmd);
1047 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1048 struct mlx4_vhcr *vhcr,
1049 struct mlx4_cmd_mailbox *inbox,
1050 struct mlx4_cmd_mailbox *outbox,
1051 struct mlx4_cmd_info *cmd);
1052 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1053 struct mlx4_vhcr *vhcr,
1054 struct mlx4_cmd_mailbox *inbox,
1055 struct mlx4_cmd_mailbox *outbox,
1056 struct mlx4_cmd_info *cmd);
1057 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
1062 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1063 struct mlx4_vhcr *vhcr,
1064 struct mlx4_cmd_mailbox *inbox,
1065 struct mlx4_cmd_mailbox *outbox,
1066 struct mlx4_cmd_info *cmd);
1067 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1068 struct mlx4_vhcr *vhcr,
1069 struct mlx4_cmd_mailbox *inbox,
1070 struct mlx4_cmd_mailbox *outbox,
1071 struct mlx4_cmd_info *cmd);
1072 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1075 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1076 struct mlx4_vhcr *vhcr,
1077 struct mlx4_cmd_mailbox *inbox,
1078 struct mlx4_cmd_mailbox *outbox,
1079 struct mlx4_cmd_info *cmd);
1081 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1082 struct mlx4_vhcr *vhcr,
1083 struct mlx4_cmd_mailbox *inbox,
1084 struct mlx4_cmd_mailbox *outbox,
1085 struct mlx4_cmd_info *cmd);
1086 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1087 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1088 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1089 int block_mcast_loopback, enum mlx4_protocol prot,
1090 enum mlx4_steer_type steer);
1091 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1092 struct mlx4_vhcr *vhcr,
1093 struct mlx4_cmd_mailbox *inbox,
1094 struct mlx4_cmd_mailbox *outbox,
1095 struct mlx4_cmd_info *cmd);
1096 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1097 struct mlx4_vhcr *vhcr,
1098 struct mlx4_cmd_mailbox *inbox,
1099 struct mlx4_cmd_mailbox *outbox,
1100 struct mlx4_cmd_info *cmd);
1101 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1102 int port, void *buf);
1103 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1104 struct mlx4_cmd_mailbox *outbox);
1105 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1106 struct mlx4_vhcr *vhcr,
1107 struct mlx4_cmd_mailbox *inbox,
1108 struct mlx4_cmd_mailbox *outbox,
1109 struct mlx4_cmd_info *cmd);
1110 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1111 struct mlx4_vhcr *vhcr,
1112 struct mlx4_cmd_mailbox *inbox,
1113 struct mlx4_cmd_mailbox *outbox,
1114 struct mlx4_cmd_info *cmd);
1115 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1116 struct mlx4_vhcr *vhcr,
1117 struct mlx4_cmd_mailbox *inbox,
1118 struct mlx4_cmd_mailbox *outbox,
1119 struct mlx4_cmd_info *cmd);
1121 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1122 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1124 static inline void set_param_l(u64 *arg, u32 val)
1126 *((u32 *)arg) = val;
1129 static inline void set_param_h(u64 *arg, u32 val)
1131 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1134 static inline u32 get_param_l(u64 *arg)
1136 return (u32) (*arg & 0xffffffff);
1139 static inline u32 get_param_h(u64 *arg)
1141 return (u32)(*arg >> 32);
1144 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1146 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1149 #define NOT_MASKED_PD_BITS 17