2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/vmalloc.h>
41 #include <linux/tcp.h>
42 #include <linux/moduleparam.h>
47 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
51 static int inline_thold __read_mostly = MAX_INLINE;
53 module_param_named(inline_thold, inline_thold, int, 0444);
54 MODULE_PARM_DESC(inline_thold, "threshold for using inline data");
56 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
57 struct mlx4_en_tx_ring *ring, int qpn, u32 size,
60 struct mlx4_en_dev *mdev = priv->mdev;
65 ring->size_mask = size - 1;
66 ring->stride = stride;
68 inline_thold = min(inline_thold, MAX_INLINE);
70 spin_lock_init(&ring->comp_lock);
72 tmp = size * sizeof(struct mlx4_en_tx_info);
73 ring->tx_info = vmalloc(tmp);
77 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
80 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
81 if (!ring->bounce_buf) {
85 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
87 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
90 en_err(priv, "Failed allocating hwq resources\n");
94 err = mlx4_en_map_buffer(&ring->wqres.buf);
96 en_err(priv, "Failed to map TX buffer\n");
100 ring->buf = ring->wqres.buf.direct.buf;
102 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
103 "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
104 ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
107 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp);
109 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
112 ring->qp.event = mlx4_en_sqp_event;
114 err = mlx4_bf_alloc(mdev->dev, &ring->bf);
116 en_dbg(DRV, priv, "working without blueflame (%d)", err);
117 ring->bf.uar = &mdev->priv_uar;
118 ring->bf.uar->map = mdev->uar_map;
119 ring->bf_enabled = false;
121 ring->bf_enabled = true;
126 mlx4_en_unmap_buffer(&ring->wqres.buf);
128 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
130 kfree(ring->bounce_buf);
131 ring->bounce_buf = NULL;
133 vfree(ring->tx_info);
134 ring->tx_info = NULL;
138 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
139 struct mlx4_en_tx_ring *ring)
141 struct mlx4_en_dev *mdev = priv->mdev;
142 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
144 if (ring->bf_enabled)
145 mlx4_bf_free(mdev->dev, &ring->bf);
146 mlx4_qp_remove(mdev->dev, &ring->qp);
147 mlx4_qp_free(mdev->dev, &ring->qp);
148 mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
149 mlx4_en_unmap_buffer(&ring->wqres.buf);
150 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
151 kfree(ring->bounce_buf);
152 ring->bounce_buf = NULL;
153 vfree(ring->tx_info);
154 ring->tx_info = NULL;
157 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
158 struct mlx4_en_tx_ring *ring,
161 struct mlx4_en_dev *mdev = priv->mdev;
166 ring->cons = 0xffffffff;
167 ring->last_nr_txbb = 1;
170 memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
171 memset(ring->buf, 0, ring->buf_size);
173 ring->qp_state = MLX4_QP_STATE_RST;
174 ring->doorbell_qpn = ring->qp.qpn << 8;
176 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
177 ring->cqn, &ring->context);
178 if (ring->bf_enabled)
179 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
181 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
182 &ring->qp, &ring->qp_state);
187 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
188 struct mlx4_en_tx_ring *ring)
190 struct mlx4_en_dev *mdev = priv->mdev;
192 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
193 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
197 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
198 struct mlx4_en_tx_ring *ring,
201 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
202 struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
203 struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
204 struct sk_buff *skb = tx_info->skb;
205 struct skb_frag_struct *frag;
206 void *end = ring->buf + ring->buf_size;
207 int frags = skb_shinfo(skb)->nr_frags;
209 __be32 *ptr = (__be32 *)tx_desc;
210 __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
212 /* Optimize the common case when there are no wraparounds */
213 if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
215 if (tx_info->linear) {
216 dma_unmap_single(priv->ddev,
217 (dma_addr_t) be64_to_cpu(data->addr),
218 be32_to_cpu(data->byte_count),
223 for (i = 0; i < frags; i++) {
224 frag = &skb_shinfo(skb)->frags[i];
225 dma_unmap_page(priv->ddev,
226 (dma_addr_t) be64_to_cpu(data[i].addr),
227 skb_frag_size(frag), PCI_DMA_TODEVICE);
230 /* Stamp the freed descriptor */
231 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
238 if ((void *) data >= end) {
239 data = ring->buf + ((void *)data - end);
242 if (tx_info->linear) {
243 dma_unmap_single(priv->ddev,
244 (dma_addr_t) be64_to_cpu(data->addr),
245 be32_to_cpu(data->byte_count),
250 for (i = 0; i < frags; i++) {
251 /* Check for wraparound before unmapping */
252 if ((void *) data >= end)
254 frag = &skb_shinfo(skb)->frags[i];
255 dma_unmap_page(priv->ddev,
256 (dma_addr_t) be64_to_cpu(data->addr),
257 skb_frag_size(frag), PCI_DMA_TODEVICE);
261 /* Stamp the freed descriptor */
262 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
265 if ((void *) ptr >= end) {
267 stamp ^= cpu_to_be32(0x80000000);
272 dev_kfree_skb_any(skb);
273 return tx_info->nr_txbb;
277 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
279 struct mlx4_en_priv *priv = netdev_priv(dev);
282 /* Skip last polled descriptor */
283 ring->cons += ring->last_nr_txbb;
284 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
285 ring->cons, ring->prod);
287 if ((u32) (ring->prod - ring->cons) > ring->size) {
288 if (netif_msg_tx_err(priv))
289 en_warn(priv, "Tx consumer passed producer!\n");
293 while (ring->cons != ring->prod) {
294 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
295 ring->cons & ring->size_mask,
296 !!(ring->cons & ring->size));
297 ring->cons += ring->last_nr_txbb;
302 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
307 static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq)
309 struct mlx4_en_priv *priv = netdev_priv(dev);
310 struct mlx4_cq *mcq = &cq->mcq;
311 struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
312 struct mlx4_cqe *cqe;
314 u16 new_index, ring_index;
315 u32 txbbs_skipped = 0;
316 u32 cons_index = mcq->cons_index;
318 u32 size_mask = ring->size_mask;
319 struct mlx4_cqe *buf = cq->buf;
324 index = cons_index & size_mask;
326 ring_index = ring->cons & size_mask;
328 /* Process all completed CQEs */
329 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
330 cons_index & size)) {
332 * make sure we read the CQE after we read the
337 /* Skip over last polled CQE */
338 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
341 txbbs_skipped += ring->last_nr_txbb;
342 ring_index = (ring_index + ring->last_nr_txbb) & size_mask;
343 /* free next descriptor */
344 ring->last_nr_txbb = mlx4_en_free_tx_desc(
345 priv, ring, ring_index,
346 !!((ring->cons + txbbs_skipped) &
348 } while (ring_index != new_index);
351 index = cons_index & size_mask;
357 * To prevent CQ overflow we first update CQ consumer and only then
360 mcq->cons_index = cons_index;
363 ring->cons += txbbs_skipped;
365 /* Wakeup Tx queue if this ring stopped it */
366 if (unlikely(ring->blocked)) {
367 if ((u32) (ring->prod - ring->cons) <=
368 ring->size - HEADROOM - MAX_DESC_TXBBS) {
370 netif_tx_wake_queue(netdev_get_tx_queue(dev, cq->ring));
371 priv->port_stats.wake_queue++;
376 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
378 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
379 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
380 struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
382 if (!spin_trylock(&ring->comp_lock))
384 mlx4_en_process_tx_cq(cq->dev, cq);
385 mod_timer(&cq->timer, jiffies + 1);
386 spin_unlock(&ring->comp_lock);
390 void mlx4_en_poll_tx_cq(unsigned long data)
392 struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data;
393 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
394 struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
397 INC_PERF_COUNTER(priv->pstats.tx_poll);
399 if (!spin_trylock_irq(&ring->comp_lock)) {
400 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
403 mlx4_en_process_tx_cq(cq->dev, cq);
404 inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb);
406 /* If there are still packets in flight and the timer has not already
407 * been scheduled by the Tx routine then schedule it here to guarantee
408 * completion processing of these packets */
409 if (inflight && priv->port_up)
410 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
412 spin_unlock_irq(&ring->comp_lock);
415 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
416 struct mlx4_en_tx_ring *ring,
418 unsigned int desc_size)
420 u32 copy = (ring->size - index) * TXBB_SIZE;
423 for (i = desc_size - copy - 4; i >= 0; i -= 4) {
424 if ((i & (TXBB_SIZE - 1)) == 0)
427 *((u32 *) (ring->buf + i)) =
428 *((u32 *) (ring->bounce_buf + copy + i));
431 for (i = copy - 4; i >= 4 ; i -= 4) {
432 if ((i & (TXBB_SIZE - 1)) == 0)
435 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
436 *((u32 *) (ring->bounce_buf + i));
439 /* Return real descriptor location */
440 return ring->buf + index * TXBB_SIZE;
443 static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind)
445 struct mlx4_en_cq *cq = &priv->tx_cq[tx_ind];
446 struct mlx4_en_tx_ring *ring = &priv->tx_ring[tx_ind];
449 /* If we don't have a pending timer, set one up to catch our recent
450 post in case the interface becomes idle */
451 if (!timer_pending(&cq->timer))
452 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
454 /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
455 if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0)
456 if (spin_trylock_irqsave(&ring->comp_lock, flags)) {
457 mlx4_en_process_tx_cq(priv->dev, cq);
458 spin_unlock_irqrestore(&ring->comp_lock, flags);
462 static int is_inline(struct sk_buff *skb, void **pfrag)
466 if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) {
467 if (skb_shinfo(skb)->nr_frags == 1) {
468 ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]);
476 } else if (unlikely(skb_shinfo(skb)->nr_frags))
485 static int inline_size(struct sk_buff *skb)
487 if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
488 <= MLX4_INLINE_ALIGN)
489 return ALIGN(skb->len + CTRL_SIZE +
490 sizeof(struct mlx4_wqe_inline_seg), 16);
492 return ALIGN(skb->len + CTRL_SIZE + 2 *
493 sizeof(struct mlx4_wqe_inline_seg), 16);
496 static int get_real_size(struct sk_buff *skb, struct net_device *dev,
497 int *lso_header_size)
499 struct mlx4_en_priv *priv = netdev_priv(dev);
502 if (skb_is_gso(skb)) {
503 *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
504 real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE +
505 ALIGN(*lso_header_size + 4, DS_SIZE);
506 if (unlikely(*lso_header_size != skb_headlen(skb))) {
507 /* We add a segment for the skb linear buffer only if
508 * it contains data */
509 if (*lso_header_size < skb_headlen(skb))
510 real_size += DS_SIZE;
512 if (netif_msg_tx_err(priv))
513 en_warn(priv, "Non-linear headers\n");
518 *lso_header_size = 0;
519 if (!is_inline(skb, NULL))
520 real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE;
522 real_size = inline_size(skb);
528 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb,
529 int real_size, u16 *vlan_tag, int tx_ind, void *fragptr)
531 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
532 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
534 if (skb->len <= spc) {
535 inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
536 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
537 if (skb_shinfo(skb)->nr_frags)
538 memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr,
539 skb_frag_size(&skb_shinfo(skb)->frags[0]));
542 inl->byte_count = cpu_to_be32(1 << 31 | spc);
543 if (skb_headlen(skb) <= spc) {
544 skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
545 if (skb_headlen(skb) < spc) {
546 memcpy(((void *)(inl + 1)) + skb_headlen(skb),
547 fragptr, spc - skb_headlen(skb));
548 fragptr += spc - skb_headlen(skb);
550 inl = (void *) (inl + 1) + spc;
551 memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
553 skb_copy_from_linear_data(skb, inl + 1, spc);
554 inl = (void *) (inl + 1) + spc;
555 skb_copy_from_linear_data_offset(skb, spc, inl + 1,
556 skb_headlen(skb) - spc);
557 if (skb_shinfo(skb)->nr_frags)
558 memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc,
559 fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0]));
563 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
565 tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag);
566 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
567 (!!vlan_tx_tag_present(skb));
568 tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
571 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb)
573 struct mlx4_en_priv *priv = netdev_priv(dev);
576 /* If we support per priority flow control and the packet contains
577 * a vlan tag, send the packet to the TX ring assigned to that priority
579 if (priv->prof->rx_ppp && vlan_tx_tag_present(skb)) {
580 vlan_tag = vlan_tx_tag_get(skb);
581 return MLX4_EN_NUM_TX_RINGS + (vlan_tag >> 13);
584 return skb_tx_hash(dev, skb);
587 static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt)
589 __iowrite64_copy(dst, src, bytecnt / 8);
592 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
594 struct mlx4_en_priv *priv = netdev_priv(dev);
595 struct mlx4_en_dev *mdev = priv->mdev;
596 struct mlx4_en_tx_ring *ring;
597 struct mlx4_en_cq *cq;
598 struct mlx4_en_tx_desc *tx_desc;
599 struct mlx4_wqe_data_seg *data;
600 struct skb_frag_struct *frag;
601 struct mlx4_en_tx_info *tx_info;
619 real_size = get_real_size(skb, dev, &lso_header_size);
620 if (unlikely(!real_size))
623 /* Align descriptor to TXBB size */
624 desc_size = ALIGN(real_size, TXBB_SIZE);
625 nr_txbb = desc_size / TXBB_SIZE;
626 if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
627 if (netif_msg_tx_err(priv))
628 en_warn(priv, "Oversized header or SG list\n");
632 tx_ind = skb->queue_mapping;
633 ring = &priv->tx_ring[tx_ind];
634 if (vlan_tx_tag_present(skb))
635 vlan_tag = vlan_tx_tag_get(skb);
637 /* Check available TXBBs And 2K spare for prefetch */
638 if (unlikely(((int)(ring->prod - ring->cons)) >
639 ring->size - HEADROOM - MAX_DESC_TXBBS)) {
640 /* every full Tx ring stops queue */
641 netif_tx_stop_queue(netdev_get_tx_queue(dev, tx_ind));
643 priv->port_stats.queue_stopped++;
645 /* Use interrupts to find out when queue opened */
646 cq = &priv->tx_cq[tx_ind];
647 mlx4_en_arm_cq(priv, cq);
648 return NETDEV_TX_BUSY;
651 /* Track current inflight packets for performance analysis */
652 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
653 (u32) (ring->prod - ring->cons - 1));
655 /* Packet is good - grab an index and transmit it */
656 index = ring->prod & ring->size_mask;
657 bf_index = ring->prod;
659 /* See if we have enough space for whole descriptor TXBB for setting
660 * SW ownership on next descriptor; if not, use a bounce buffer. */
661 if (likely(index + nr_txbb <= ring->size))
662 tx_desc = ring->buf + index * TXBB_SIZE;
664 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
668 /* Save skb in tx_info ring */
669 tx_info = &ring->tx_info[index];
671 tx_info->nr_txbb = nr_txbb;
673 /* Prepare ctrl segement apart opcode+ownership, which depends on
674 * whether LSO is used */
675 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
676 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
677 !!vlan_tx_tag_present(skb);
678 tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
679 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
680 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
681 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
682 MLX4_WQE_CTRL_TCP_UDP_CSUM);
686 /* Copy dst mac address to wqe */
687 ethh = (struct ethhdr *)skb->data;
688 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
689 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
690 /* Handle LSO (TSO) packets */
691 if (lso_header_size) {
692 /* Mark opcode as LSO */
693 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
694 ((ring->prod & ring->size) ?
695 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
697 /* Fill in the LSO prefix */
698 tx_desc->lso.mss_hdr_size = cpu_to_be32(
699 skb_shinfo(skb)->gso_size << 16 | lso_header_size);
702 * note that we already verified that it is linear */
703 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
704 data = ((void *) &tx_desc->lso +
705 ALIGN(lso_header_size + 4, DS_SIZE));
707 priv->port_stats.tso_packets++;
708 i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) +
709 !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size);
710 ring->bytes += skb->len + (i - 1) * lso_header_size;
713 /* Normal (Non LSO) packet */
714 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
715 ((ring->prod & ring->size) ?
716 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
717 data = &tx_desc->data;
718 ring->bytes += max(skb->len, (unsigned int) ETH_ZLEN);
722 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
725 /* valid only for none inline segments */
726 tx_info->data_offset = (void *) data - (void *) tx_desc;
728 tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0;
729 data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1;
731 if (!is_inline(skb, &fragptr)) {
733 for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) {
734 frag = &skb_shinfo(skb)->frags[i];
735 dma = skb_frag_dma_map(priv->ddev, frag,
736 0, skb_frag_size(frag),
738 data->addr = cpu_to_be64(dma);
739 data->lkey = cpu_to_be32(mdev->mr.key);
741 data->byte_count = cpu_to_be32(skb_frag_size(frag));
745 /* Map linear part */
746 if (tx_info->linear) {
747 dma = dma_map_single(priv->ddev, skb->data + lso_header_size,
748 skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE);
749 data->addr = cpu_to_be64(dma);
750 data->lkey = cpu_to_be32(mdev->mr.key);
752 data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size);
756 build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr);
760 ring->prod += nr_txbb;
762 /* If we used a bounce buffer then copy descriptor back into place */
764 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
766 /* Run destructor before passing skb to HW */
767 if (likely(!skb_shared(skb)))
770 if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tag) {
771 *(__be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);
772 op_own |= htonl((bf_index & 0xffff) << 8);
773 /* Ensure new descirptor hits memory
774 * before setting ownership of this descriptor to HW */
776 tx_desc->ctrl.owner_opcode = op_own;
780 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl,
785 ring->bf.offset ^= ring->bf.buf_size;
787 /* Ensure new descirptor hits memory
788 * before setting ownership of this descriptor to HW */
790 tx_desc->ctrl.owner_opcode = op_own;
792 iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL);
796 mlx4_en_xmit_poll(priv, tx_ind);
801 dev_kfree_skb_any(skb);
802 priv->stats.tx_dropped++;