drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/bpf.h>
  36 #include <linux/mlx4/cq.h>
  37 #include <linux/slab.h>
  38 #include <linux/mlx4/qp.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/rculist.h>
  41 #include <linux/if_ether.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/vmalloc.h>
  44 #include <linux/irq.h>
  45
  46 #if IS_ENABLED(CONFIG_IPV6)
  47 #include <net/ip6_checksum.h>
  48 #endif
  49
  50 #include "mlx4_en.h"
  51
  52 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  53                             struct mlx4_en_rx_alloc *page_alloc,
  54                             const struct mlx4_en_frag_info *frag_info,
  55                             gfp_t _gfp)
  56 {
  57         int order;
  58         struct page *page;
  59         dma_addr_t dma;
  60
  61         for (order = frag_info->order; ;) {
  62                 gfp_t gfp = _gfp;
  63
  64                 if (order)
  65                         gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
  66                 page = alloc_pages(gfp, order);
  67                 if (likely(page))
  68                         break;
  69                 if (--order < 0 ||
  70                     ((PAGE_SIZE << order) < frag_info->frag_size))
  71                         return -ENOMEM;
  72         }
  73         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  74                            frag_info->dma_dir);
  75         if (unlikely(dma_mapping_error(priv->ddev, dma))) {
  76                 put_page(page);
  77                 return -ENOMEM;
  78         }
  79         page_alloc->page_size = PAGE_SIZE << order;
  80         page_alloc->page = page;
  81         page_alloc->dma = dma;
  82         page_alloc->page_offset = 0;
  83         /* Not doing get_page() for each frag is a big win
  84          * on asymetric workloads. Note we can not use atomic_set().
  85          */
  86         page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
  87         return 0;
  88 }
  89
  90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  91                                struct mlx4_en_rx_desc *rx_desc,
  92                                struct mlx4_en_rx_alloc *frags,
  93                                struct mlx4_en_rx_alloc *ring_alloc,
  94                                gfp_t gfp)
  95 {
  96         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  97         const struct mlx4_en_frag_info *frag_info;
  98         struct page *page;
  99         dma_addr_t dma;
 100         int i;
 101
 102         for (i = 0; i < priv->num_frags; i++) {
 103                 frag_info = &priv->frag_info[i];
 104                 page_alloc[i] = ring_alloc[i];
 105                 page_alloc[i].page_offset += frag_info->frag_stride;
 106
 107                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 108                     ring_alloc[i].page_size)
 109                         continue;
 110
 111                 if (unlikely(mlx4_alloc_pages(priv, &page_alloc[i],
 112                                               frag_info, gfp)))
 113                         goto out;
 114         }
 115
 116         for (i = 0; i < priv->num_frags; i++) {
 117                 frags[i] = ring_alloc[i];
 118                 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
 119                 ring_alloc[i] = page_alloc[i];
 120                 rx_desc->data[i].addr = cpu_to_be64(dma);
 121         }
 122
 123         return 0;
 124
 125 out:
 126         while (i--) {
 127                 if (page_alloc[i].page != ring_alloc[i].page) {
 128                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 129                                 page_alloc[i].page_size,
 130                                 priv->frag_info[i].dma_dir);
 131                         page = page_alloc[i].page;
 132                         /* Revert changes done by mlx4_alloc_pages */
 133                         page_ref_sub(page, page_alloc[i].page_size /
 134                                            priv->frag_info[i].frag_stride - 1);
 135                         put_page(page);
 136                 }
 137         }
 138         return -ENOMEM;
 139 }
 140
 141 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 142                               struct mlx4_en_rx_alloc *frags,
 143                               int i)
 144 {
 145         if (frags[i].page) {
 146                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 147                 u32 next_frag_end = frags[i].page_offset +
 148                                 2 * frag_info->frag_stride;
 149
 150                 if (next_frag_end > frags[i].page_size) {
 151                         dma_unmap_page(priv->ddev, frags[i].dma,
 152                                        frags[i].page_size, frag_info->dma_dir);
 153                 }
 154                 put_page(frags[i].page);
 155         }
 156 }
 157
 158 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 159                                   struct mlx4_en_rx_ring *ring)
 160 {
 161         int i;
 162         struct mlx4_en_rx_alloc *page_alloc;
 163
 164         for (i = 0; i < priv->num_frags; i++) {
 165                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 166
 167                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 168                                      frag_info, GFP_KERNEL | __GFP_COLD))
 169                         goto out;
 170
 171                 en_dbg(DRV, priv, "  frag %d allocator: - size:%d frags:%d\n",
 172                        i, ring->page_alloc[i].page_size,
 173                        page_ref_count(ring->page_alloc[i].page));
 174         }
 175         return 0;
 176
 177 out:
 178         while (i--) {
 179                 struct page *page;
 180
 181                 page_alloc = &ring->page_alloc[i];
 182                 dma_unmap_page(priv->ddev, page_alloc->dma,
 183                                page_alloc->page_size,
 184                                priv->frag_info[i].dma_dir);
 185                 page = page_alloc->page;
 186                 /* Revert changes done by mlx4_alloc_pages */
 187                 page_ref_sub(page, page_alloc->page_size /
 188                                    priv->frag_info[i].frag_stride - 1);
 189                 put_page(page);
 190                 page_alloc->page = NULL;
 191         }
 192         return -ENOMEM;
 193 }
 194
 195 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 196                                       struct mlx4_en_rx_ring *ring)
 197 {
 198         struct mlx4_en_rx_alloc *page_alloc;
 199         int i;
 200
 201         for (i = 0; i < priv->num_frags; i++) {
 202                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 203
 204                 page_alloc = &ring->page_alloc[i];
 205                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 206                        i, page_count(page_alloc->page));
 207
 208                 dma_unmap_page(priv->ddev, page_alloc->dma,
 209                                 page_alloc->page_size, frag_info->dma_dir);
 210                 while (page_alloc->page_offset + frag_info->frag_stride <
 211                        page_alloc->page_size) {
 212                         put_page(page_alloc->page);
 213                         page_alloc->page_offset += frag_info->frag_stride;
 214                 }
 215                 page_alloc->page = NULL;
 216         }
 217 }
 218
 219 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 220                                  struct mlx4_en_rx_ring *ring, int index)
 221 {
 222         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 223         int possible_frags;
 224         int i;
 225
 226         /* Set size and memtype fields */
 227         for (i = 0; i < priv->num_frags; i++) {
 228                 rx_desc->data[i].byte_count =
 229                         cpu_to_be32(priv->frag_info[i].frag_size);
 230                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 231         }
 232
 233         /* If the number of used fragments does not fill up the ring stride,
 234          * remaining (unused) fragments must be padded with null address/size
 235          * and a special memory key */
 236         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 237         for (i = priv->num_frags; i < possible_frags; i++) {
 238                 rx_desc->data[i].byte_count = 0;
 239                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 240                 rx_desc->data[i].addr = 0;
 241         }
 242 }
 243
 244 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 245                                    struct mlx4_en_rx_ring *ring, int index,
 246                                    gfp_t gfp)
 247 {
 248         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 249         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 250                                         (index << priv->log_rx_info);
 251
 252         if (ring->page_cache.index > 0) {
 253                 frags[0] = ring->page_cache.buf[--ring->page_cache.index];
 254                 rx_desc->data[0].addr = cpu_to_be64(frags[0].dma);
 255                 return 0;
 256         }
 257
 258         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 259 }
 260
 261 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
 262 {
 263         return ring->prod == ring->cons;
 264 }
 265
 266 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 267 {
 268         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 269 }
 270
 271 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 272                                  struct mlx4_en_rx_ring *ring,
 273                                  int index)
 274 {
 275         struct mlx4_en_rx_alloc *frags;
 276         int nr;
 277
 278         frags = ring->rx_info + (index << priv->log_rx_info);
 279         for (nr = 0; nr < priv->num_frags; nr++) {
 280                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 281                 mlx4_en_free_frag(priv, frags, nr);
 282         }
 283 }
 284
 285 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 286 {
 287         struct mlx4_en_rx_ring *ring;
 288         int ring_ind;
 289         int buf_ind;
 290         int new_size;
 291
 292         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 293                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 294                         ring = priv->rx_ring[ring_ind];
 295
 296                         if (mlx4_en_prepare_rx_desc(priv, ring,
 297                                                     ring->actual_size,
 298                                                     GFP_KERNEL | __GFP_COLD)) {
 299                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 300                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 301                                         return -ENOMEM;
 302                                 } else {
 303                                         new_size = rounddown_pow_of_two(ring->actual_size);
 304                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 305                                                 ring->actual_size, new_size);
 306                                         goto reduce_rings;
 307                                 }
 308                         }
 309                         ring->actual_size++;
 310                         ring->prod++;
 311                 }
 312         }
 313         return 0;
 314
 315 reduce_rings:
 316         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 317                 ring = priv->rx_ring[ring_ind];
 318                 while (ring->actual_size > new_size) {
 319                         ring->actual_size--;
 320                         ring->prod--;
 321                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 322                 }
 323         }
 324
 325         return 0;
 326 }
 327
 328 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 329                                 struct mlx4_en_rx_ring *ring)
 330 {
 331         int index;
 332
 333         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 334                ring->cons, ring->prod);
 335
 336         /* Unmap and free Rx buffers */
 337         while (!mlx4_en_is_ring_empty(ring)) {
 338                 index = ring->cons & ring->size_mask;
 339                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 340                 mlx4_en_free_rx_desc(priv, ring, index);
 341                 ++ring->cons;
 342         }
 343 }
 344
 345 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 346 {
 347         int i;
 348         int num_of_eqs;
 349         int num_rx_rings;
 350         struct mlx4_dev *dev = mdev->dev;
 351
 352         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 353                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 354                                    min_t(int,
 355                                          mlx4_get_eqs_per_port(mdev->dev, i),
 356                                          DEF_RX_RINGS));
 357
 358                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 359                         min_t(int, num_of_eqs,
 360                               netif_get_num_default_rss_queues());
 361                 mdev->profile.prof[i].rx_ring_num =
 362                         rounddown_pow_of_two(num_rx_rings);
 363         }
 364 }
 365
 366 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 367                            struct mlx4_en_rx_ring **pring,
 368                            u32 size, u16 stride, int node)
 369 {
 370         struct mlx4_en_dev *mdev = priv->mdev;
 371         struct mlx4_en_rx_ring *ring;
 372         int err = -ENOMEM;
 373         int tmp;
 374
 375         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 376         if (!ring) {
 377                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 378                 if (!ring) {
 379                         en_err(priv, "Failed to allocate RX ring structure\n");
 380                         return -ENOMEM;
 381                 }
 382         }
 383
 384         ring->prod = 0;
 385         ring->cons = 0;
 386         ring->size = size;
 387         ring->size_mask = size - 1;
 388         ring->stride = stride;
 389         ring->log_stride = ffs(ring->stride) - 1;
 390         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 391
 392         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 393                                         sizeof(struct mlx4_en_rx_alloc));
 394         ring->rx_info = vmalloc_node(tmp, node);
 395         if (!ring->rx_info) {
 396                 ring->rx_info = vmalloc(tmp);
 397                 if (!ring->rx_info) {
 398                         err = -ENOMEM;
 399                         goto err_ring;
 400                 }
 401         }
 402
 403         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 404                  ring->rx_info, tmp);
 405
 406         /* Allocate HW buffers on provided NUMA node */
 407         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 408         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 409         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 410         if (err)
 411                 goto err_info;
 412
 413         ring->buf = ring->wqres.buf.direct.buf;
 414
 415         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 416
 417         *pring = ring;
 418         return 0;
 419
 420 err_info:
 421         vfree(ring->rx_info);
 422         ring->rx_info = NULL;
 423 err_ring:
 424         kfree(ring);
 425         *pring = NULL;
 426
 427         return err;
 428 }
 429
 430 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 431 {
 432         struct mlx4_en_rx_ring *ring;
 433         int i;
 434         int ring_ind;
 435         int err;
 436         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 437                                         DS_SIZE * priv->num_frags);
 438
 439         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 440                 ring = priv->rx_ring[ring_ind];
 441
 442                 ring->prod = 0;
 443                 ring->cons = 0;
 444                 ring->actual_size = 0;
 445                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 446
 447                 ring->stride = stride;
 448                 if (ring->stride <= TXBB_SIZE) {
 449                         /* Stamp first unused send wqe */
 450                         __be32 *ptr = (__be32 *)ring->buf;
 451                         __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
 452                         *ptr = stamp;
 453                         /* Move pointer to start of rx section */
 454                         ring->buf += TXBB_SIZE;
 455                 }
 456
 457                 ring->log_stride = ffs(ring->stride) - 1;
 458                 ring->buf_size = ring->size * ring->stride;
 459
 460                 memset(ring->buf, 0, ring->buf_size);
 461                 mlx4_en_update_rx_prod_db(ring);
 462
 463                 /* Initialize all descriptors */
 464                 for (i = 0; i < ring->size; i++)
 465                         mlx4_en_init_rx_desc(priv, ring, i);
 466
 467                 /* Initialize page allocators */
 468                 err = mlx4_en_init_allocator(priv, ring);
 469                 if (err) {
 470                         en_err(priv, "Failed initializing ring allocator\n");
 471                         if (ring->stride <= TXBB_SIZE)
 472                                 ring->buf -= TXBB_SIZE;
 473                         ring_ind--;
 474                         goto err_allocator;
 475                 }
 476         }
 477         err = mlx4_en_fill_rx_buffers(priv);
 478         if (err)
 479                 goto err_buffers;
 480
 481         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 482                 ring = priv->rx_ring[ring_ind];
 483
 484                 ring->size_mask = ring->actual_size - 1;
 485                 mlx4_en_update_rx_prod_db(ring);
 486         }
 487
 488         return 0;
 489
 490 err_buffers:
 491         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 492                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 493
 494         ring_ind = priv->rx_ring_num - 1;
 495 err_allocator:
 496         while (ring_ind >= 0) {
 497                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 498                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 499                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 500                 ring_ind--;
 501         }
 502         return err;
 503 }
 504
 505 /* We recover from out of memory by scheduling our napi poll
 506  * function (mlx4_en_process_cq), which tries to allocate
 507  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 508  */
 509 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 510 {
 511         int ring;
 512
 513         if (!priv->port_up)
 514                 return;
 515
 516         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 517                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {
 518                         local_bh_disable();
 519                         napi_reschedule(&priv->rx_cq[ring]->napi);
 520                         local_bh_enable();
 521                 }
 522         }
 523 }
 524
 525 /* When the rx ring is running in page-per-packet mode, a released frame can go
 526  * directly into a small cache, to avoid unmapping or touching the page
 527  * allocator. In bpf prog performance scenarios, buffers are either forwarded
 528  * or dropped, never converted to skbs, so every page can come directly from
 529  * this cache when it is sized to be a multiple of the napi budget.
 530  */
 531 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
 532                         struct mlx4_en_rx_alloc *frame)
 533 {
 534         struct mlx4_en_page_cache *cache = &ring->page_cache;
 535
 536         if (cache->index >= MLX4_EN_CACHE_SIZE)
 537                 return false;
 538
 539         cache->buf[cache->index++] = *frame;
 540         return true;
 541 }
 542
 543 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 544                              struct mlx4_en_rx_ring **pring,
 545                              u32 size, u16 stride)
 546 {
 547         struct mlx4_en_dev *mdev = priv->mdev;
 548         struct mlx4_en_rx_ring *ring = *pring;
 549         struct bpf_prog *old_prog;
 550
 551         old_prog = rcu_dereference_protected(
 552                                         ring->xdp_prog,
 553                                         lockdep_is_held(&mdev->state_lock));
 554         if (old_prog)
 555                 bpf_prog_put(old_prog);
 556         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 557         vfree(ring->rx_info);
 558         ring->rx_info = NULL;
 559         kfree(ring);
 560         *pring = NULL;
 561 }
 562
 563 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 564                                 struct mlx4_en_rx_ring *ring)
 565 {
 566         int i;
 567
 568         for (i = 0; i < ring->page_cache.index; i++) {
 569                 struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i];
 570
 571                 dma_unmap_page(priv->ddev, frame->dma, frame->page_size,
 572                                priv->frag_info[0].dma_dir);
 573                 put_page(frame->page);
 574         }
 575         ring->page_cache.index = 0;
 576         mlx4_en_free_rx_buf(priv, ring);
 577         if (ring->stride <= TXBB_SIZE)
 578                 ring->buf -= TXBB_SIZE;
 579         mlx4_en_destroy_allocator(priv, ring);
 580 }
 581
 582
 583 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 584                                     struct mlx4_en_rx_desc *rx_desc,
 585                                     struct mlx4_en_rx_alloc *frags,
 586                                     struct sk_buff *skb,
 587                                     int length)
 588 {
 589         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 590         int nr;
 591         dma_addr_t dma;
 592
 593         /* Collect used fragments while replacing them in the HW descriptors */
 594         for (nr = 0; nr < priv->num_frags; nr++) {
 595                 struct mlx4_en_frag_info *frag_info = &priv->frag_info[nr];
 596                 u32 next_frag_end = frags[nr].page_offset +
 597                                 2 * frag_info->frag_stride;
 598
 599                 if (length <= frag_info->frag_prefix_size)
 600                         break;
 601                 if (unlikely(!frags[nr].page))
 602                         goto fail;
 603
 604                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 605                 if (next_frag_end > frags[nr].page_size)
 606                         dma_unmap_page(priv->ddev, frags[nr].dma,
 607                                        frags[nr].page_size, frag_info->dma_dir);
 608                 else
 609                         dma_sync_single_for_cpu(priv->ddev, dma,
 610                                                 frag_info->frag_size,
 611                                                 DMA_FROM_DEVICE);
 612
 613                 /* Save page reference in skb */
 614                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 615                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 616                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
 617                 skb->truesize += frag_info->frag_stride;
 618                 frags[nr].page = NULL;
 619         }
 620         /* Adjust size of last fragment to match actual length */
 621         if (nr > 0)
 622                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 623                         length - priv->frag_info[nr - 1].frag_prefix_size);
 624         return nr;
 625
 626 fail:
 627         while (nr > 0) {
 628                 nr--;
 629                 __skb_frag_unref(&skb_frags_rx[nr]);
 630         }
 631         return 0;
 632 }
 633
 634
 635 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 636                                       struct mlx4_en_rx_desc *rx_desc,
 637                                       struct mlx4_en_rx_alloc *frags,
 638                                       unsigned int length)
 639 {
 640         struct sk_buff *skb;
 641         void *va;
 642         int used_frags;
 643         dma_addr_t dma;
 644
 645         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 646         if (unlikely(!skb)) {
 647                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 648                 return NULL;
 649         }
 650         skb_reserve(skb, NET_IP_ALIGN);
 651         skb->len = length;
 652
 653         /* Get pointer to first fragment so we could copy the headers into the
 654          * (linear part of the) skb */
 655         va = page_address(frags[0].page) + frags[0].page_offset;
 656
 657         if (length <= SMALL_PACKET_SIZE) {
 658                 /* We are copying all relevant data to the skb - temporarily
 659                  * sync buffers for the copy */
 660                 dma = be64_to_cpu(rx_desc->data[0].addr);
 661                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 662                                         DMA_FROM_DEVICE);
 663                 skb_copy_to_linear_data(skb, va, length);
 664                 skb->tail += length;
 665         } else {
 666                 unsigned int pull_len;
 667
 668                 /* Move relevant fragments to skb */
 669                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 670                                                         skb, length);
 671                 if (unlikely(!used_frags)) {
 672                         kfree_skb(skb);
 673                         return NULL;
 674                 }
 675                 skb_shinfo(skb)->nr_frags = used_frags;
 676
 677                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 678                 /* Copy headers into the skb linear buffer */
 679                 memcpy(skb->data, va, pull_len);
 680                 skb->tail += pull_len;
 681
 682                 /* Skip headers in first fragment */
 683                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 684
 685                 /* Adjust size of first fragment */
 686                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 687                 skb->data_len = length - pull_len;
 688         }
 689         return skb;
 690 }
 691
 692 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 693 {
 694         int i;
 695         int offset = ETH_HLEN;
 696
 697         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 698                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 699                         goto out_loopback;
 700         }
 701         /* Loopback found */
 702         priv->loopback_ok = 1;
 703
 704 out_loopback:
 705         dev_kfree_skb_any(skb);
 706 }
 707
 708 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 709                                      struct mlx4_en_rx_ring *ring)
 710 {
 711         int index = ring->prod & ring->size_mask;
 712
 713         while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
 714                 if (mlx4_en_prepare_rx_desc(priv, ring, index,
 715                                             GFP_ATOMIC | __GFP_COLD))
 716                         break;
 717                 ring->prod++;
 718                 index = ring->prod & ring->size_mask;
 719         }
 720 }
 721
 722 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 723  * over it and add it to the hardware's checksum calculation
 724  */
 725 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 726                                          struct vlan_hdr *vlanh)
 727 {
 728         return csum_add(hw_checksum, *(__wsum *)vlanh);
 729 }
 730
 731 /* Although the stack expects checksum which doesn't include the pseudo
 732  * header, the HW adds it. To address that, we are subtracting the pseudo
 733  * header checksum from the checksum value provided by the HW.
 734  */
 735 static int get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 736                                struct iphdr *iph)
 737 {
 738         __u16 length_for_csum = 0;
 739         __wsum csum_pseudo_header = 0;
 740         __u8 ipproto = iph->protocol;
 741
 742         if (unlikely(ipproto == IPPROTO_SCTP))
 743                 return -1;
 744
 745         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 746         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 747                                                 length_for_csum, ipproto, 0);
 748         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 749         return 0;
 750 }
 751
 752 #if IS_ENABLED(CONFIG_IPV6)
 753 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 754  * we also compute/add the IP header checksum which
 755  * is not added by the HW.
 756  */
 757 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 758                                struct ipv6hdr *ipv6h)
 759 {
 760         __u8 nexthdr = ipv6h->nexthdr;
 761         __wsum csum_pseudo_hdr = 0;
 762
 763         if (unlikely(nexthdr == IPPROTO_FRAGMENT ||
 764                      nexthdr == IPPROTO_HOPOPTS ||
 765                      nexthdr == IPPROTO_SCTP))
 766                 return -1;
 767         hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(nexthdr));
 768
 769         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 770                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 771         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 772         csum_pseudo_hdr = csum_add(csum_pseudo_hdr,
 773                                    (__force __wsum)htons(nexthdr));
 774
 775         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 776         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 777         return 0;
 778 }
 779 #endif
 780
 781 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 782
 783 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 784                       netdev_features_t dev_features)
 785 {
 786         __wsum hw_checksum = 0;
 787         void *hdr;
 788
 789         /* CQE csum doesn't cover padding octets in short ethernet
 790          * frames. And the pad field is appended prior to calculating
 791          * and appending the FCS field.
 792          *
 793          * Detecting these padded frames requires to verify and parse
 794          * IP headers, so we simply force all those small frames to skip
 795          * checksum complete.
 796          */
 797         if (short_frame(skb->len))
 798                 return -EINVAL;
 799
 800         hdr = (u8 *)va + sizeof(struct ethhdr);
 801         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 802
 803         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 804             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 805                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 806                 hdr += sizeof(struct vlan_hdr);
 807         }
 808
 809         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 810                 return get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 811 #if IS_ENABLED(CONFIG_IPV6)
 812         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 813                 return get_fixed_ipv6_csum(hw_checksum, skb, hdr);
 814 #endif
 815         return 0;
 816 }
 817
 818 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 819 {
 820         struct mlx4_en_priv *priv = netdev_priv(dev);
 821         struct mlx4_en_dev *mdev = priv->mdev;
 822         struct mlx4_cqe *cqe;
 823         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 824         struct mlx4_en_rx_alloc *frags;
 825         struct mlx4_en_rx_desc *rx_desc;
 826         struct bpf_prog *xdp_prog;
 827         int doorbell_pending;
 828         struct sk_buff *skb;
 829         int tx_index;
 830         int index;
 831         int nr;
 832         unsigned int length;
 833         int polled = 0;
 834         int ip_summed;
 835         int factor = priv->cqe_factor;
 836         u64 timestamp;
 837         bool l2_tunnel;
 838
 839         if (unlikely(!priv->port_up))
 840                 return 0;
 841
 842         if (unlikely(budget <= 0))
 843                 return polled;
 844
 845         /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
 846         rcu_read_lock();
 847         xdp_prog = rcu_dereference(ring->xdp_prog);
 848         doorbell_pending = 0;
 849         tx_index = (priv->tx_ring_num - priv->xdp_ring_num) + cq->ring;
 850
 851         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 852          * descriptor offset can be deduced from the CQE index instead of
 853          * reading 'cqe->index' */
 854         index = cq->mcq.cons_index & ring->size_mask;
 855         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 856
 857         /* Process all completed CQEs */
 858         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 859                     cq->mcq.cons_index & cq->size)) {
 860
 861                 frags = ring->rx_info + (index << priv->log_rx_info);
 862                 rx_desc = ring->buf + (index << ring->log_stride);
 863
 864                 /*
 865                  * make sure we read the CQE after we read the ownership bit
 866                  */
 867                 dma_rmb();
 868
 869                 /* Drop packet on bad receive or bad checksum */
 870                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 871                                                 MLX4_CQE_OPCODE_ERROR)) {
 872                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 873                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 874                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 875                         goto next;
 876                 }
 877                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 878                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 879                         goto next;
 880                 }
 881
 882                 /* Check if we need to drop the packet if SRIOV is not enabled
 883                  * and not performing the selftest or flb disabled
 884                  */
 885                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 886                         struct ethhdr *ethh;
 887                         dma_addr_t dma;
 888                         /* Get pointer to first fragment since we haven't
 889                          * skb yet and cast it to ethhdr struct
 890                          */
 891                         dma = be64_to_cpu(rx_desc->data[0].addr);
 892                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 893                                                 DMA_FROM_DEVICE);
 894                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 895                                                  frags[0].page_offset);
 896
 897                         if (is_multicast_ether_addr(ethh->h_dest)) {
 898                                 struct mlx4_mac_entry *entry;
 899                                 struct hlist_head *bucket;
 900                                 unsigned int mac_hash;
 901
 902                                 /* Drop the packet, since HW loopback-ed it */
 903                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 904                                 bucket = &priv->mac_hash[mac_hash];
 905                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 906                                         if (ether_addr_equal_64bits(entry->mac,
 907                                                                     ethh->h_source))
 908                                                 goto next;
 909                                 }
 910                         }
 911                 }
 912
 913                 /*
 914                  * Packet is OK - process it.
 915                  */
 916                 length = be32_to_cpu(cqe->byte_cnt);
 917                 length -= ring->fcs_del;
 918                 ring->bytes += length;
 919                 ring->packets++;
 920                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 921                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 922
 923                 /* A bpf program gets first chance to drop the packet. It may
 924                  * read bytes but not past the end of the frag.
 925                  */
 926                 if (xdp_prog) {
 927                         struct xdp_buff xdp;
 928                         dma_addr_t dma;
 929                         u32 act;
 930
 931                         dma = be64_to_cpu(rx_desc->data[0].addr);
 932                         dma_sync_single_for_cpu(priv->ddev, dma,
 933                                                 priv->frag_info[0].frag_size,
 934                                                 DMA_FROM_DEVICE);
 935
 936                         xdp.data = page_address(frags[0].page) +
 937                                                         frags[0].page_offset;
 938                         xdp.data_end = xdp.data + length;
 939
 940                         act = bpf_prog_run_xdp(xdp_prog, &xdp);
 941                         switch (act) {
 942                         case XDP_PASS:
 943                                 break;
 944                         case XDP_TX:
 945                                 if (likely(!mlx4_en_xmit_frame(frags, dev,
 946                                                         length, tx_index,
 947                                                         &doorbell_pending)))
 948                                         goto consumed;
 949                                 goto xdp_drop; /* Drop on xmit failure */
 950                         default:
 951                                 bpf_warn_invalid_xdp_action(act);
 952                         case XDP_ABORTED:
 953                         case XDP_DROP:
 954 xdp_drop:
 955                                 if (likely(mlx4_en_rx_recycle(ring, frags)))
 956                                         goto consumed;
 957                                 goto next;
 958                         }
 959                 }
 960
 961                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 962                         /* TODO: For IP non TCP/UDP packets when csum complete is
 963                          * not an option (not supported or any other reason) we can
 964                          * actually check cqe IPOK status bit and report
 965                          * CHECKSUM_UNNECESSARY rather than CHECKSUM_NONE
 966                          */
 967                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 968                                                       MLX4_CQE_STATUS_UDP)) {
 969                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 970                                     cqe->checksum == cpu_to_be16(0xffff)) {
 971                                         ip_summed = CHECKSUM_UNNECESSARY;
 972                                         ring->csum_ok++;
 973                                 } else {
 974                                         ip_summed = CHECKSUM_NONE;
 975                                         ring->csum_none++;
 976                                 }
 977                         } else {
 978                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 979                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 980                                                                MLX4_CQE_STATUS_IPV6))) {
 981                                         ip_summed = CHECKSUM_COMPLETE;
 982                                         ring->csum_complete++;
 983                                 } else {
 984                                         ip_summed = CHECKSUM_NONE;
 985                                         ring->csum_none++;
 986                                 }
 987                         }
 988                 } else {
 989                         ip_summed = CHECKSUM_NONE;
 990                         ring->csum_none++;
 991                 }
 992
 993                 /* This packet is eligible for GRO if it is:
 994                  * - DIX Ethernet (type interpretation)
 995                  * - TCP/IP (v4)
 996                  * - without IP options
 997                  * - not an IP fragment
 998                  */
 999                 if (dev->features & NETIF_F_GRO) {
1000                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
1001                         if (!gro_skb)
1002                                 goto next;
1003
1004                         nr = mlx4_en_complete_rx_desc(priv,
1005                                 rx_desc, frags, gro_skb,
1006                                 length);
1007                         if (!nr)
1008                                 goto next;
1009
1010                         if (ip_summed == CHECKSUM_COMPLETE) {
1011                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
1012                                 if (check_csum(cqe, gro_skb, va,
1013                                                dev->features)) {
1014                                         ip_summed = CHECKSUM_NONE;
1015                                         ring->csum_none++;
1016                                         ring->csum_complete--;
1017                                 }
1018                         }
1019
1020                         skb_shinfo(gro_skb)->nr_frags = nr;
1021                         gro_skb->len = length;
1022                         gro_skb->data_len = length;
1023                         gro_skb->ip_summed = ip_summed;
1024
1025                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1026                                 gro_skb->csum_level = 1;
1027
1028                         if ((cqe->vlan_my_qpn &
1029                             cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
1030                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1031                                 u16 vid = be16_to_cpu(cqe->sl_vid);
1032
1033                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
1034                         } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1035                                   MLX4_CQE_SVLAN_PRESENT_MASK) &&
1036                                  (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
1037                                 __vlan_hwaccel_put_tag(gro_skb,
1038                                                        htons(ETH_P_8021AD),
1039                                                        be16_to_cpu(cqe->sl_vid));
1040                         }
1041
1042                         if (dev->features & NETIF_F_RXHASH)
1043                                 skb_set_hash(gro_skb,
1044                                              be32_to_cpu(cqe->immed_rss_invalid),
1045                                              (ip_summed == CHECKSUM_UNNECESSARY) ?
1046                                                 PKT_HASH_TYPE_L4 :
1047                                                 PKT_HASH_TYPE_L3);
1048
1049                         skb_record_rx_queue(gro_skb, cq->ring);
1050
1051                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1052                                 timestamp = mlx4_en_get_cqe_ts(cqe);
1053                                 mlx4_en_fill_hwtstamps(mdev,
1054                                                        skb_hwtstamps(gro_skb),
1055                                                        timestamp);
1056                         }
1057
1058                         napi_gro_frags(&cq->napi);
1059                         goto next;
1060                 }
1061
1062                 /* GRO not possible, complete processing here */
1063                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
1064                 if (unlikely(!skb)) {
1065                         ring->dropped++;
1066                         goto next;
1067                 }
1068
1069                 if (unlikely(priv->validate_loopback)) {
1070                         validate_loopback(priv, skb);
1071                         goto next;
1072                 }
1073
1074                 if (ip_summed == CHECKSUM_COMPLETE) {
1075                         if (check_csum(cqe, skb, skb->data, dev->features)) {
1076                                 ip_summed = CHECKSUM_NONE;
1077                                 ring->csum_complete--;
1078                                 ring->csum_none++;
1079                         }
1080                 }
1081
1082                 skb->ip_summed = ip_summed;
1083                 skb->protocol = eth_type_trans(skb, dev);
1084                 skb_record_rx_queue(skb, cq->ring);
1085
1086                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1087                         skb->csum_level = 1;
1088
1089                 if (dev->features & NETIF_F_RXHASH)
1090                         skb_set_hash(skb,
1091                                      be32_to_cpu(cqe->immed_rss_invalid),
1092                                      (ip_summed == CHECKSUM_UNNECESSARY) ?
1093                                         PKT_HASH_TYPE_L4 :
1094                                         PKT_HASH_TYPE_L3);
1095
1096                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
1097                     MLX4_CQE_CVLAN_PRESENT_MASK) &&
1098                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
1099                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
1100                 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1101                           MLX4_CQE_SVLAN_PRESENT_MASK) &&
1102                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
1103                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
1104                                                be16_to_cpu(cqe->sl_vid));
1105
1106                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1107                         timestamp = mlx4_en_get_cqe_ts(cqe);
1108                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
1109                                                timestamp);
1110                 }
1111
1112                 napi_gro_receive(&cq->napi, skb);
1113 next:
1114                 for (nr = 0; nr < priv->num_frags; nr++)
1115                         mlx4_en_free_frag(priv, frags, nr);
1116
1117 consumed:
1118                 ++cq->mcq.cons_index;
1119                 index = (cq->mcq.cons_index) & ring->size_mask;
1120                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1121                 if (++polled == budget)
1122                         goto out;
1123         }
1124
1125 out:
1126         rcu_read_unlock();
1127         if (doorbell_pending)
1128                 mlx4_en_xmit_doorbell(priv->tx_ring[tx_index]);
1129
1130         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1131         mlx4_cq_set_ci(&cq->mcq);
1132         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1133         ring->cons = cq->mcq.cons_index;
1134         mlx4_en_refill_rx_buffers(priv, ring);
1135         mlx4_en_update_rx_prod_db(ring);
1136         return polled;
1137 }
1138
1139
1140 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1141 {
1142         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1143         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1144
1145         if (likely(priv->port_up))
1146                 napi_schedule_irqoff(&cq->napi);
1147         else
1148                 mlx4_en_arm_cq(priv, cq);
1149 }
1150
1151 /* Rx CQ polling - called by NAPI */
1152 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1153 {
1154         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1155         struct net_device *dev = cq->dev;
1156         struct mlx4_en_priv *priv = netdev_priv(dev);
1157         int done;
1158
1159         done = mlx4_en_process_rx_cq(dev, cq, budget);
1160
1161         /* If we used up all the quota - we're probably not done yet... */
1162         if (done == budget) {
1163                 const struct cpumask *aff;
1164                 struct irq_data *idata;
1165                 int cpu_curr;
1166
1167                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1168
1169                 cpu_curr = smp_processor_id();
1170                 idata = irq_desc_get_irq_data(cq->irq_desc);
1171                 aff = irq_data_get_affinity_mask(idata);
1172
1173                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1174                         return budget;
1175
1176                 /* Current cpu is not according to smp_irq_affinity -
1177                  * probably affinity changed. need to stop this NAPI
1178                  * poll, and restart it on the right CPU
1179                  */
1180                 done = 0;
1181         }
1182         /* Done for now */
1183         napi_complete_done(napi, done);
1184         mlx4_en_arm_cq(priv, cq);
1185         return done;
1186 }
1187
1188 static const int frag_sizes[] = {
1189         FRAG_SZ0,
1190         FRAG_SZ1,
1191         FRAG_SZ2,
1192         FRAG_SZ3
1193 };
1194
1195 void mlx4_en_calc_rx_buf(struct net_device *dev)
1196 {
1197         enum dma_data_direction dma_dir = PCI_DMA_FROMDEVICE;
1198         struct mlx4_en_priv *priv = netdev_priv(dev);
1199         int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
1200         int order = MLX4_EN_ALLOC_PREFER_ORDER;
1201         u32 align = SMP_CACHE_BYTES;
1202         int buf_size = 0;
1203         int i = 0;
1204
1205         /* bpf requires buffers to be set up as 1 packet per page.
1206          * This only works when num_frags == 1.
1207          */
1208         if (priv->xdp_ring_num) {
1209                 dma_dir = PCI_DMA_BIDIRECTIONAL;
1210                 /* This will gain efficient xdp frame recycling at the expense
1211                  * of more costly truesize accounting
1212                  */
1213                 align = PAGE_SIZE;
1214                 order = 0;
1215         }
1216
1217         while (buf_size < eff_mtu) {
1218                 priv->frag_info[i].order = order;
1219                 priv->frag_info[i].frag_size =
1220                         (eff_mtu > buf_size + frag_sizes[i]) ?
1221                                 frag_sizes[i] : eff_mtu - buf_size;
1222                 priv->frag_info[i].frag_prefix_size = buf_size;
1223                 priv->frag_info[i].frag_stride =
1224                                 ALIGN(priv->frag_info[i].frag_size, align);
1225                 priv->frag_info[i].dma_dir = dma_dir;
1226                 buf_size += priv->frag_info[i].frag_size;
1227                 i++;
1228         }
1229
1230         priv->num_frags = i;
1231         priv->rx_skb_size = eff_mtu;
1232         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1233
1234         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1235                eff_mtu, priv->num_frags);
1236         for (i = 0; i < priv->num_frags; i++) {
1237                 en_err(priv,
1238                        "  frag:%d - size:%d prefix:%d stride:%d\n",
1239                        i,
1240                        priv->frag_info[i].frag_size,
1241                        priv->frag_info[i].frag_prefix_size,
1242                        priv->frag_info[i].frag_stride);
1243         }
1244 }
1245
1246 /* RSS related functions */
1247
1248 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1249                                  struct mlx4_en_rx_ring *ring,
1250                                  enum mlx4_qp_state *state,
1251                                  struct mlx4_qp *qp)
1252 {
1253         struct mlx4_en_dev *mdev = priv->mdev;
1254         struct mlx4_qp_context *context;
1255         int err = 0;
1256
1257         context = kmalloc(sizeof(*context), GFP_KERNEL);
1258         if (!context)
1259                 return -ENOMEM;
1260
1261         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1262         if (err) {
1263                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1264                 goto out;
1265         }
1266         qp->event = mlx4_en_sqp_event;
1267
1268         memset(context, 0, sizeof *context);
1269         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1270                                 qpn, ring->cqn, -1, context);
1271         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1272
1273         /* Cancel FCS removal if FW allows */
1274         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1275                 context->param3 |= cpu_to_be32(1 << 29);
1276                 if (priv->dev->features & NETIF_F_RXFCS)
1277                         ring->fcs_del = 0;
1278                 else
1279                         ring->fcs_del = ETH_FCS_LEN;
1280         } else
1281                 ring->fcs_del = 0;
1282
1283         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1284         if (err) {
1285                 mlx4_qp_remove(mdev->dev, qp);
1286                 mlx4_qp_free(mdev->dev, qp);
1287         }
1288         mlx4_en_update_rx_prod_db(ring);
1289 out:
1290         kfree(context);
1291         return err;
1292 }
1293
1294 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1295 {
1296         int err;
1297         u32 qpn;
1298
1299         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1300                                     MLX4_RESERVE_A0_QP);
1301         if (err) {
1302                 en_err(priv, "Failed reserving drop qpn\n");
1303                 return err;
1304         }
1305         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1306         if (err) {
1307                 en_err(priv, "Failed allocating drop qp\n");
1308                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1309                 return err;
1310         }
1311
1312         return 0;
1313 }
1314
1315 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1316 {
1317         u32 qpn;
1318
1319         qpn = priv->drop_qp.qpn;
1320         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1321         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1322         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1323 }
1324
1325 /* Allocate rx qp's and configure them according to rss map */
1326 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1327 {
1328         struct mlx4_en_dev *mdev = priv->mdev;
1329         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1330         struct mlx4_qp_context context;
1331         struct mlx4_rss_context *rss_context;
1332         int rss_rings;
1333         void *ptr;
1334         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1335                         MLX4_RSS_TCP_IPV6);
1336         int i, qpn;
1337         int err = 0;
1338         int good_qps = 0;
1339
1340         en_dbg(DRV, priv, "Configuring rss steering\n");
1341         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1342                                     priv->rx_ring_num,
1343                                     &rss_map->base_qpn, 0);
1344         if (err) {
1345                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1346                 return err;
1347         }
1348
1349         for (i = 0; i < priv->rx_ring_num; i++) {
1350                 qpn = rss_map->base_qpn + i;
1351                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1352                                             &rss_map->state[i],
1353                                             &rss_map->qps[i]);
1354                 if (err)
1355                         goto rss_err;
1356
1357                 ++good_qps;
1358         }
1359
1360         /* Configure RSS indirection qp */
1361         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1362         if (err) {
1363                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1364                 goto rss_err;
1365         }
1366         rss_map->indir_qp.event = mlx4_en_sqp_event;
1367         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1368                                 priv->rx_ring[0]->cqn, -1, &context);
1369
1370         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1371                 rss_rings = priv->rx_ring_num;
1372         else
1373                 rss_rings = priv->prof->rss_rings;
1374
1375         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1376                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1377         rss_context = ptr;
1378         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1379                                             (rss_map->base_qpn));
1380         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1381         if (priv->mdev->profile.udp_rss) {
1382                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1383                 rss_context->base_qpn_udp = rss_context->default_qpn;
1384         }
1385
1386         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1387                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1388                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1389         }
1390
1391         rss_context->flags = rss_mask;
1392         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1393         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1394                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1395         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1396                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1397                 memcpy(rss_context->rss_key, priv->rss_key,
1398                        MLX4_EN_RSS_KEY_SIZE);
1399         } else {
1400                 en_err(priv, "Unknown RSS hash function requested\n");
1401                 err = -EINVAL;
1402                 goto indir_err;
1403         }
1404         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1405                                &rss_map->indir_qp, &rss_map->indir_state);
1406         if (err)
1407                 goto indir_err;
1408
1409         return 0;
1410
1411 indir_err:
1412         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1413                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1414         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1415         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1416 rss_err:
1417         for (i = 0; i < good_qps; i++) {
1418                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1419                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1420                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1421                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1422         }
1423         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1424         return err;
1425 }
1426
1427 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1428 {
1429         struct mlx4_en_dev *mdev = priv->mdev;
1430         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1431         int i;
1432
1433         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1434                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1435         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1436         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1437
1438         for (i = 0; i < priv->rx_ring_num; i++) {
1439                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1440                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1441                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1442                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1443         }
1444         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1445 }