1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 #ifndef _E1000_DEFINES_H_
25 #define _E1000_DEFINES_H_
27 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
28 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
29 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
31 /* Definitions for power management and wakeup registers */
33 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
35 /* Wake Up Filter Control */
36 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
37 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
38 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
39 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
40 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
43 #define E1000_WUS_EX 0x00000004 /* Directed Exact */
44 #define E1000_WUS_ARPD 0x00000020 /* Directed ARP Request */
45 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 */
46 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 */
47 #define E1000_WUS_NSD 0x00000400 /* Directed IPv6 Neighbor Solicitation */
49 /* Packet types that are enabled for wake packet delivery */
50 #define WAKE_PKT_WUS ( \
57 /* Wake Up Packet Length */
58 #define E1000_WUPL_MASK 0x00000FFF
60 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
61 #define E1000_WUPM_BYTES 128
63 /* Extended Device Control */
64 #define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */
65 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
66 #define E1000_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */
67 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */
69 /* Physical Func Reset Done Indication */
70 #define E1000_CTRL_EXT_PFRSTD 0x00004000
71 #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */
72 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
73 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
74 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
75 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
76 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
77 #define E1000_CTRL_EXT_EIAME 0x01000000
78 #define E1000_CTRL_EXT_IRCA 0x00000001
79 /* Interrupt delay cancellation */
80 /* Driver loaded bit for FW */
81 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000
82 /* Interrupt acknowledge Auto-mask */
83 /* Clear Interrupt timers after IMS clear */
84 /* packet buffer parity error detection enabled */
85 /* descriptor FIFO parity error detection enable */
86 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
87 #define E1000_CTRL_EXT_PHYPDEN 0x00100000
88 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
89 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
90 #define E1000_I2CCMD_OPCODE_READ 0x08000000
91 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
92 #define E1000_I2CCMD_READY 0x20000000
93 #define E1000_I2CCMD_ERROR 0x80000000
94 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
95 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
96 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
97 #define E1000_I2CCMD_PHY_TIMEOUT 200
98 #define E1000_IVAR_VALID 0x80
99 #define E1000_GPIE_NSICR 0x00000001
100 #define E1000_GPIE_MSIX_MODE 0x00000010
101 #define E1000_GPIE_EIAME 0x40000000
102 #define E1000_GPIE_PBA 0x80000000
104 /* Receive Descriptor bit definitions */
105 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
106 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
107 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
108 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
109 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
110 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
111 #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */
113 #define E1000_RXDEXT_STATERR_LB 0x00040000
114 #define E1000_RXDEXT_STATERR_CE 0x01000000
115 #define E1000_RXDEXT_STATERR_SE 0x02000000
116 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
117 #define E1000_RXDEXT_STATERR_CXE 0x10000000
118 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
119 #define E1000_RXDEXT_STATERR_IPE 0x40000000
120 #define E1000_RXDEXT_STATERR_RXE 0x80000000
122 /* Same mask, but for extended and packet split descriptors */
123 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
124 E1000_RXDEXT_STATERR_CE | \
125 E1000_RXDEXT_STATERR_SE | \
126 E1000_RXDEXT_STATERR_SEQ | \
127 E1000_RXDEXT_STATERR_CXE | \
128 E1000_RXDEXT_STATERR_RXE)
130 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
131 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
132 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
133 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
134 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
137 /* Management Control */
138 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
139 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
140 #define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */
141 /* Enable Neighbor Discovery Filtering */
142 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
143 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
144 /* Enable MAC address filtering */
145 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
147 /* Receive Control */
148 #define E1000_RCTL_EN 0x00000002 /* enable */
149 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
150 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
151 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
152 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
153 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
154 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
155 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
156 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
157 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
158 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
159 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
160 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
161 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
162 #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */
163 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
164 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
166 /* Use byte values for the following shift parameters
168 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
169 * E1000_PSRCTL_BSIZE0_MASK) |
170 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
171 * E1000_PSRCTL_BSIZE1_MASK) |
172 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
173 * E1000_PSRCTL_BSIZE2_MASK) |
174 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
175 * E1000_PSRCTL_BSIZE3_MASK))
176 * where value0 = [128..16256], default=256
177 * value1 = [1024..64512], default=4096
178 * value2 = [0..64512], default=4096
179 * value3 = [0..64512], default=0
182 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
183 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
184 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
185 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
187 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
188 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
189 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
190 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
192 /* SWFW_SYNC Definitions */
193 #define E1000_SWFW_EEP_SM 0x1
194 #define E1000_SWFW_PHY0_SM 0x2
195 #define E1000_SWFW_PHY1_SM 0x4
196 #define E1000_SWFW_PHY2_SM 0x20
197 #define E1000_SWFW_PHY3_SM 0x40
199 /* FACTPS Definitions */
201 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
202 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
203 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
204 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
205 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
206 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
207 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
208 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
209 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
210 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
211 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
212 /* Defined polarity of Dock/Undock indication in SDP[0] */
213 /* Reset both PHY ports, through PHYRST_N pin */
214 /* enable link status from external LINK_0 and LINK_1 pins */
215 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
216 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
217 #define E1000_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */
218 #define E1000_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */
219 #define E1000_CTRL_RST 0x04000000 /* Global reset */
220 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
221 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
222 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
223 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
224 /* Initiate an interrupt to manageability engine */
225 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
227 /* Bit definitions for the Management Data IO (MDIO) and Management Data
228 * Clock (MDC) pins in the Device Control Register.
231 #define E1000_CONNSW_ENRGSRC 0x4
232 #define E1000_CONNSW_PHYSD 0x400
233 #define E1000_CONNSW_PHY_PDN 0x800
234 #define E1000_CONNSW_SERDESD 0x200
235 #define E1000_CONNSW_AUTOSENSE_CONF 0x2
236 #define E1000_CONNSW_AUTOSENSE_EN 0x1
237 #define E1000_PCS_CFG_PCS_EN 8
238 #define E1000_PCS_LCTL_FLV_LINK_UP 1
239 #define E1000_PCS_LCTL_FSV_100 2
240 #define E1000_PCS_LCTL_FSV_1000 4
241 #define E1000_PCS_LCTL_FDV_FULL 8
242 #define E1000_PCS_LCTL_FSD 0x10
243 #define E1000_PCS_LCTL_FORCE_LINK 0x20
244 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
245 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
246 #define E1000_PCS_LCTL_AN_RESTART 0x20000
247 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
248 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
250 #define E1000_PCS_LSTS_LINK_OK 1
251 #define E1000_PCS_LSTS_SPEED_100 2
252 #define E1000_PCS_LSTS_SPEED_1000 4
253 #define E1000_PCS_LSTS_DUPLEX_FULL 8
254 #define E1000_PCS_LSTS_SYNK_OK 0x10
257 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
258 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
259 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
260 #define E1000_STATUS_FUNC_SHIFT 2
261 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
262 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
263 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
264 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
265 /* Change in Dock/Undock state. Clear on write '0'. */
266 /* Status of Master requests. */
267 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
268 /* BMC external code execution disabled */
270 #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */
271 #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */
272 /* Constants used to intrepret the masked PCI-X bus speed. */
275 #define SPEED_100 100
276 #define SPEED_1000 1000
277 #define SPEED_2500 2500
278 #define HALF_DUPLEX 1
279 #define FULL_DUPLEX 2
282 #define ADVERTISE_10_HALF 0x0001
283 #define ADVERTISE_10_FULL 0x0002
284 #define ADVERTISE_100_HALF 0x0004
285 #define ADVERTISE_100_FULL 0x0008
286 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
287 #define ADVERTISE_1000_FULL 0x0020
289 /* 1000/H is not supported, nor spec-compliant. */
290 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
291 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
293 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
294 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
295 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
296 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
297 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
299 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
301 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
304 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
305 #define E1000_LEDCTL_LED0_BLINK 0x00000080
306 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
307 #define E1000_LEDCTL_LED0_IVRT 0x00000040
309 #define E1000_LEDCTL_MODE_LED_ON 0xE
310 #define E1000_LEDCTL_MODE_LED_OFF 0xF
312 /* Transmit Descriptor bit definitions */
313 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
314 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
315 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
316 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
317 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
318 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
319 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
320 /* Extended desc bits for Linksec and timesync */
322 /* Transmit Control */
323 #define E1000_TCTL_EN 0x00000002 /* enable tx */
324 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
325 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
326 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
327 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
329 /* DMA Coalescing register fields */
330 #define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coal Watchdog Timer */
331 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coal Rx Threshold */
332 #define E1000_DMACR_DMACTHR_SHIFT 16
333 #define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe trans */
334 #define E1000_DMACR_DMAC_LX_SHIFT 28
335 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
336 /* DMA Coalescing BMC-to-OS Watchdog Enable */
337 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
339 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coal Tx Threshold */
341 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
343 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Rx Traffic Rate Thresh */
344 #define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rx pkt rate curr window */
346 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rx Current Cnt */
348 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* FC Rx Thresh High val */
349 #define E1000_FCRTC_RTH_COAL_SHIFT 4
350 #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */
352 /* Timestamp in Rx buffer */
353 #define E1000_RXPBS_CFG_TS_EN 0x80000000
355 #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
356 #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
359 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
361 /* Receive Checksum Control */
362 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
363 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
364 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
365 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
367 /* Header split receive */
368 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
369 #define E1000_RFCTL_LEF 0x00040000
371 /* Collision related configuration parameters */
372 #define E1000_COLLISION_THRESHOLD 15
373 #define E1000_CT_SHIFT 4
374 #define E1000_COLLISION_DISTANCE 63
375 #define E1000_COLD_SHIFT 12
377 /* Ethertype field values */
378 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
380 /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
381 #define MAX_JUMBO_FRAME_SIZE 0x2600
382 #define MAX_STD_JUMBO_FRAME_SIZE 9216
385 #define E1000_PBA_34K 0x0022
386 #define E1000_PBA_64K 0x0040 /* 64KB */
388 /* SW Semaphore Register */
389 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
390 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
392 /* Interrupt Cause Read */
393 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
394 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
395 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
396 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
397 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
398 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
399 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
400 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
401 /* If this bit asserted, the driver should claim the interrupt */
402 #define E1000_ICR_INT_ASSERTED 0x80000000
403 /* LAN connected device generates an interrupt */
404 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
406 /* Extended Interrupt Cause Read */
407 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
408 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
409 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
410 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
411 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
412 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
413 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
414 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
415 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
418 /* This defines the bits that are set in the Interrupt Mask
419 * Set/Read Register. Each bit is documented below:
420 * o RXT0 = Receiver Timer Interrupt (ring 0)
421 * o TXDW = Transmit Descriptor Written Back
422 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
423 * o RXSEQ = Receive Sequence Error
424 * o LSC = Link Status Change
426 #define IMS_ENABLE_MASK ( \
434 /* Interrupt Mask Set */
435 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
436 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
437 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
438 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */
439 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
440 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
441 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
442 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
443 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
445 /* Extended Interrupt Mask Set */
446 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
448 /* Interrupt Cause Set */
449 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
450 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
451 #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
453 /* Extended Interrupt Cause Set */
454 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
455 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
458 /* Transmit Descriptor Control */
459 /* Enable the counting of descriptors still to be processed. */
461 /* Flow Control Constants */
462 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
463 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
464 #define FLOW_CONTROL_TYPE 0x8808
466 /* Transmit Config Word */
467 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
468 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
470 /* 802.1q VLAN Packet Size */
471 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
472 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
474 /* Receive Address */
475 /* Number of high/low register pairs in the RAR. The RAR (Receive Address
476 * Registers) holds the directed and multicast addresses that we monitor.
477 * Technically, we have 16 spots. However, we reserve one of these spots
478 * (RAR[15]) for our directed address used by controllers with
479 * manageability enabled, allowing us room for 15 multicast addresses.
481 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
482 #define E1000_RAL_MAC_ADDR_LEN 4
483 #define E1000_RAH_MAC_ADDR_LEN 2
484 #define E1000_RAH_POOL_MASK 0x03FC0000
485 #define E1000_RAH_POOL_1 0x00040000
488 #define E1000_ERR_NVM 1
489 #define E1000_ERR_PHY 2
490 #define E1000_ERR_CONFIG 3
491 #define E1000_ERR_PARAM 4
492 #define E1000_ERR_MAC_INIT 5
493 #define E1000_ERR_RESET 9
494 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
495 #define E1000_BLK_PHY_RESET 12
496 #define E1000_ERR_SWFW_SYNC 13
497 #define E1000_NOT_IMPLEMENTED 14
498 #define E1000_ERR_MBX 15
499 #define E1000_ERR_INVALID_ARGUMENT 16
500 #define E1000_ERR_NO_SPACE 17
501 #define E1000_ERR_NVM_PBA_SECTION 18
502 #define E1000_ERR_INVM_VALUE_NOT_FOUND 19
503 #define E1000_ERR_I2C 20
505 /* Loop limit on how long we wait for auto-negotiation to complete */
506 #define COPPER_LINK_UP_LIMIT 10
507 #define PHY_AUTO_NEG_LIMIT 45
508 #define PHY_FORCE_LIMIT 20
509 /* Number of 100 microseconds we wait for PCI Express master disable */
510 #define MASTER_DISABLE_TIMEOUT 800
511 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
512 #define PHY_CFG_TIMEOUT 100
513 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
514 /* Number of milliseconds for NVM auto read done after MAC reset. */
515 #define AUTO_READ_DONE_TIMEOUT 10
518 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
520 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */
521 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */
523 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */
524 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */
525 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
526 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
527 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
528 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08
529 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
530 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */
532 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
533 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
534 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
535 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
536 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
537 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
539 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
540 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
541 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
542 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
543 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
544 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
545 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
546 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
547 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
548 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
549 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
551 #define E1000_TIMINCA_16NS_SHIFT 24
553 /* Time Sync Interrupt Cause/Mask Register Bits */
555 #define TSINTR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */
556 #define TSINTR_TXTS BIT(1) /* Transmit Timestamp. */
557 #define TSINTR_RXTS BIT(2) /* Receive Timestamp. */
558 #define TSINTR_TT0 BIT(3) /* Target Time 0 Trigger. */
559 #define TSINTR_TT1 BIT(4) /* Target Time 1 Trigger. */
560 #define TSINTR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */
561 #define TSINTR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */
562 #define TSINTR_TADJ BIT(7) /* Time Adjust Done. */
564 #define TSYNC_INTERRUPTS TSINTR_TXTS
565 #define E1000_TSICR_TXTS TSINTR_TXTS
567 /* TSAUXC Configuration Bits */
568 #define TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */
569 #define TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */
570 #define TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */
571 #define TSAUXC_SAMP_AUT0 BIT(3) /* Latch SYSTIML/H into AUXSTMPL/0. */
572 #define TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */
573 #define TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */
574 #define TSAUXC_SAMP_AUT1 BIT(6) /* Latch SYSTIML/H into AUXSTMPL/1. */
575 #define TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */
576 #define TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */
577 #define TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */
578 #define TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */
579 #define TSAUXC_AUTT1 BIT(11) /* Auxiliary Timestamp Taken. */
580 #define TSAUXC_PLSG BIT(17) /* Generate a pulse. */
581 #define TSAUXC_DISABLE BIT(31) /* Disable SYSTIM Count Operation. */
583 /* SDP Configuration Bits */
584 #define AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */
585 #define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
586 #define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */
587 #define AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */
588 #define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
589 #define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
590 #define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */
591 #define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
592 #define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */
593 #define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
594 #define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
595 #define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
596 #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
597 #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
598 #define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */
599 #define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
600 #define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
601 #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
602 #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
603 #define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */
604 #define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
605 #define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
606 #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
607 #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
608 #define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */
609 #define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
610 #define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
611 #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
612 #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
613 #define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */
615 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
616 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
617 #define E1000_MDICNFG_PHY_MASK 0x03E00000
618 #define E1000_MDICNFG_PHY_SHIFT 21
620 #define E1000_MEDIA_PORT_COPPER 1
621 #define E1000_MEDIA_PORT_OTHER 2
622 #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2
623 #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3
624 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */
625 #define E1000_M88E1112_MAC_CTRL_1 0x10
626 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */
627 #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7
628 #define E1000_M88E1112_PAGE_ADDR 0x16
629 #define E1000_M88E1112_STATUS 0x01
630 #define E1000_M88E1512_CFG_REG_1 0x0010
631 #define E1000_M88E1512_CFG_REG_2 0x0011
632 #define E1000_M88E1512_CFG_REG_3 0x0007
633 #define E1000_M88E1512_MODE 0x0014
635 /* PCI Express Control */
636 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
637 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
638 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
639 #define E1000_GCR_CAP_VER2 0x00040000
641 /* mPHY Address Control and Data Registers */
642 #define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */
643 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
644 #define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */
646 /* mPHY PCS CLK Register */
647 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */
648 /* mPHY Near End Digital Loopback Override Bit */
649 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
651 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
652 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
654 /* PHY Control Register */
655 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
656 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
657 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
658 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
659 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
660 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
661 #define MII_CR_SPEED_1000 0x0040
662 #define MII_CR_SPEED_100 0x2000
663 #define MII_CR_SPEED_10 0x0000
665 /* PHY Status Register */
666 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
667 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
669 /* Autoneg Advertisement Register */
670 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
671 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
672 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
673 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
674 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
675 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
677 /* Link Partner Ability Register (Base Page) */
678 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
679 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
681 /* Autoneg Expansion Register */
683 /* 1000BASE-T Control Register */
684 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
685 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
686 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
687 /* 0=Configure PHY as Slave */
688 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
689 /* 0=Automatic Master/Slave config */
691 /* 1000BASE-T Status Register */
692 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
693 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
696 /* PHY 1000 MII Register/Bit Definitions */
697 /* PHY Registers defined by IEEE */
698 #define PHY_CONTROL 0x00 /* Control Register */
699 #define PHY_STATUS 0x01 /* Status Register */
700 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
701 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
702 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
703 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
704 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
705 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
708 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
709 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
710 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
711 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
712 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
713 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
714 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
715 /* NVM Addressing bits based on type 0=small, 1=large */
716 #define E1000_EECD_ADDR_BITS 0x00000400
717 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
718 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
719 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
720 #define E1000_EECD_SIZE_EX_SHIFT 11
721 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
722 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
723 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
724 #define E1000_FLUDONE_ATTEMPTS 20000
725 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
726 #define E1000_I210_FIFO_SEL_RX 0x00
727 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
728 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
729 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
730 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
731 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */
732 /* Secure FLASH mode requires removing MSb */
733 #define E1000_I210_FW_PTR_MASK 0x7FFF
734 /* Firmware code revision field word offset*/
735 #define E1000_I210_FW_VER_OFFSET 328
736 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
737 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
738 #define E1000_FLUDONE_ATTEMPTS 20000
739 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
740 #define E1000_I210_FIFO_SEL_RX 0x00
741 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
742 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
743 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
744 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
747 /* Offset to data in NVM read/write registers */
748 #define E1000_NVM_RW_REG_DATA 16
749 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
750 #define E1000_NVM_RW_REG_START 1 /* Start operation */
751 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
752 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
754 /* NVM Word Offsets */
755 #define NVM_COMPAT 0x0003
756 #define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */
757 #define NVM_VERSION 0x0005
758 #define NVM_INIT_CONTROL2_REG 0x000F
759 #define NVM_INIT_CONTROL3_PORT_B 0x0014
760 #define NVM_INIT_CONTROL3_PORT_A 0x0024
761 #define NVM_ALT_MAC_ADDR_PTR 0x0037
762 #define NVM_CHECKSUM_REG 0x003F
763 #define NVM_COMPATIBILITY_REG_3 0x0003
764 #define NVM_COMPATIBILITY_BIT_MASK 0x8000
765 #define NVM_MAC_ADDR 0x0000
766 #define NVM_SUB_DEV_ID 0x000B
767 #define NVM_SUB_VEN_ID 0x000C
768 #define NVM_DEV_ID 0x000D
769 #define NVM_VEN_ID 0x000E
770 #define NVM_INIT_CTRL_2 0x000F
771 #define NVM_INIT_CTRL_4 0x0013
772 #define NVM_LED_1_CFG 0x001C
773 #define NVM_LED_0_2_CFG 0x001F
774 #define NVM_ETRACK_WORD 0x0042
775 #define NVM_ETRACK_HIWORD 0x0043
776 #define NVM_COMB_VER_OFF 0x0083
777 #define NVM_COMB_VER_PTR 0x003d
779 /* NVM version defines */
780 #define NVM_MAJOR_MASK 0xF000
781 #define NVM_MINOR_MASK 0x0FF0
782 #define NVM_IMAGE_ID_MASK 0x000F
783 #define NVM_COMB_VER_MASK 0x00FF
784 #define NVM_MAJOR_SHIFT 12
785 #define NVM_MINOR_SHIFT 4
786 #define NVM_COMB_VER_SHFT 8
787 #define NVM_VER_INVALID 0xFFFF
788 #define NVM_ETRACK_SHIFT 16
789 #define NVM_ETRACK_VALID 0x8000
790 #define NVM_NEW_DEC_MASK 0x0F00
791 #define NVM_HEX_CONV 16
792 #define NVM_HEX_TENS 10
794 #define NVM_ETS_CFG 0x003E
795 #define NVM_ETS_LTHRES_DELTA_MASK 0x07C0
796 #define NVM_ETS_LTHRES_DELTA_SHIFT 6
797 #define NVM_ETS_TYPE_MASK 0x0038
798 #define NVM_ETS_TYPE_SHIFT 3
799 #define NVM_ETS_TYPE_EMC 0x000
800 #define NVM_ETS_NUM_SENSORS_MASK 0x0007
801 #define NVM_ETS_DATA_LOC_MASK 0x3C00
802 #define NVM_ETS_DATA_LOC_SHIFT 10
803 #define NVM_ETS_DATA_INDEX_MASK 0x0300
804 #define NVM_ETS_DATA_INDEX_SHIFT 8
805 #define NVM_ETS_DATA_HTHRESH_MASK 0x00FF
807 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
808 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
809 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
810 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
812 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
814 /* Mask bits for fields in Word 0x24 of the NVM */
815 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
816 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */
818 /* Mask bits for fields in Word 0x0f of the NVM */
819 #define NVM_WORD0F_PAUSE_MASK 0x3000
820 #define NVM_WORD0F_ASM_DIR 0x2000
822 /* Mask bits for fields in Word 0x1a of the NVM */
824 /* length of string needed to store part num */
825 #define E1000_PBANUM_LENGTH 11
827 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
828 #define NVM_SUM 0xBABA
830 #define NVM_PBA_OFFSET_0 8
831 #define NVM_PBA_OFFSET_1 9
832 #define NVM_RESERVED_WORD 0xFFFF
833 #define NVM_PBA_PTR_GUARD 0xFAFA
834 #define NVM_WORD_SIZE_BASE_SHIFT 6
836 /* NVM Commands - Microwire */
838 /* NVM Commands - SPI */
839 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
840 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
841 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
842 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
843 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
844 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
846 /* SPI NVM Status Register */
847 #define NVM_STATUS_RDY_SPI 0x01
849 /* Word definitions for ID LED Settings */
850 #define ID_LED_RESERVED_0000 0x0000
851 #define ID_LED_RESERVED_FFFF 0xFFFF
852 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
853 (ID_LED_OFF1_OFF2 << 8) | \
854 (ID_LED_DEF1_DEF2 << 4) | \
856 #define ID_LED_DEF1_DEF2 0x1
857 #define ID_LED_DEF1_ON2 0x2
858 #define ID_LED_DEF1_OFF2 0x3
859 #define ID_LED_ON1_DEF2 0x4
860 #define ID_LED_ON1_ON2 0x5
861 #define ID_LED_ON1_OFF2 0x6
862 #define ID_LED_OFF1_DEF2 0x7
863 #define ID_LED_OFF1_ON2 0x8
864 #define ID_LED_OFF1_OFF2 0x9
866 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
867 #define IGP_ACTIVITY_LED_ENABLE 0x0300
868 #define IGP_LED3_MODE 0x07000000
870 /* PCI/PCI-X/PCI-EX Config space */
871 #define PCIE_DEVICE_CONTROL2 0x28
872 #define PCIE_DEVICE_CONTROL2_16ms 0x0005
874 #define PHY_REVISION_MASK 0xFFFFFFF0
875 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
876 #define MAX_PHY_MULTI_PAGE_REG 0xF
878 /* Bit definitions for valid PHY IDs. */
882 #define M88E1111_I_PHY_ID 0x01410CC0
883 #define M88E1112_E_PHY_ID 0x01410C90
884 #define I347AT4_E_PHY_ID 0x01410DC0
885 #define IGP03E1000_E_PHY_ID 0x02A80390
886 #define I82580_I_PHY_ID 0x015403A0
887 #define I350_I_PHY_ID 0x015403B0
888 #define M88_VENDOR 0x0141
889 #define I210_I_PHY_ID 0x01410C00
890 #define M88E1543_E_PHY_ID 0x01410EA0
891 #define M88E1512_E_PHY_ID 0x01410DD0
892 #define BCM54616_E_PHY_ID 0x03625D10
894 /* M88E1000 Specific Registers */
895 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
896 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
897 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
899 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
900 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
902 /* M88E1000 PHY Specific Control Register */
903 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
904 /* 1=CLK125 low, 0=CLK125 toggling */
905 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
906 /* Manual MDI configuration */
907 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
908 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
909 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
910 /* Auto crossover enabled all speeds */
911 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
912 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
913 * 0=Normal 10BASE-T Rx Threshold
915 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
916 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
918 /* M88E1000 PHY Specific Status Register */
919 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
920 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
921 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
928 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
929 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
930 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
932 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
934 /* M88E1000 Extended PHY Specific Control Register */
935 /* 1 = Lost lock detect enabled.
936 * Will assert lost lock and bring
937 * link down if idle not seen
938 * within 1ms in 1000BASE-T
940 /* Number of times we will attempt to autonegotiate before downshifting if we
943 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
944 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
945 /* Number of times we will attempt to autonegotiate before downshifting if we
948 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
949 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
950 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
952 /* Intel i347-AT4 Registers */
954 #define I347AT4_PCDL0 0x10 /* Pair 0 PHY Cable Diagnostics Length */
955 #define I347AT4_PCDL1 0x11 /* Pair 1 PHY Cable Diagnostics Length */
956 #define I347AT4_PCDL2 0x12 /* Pair 2 PHY Cable Diagnostics Length */
957 #define I347AT4_PCDL3 0x13 /* Pair 3 PHY Cable Diagnostics Length */
958 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
959 #define I347AT4_PAGE_SELECT 0x16
961 /* i347-AT4 Extended PHY Specific Control Register */
963 /* Number of times we will attempt to autonegotiate before downshifting if we
966 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
967 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
968 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
969 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
970 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
971 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
972 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
973 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
974 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
975 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
977 /* i347-AT4 PHY Cable Diagnostics Control */
978 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
980 /* Marvell 1112 only registers */
981 #define M88E1112_VCT_DSP_DISTANCE 0x001A
983 /* M88EC018 Rev 2 specific DownShift settings */
984 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
985 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
988 #define E1000_MDIC_DATA_MASK 0x0000FFFF
989 #define E1000_MDIC_REG_MASK 0x001F0000
990 #define E1000_MDIC_REG_SHIFT 16
991 #define E1000_MDIC_PHY_MASK 0x03E00000
992 #define E1000_MDIC_PHY_SHIFT 21
993 #define E1000_MDIC_OP_WRITE 0x04000000
994 #define E1000_MDIC_OP_READ 0x08000000
995 #define E1000_MDIC_READY 0x10000000
996 #define E1000_MDIC_INT_EN 0x20000000
997 #define E1000_MDIC_ERROR 0x40000000
998 #define E1000_MDIC_DEST 0x80000000
1000 /* Thermal Sensor */
1001 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
1002 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */
1004 /* Energy Efficient Ethernet */
1005 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */
1006 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */
1007 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */
1008 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */
1009 #define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */
1010 #define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */
1011 #define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */
1012 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
1013 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
1014 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
1015 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
1016 #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
1017 #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
1018 #define E1000_M88E1543_EEE_CTRL_1 0x0
1019 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
1020 #define E1000_M88E1543_FIBER_CTRL 0x0
1021 #define E1000_EEE_ADV_DEV_I354 7
1022 #define E1000_EEE_ADV_ADDR_I354 60
1023 #define E1000_EEE_ADV_100_SUPPORTED BIT(1) /* 100BaseTx EEE Supported */
1024 #define E1000_EEE_ADV_1000_SUPPORTED BIT(2) /* 1000BaseT EEE Supported */
1025 #define E1000_PCS_STATUS_DEV_I354 3
1026 #define E1000_PCS_STATUS_ADDR_I354 1
1027 #define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */
1028 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
1029 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
1031 /* SerDes Control */
1032 #define E1000_GEN_CTL_READY 0x80000000
1033 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1034 #define E1000_GEN_POLL_TIMEOUT 640
1036 #define E1000_VFTA_ENTRY_SHIFT 5
1037 #define E1000_VFTA_ENTRY_MASK 0x7F
1038 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
1040 /* DMA Coalescing register fields */
1041 #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power on DMA coal */
1043 /* Tx Rate-Scheduler Config fields */
1044 #define E1000_RTTBCNRC_RS_ENA 0x80000000
1045 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1046 #define E1000_RTTBCNRC_RF_INT_SHIFT 14
1047 #define E1000_RTTBCNRC_RF_INT_MASK \
1048 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1050 #define E1000_VLAPQF_QUEUE_SEL(_n, q_idx) (q_idx << ((_n) * 4))
1051 #define E1000_VLAPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4))
1052 #define E1000_VLAPQF_QUEUE_MASK 0x03
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