drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Huawei HiNIC PCI Express Linux driver
   4  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/types.h>
   9 #include <linux/pci.h>
  10 #include <linux/device.h>
  11 #include <linux/errno.h>
  12 #include <linux/slab.h>
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/log2.h>
  17 #include <linux/err.h>
  18
  19 #include "hinic_hw_if.h"
  20 #include "hinic_hw_eqs.h"
  21 #include "hinic_hw_mgmt.h"
  22 #include "hinic_hw_qp_ctxt.h"
  23 #include "hinic_hw_qp.h"
  24 #include "hinic_hw_io.h"
  25 #include "hinic_hw_dev.h"
  26
  27 #define IO_STATUS_TIMEOUT               100
  28 #define OUTBOUND_STATE_TIMEOUT          100
  29 #define DB_STATE_TIMEOUT                100
  30
  31 #define MAX_IRQS(max_qps, num_aeqs, num_ceqs)   \
  32                  (2 * (max_qps) + (num_aeqs) + (num_ceqs))
  33
  34 #define ADDR_IN_4BYTES(addr)            ((addr) >> 2)
  35
  36 enum intr_type {
  37         INTR_MSIX_TYPE,
  38 };
  39
  40 enum io_status {
  41         IO_STOPPED = 0,
  42         IO_RUNNING = 1,
  43 };
  44
  45 enum hw_ioctxt_set_cmdq_depth {
  46         HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT,
  47 };
  48
  49 /* HW struct */
  50 struct hinic_dev_cap {
  51         u8      status;
  52         u8      version;
  53         u8      rsvd0[6];
  54
  55         u8      rsvd1[5];
  56         u8      intr_type;
  57         u8      rsvd2[66];
  58         u16     max_sqs;
  59         u16     max_rqs;
  60         u8      rsvd3[208];
  61 };
  62
  63 /**
  64  * get_capability - convert device capabilities to NIC capabilities
  65  * @hwdev: the HW device to set and convert device capabilities for
  66  * @dev_cap: device capabilities from FW
  67  *
  68  * Return 0 - Success, negative - Failure
  69  **/
  70 static int get_capability(struct hinic_hwdev *hwdev,
  71                           struct hinic_dev_cap *dev_cap)
  72 {
  73         struct hinic_cap *nic_cap = &hwdev->nic_cap;
  74         int num_aeqs, num_ceqs, num_irqs;
  75
  76         if (!HINIC_IS_PF(hwdev->hwif) && !HINIC_IS_PPF(hwdev->hwif))
  77                 return -EINVAL;
  78
  79         if (dev_cap->intr_type != INTR_MSIX_TYPE)
  80                 return -EFAULT;
  81
  82         num_aeqs = HINIC_HWIF_NUM_AEQS(hwdev->hwif);
  83         num_ceqs = HINIC_HWIF_NUM_CEQS(hwdev->hwif);
  84         num_irqs = HINIC_HWIF_NUM_IRQS(hwdev->hwif);
  85
  86         /* Each QP has its own (SQ + RQ) interrupts */
  87         nic_cap->num_qps = (num_irqs - (num_aeqs + num_ceqs)) / 2;
  88
  89         if (nic_cap->num_qps > HINIC_Q_CTXT_MAX)
  90                 nic_cap->num_qps = HINIC_Q_CTXT_MAX;
  91
  92         nic_cap->max_qps = dev_cap->max_sqs + 1;
  93         if (nic_cap->max_qps != (dev_cap->max_rqs + 1))
  94                 return -EFAULT;
  95
  96         if (nic_cap->num_qps > nic_cap->max_qps)
  97                 nic_cap->num_qps = nic_cap->max_qps;
  98
  99         return 0;
 100 }
 101
 102 /**
 103  * get_cap_from_fw - get device capabilities from FW
 104  * @pfhwdev: the PF HW device to get capabilities for
 105  *
 106  * Return 0 - Success, negative - Failure
 107  **/
 108 static int get_cap_from_fw(struct hinic_pfhwdev *pfhwdev)
 109 {
 110         struct hinic_hwdev *hwdev = &pfhwdev->hwdev;
 111         struct hinic_hwif *hwif = hwdev->hwif;
 112         struct pci_dev *pdev = hwif->pdev;
 113         struct hinic_dev_cap dev_cap;
 114         u16 in_len, out_len;
 115         int err;
 116
 117         in_len = 0;
 118         out_len = sizeof(dev_cap);
 119
 120         err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_CFGM,
 121                                 HINIC_CFG_NIC_CAP, &dev_cap, in_len, &dev_cap,
 122                                 &out_len, HINIC_MGMT_MSG_SYNC);
 123         if (err) {
 124                 dev_err(&pdev->dev, "Failed to get capability from FW\n");
 125                 return err;
 126         }
 127
 128         return get_capability(hwdev, &dev_cap);
 129 }
 130
 131 /**
 132  * get_dev_cap - get device capabilities
 133  * @hwdev: the NIC HW device to get capabilities for
 134  *
 135  * Return 0 - Success, negative - Failure
 136  **/
 137 static int get_dev_cap(struct hinic_hwdev *hwdev)
 138 {
 139         struct hinic_hwif *hwif = hwdev->hwif;
 140         struct pci_dev *pdev = hwif->pdev;
 141         struct hinic_pfhwdev *pfhwdev;
 142         int err;
 143
 144         switch (HINIC_FUNC_TYPE(hwif)) {
 145         case HINIC_PPF:
 146         case HINIC_PF:
 147                 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 148
 149                 err = get_cap_from_fw(pfhwdev);
 150                 if (err) {
 151                         dev_err(&pdev->dev, "Failed to get capability from FW\n");
 152                         return err;
 153                 }
 154                 break;
 155
 156         default:
 157                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 158                 return -EINVAL;
 159         }
 160
 161         return 0;
 162 }
 163
 164 /**
 165  * init_msix - enable the msix and save the entries
 166  * @hwdev: the NIC HW device
 167  *
 168  * Return 0 - Success, negative - Failure
 169  **/
 170 static int init_msix(struct hinic_hwdev *hwdev)
 171 {
 172         struct hinic_hwif *hwif = hwdev->hwif;
 173         struct pci_dev *pdev = hwif->pdev;
 174         int nr_irqs, num_aeqs, num_ceqs;
 175         size_t msix_entries_size;
 176         int i, err;
 177
 178         num_aeqs = HINIC_HWIF_NUM_AEQS(hwif);
 179         num_ceqs = HINIC_HWIF_NUM_CEQS(hwif);
 180         nr_irqs = MAX_IRQS(HINIC_MAX_QPS, num_aeqs, num_ceqs);
 181         if (nr_irqs > HINIC_HWIF_NUM_IRQS(hwif))
 182                 nr_irqs = HINIC_HWIF_NUM_IRQS(hwif);
 183
 184         msix_entries_size = nr_irqs * sizeof(*hwdev->msix_entries);
 185         hwdev->msix_entries = devm_kzalloc(&pdev->dev, msix_entries_size,
 186                                            GFP_KERNEL);
 187         if (!hwdev->msix_entries)
 188                 return -ENOMEM;
 189
 190         for (i = 0; i < nr_irqs; i++)
 191                 hwdev->msix_entries[i].entry = i;
 192
 193         err = pci_enable_msix_exact(pdev, hwdev->msix_entries, nr_irqs);
 194         if (err) {
 195                 dev_err(&pdev->dev, "Failed to enable pci msix\n");
 196                 return err;
 197         }
 198
 199         return 0;
 200 }
 201
 202 /**
 203  * disable_msix - disable the msix
 204  * @hwdev: the NIC HW device
 205  **/
 206 static void disable_msix(struct hinic_hwdev *hwdev)
 207 {
 208         struct hinic_hwif *hwif = hwdev->hwif;
 209         struct pci_dev *pdev = hwif->pdev;
 210
 211         pci_disable_msix(pdev);
 212 }
 213
 214 /**
 215  * hinic_port_msg_cmd - send port msg to mgmt
 216  * @hwdev: the NIC HW device
 217  * @cmd: the port command
 218  * @buf_in: input buffer
 219  * @in_size: input size
 220  * @buf_out: output buffer
 221  * @out_size: returned output size
 222  *
 223  * Return 0 - Success, negative - Failure
 224  **/
 225 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
 226                        void *buf_in, u16 in_size, void *buf_out, u16 *out_size)
 227 {
 228         struct hinic_hwif *hwif = hwdev->hwif;
 229         struct pci_dev *pdev = hwif->pdev;
 230         struct hinic_pfhwdev *pfhwdev;
 231
 232         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 233                 dev_err(&pdev->dev, "unsupported PCI Function type\n");
 234                 return -EINVAL;
 235         }
 236
 237         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 238
 239         return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC, cmd,
 240                                  buf_in, in_size, buf_out, out_size,
 241                                  HINIC_MGMT_MSG_SYNC);
 242 }
 243
 244 /**
 245  * init_fw_ctxt- Init Firmware tables before network mgmt and io operations
 246  * @hwdev: the NIC HW device
 247  *
 248  * Return 0 - Success, negative - Failure
 249  **/
 250 static int init_fw_ctxt(struct hinic_hwdev *hwdev)
 251 {
 252         struct hinic_hwif *hwif = hwdev->hwif;
 253         struct pci_dev *pdev = hwif->pdev;
 254         struct hinic_cmd_fw_ctxt fw_ctxt;
 255         u16 out_size;
 256         int err;
 257
 258         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 259                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 260                 return -EINVAL;
 261         }
 262
 263         fw_ctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 264         fw_ctxt.rx_buf_sz = HINIC_RX_BUF_SZ;
 265
 266         err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_FWCTXT_INIT,
 267                                  &fw_ctxt, sizeof(fw_ctxt),
 268                                  &fw_ctxt, &out_size);
 269         if (err || (out_size != sizeof(fw_ctxt)) || fw_ctxt.status) {
 270                 dev_err(&pdev->dev, "Failed to init FW ctxt, ret = %d\n",
 271                         fw_ctxt.status);
 272                 return -EFAULT;
 273         }
 274
 275         return 0;
 276 }
 277
 278 /**
 279  * set_hw_ioctxt - set the shape of the IO queues in FW
 280  * @hwdev: the NIC HW device
 281  * @rq_depth: rq depth
 282  * @sq_depth: sq depth
 283  *
 284  * Return 0 - Success, negative - Failure
 285  **/
 286 static int set_hw_ioctxt(struct hinic_hwdev *hwdev, unsigned int rq_depth,
 287                          unsigned int sq_depth)
 288 {
 289         struct hinic_hwif *hwif = hwdev->hwif;
 290         struct hinic_cmd_hw_ioctxt hw_ioctxt;
 291         struct pci_dev *pdev = hwif->pdev;
 292         struct hinic_pfhwdev *pfhwdev;
 293
 294         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 295                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 296                 return -EINVAL;
 297         }
 298
 299         hw_ioctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 300         hw_ioctxt.ppf_idx = HINIC_HWIF_PPF_IDX(hwif);
 301
 302         hw_ioctxt.set_cmdq_depth = HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT;
 303         hw_ioctxt.cmdq_depth = 0;
 304
 305         hw_ioctxt.lro_en = 1;
 306
 307         hw_ioctxt.rq_depth  = ilog2(rq_depth);
 308
 309         hw_ioctxt.rx_buf_sz_idx = HINIC_RX_BUF_SZ_IDX;
 310
 311         hw_ioctxt.sq_depth  = ilog2(sq_depth);
 312
 313         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 314
 315         return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM,
 316                                  HINIC_COMM_CMD_HWCTXT_SET,
 317                                  &hw_ioctxt, sizeof(hw_ioctxt), NULL,
 318                                  NULL, HINIC_MGMT_MSG_SYNC);
 319 }
 320
 321 static int wait_for_outbound_state(struct hinic_hwdev *hwdev)
 322 {
 323         enum hinic_outbound_state outbound_state;
 324         struct hinic_hwif *hwif = hwdev->hwif;
 325         struct pci_dev *pdev = hwif->pdev;
 326         unsigned long end;
 327
 328         end = jiffies + msecs_to_jiffies(OUTBOUND_STATE_TIMEOUT);
 329         do {
 330                 outbound_state = hinic_outbound_state_get(hwif);
 331
 332                 if (outbound_state == HINIC_OUTBOUND_ENABLE)
 333                         return 0;
 334
 335                 msleep(20);
 336         } while (time_before(jiffies, end));
 337
 338         dev_err(&pdev->dev, "Wait for OUTBOUND - Timeout\n");
 339         return -EFAULT;
 340 }
 341
 342 static int wait_for_db_state(struct hinic_hwdev *hwdev)
 343 {
 344         struct hinic_hwif *hwif = hwdev->hwif;
 345         struct pci_dev *pdev = hwif->pdev;
 346         enum hinic_db_state db_state;
 347         unsigned long end;
 348
 349         end = jiffies + msecs_to_jiffies(DB_STATE_TIMEOUT);
 350         do {
 351                 db_state = hinic_db_state_get(hwif);
 352
 353                 if (db_state == HINIC_DB_ENABLE)
 354                         return 0;
 355
 356                 msleep(20);
 357         } while (time_before(jiffies, end));
 358
 359         dev_err(&pdev->dev, "Wait for DB - Timeout\n");
 360         return -EFAULT;
 361 }
 362
 363 /**
 364  * clear_io_resource - set the IO resources as not active in the NIC
 365  * @hwdev: the NIC HW device
 366  *
 367  * Return 0 - Success, negative - Failure
 368  **/
 369 static int clear_io_resources(struct hinic_hwdev *hwdev)
 370 {
 371         struct hinic_cmd_clear_io_res cmd_clear_io_res;
 372         struct hinic_hwif *hwif = hwdev->hwif;
 373         struct pci_dev *pdev = hwif->pdev;
 374         struct hinic_pfhwdev *pfhwdev;
 375         int err;
 376
 377         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 378                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 379                 return -EINVAL;
 380         }
 381
 382         /* sleep 100ms to wait for firmware stopping I/O */
 383         msleep(100);
 384
 385         cmd_clear_io_res.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 386
 387         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 388
 389         err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM,
 390                                 HINIC_COMM_CMD_IO_RES_CLEAR, &cmd_clear_io_res,
 391                                 sizeof(cmd_clear_io_res), NULL, NULL,
 392                                 HINIC_MGMT_MSG_SYNC);
 393         if (err) {
 394                 dev_err(&pdev->dev, "Failed to clear IO resources\n");
 395                 return err;
 396         }
 397
 398         return 0;
 399 }
 400
 401 /**
 402  * set_resources_state - set the state of the resources in the NIC
 403  * @hwdev: the NIC HW device
 404  * @state: the state to set
 405  *
 406  * Return 0 - Success, negative - Failure
 407  **/
 408 static int set_resources_state(struct hinic_hwdev *hwdev,
 409                                enum hinic_res_state state)
 410 {
 411         struct hinic_cmd_set_res_state res_state;
 412         struct hinic_hwif *hwif = hwdev->hwif;
 413         struct pci_dev *pdev = hwif->pdev;
 414         struct hinic_pfhwdev *pfhwdev;
 415
 416         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 417                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 418                 return -EINVAL;
 419         }
 420
 421         res_state.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 422         res_state.state = state;
 423
 424         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 425
 426         return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt,
 427                                  HINIC_MOD_COMM,
 428                                  HINIC_COMM_CMD_RES_STATE_SET,
 429                                  &res_state, sizeof(res_state), NULL,
 430                                  NULL, HINIC_MGMT_MSG_SYNC);
 431 }
 432
 433 /**
 434  * get_base_qpn - get the first qp number
 435  * @hwdev: the NIC HW device
 436  * @base_qpn: returned qp number
 437  *
 438  * Return 0 - Success, negative - Failure
 439  **/
 440 static int get_base_qpn(struct hinic_hwdev *hwdev, u16 *base_qpn)
 441 {
 442         struct hinic_cmd_base_qpn cmd_base_qpn;
 443         struct hinic_hwif *hwif = hwdev->hwif;
 444         struct pci_dev *pdev = hwif->pdev;
 445         u16 out_size;
 446         int err;
 447
 448         cmd_base_qpn.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 449
 450         err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_GLOBAL_QPN,
 451                                  &cmd_base_qpn, sizeof(cmd_base_qpn),
 452                                  &cmd_base_qpn, &out_size);
 453         if (err || (out_size != sizeof(cmd_base_qpn)) || cmd_base_qpn.status) {
 454                 dev_err(&pdev->dev, "Failed to get base qpn, status = %d\n",
 455                         cmd_base_qpn.status);
 456                 return -EFAULT;
 457         }
 458
 459         *base_qpn = cmd_base_qpn.qpn;
 460         return 0;
 461 }
 462
 463 /**
 464  * hinic_hwdev_ifup - Preparing the HW for passing IO
 465  * @hwdev: the NIC HW device
 466  *
 467  * Return 0 - Success, negative - Failure
 468  **/
 469 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev)
 470 {
 471         struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
 472         struct hinic_cap *nic_cap = &hwdev->nic_cap;
 473         struct hinic_hwif *hwif = hwdev->hwif;
 474         int err, num_aeqs, num_ceqs, num_qps;
 475         struct msix_entry *ceq_msix_entries;
 476         struct msix_entry *sq_msix_entries;
 477         struct msix_entry *rq_msix_entries;
 478         struct pci_dev *pdev = hwif->pdev;
 479         u16 base_qpn;
 480
 481         err = get_base_qpn(hwdev, &base_qpn);
 482         if (err) {
 483                 dev_err(&pdev->dev, "Failed to get global base qp number\n");
 484                 return err;
 485         }
 486
 487         num_aeqs = HINIC_HWIF_NUM_AEQS(hwif);
 488         num_ceqs = HINIC_HWIF_NUM_CEQS(hwif);
 489
 490         ceq_msix_entries = &hwdev->msix_entries[num_aeqs];
 491
 492         err = hinic_io_init(func_to_io, hwif, nic_cap->max_qps, num_ceqs,
 493                             ceq_msix_entries);
 494         if (err) {
 495                 dev_err(&pdev->dev, "Failed to init IO channel\n");
 496                 return err;
 497         }
 498
 499         num_qps = nic_cap->num_qps;
 500         sq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs];
 501         rq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs + num_qps];
 502
 503         err = hinic_io_create_qps(func_to_io, base_qpn, num_qps,
 504                                   sq_msix_entries, rq_msix_entries);
 505         if (err) {
 506                 dev_err(&pdev->dev, "Failed to create QPs\n");
 507                 goto err_create_qps;
 508         }
 509
 510         err = wait_for_db_state(hwdev);
 511         if (err) {
 512                 dev_warn(&pdev->dev, "db - disabled, try again\n");
 513                 hinic_db_state_set(hwif, HINIC_DB_ENABLE);
 514         }
 515
 516         err = set_hw_ioctxt(hwdev, HINIC_SQ_DEPTH, HINIC_RQ_DEPTH);
 517         if (err) {
 518                 dev_err(&pdev->dev, "Failed to set HW IO ctxt\n");
 519                 goto err_hw_ioctxt;
 520         }
 521
 522         return 0;
 523
 524 err_hw_ioctxt:
 525         hinic_io_destroy_qps(func_to_io, num_qps);
 526
 527 err_create_qps:
 528         hinic_io_free(func_to_io);
 529         return err;
 530 }
 531
 532 /**
 533  * hinic_hwdev_ifdown - Closing the HW for passing IO
 534  * @hwdev: the NIC HW device
 535  *
 536  **/
 537 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev)
 538 {
 539         struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
 540         struct hinic_cap *nic_cap = &hwdev->nic_cap;
 541
 542         clear_io_resources(hwdev);
 543
 544         hinic_io_destroy_qps(func_to_io, nic_cap->num_qps);
 545         hinic_io_free(func_to_io);
 546 }
 547
 548 /**
 549  * hinic_hwdev_cb_register - register callback handler for MGMT events
 550  * @hwdev: the NIC HW device
 551  * @cmd: the mgmt event
 552  * @handle: private data for the handler
 553  * @handler: event handler
 554  **/
 555 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
 556                              enum hinic_mgmt_msg_cmd cmd, void *handle,
 557                              void (*handler)(void *handle, void *buf_in,
 558                                              u16 in_size, void *buf_out,
 559                                              u16 *out_size))
 560 {
 561         struct hinic_hwif *hwif = hwdev->hwif;
 562         struct pci_dev *pdev = hwif->pdev;
 563         struct hinic_pfhwdev *pfhwdev;
 564         struct hinic_nic_cb *nic_cb;
 565         u8 cmd_cb;
 566
 567         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 568                 dev_err(&pdev->dev, "unsupported PCI Function type\n");
 569                 return;
 570         }
 571
 572         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 573
 574         cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE;
 575         nic_cb = &pfhwdev->nic_cb[cmd_cb];
 576
 577         nic_cb->handler = handler;
 578         nic_cb->handle = handle;
 579         nic_cb->cb_state = HINIC_CB_ENABLED;
 580 }
 581
 582 /**
 583  * hinic_hwdev_cb_unregister - unregister callback handler for MGMT events
 584  * @hwdev: the NIC HW device
 585  * @cmd: the mgmt event
 586  **/
 587 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
 588                                enum hinic_mgmt_msg_cmd cmd)
 589 {
 590         struct hinic_hwif *hwif = hwdev->hwif;
 591         struct pci_dev *pdev = hwif->pdev;
 592         struct hinic_pfhwdev *pfhwdev;
 593         struct hinic_nic_cb *nic_cb;
 594         u8 cmd_cb;
 595
 596         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 597                 dev_err(&pdev->dev, "unsupported PCI Function type\n");
 598                 return;
 599         }
 600
 601         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 602
 603         cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE;
 604         nic_cb = &pfhwdev->nic_cb[cmd_cb];
 605
 606         nic_cb->cb_state &= ~HINIC_CB_ENABLED;
 607
 608         while (nic_cb->cb_state & HINIC_CB_RUNNING)
 609                 schedule();
 610
 611         nic_cb->handler = NULL;
 612 }
 613
 614 /**
 615  * nic_mgmt_msg_handler - nic mgmt event handler
 616  * @handle: private data for the handler
 617  * @buf_in: input buffer
 618  * @in_size: input size
 619  * @buf_out: output buffer
 620  * @out_size: returned output size
 621  **/
 622 static void nic_mgmt_msg_handler(void *handle, u8 cmd, void *buf_in,
 623                                  u16 in_size, void *buf_out, u16 *out_size)
 624 {
 625         struct hinic_pfhwdev *pfhwdev = handle;
 626         enum hinic_cb_state cb_state;
 627         struct hinic_nic_cb *nic_cb;
 628         struct hinic_hwdev *hwdev;
 629         struct hinic_hwif *hwif;
 630         struct pci_dev *pdev;
 631         u8 cmd_cb;
 632
 633         hwdev = &pfhwdev->hwdev;
 634         hwif = hwdev->hwif;
 635         pdev = hwif->pdev;
 636
 637         if ((cmd < HINIC_MGMT_MSG_CMD_BASE) ||
 638             (cmd >= HINIC_MGMT_MSG_CMD_MAX)) {
 639                 dev_err(&pdev->dev, "unknown L2NIC event, cmd = %d\n", cmd);
 640                 return;
 641         }
 642
 643         cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE;
 644
 645         nic_cb = &pfhwdev->nic_cb[cmd_cb];
 646
 647         cb_state = cmpxchg(&nic_cb->cb_state,
 648                            HINIC_CB_ENABLED,
 649                            HINIC_CB_ENABLED | HINIC_CB_RUNNING);
 650
 651         if ((cb_state == HINIC_CB_ENABLED) && (nic_cb->handler))
 652                 nic_cb->handler(nic_cb->handle, buf_in,
 653                                 in_size, buf_out, out_size);
 654         else
 655                 dev_err(&pdev->dev, "Unhandled NIC Event %d\n", cmd);
 656
 657         nic_cb->cb_state &= ~HINIC_CB_RUNNING;
 658 }
 659
 660 /**
 661  * init_pfhwdev - Initialize the extended components of PF
 662  * @pfhwdev: the HW device for PF
 663  *
 664  * Return 0 - success, negative - failure
 665  **/
 666 static int init_pfhwdev(struct hinic_pfhwdev *pfhwdev)
 667 {
 668         struct hinic_hwdev *hwdev = &pfhwdev->hwdev;
 669         struct hinic_hwif *hwif = hwdev->hwif;
 670         struct pci_dev *pdev = hwif->pdev;
 671         int err;
 672
 673         err = hinic_pf_to_mgmt_init(&pfhwdev->pf_to_mgmt, hwif);
 674         if (err) {
 675                 dev_err(&pdev->dev, "Failed to initialize PF to MGMT channel\n");
 676                 return err;
 677         }
 678
 679         hinic_register_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC,
 680                                    pfhwdev, nic_mgmt_msg_handler);
 681
 682         hinic_set_pf_action(hwif, HINIC_PF_MGMT_ACTIVE);
 683         return 0;
 684 }
 685
 686 /**
 687  * free_pfhwdev - Free the extended components of PF
 688  * @pfhwdev: the HW device for PF
 689  **/
 690 static void free_pfhwdev(struct hinic_pfhwdev *pfhwdev)
 691 {
 692         struct hinic_hwdev *hwdev = &pfhwdev->hwdev;
 693
 694         hinic_set_pf_action(hwdev->hwif, HINIC_PF_MGMT_INIT);
 695
 696         hinic_unregister_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC);
 697
 698         hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt);
 699 }
 700
 701 /**
 702  * hinic_init_hwdev - Initialize the NIC HW
 703  * @pdev: the NIC pci device
 704  *
 705  * Return initialized NIC HW device
 706  *
 707  * Initialize the NIC HW device and return a pointer to it
 708  **/
 709 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev)
 710 {
 711         struct hinic_pfhwdev *pfhwdev;
 712         struct hinic_hwdev *hwdev;
 713         struct hinic_hwif *hwif;
 714         int err, num_aeqs;
 715
 716         hwif = devm_kzalloc(&pdev->dev, sizeof(*hwif), GFP_KERNEL);
 717         if (!hwif)
 718                 return ERR_PTR(-ENOMEM);
 719
 720         err = hinic_init_hwif(hwif, pdev);
 721         if (err) {
 722                 dev_err(&pdev->dev, "Failed to init HW interface\n");
 723                 return ERR_PTR(err);
 724         }
 725
 726         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 727                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 728                 err = -EFAULT;
 729                 goto err_func_type;
 730         }
 731
 732         pfhwdev = devm_kzalloc(&pdev->dev, sizeof(*pfhwdev), GFP_KERNEL);
 733         if (!pfhwdev) {
 734                 err = -ENOMEM;
 735                 goto err_pfhwdev_alloc;
 736         }
 737
 738         hwdev = &pfhwdev->hwdev;
 739         hwdev->hwif = hwif;
 740
 741         err = init_msix(hwdev);
 742         if (err) {
 743                 dev_err(&pdev->dev, "Failed to init msix\n");
 744                 goto err_init_msix;
 745         }
 746
 747         err = wait_for_outbound_state(hwdev);
 748         if (err) {
 749                 dev_warn(&pdev->dev, "outbound - disabled, try again\n");
 750                 hinic_outbound_state_set(hwif, HINIC_OUTBOUND_ENABLE);
 751         }
 752
 753         num_aeqs = HINIC_HWIF_NUM_AEQS(hwif);
 754
 755         err = hinic_aeqs_init(&hwdev->aeqs, hwif, num_aeqs,
 756                               HINIC_DEFAULT_AEQ_LEN, HINIC_EQ_PAGE_SIZE,
 757                               hwdev->msix_entries);
 758         if (err) {
 759                 dev_err(&pdev->dev, "Failed to init async event queues\n");
 760                 goto err_aeqs_init;
 761         }
 762
 763         err = init_pfhwdev(pfhwdev);
 764         if (err) {
 765                 dev_err(&pdev->dev, "Failed to init PF HW device\n");
 766                 goto err_init_pfhwdev;
 767         }
 768
 769         err = get_dev_cap(hwdev);
 770         if (err) {
 771                 dev_err(&pdev->dev, "Failed to get device capabilities\n");
 772                 goto err_dev_cap;
 773         }
 774
 775         err = init_fw_ctxt(hwdev);
 776         if (err) {
 777                 dev_err(&pdev->dev, "Failed to init function table\n");
 778                 goto err_init_fw_ctxt;
 779         }
 780
 781         err = set_resources_state(hwdev, HINIC_RES_ACTIVE);
 782         if (err) {
 783                 dev_err(&pdev->dev, "Failed to set resources state\n");
 784                 goto err_resources_state;
 785         }
 786
 787         return hwdev;
 788
 789 err_resources_state:
 790 err_init_fw_ctxt:
 791 err_dev_cap:
 792         free_pfhwdev(pfhwdev);
 793
 794 err_init_pfhwdev:
 795         hinic_aeqs_free(&hwdev->aeqs);
 796
 797 err_aeqs_init:
 798         disable_msix(hwdev);
 799
 800 err_init_msix:
 801 err_pfhwdev_alloc:
 802 err_func_type:
 803         hinic_free_hwif(hwif);
 804         return ERR_PTR(err);
 805 }
 806
 807 /**
 808  * hinic_free_hwdev - Free the NIC HW device
 809  * @hwdev: the NIC HW device
 810  **/
 811 void hinic_free_hwdev(struct hinic_hwdev *hwdev)
 812 {
 813         struct hinic_pfhwdev *pfhwdev = container_of(hwdev,
 814                                                      struct hinic_pfhwdev,
 815                                                      hwdev);
 816
 817         set_resources_state(hwdev, HINIC_RES_CLEAN);
 818
 819         free_pfhwdev(pfhwdev);
 820
 821         hinic_aeqs_free(&hwdev->aeqs);
 822
 823         disable_msix(hwdev);
 824
 825         hinic_free_hwif(hwdev->hwif);
 826 }
 827
 828 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev)
 829 {
 830         struct hinic_cap *nic_cap = &hwdev->nic_cap;
 831
 832         return nic_cap->max_qps;
 833 }
 834
 835 /**
 836  * hinic_hwdev_num_qps - return the number QPs available for use
 837  * @hwdev: the NIC HW device
 838  *
 839  * Return number QPs available for use
 840  **/
 841 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev)
 842 {
 843         struct hinic_cap *nic_cap = &hwdev->nic_cap;
 844
 845         return nic_cap->num_qps;
 846 }
 847
 848 /**
 849  * hinic_hwdev_get_sq - get SQ
 850  * @hwdev: the NIC HW device
 851  * @i: the position of the SQ
 852  *
 853  * Return: the SQ in the i position
 854  **/
 855 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i)
 856 {
 857         struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
 858         struct hinic_qp *qp = &func_to_io->qps[i];
 859
 860         if (i >= hinic_hwdev_num_qps(hwdev))
 861                 return NULL;
 862
 863         return &qp->sq;
 864 }
 865
 866 /**
 867  * hinic_hwdev_get_sq - get RQ
 868  * @hwdev: the NIC HW device
 869  * @i: the position of the RQ
 870  *
 871  * Return: the RQ in the i position
 872  **/
 873 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i)
 874 {
 875         struct hinic_func_to_io *func_to_io = &hwdev->func_to_io;
 876         struct hinic_qp *qp = &func_to_io->qps[i];
 877
 878         if (i >= hinic_hwdev_num_qps(hwdev))
 879                 return NULL;
 880
 881         return &qp->rq;
 882 }
 883
 884 /**
 885  * hinic_hwdev_msix_cnt_set - clear message attribute counters for msix entry
 886  * @hwdev: the NIC HW device
 887  * @msix_index: msix_index
 888  *
 889  * Return 0 - Success, negative - Failure
 890  **/
 891 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index)
 892 {
 893         return hinic_msix_attr_cnt_clear(hwdev->hwif, msix_index);
 894 }
 895
 896 /**
 897  * hinic_hwdev_msix_set - set message attribute for msix entry
 898  * @hwdev: the NIC HW device
 899  * @msix_index: msix_index
 900  * @pending_limit: the maximum pending interrupt events (unit 8)
 901  * @coalesc_timer: coalesc period for interrupt (unit 8 us)
 902  * @lli_timer: replenishing period for low latency credit (unit 8 us)
 903  * @lli_credit_limit: maximum credits for low latency msix messages (unit 8)
 904  * @resend_timer: maximum wait for resending msix (unit coalesc period)
 905  *
 906  * Return 0 - Success, negative - Failure
 907  **/
 908 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
 909                          u8 pending_limit, u8 coalesc_timer,
 910                          u8 lli_timer_cfg, u8 lli_credit_limit,
 911                          u8 resend_timer)
 912 {
 913         return hinic_msix_attr_set(hwdev->hwif, msix_index,
 914                                    pending_limit, coalesc_timer,
 915                                    lli_timer_cfg, lli_credit_limit,
 916                                    resend_timer);
 917 }
 918
 919 /**
 920  * hinic_hwdev_hw_ci_addr_set - set cons idx addr and attributes in HW for sq
 921  * @hwdev: the NIC HW device
 922  * @sq: send queue
 923  * @pending_limit: the maximum pending update ci events (unit 8)
 924  * @coalesc_timer: coalesc period for update ci (unit 8 us)
 925  *
 926  * Return 0 - Success, negative - Failure
 927  **/
 928 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
 929                                u8 pending_limit, u8 coalesc_timer)
 930 {
 931         struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq);
 932         struct hinic_hwif *hwif = hwdev->hwif;
 933         struct pci_dev *pdev = hwif->pdev;
 934         struct hinic_pfhwdev *pfhwdev;
 935         struct hinic_cmd_hw_ci hw_ci;
 936
 937         if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) {
 938                 dev_err(&pdev->dev, "Unsupported PCI Function type\n");
 939                 return -EINVAL;
 940         }
 941
 942         hw_ci.dma_attr_off  = 0;
 943         hw_ci.pending_limit = pending_limit;
 944         hw_ci.coalesc_timer = coalesc_timer;
 945
 946         hw_ci.msix_en = 1;
 947         hw_ci.msix_entry_idx = sq->msix_entry;
 948
 949         hw_ci.func_idx = HINIC_HWIF_FUNC_IDX(hwif);
 950
 951         hw_ci.sq_id = qp->q_id;
 952
 953         hw_ci.ci_addr = ADDR_IN_4BYTES(sq->hw_ci_dma_addr);
 954
 955         pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev);
 956         return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt,
 957                                  HINIC_MOD_COMM,
 958                                  HINIC_COMM_CMD_SQ_HI_CI_SET,
 959                                  &hw_ci, sizeof(hw_ci), NULL,
 960                                  NULL, HINIC_MGMT_MSG_SYNC);
 961 }
 962
 963 /**
 964  * hinic_hwdev_set_msix_state- set msix state
 965  * @hwdev: the NIC HW device
 966  * @msix_index: IRQ corresponding index number
 967  * @flag: msix state
 968  *
 969  **/
 970 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
 971                                 enum hinic_msix_state flag)
 972 {
 973         hinic_set_msix_state(hwdev->hwif, msix_index, flag);
 974 }