drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F) {
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201                 adap->flags &= ~CXGB4_FW_OK;
 202         }
 203 }
 204
 205 /*
 206  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 207  */
 208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 209                          u32 mbox_addr)
 210 {
 211         for ( ; nflit; nflit--, mbox_addr += 8)
 212                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 213 }
 214
 215 /*
 216  * Handle a FW assertion reported in a mailbox.
 217  */
 218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 219 {
 220         struct fw_debug_cmd asrt;
 221
 222         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 223         dev_alert(adap->pdev_dev,
 224                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 225                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 226                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 227 }
 228
 229 /**
 230  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 231  *      @adapter: the adapter
 232  *      @cmd: the Firmware Mailbox Command or Reply
 233  *      @size: command length in bytes
 234  *      @access: the time (ms) needed to access the Firmware Mailbox
 235  *      @execute: the time (ms) the command spent being executed
 236  */
 237 static void t4_record_mbox(struct adapter *adapter,
 238                            const __be64 *cmd, unsigned int size,
 239                            int access, int execute)
 240 {
 241         struct mbox_cmd_log *log = adapter->mbox_log;
 242         struct mbox_cmd *entry;
 243         int i;
 244
 245         entry = mbox_cmd_log_entry(log, log->cursor++);
 246         if (log->cursor == log->size)
 247                 log->cursor = 0;
 248
 249         for (i = 0; i < size / 8; i++)
 250                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 251         while (i < MBOX_LEN / 8)
 252                 entry->cmd[i++] = 0;
 253         entry->timestamp = jiffies;
 254         entry->seqno = log->seqno++;
 255         entry->access = access;
 256         entry->execute = execute;
 257 }
 258
 259 /**
 260  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 261  *      @adap: the adapter
 262  *      @mbox: index of the mailbox to use
 263  *      @cmd: the command to write
 264  *      @size: command length in bytes
 265  *      @rpl: where to optionally store the reply
 266  *      @sleep_ok: if true we may sleep while awaiting command completion
 267  *      @timeout: time to wait for command to finish before timing out
 268  *
 269  *      Sends the given command to FW through the selected mailbox and waits
 270  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 271  *      store the FW's reply to the command.  The command and its optional
 272  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 273  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 274  *      the response.  If sleeping is allowed we use progressive backoff
 275  *      otherwise we spin.
 276  *
 277  *      The return value is 0 on success or a negative errno on failure.  A
 278  *      failure can happen either because we are not able to execute the
 279  *      command or FW executes it but signals an error.  In the latter case
 280  *      the return value is the error code indicated by FW (negated).
 281  */
 282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 283                             int size, void *rpl, bool sleep_ok, int timeout)
 284 {
 285         static const int delay[] = {
 286                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 287         };
 288
 289         struct mbox_list entry;
 290         u16 access = 0;
 291         u16 execute = 0;
 292         u32 v;
 293         u64 res;
 294         int i, ms, delay_idx, ret;
 295         const __be64 *p = cmd;
 296         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 297         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 298         __be64 cmd_rpl[MBOX_LEN / 8];
 299         u32 pcie_fw;
 300
 301         if ((size & 15) || size > MBOX_LEN)
 302                 return -EINVAL;
 303
 304         /*
 305          * If the device is off-line, as in EEH, commands will time out.
 306          * Fail them early so we don't waste time waiting.
 307          */
 308         if (adap->pdev->error_state != pci_channel_io_normal)
 309                 return -EIO;
 310
 311         /* If we have a negative timeout, that implies that we can't sleep. */
 312         if (timeout < 0) {
 313                 sleep_ok = false;
 314                 timeout = -timeout;
 315         }
 316
 317         /* Queue ourselves onto the mailbox access list.  When our entry is at
 318          * the front of the list, we have rights to access the mailbox.  So we
 319          * wait [for a while] till we're at the front [or bail out with an
 320          * EBUSY] ...
 321          */
 322         spin_lock_bh(&adap->mbox_lock);
 323         list_add_tail(&entry.list, &adap->mlist.list);
 324         spin_unlock_bh(&adap->mbox_lock);
 325
 326         delay_idx = 0;
 327         ms = delay[0];
 328
 329         for (i = 0; ; i += ms) {
 330                 /* If we've waited too long, return a busy indication.  This
 331                  * really ought to be based on our initial position in the
 332                  * mailbox access list but this is a start.  We very rarely
 333                  * contend on access to the mailbox ...
 334                  */
 335                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 336                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 337                         spin_lock_bh(&adap->mbox_lock);
 338                         list_del(&entry.list);
 339                         spin_unlock_bh(&adap->mbox_lock);
 340                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 341                         t4_record_mbox(adap, cmd, size, access, ret);
 342                         return ret;
 343                 }
 344
 345                 /* If we're at the head, break out and start the mailbox
 346                  * protocol.
 347                  */
 348                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 349                                      list) == &entry)
 350                         break;
 351
 352                 /* Delay for a bit before checking again ... */
 353                 if (sleep_ok) {
 354                         ms = delay[delay_idx];  /* last element may repeat */
 355                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 356                                 delay_idx++;
 357                         msleep(ms);
 358                 } else {
 359                         mdelay(ms);
 360                 }
 361         }
 362
 363         /* Loop trying to get ownership of the mailbox.  Return an error
 364          * if we can't gain ownership.
 365          */
 366         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 368                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 369         if (v != MBOX_OWNER_DRV) {
 370                 spin_lock_bh(&adap->mbox_lock);
 371                 list_del(&entry.list);
 372                 spin_unlock_bh(&adap->mbox_lock);
 373                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 374                 t4_record_mbox(adap, cmd, size, access, ret);
 375                 return ret;
 376         }
 377
 378         /* Copy in the new mailbox command and send it on its way ... */
 379         t4_record_mbox(adap, cmd, size, access, 0);
 380         for (i = 0; i < size; i += 8)
 381                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 382
 383         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 384         t4_read_reg(adap, ctl_reg);          /* flush write */
 385
 386         delay_idx = 0;
 387         ms = delay[0];
 388
 389         for (i = 0;
 390              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 391              i < timeout;
 392              i += ms) {
 393                 if (sleep_ok) {
 394                         ms = delay[delay_idx];  /* last element may repeat */
 395                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 396                                 delay_idx++;
 397                         msleep(ms);
 398                 } else
 399                         mdelay(ms);
 400
 401                 v = t4_read_reg(adap, ctl_reg);
 402                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 403                         if (!(v & MBMSGVALID_F)) {
 404                                 t4_write_reg(adap, ctl_reg, 0);
 405                                 continue;
 406                         }
 407
 408                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 409                         res = be64_to_cpu(cmd_rpl[0]);
 410
 411                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 412                                 fw_asrt(adap, data_reg);
 413                                 res = FW_CMD_RETVAL_V(EIO);
 414                         } else if (rpl) {
 415                                 memcpy(rpl, cmd_rpl, size);
 416                         }
 417
 418                         t4_write_reg(adap, ctl_reg, 0);
 419
 420                         execute = i + ms;
 421                         t4_record_mbox(adap, cmd_rpl,
 422                                        MBOX_LEN, access, execute);
 423                         spin_lock_bh(&adap->mbox_lock);
 424                         list_del(&entry.list);
 425                         spin_unlock_bh(&adap->mbox_lock);
 426                         return -FW_CMD_RETVAL_G((int)res);
 427                 }
 428         }
 429
 430         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 431         t4_record_mbox(adap, cmd, size, access, ret);
 432         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 433                 *(const u8 *)cmd, mbox);
 434         t4_report_fw_error(adap);
 435         spin_lock_bh(&adap->mbox_lock);
 436         list_del(&entry.list);
 437         spin_unlock_bh(&adap->mbox_lock);
 438         t4_fatal_err(adap);
 439         return ret;
 440 }
 441
 442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 443                     void *rpl, bool sleep_ok)
 444 {
 445         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 446                                        FW_CMD_MAX_TIMEOUT);
 447 }
 448
 449 static int t4_edc_err_read(struct adapter *adap, int idx)
 450 {
 451         u32 edc_ecc_err_addr_reg;
 452         u32 rdata_reg;
 453
 454         if (is_t4(adap->params.chip)) {
 455                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 456                 return 0;
 457         }
 458         if (idx != 0 && idx != 1) {
 459                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 460                 return 0;
 461         }
 462
 463         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 464         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 465
 466         CH_WARN(adap,
 467                 "edc%d err addr 0x%x: 0x%x.\n",
 468                 idx, edc_ecc_err_addr_reg,
 469                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 470         CH_WARN(adap,
 471                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 472                 rdata_reg,
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 480                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 481                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 482
 483         return 0;
 484 }
 485
 486 /**
 487  * t4_memory_rw_init - Get memory window relative offset, base, and size.
 488  * @adap: the adapter
 489  * @win: PCI-E Memory Window to use
 490  * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
 491  * @mem_off: memory relative offset with respect to @mtype.
 492  * @mem_base: configured memory base address.
 493  * @mem_aperture: configured memory window aperture.
 494  *
 495  * Get the configured memory window's relative offset, base, and size.
 496  */
 497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
 498                       u32 *mem_base, u32 *mem_aperture)
 499 {
 500         u32 edc_size, mc_size, mem_reg;
 501
 502         /* Offset into the region of memory which is being accessed
 503          * MEM_EDC0 = 0
 504          * MEM_EDC1 = 1
 505          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 506          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 507          * MEM_HMA  = 4
 508          */
 509         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 510         if (mtype == MEM_HMA) {
 511                 *mem_off = 2 * (edc_size * 1024 * 1024);
 512         } else if (mtype != MEM_MC1) {
 513                 *mem_off = (mtype * (edc_size * 1024 * 1024));
 514         } else {
 515                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 516                                                       MA_EXT_MEMORY0_BAR_A));
 517                 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 518         }
 519
 520         /* Each PCI-E Memory Window is programmed with a window size -- or
 521          * "aperture" -- which controls the granularity of its mapping onto
 522          * adapter memory.  We need to grab that aperture in order to know
 523          * how to use the specified window.  The window is also programmed
 524          * with the base address of the Memory Window in BAR0's address
 525          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 526          * the address is relative to BAR0.
 527          */
 528         mem_reg = t4_read_reg(adap,
 529                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 530                                                   win));
 531         /* a dead adapter will return 0xffffffff for PIO reads */
 532         if (mem_reg == 0xffffffff)
 533                 return -ENXIO;
 534
 535         *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 536         *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 537         if (is_t4(adap->params.chip))
 538                 *mem_base -= adap->t4_bar0;
 539
 540         return 0;
 541 }
 542
 543 /**
 544  * t4_memory_update_win - Move memory window to specified address.
 545  * @adap: the adapter
 546  * @win: PCI-E Memory Window to use
 547  * @addr: location to move.
 548  *
 549  * Move memory window to specified address.
 550  */
 551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
 552 {
 553         t4_write_reg(adap,
 554                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 555                      addr);
 556         /* Read it back to ensure that changes propagate before we
 557          * attempt to use the new value.
 558          */
 559         t4_read_reg(adap,
 560                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 561 }
 562
 563 /**
 564  * t4_memory_rw_residual - Read/Write residual data.
 565  * @adap: the adapter
 566  * @off: relative offset within residual to start read/write.
 567  * @addr: address within indicated memory type.
 568  * @buf: host memory buffer
 569  * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 570  *
 571  * Read/Write residual data less than 32-bits.
 572  */
 573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
 574                            int dir)
 575 {
 576         union {
 577                 u32 word;
 578                 char byte[4];
 579         } last;
 580         unsigned char *bp;
 581         int i;
 582
 583         if (dir == T4_MEMORY_READ) {
 584                 last.word = le32_to_cpu((__force __le32)
 585                                         t4_read_reg(adap, addr));
 586                 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
 587                         bp[i] = last.byte[i];
 588         } else {
 589                 last.word = *buf;
 590                 for (i = off; i < 4; i++)
 591                         last.byte[i] = 0;
 592                 t4_write_reg(adap, addr,
 593                              (__force u32)cpu_to_le32(last.word));
 594         }
 595 }
 596
 597 /**
 598  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 599  *      @adap: the adapter
 600  *      @win: PCI-E Memory Window to use
 601  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 602  *      @addr: address within indicated memory type
 603  *      @len: amount of memory to transfer
 604  *      @hbuf: host memory buffer
 605  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 606  *
 607  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 608  *      firmware memory address and host buffer must be aligned on 32-bit
 609  *      boundaries; the length may be arbitrary.  The memory is transferred as
 610  *      a raw byte sequence from/to the firmware's memory.  If this memory
 611  *      contains data structures which contain multi-byte integers, it's the
 612  *      caller's responsibility to perform appropriate byte order conversions.
 613  */
 614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 615                  u32 len, void *hbuf, int dir)
 616 {
 617         u32 pos, offset, resid, memoffset;
 618         u32 win_pf, mem_aperture, mem_base;
 619         u32 *buf;
 620         int ret;
 621
 622         /* Argument sanity checks ...
 623          */
 624         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 625                 return -EINVAL;
 626         buf = (u32 *)hbuf;
 627
 628         /* It's convenient to be able to handle lengths which aren't a
 629          * multiple of 32-bits because we often end up transferring files to
 630          * the firmware.  So we'll handle that by normalizing the length here
 631          * and then handling any residual transfer at the end.
 632          */
 633         resid = len & 0x3;
 634         len -= resid;
 635
 636         ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
 637                                 &mem_aperture);
 638         if (ret)
 639                 return ret;
 640
 641         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 642         addr = addr + memoffset;
 643
 644         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 645
 646         /* Calculate our initial PCI-E Memory Window Position and Offset into
 647          * that Window.
 648          */
 649         pos = addr & ~(mem_aperture - 1);
 650         offset = addr - pos;
 651
 652         /* Set up initial PCI-E Memory Window to cover the start of our
 653          * transfer.
 654          */
 655         t4_memory_update_win(adap, win, pos | win_pf);
 656
 657         /* Transfer data to/from the adapter as long as there's an integral
 658          * number of 32-bit transfers to complete.
 659          *
 660          * A note on Endianness issues:
 661          *
 662          * The "register" reads and writes below from/to the PCI-E Memory
 663          * Window invoke the standard adapter Big-Endian to PCI-E Link
 664          * Little-Endian "swizzel."  As a result, if we have the following
 665          * data in adapter memory:
 666          *
 667          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 668          *     Address:      i+0  i+1  i+2  i+3
 669          *
 670          * Then a read of the adapter memory via the PCI-E Memory Window
 671          * will yield:
 672          *
 673          *     x = readl(i)
 674          *         31                  0
 675          *         [ b3 | b2 | b1 | b0 ]
 676          *
 677          * If this value is stored into local memory on a Little-Endian system
 678          * it will show up correctly in local memory as:
 679          *
 680          *     ( ..., b0, b1, b2, b3, ... )
 681          *
 682          * But on a Big-Endian system, the store will show up in memory
 683          * incorrectly swizzled as:
 684          *
 685          *     ( ..., b3, b2, b1, b0, ... )
 686          *
 687          * So we need to account for this in the reads and writes to the
 688          * PCI-E Memory Window below by undoing the register read/write
 689          * swizzels.
 690          */
 691         while (len > 0) {
 692                 if (dir == T4_MEMORY_READ)
 693                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 694                                                 mem_base + offset));
 695                 else
 696                         t4_write_reg(adap, mem_base + offset,
 697                                      (__force u32)cpu_to_le32(*buf++));
 698                 offset += sizeof(__be32);
 699                 len -= sizeof(__be32);
 700
 701                 /* If we've reached the end of our current window aperture,
 702                  * move the PCI-E Memory Window on to the next.  Note that
 703                  * doing this here after "len" may be 0 allows us to set up
 704                  * the PCI-E Memory Window for a possible final residual
 705                  * transfer below ...
 706                  */
 707                 if (offset == mem_aperture) {
 708                         pos += mem_aperture;
 709                         offset = 0;
 710                         t4_memory_update_win(adap, win, pos | win_pf);
 711                 }
 712         }
 713
 714         /* If the original transfer had a length which wasn't a multiple of
 715          * 32-bits, now's where we need to finish off the transfer of the
 716          * residual amount.  The PCI-E Memory Window has already been moved
 717          * above (if necessary) to cover this final transfer.
 718          */
 719         if (resid)
 720                 t4_memory_rw_residual(adap, resid, mem_base + offset,
 721                                       (u8 *)buf, dir);
 722
 723         return 0;
 724 }
 725
 726 /* Return the specified PCI-E Configuration Space register from our Physical
 727  * Function.  We try first via a Firmware LDST Command since we prefer to let
 728  * the firmware own all of these registers, but if that fails we go for it
 729  * directly ourselves.
 730  */
 731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 732 {
 733         u32 val, ldst_addrspace;
 734
 735         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 736          * retrieve the specified PCI-E Configuration Space register.
 737          */
 738         struct fw_ldst_cmd ldst_cmd;
 739         int ret;
 740
 741         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 742         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 743         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 744                                                FW_CMD_REQUEST_F |
 745                                                FW_CMD_READ_F |
 746                                                ldst_addrspace);
 747         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 748         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 749         ldst_cmd.u.pcie.ctrl_to_fn =
 750                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 751         ldst_cmd.u.pcie.r = reg;
 752
 753         /* If the LDST Command succeeds, return the result, otherwise
 754          * fall through to reading it directly ourselves ...
 755          */
 756         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 757                          &ldst_cmd);
 758         if (ret == 0)
 759                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 760         else
 761                 /* Read the desired Configuration Space register via the PCI-E
 762                  * Backdoor mechanism.
 763                  */
 764                 t4_hw_pci_read_cfg4(adap, reg, &val);
 765         return val;
 766 }
 767
 768 /* Get the window based on base passed to it.
 769  * Window aperture is currently unhandled, but there is no use case for it
 770  * right now
 771  */
 772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 773                          u32 memwin_base)
 774 {
 775         u32 ret;
 776
 777         if (is_t4(adap->params.chip)) {
 778                 u32 bar0;
 779
 780                 /* Truncation intentional: we only read the bottom 32-bits of
 781                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 782                  * mechanism to read BAR0 instead of using
 783                  * pci_resource_start() because we could be operating from
 784                  * within a Virtual Machine which is trapping our accesses to
 785                  * our Configuration Space and we need to set up the PCI-E
 786                  * Memory Window decoders with the actual addresses which will
 787                  * be coming across the PCI-E link.
 788                  */
 789                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 790                 bar0 &= pci_mask;
 791                 adap->t4_bar0 = bar0;
 792
 793                 ret = bar0 + memwin_base;
 794         } else {
 795                 /* For T5, only relative offset inside the PCIe BAR is passed */
 796                 ret = memwin_base;
 797         }
 798         return ret;
 799 }
 800
 801 /* Get the default utility window (win0) used by everyone */
 802 u32 t4_get_util_window(struct adapter *adap)
 803 {
 804         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 805                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 806 }
 807
 808 /* Set up memory window for accessing adapter memory ranges.  (Read
 809  * back MA register to ensure that changes propagate before we attempt
 810  * to use the new values.)
 811  */
 812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 813 {
 814         t4_write_reg(adap,
 815                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 816                      memwin_base | BIR_V(0) |
 817                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 818         t4_read_reg(adap,
 819                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 820 }
 821
 822 /**
 823  *      t4_get_regs_len - return the size of the chips register set
 824  *      @adapter: the adapter
 825  *
 826  *      Returns the size of the chip's BAR0 register space.
 827  */
 828 unsigned int t4_get_regs_len(struct adapter *adapter)
 829 {
 830         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 831
 832         switch (chip_version) {
 833         case CHELSIO_T4:
 834                 return T4_REGMAP_SIZE;
 835
 836         case CHELSIO_T5:
 837         case CHELSIO_T6:
 838                 return T5_REGMAP_SIZE;
 839         }
 840
 841         dev_err(adapter->pdev_dev,
 842                 "Unsupported chip version %d\n", chip_version);
 843         return 0;
 844 }
 845
 846 /**
 847  *      t4_get_regs - read chip registers into provided buffer
 848  *      @adap: the adapter
 849  *      @buf: register buffer
 850  *      @buf_size: size (in bytes) of register buffer
 851  *
 852  *      If the provided register buffer isn't large enough for the chip's
 853  *      full register range, the register dump will be truncated to the
 854  *      register buffer's size.
 855  */
 856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 857 {
 858         static const unsigned int t4_reg_ranges[] = {
 859                 0x1008, 0x1108,
 860                 0x1180, 0x1184,
 861                 0x1190, 0x1194,
 862                 0x11a0, 0x11a4,
 863                 0x11b0, 0x11b4,
 864                 0x11fc, 0x123c,
 865                 0x1300, 0x173c,
 866                 0x1800, 0x18fc,
 867                 0x3000, 0x30d8,
 868                 0x30e0, 0x30e4,
 869                 0x30ec, 0x5910,
 870                 0x5920, 0x5924,
 871                 0x5960, 0x5960,
 872                 0x5968, 0x5968,
 873                 0x5970, 0x5970,
 874                 0x5978, 0x5978,
 875                 0x5980, 0x5980,
 876                 0x5988, 0x5988,
 877                 0x5990, 0x5990,
 878                 0x5998, 0x5998,
 879                 0x59a0, 0x59d4,
 880                 0x5a00, 0x5ae0,
 881                 0x5ae8, 0x5ae8,
 882                 0x5af0, 0x5af0,
 883                 0x5af8, 0x5af8,
 884                 0x6000, 0x6098,
 885                 0x6100, 0x6150,
 886                 0x6200, 0x6208,
 887                 0x6240, 0x6248,
 888                 0x6280, 0x62b0,
 889                 0x62c0, 0x6338,
 890                 0x6370, 0x638c,
 891                 0x6400, 0x643c,
 892                 0x6500, 0x6524,
 893                 0x6a00, 0x6a04,
 894                 0x6a14, 0x6a38,
 895                 0x6a60, 0x6a70,
 896                 0x6a78, 0x6a78,
 897                 0x6b00, 0x6b0c,
 898                 0x6b1c, 0x6b84,
 899                 0x6bf0, 0x6bf8,
 900                 0x6c00, 0x6c0c,
 901                 0x6c1c, 0x6c84,
 902                 0x6cf0, 0x6cf8,
 903                 0x6d00, 0x6d0c,
 904                 0x6d1c, 0x6d84,
 905                 0x6df0, 0x6df8,
 906                 0x6e00, 0x6e0c,
 907                 0x6e1c, 0x6e84,
 908                 0x6ef0, 0x6ef8,
 909                 0x6f00, 0x6f0c,
 910                 0x6f1c, 0x6f84,
 911                 0x6ff0, 0x6ff8,
 912                 0x7000, 0x700c,
 913                 0x701c, 0x7084,
 914                 0x70f0, 0x70f8,
 915                 0x7100, 0x710c,
 916                 0x711c, 0x7184,
 917                 0x71f0, 0x71f8,
 918                 0x7200, 0x720c,
 919                 0x721c, 0x7284,
 920                 0x72f0, 0x72f8,
 921                 0x7300, 0x730c,
 922                 0x731c, 0x7384,
 923                 0x73f0, 0x73f8,
 924                 0x7400, 0x7450,
 925                 0x7500, 0x7530,
 926                 0x7600, 0x760c,
 927                 0x7614, 0x761c,
 928                 0x7680, 0x76cc,
 929                 0x7700, 0x7798,
 930                 0x77c0, 0x77fc,
 931                 0x7900, 0x79fc,
 932                 0x7b00, 0x7b58,
 933                 0x7b60, 0x7b84,
 934                 0x7b8c, 0x7c38,
 935                 0x7d00, 0x7d38,
 936                 0x7d40, 0x7d80,
 937                 0x7d8c, 0x7ddc,
 938                 0x7de4, 0x7e04,
 939                 0x7e10, 0x7e1c,
 940                 0x7e24, 0x7e38,
 941                 0x7e40, 0x7e44,
 942                 0x7e4c, 0x7e78,
 943                 0x7e80, 0x7ea4,
 944                 0x7eac, 0x7edc,
 945                 0x7ee8, 0x7efc,
 946                 0x8dc0, 0x8e04,
 947                 0x8e10, 0x8e1c,
 948                 0x8e30, 0x8e78,
 949                 0x8ea0, 0x8eb8,
 950                 0x8ec0, 0x8f6c,
 951                 0x8fc0, 0x9008,
 952                 0x9010, 0x9058,
 953                 0x9060, 0x9060,
 954                 0x9068, 0x9074,
 955                 0x90fc, 0x90fc,
 956                 0x9400, 0x9408,
 957                 0x9410, 0x9458,
 958                 0x9600, 0x9600,
 959                 0x9608, 0x9638,
 960                 0x9640, 0x96bc,
 961                 0x9800, 0x9808,
 962                 0x9820, 0x983c,
 963                 0x9850, 0x9864,
 964                 0x9c00, 0x9c6c,
 965                 0x9c80, 0x9cec,
 966                 0x9d00, 0x9d6c,
 967                 0x9d80, 0x9dec,
 968                 0x9e00, 0x9e6c,
 969                 0x9e80, 0x9eec,
 970                 0x9f00, 0x9f6c,
 971                 0x9f80, 0x9fec,
 972                 0xd004, 0xd004,
 973                 0xd010, 0xd03c,
 974                 0xdfc0, 0xdfe0,
 975                 0xe000, 0xea7c,
 976                 0xf000, 0x11110,
 977                 0x11118, 0x11190,
 978                 0x19040, 0x1906c,
 979                 0x19078, 0x19080,
 980                 0x1908c, 0x190e4,
 981                 0x190f0, 0x190f8,
 982                 0x19100, 0x19110,
 983                 0x19120, 0x19124,
 984                 0x19150, 0x19194,
 985                 0x1919c, 0x191b0,
 986                 0x191d0, 0x191e8,
 987                 0x19238, 0x1924c,
 988                 0x193f8, 0x1943c,
 989                 0x1944c, 0x19474,
 990                 0x19490, 0x194e0,
 991                 0x194f0, 0x194f8,
 992                 0x19800, 0x19c08,
 993                 0x19c10, 0x19c90,
 994                 0x19ca0, 0x19ce4,
 995                 0x19cf0, 0x19d40,
 996                 0x19d50, 0x19d94,
 997                 0x19da0, 0x19de8,
 998                 0x19df0, 0x19e40,
 999                 0x19e50, 0x19e90,
1000                 0x19ea0, 0x19f4c,
1001                 0x1a000, 0x1a004,
1002                 0x1a010, 0x1a06c,
1003                 0x1a0b0, 0x1a0e4,
1004                 0x1a0ec, 0x1a0f4,
1005                 0x1a100, 0x1a108,
1006                 0x1a114, 0x1a120,
1007                 0x1a128, 0x1a130,
1008                 0x1a138, 0x1a138,
1009                 0x1a190, 0x1a1c4,
1010                 0x1a1fc, 0x1a1fc,
1011                 0x1e040, 0x1e04c,
1012                 0x1e284, 0x1e28c,
1013                 0x1e2c0, 0x1e2c0,
1014                 0x1e2e0, 0x1e2e0,
1015                 0x1e300, 0x1e384,
1016                 0x1e3c0, 0x1e3c8,
1017                 0x1e440, 0x1e44c,
1018                 0x1e684, 0x1e68c,
1019                 0x1e6c0, 0x1e6c0,
1020                 0x1e6e0, 0x1e6e0,
1021                 0x1e700, 0x1e784,
1022                 0x1e7c0, 0x1e7c8,
1023                 0x1e840, 0x1e84c,
1024                 0x1ea84, 0x1ea8c,
1025                 0x1eac0, 0x1eac0,
1026                 0x1eae0, 0x1eae0,
1027                 0x1eb00, 0x1eb84,
1028                 0x1ebc0, 0x1ebc8,
1029                 0x1ec40, 0x1ec4c,
1030                 0x1ee84, 0x1ee8c,
1031                 0x1eec0, 0x1eec0,
1032                 0x1eee0, 0x1eee0,
1033                 0x1ef00, 0x1ef84,
1034                 0x1efc0, 0x1efc8,
1035                 0x1f040, 0x1f04c,
1036                 0x1f284, 0x1f28c,
1037                 0x1f2c0, 0x1f2c0,
1038                 0x1f2e0, 0x1f2e0,
1039                 0x1f300, 0x1f384,
1040                 0x1f3c0, 0x1f3c8,
1041                 0x1f440, 0x1f44c,
1042                 0x1f684, 0x1f68c,
1043                 0x1f6c0, 0x1f6c0,
1044                 0x1f6e0, 0x1f6e0,
1045                 0x1f700, 0x1f784,
1046                 0x1f7c0, 0x1f7c8,
1047                 0x1f840, 0x1f84c,
1048                 0x1fa84, 0x1fa8c,
1049                 0x1fac0, 0x1fac0,
1050                 0x1fae0, 0x1fae0,
1051                 0x1fb00, 0x1fb84,
1052                 0x1fbc0, 0x1fbc8,
1053                 0x1fc40, 0x1fc4c,
1054                 0x1fe84, 0x1fe8c,
1055                 0x1fec0, 0x1fec0,
1056                 0x1fee0, 0x1fee0,
1057                 0x1ff00, 0x1ff84,
1058                 0x1ffc0, 0x1ffc8,
1059                 0x20000, 0x2002c,
1060                 0x20100, 0x2013c,
1061                 0x20190, 0x201a0,
1062                 0x201a8, 0x201b8,
1063                 0x201c4, 0x201c8,
1064                 0x20200, 0x20318,
1065                 0x20400, 0x204b4,
1066                 0x204c0, 0x20528,
1067                 0x20540, 0x20614,
1068                 0x21000, 0x21040,
1069                 0x2104c, 0x21060,
1070                 0x210c0, 0x210ec,
1071                 0x21200, 0x21268,
1072                 0x21270, 0x21284,
1073                 0x212fc, 0x21388,
1074                 0x21400, 0x21404,
1075                 0x21500, 0x21500,
1076                 0x21510, 0x21518,
1077                 0x2152c, 0x21530,
1078                 0x2153c, 0x2153c,
1079                 0x21550, 0x21554,
1080                 0x21600, 0x21600,
1081                 0x21608, 0x2161c,
1082                 0x21624, 0x21628,
1083                 0x21630, 0x21634,
1084                 0x2163c, 0x2163c,
1085                 0x21700, 0x2171c,
1086                 0x21780, 0x2178c,
1087                 0x21800, 0x21818,
1088                 0x21820, 0x21828,
1089                 0x21830, 0x21848,
1090                 0x21850, 0x21854,
1091                 0x21860, 0x21868,
1092                 0x21870, 0x21870,
1093                 0x21878, 0x21898,
1094                 0x218a0, 0x218a8,
1095                 0x218b0, 0x218c8,
1096                 0x218d0, 0x218d4,
1097                 0x218e0, 0x218e8,
1098                 0x218f0, 0x218f0,
1099                 0x218f8, 0x21a18,
1100                 0x21a20, 0x21a28,
1101                 0x21a30, 0x21a48,
1102                 0x21a50, 0x21a54,
1103                 0x21a60, 0x21a68,
1104                 0x21a70, 0x21a70,
1105                 0x21a78, 0x21a98,
1106                 0x21aa0, 0x21aa8,
1107                 0x21ab0, 0x21ac8,
1108                 0x21ad0, 0x21ad4,
1109                 0x21ae0, 0x21ae8,
1110                 0x21af0, 0x21af0,
1111                 0x21af8, 0x21c18,
1112                 0x21c20, 0x21c20,
1113                 0x21c28, 0x21c30,
1114                 0x21c38, 0x21c38,
1115                 0x21c80, 0x21c98,
1116                 0x21ca0, 0x21ca8,
1117                 0x21cb0, 0x21cc8,
1118                 0x21cd0, 0x21cd4,
1119                 0x21ce0, 0x21ce8,
1120                 0x21cf0, 0x21cf0,
1121                 0x21cf8, 0x21d7c,
1122                 0x21e00, 0x21e04,
1123                 0x22000, 0x2202c,
1124                 0x22100, 0x2213c,
1125                 0x22190, 0x221a0,
1126                 0x221a8, 0x221b8,
1127                 0x221c4, 0x221c8,
1128                 0x22200, 0x22318,
1129                 0x22400, 0x224b4,
1130                 0x224c0, 0x22528,
1131                 0x22540, 0x22614,
1132                 0x23000, 0x23040,
1133                 0x2304c, 0x23060,
1134                 0x230c0, 0x230ec,
1135                 0x23200, 0x23268,
1136                 0x23270, 0x23284,
1137                 0x232fc, 0x23388,
1138                 0x23400, 0x23404,
1139                 0x23500, 0x23500,
1140                 0x23510, 0x23518,
1141                 0x2352c, 0x23530,
1142                 0x2353c, 0x2353c,
1143                 0x23550, 0x23554,
1144                 0x23600, 0x23600,
1145                 0x23608, 0x2361c,
1146                 0x23624, 0x23628,
1147                 0x23630, 0x23634,
1148                 0x2363c, 0x2363c,
1149                 0x23700, 0x2371c,
1150                 0x23780, 0x2378c,
1151                 0x23800, 0x23818,
1152                 0x23820, 0x23828,
1153                 0x23830, 0x23848,
1154                 0x23850, 0x23854,
1155                 0x23860, 0x23868,
1156                 0x23870, 0x23870,
1157                 0x23878, 0x23898,
1158                 0x238a0, 0x238a8,
1159                 0x238b0, 0x238c8,
1160                 0x238d0, 0x238d4,
1161                 0x238e0, 0x238e8,
1162                 0x238f0, 0x238f0,
1163                 0x238f8, 0x23a18,
1164                 0x23a20, 0x23a28,
1165                 0x23a30, 0x23a48,
1166                 0x23a50, 0x23a54,
1167                 0x23a60, 0x23a68,
1168                 0x23a70, 0x23a70,
1169                 0x23a78, 0x23a98,
1170                 0x23aa0, 0x23aa8,
1171                 0x23ab0, 0x23ac8,
1172                 0x23ad0, 0x23ad4,
1173                 0x23ae0, 0x23ae8,
1174                 0x23af0, 0x23af0,
1175                 0x23af8, 0x23c18,
1176                 0x23c20, 0x23c20,
1177                 0x23c28, 0x23c30,
1178                 0x23c38, 0x23c38,
1179                 0x23c80, 0x23c98,
1180                 0x23ca0, 0x23ca8,
1181                 0x23cb0, 0x23cc8,
1182                 0x23cd0, 0x23cd4,
1183                 0x23ce0, 0x23ce8,
1184                 0x23cf0, 0x23cf0,
1185                 0x23cf8, 0x23d7c,
1186                 0x23e00, 0x23e04,
1187                 0x24000, 0x2402c,
1188                 0x24100, 0x2413c,
1189                 0x24190, 0x241a0,
1190                 0x241a8, 0x241b8,
1191                 0x241c4, 0x241c8,
1192                 0x24200, 0x24318,
1193                 0x24400, 0x244b4,
1194                 0x244c0, 0x24528,
1195                 0x24540, 0x24614,
1196                 0x25000, 0x25040,
1197                 0x2504c, 0x25060,
1198                 0x250c0, 0x250ec,
1199                 0x25200, 0x25268,
1200                 0x25270, 0x25284,
1201                 0x252fc, 0x25388,
1202                 0x25400, 0x25404,
1203                 0x25500, 0x25500,
1204                 0x25510, 0x25518,
1205                 0x2552c, 0x25530,
1206                 0x2553c, 0x2553c,
1207                 0x25550, 0x25554,
1208                 0x25600, 0x25600,
1209                 0x25608, 0x2561c,
1210                 0x25624, 0x25628,
1211                 0x25630, 0x25634,
1212                 0x2563c, 0x2563c,
1213                 0x25700, 0x2571c,
1214                 0x25780, 0x2578c,
1215                 0x25800, 0x25818,
1216                 0x25820, 0x25828,
1217                 0x25830, 0x25848,
1218                 0x25850, 0x25854,
1219                 0x25860, 0x25868,
1220                 0x25870, 0x25870,
1221                 0x25878, 0x25898,
1222                 0x258a0, 0x258a8,
1223                 0x258b0, 0x258c8,
1224                 0x258d0, 0x258d4,
1225                 0x258e0, 0x258e8,
1226                 0x258f0, 0x258f0,
1227                 0x258f8, 0x25a18,
1228                 0x25a20, 0x25a28,
1229                 0x25a30, 0x25a48,
1230                 0x25a50, 0x25a54,
1231                 0x25a60, 0x25a68,
1232                 0x25a70, 0x25a70,
1233                 0x25a78, 0x25a98,
1234                 0x25aa0, 0x25aa8,
1235                 0x25ab0, 0x25ac8,
1236                 0x25ad0, 0x25ad4,
1237                 0x25ae0, 0x25ae8,
1238                 0x25af0, 0x25af0,
1239                 0x25af8, 0x25c18,
1240                 0x25c20, 0x25c20,
1241                 0x25c28, 0x25c30,
1242                 0x25c38, 0x25c38,
1243                 0x25c80, 0x25c98,
1244                 0x25ca0, 0x25ca8,
1245                 0x25cb0, 0x25cc8,
1246                 0x25cd0, 0x25cd4,
1247                 0x25ce0, 0x25ce8,
1248                 0x25cf0, 0x25cf0,
1249                 0x25cf8, 0x25d7c,
1250                 0x25e00, 0x25e04,
1251                 0x26000, 0x2602c,
1252                 0x26100, 0x2613c,
1253                 0x26190, 0x261a0,
1254                 0x261a8, 0x261b8,
1255                 0x261c4, 0x261c8,
1256                 0x26200, 0x26318,
1257                 0x26400, 0x264b4,
1258                 0x264c0, 0x26528,
1259                 0x26540, 0x26614,
1260                 0x27000, 0x27040,
1261                 0x2704c, 0x27060,
1262                 0x270c0, 0x270ec,
1263                 0x27200, 0x27268,
1264                 0x27270, 0x27284,
1265                 0x272fc, 0x27388,
1266                 0x27400, 0x27404,
1267                 0x27500, 0x27500,
1268                 0x27510, 0x27518,
1269                 0x2752c, 0x27530,
1270                 0x2753c, 0x2753c,
1271                 0x27550, 0x27554,
1272                 0x27600, 0x27600,
1273                 0x27608, 0x2761c,
1274                 0x27624, 0x27628,
1275                 0x27630, 0x27634,
1276                 0x2763c, 0x2763c,
1277                 0x27700, 0x2771c,
1278                 0x27780, 0x2778c,
1279                 0x27800, 0x27818,
1280                 0x27820, 0x27828,
1281                 0x27830, 0x27848,
1282                 0x27850, 0x27854,
1283                 0x27860, 0x27868,
1284                 0x27870, 0x27870,
1285                 0x27878, 0x27898,
1286                 0x278a0, 0x278a8,
1287                 0x278b0, 0x278c8,
1288                 0x278d0, 0x278d4,
1289                 0x278e0, 0x278e8,
1290                 0x278f0, 0x278f0,
1291                 0x278f8, 0x27a18,
1292                 0x27a20, 0x27a28,
1293                 0x27a30, 0x27a48,
1294                 0x27a50, 0x27a54,
1295                 0x27a60, 0x27a68,
1296                 0x27a70, 0x27a70,
1297                 0x27a78, 0x27a98,
1298                 0x27aa0, 0x27aa8,
1299                 0x27ab0, 0x27ac8,
1300                 0x27ad0, 0x27ad4,
1301                 0x27ae0, 0x27ae8,
1302                 0x27af0, 0x27af0,
1303                 0x27af8, 0x27c18,
1304                 0x27c20, 0x27c20,
1305                 0x27c28, 0x27c30,
1306                 0x27c38, 0x27c38,
1307                 0x27c80, 0x27c98,
1308                 0x27ca0, 0x27ca8,
1309                 0x27cb0, 0x27cc8,
1310                 0x27cd0, 0x27cd4,
1311                 0x27ce0, 0x27ce8,
1312                 0x27cf0, 0x27cf0,
1313                 0x27cf8, 0x27d7c,
1314                 0x27e00, 0x27e04,
1315         };
1316
1317         static const unsigned int t5_reg_ranges[] = {
1318                 0x1008, 0x10c0,
1319                 0x10cc, 0x10f8,
1320                 0x1100, 0x1100,
1321                 0x110c, 0x1148,
1322                 0x1180, 0x1184,
1323                 0x1190, 0x1194,
1324                 0x11a0, 0x11a4,
1325                 0x11b0, 0x11b4,
1326                 0x11fc, 0x123c,
1327                 0x1280, 0x173c,
1328                 0x1800, 0x18fc,
1329                 0x3000, 0x3028,
1330                 0x3060, 0x30b0,
1331                 0x30b8, 0x30d8,
1332                 0x30e0, 0x30fc,
1333                 0x3140, 0x357c,
1334                 0x35a8, 0x35cc,
1335                 0x35ec, 0x35ec,
1336                 0x3600, 0x5624,
1337                 0x56cc, 0x56ec,
1338                 0x56f4, 0x5720,
1339                 0x5728, 0x575c,
1340                 0x580c, 0x5814,
1341                 0x5890, 0x589c,
1342                 0x58a4, 0x58ac,
1343                 0x58b8, 0x58bc,
1344                 0x5940, 0x59c8,
1345                 0x59d0, 0x59dc,
1346                 0x59fc, 0x5a18,
1347                 0x5a60, 0x5a70,
1348                 0x5a80, 0x5a9c,
1349                 0x5b94, 0x5bfc,
1350                 0x6000, 0x6020,
1351                 0x6028, 0x6040,
1352                 0x6058, 0x609c,
1353                 0x60a8, 0x614c,
1354                 0x7700, 0x7798,
1355                 0x77c0, 0x78fc,
1356                 0x7b00, 0x7b58,
1357                 0x7b60, 0x7b84,
1358                 0x7b8c, 0x7c54,
1359                 0x7d00, 0x7d38,
1360                 0x7d40, 0x7d80,
1361                 0x7d8c, 0x7ddc,
1362                 0x7de4, 0x7e04,
1363                 0x7e10, 0x7e1c,
1364                 0x7e24, 0x7e38,
1365                 0x7e40, 0x7e44,
1366                 0x7e4c, 0x7e78,
1367                 0x7e80, 0x7edc,
1368                 0x7ee8, 0x7efc,
1369                 0x8dc0, 0x8de0,
1370                 0x8df8, 0x8e04,
1371                 0x8e10, 0x8e84,
1372                 0x8ea0, 0x8f84,
1373                 0x8fc0, 0x9058,
1374                 0x9060, 0x9060,
1375                 0x9068, 0x90f8,
1376                 0x9400, 0x9408,
1377                 0x9410, 0x9470,
1378                 0x9600, 0x9600,
1379                 0x9608, 0x9638,
1380                 0x9640, 0x96f4,
1381                 0x9800, 0x9808,
1382                 0x9820, 0x983c,
1383                 0x9850, 0x9864,
1384                 0x9c00, 0x9c6c,
1385                 0x9c80, 0x9cec,
1386                 0x9d00, 0x9d6c,
1387                 0x9d80, 0x9dec,
1388                 0x9e00, 0x9e6c,
1389                 0x9e80, 0x9eec,
1390                 0x9f00, 0x9f6c,
1391                 0x9f80, 0xa020,
1392                 0xd004, 0xd004,
1393                 0xd010, 0xd03c,
1394                 0xdfc0, 0xdfe0,
1395                 0xe000, 0x1106c,
1396                 0x11074, 0x11088,
1397                 0x1109c, 0x1117c,
1398                 0x11190, 0x11204,
1399                 0x19040, 0x1906c,
1400                 0x19078, 0x19080,
1401                 0x1908c, 0x190e8,
1402                 0x190f0, 0x190f8,
1403                 0x19100, 0x19110,
1404                 0x19120, 0x19124,
1405                 0x19150, 0x19194,
1406                 0x1919c, 0x191b0,
1407                 0x191d0, 0x191e8,
1408                 0x19238, 0x19290,
1409                 0x193f8, 0x19428,
1410                 0x19430, 0x19444,
1411                 0x1944c, 0x1946c,
1412                 0x19474, 0x19474,
1413                 0x19490, 0x194cc,
1414                 0x194f0, 0x194f8,
1415                 0x19c00, 0x19c08,
1416                 0x19c10, 0x19c60,
1417                 0x19c94, 0x19ce4,
1418                 0x19cf0, 0x19d40,
1419                 0x19d50, 0x19d94,
1420                 0x19da0, 0x19de8,
1421                 0x19df0, 0x19e10,
1422                 0x19e50, 0x19e90,
1423                 0x19ea0, 0x19f24,
1424                 0x19f34, 0x19f34,
1425                 0x19f40, 0x19f50,
1426                 0x19f90, 0x19fb4,
1427                 0x19fc4, 0x19fe4,
1428                 0x1a000, 0x1a004,
1429                 0x1a010, 0x1a06c,
1430                 0x1a0b0, 0x1a0e4,
1431                 0x1a0ec, 0x1a0f8,
1432                 0x1a100, 0x1a108,
1433                 0x1a114, 0x1a120,
1434                 0x1a128, 0x1a130,
1435                 0x1a138, 0x1a138,
1436                 0x1a190, 0x1a1c4,
1437                 0x1a1fc, 0x1a1fc,
1438                 0x1e008, 0x1e00c,
1439                 0x1e040, 0x1e044,
1440                 0x1e04c, 0x1e04c,
1441                 0x1e284, 0x1e290,
1442                 0x1e2c0, 0x1e2c0,
1443                 0x1e2e0, 0x1e2e0,
1444                 0x1e300, 0x1e384,
1445                 0x1e3c0, 0x1e3c8,
1446                 0x1e408, 0x1e40c,
1447                 0x1e440, 0x1e444,
1448                 0x1e44c, 0x1e44c,
1449                 0x1e684, 0x1e690,
1450                 0x1e6c0, 0x1e6c0,
1451                 0x1e6e0, 0x1e6e0,
1452                 0x1e700, 0x1e784,
1453                 0x1e7c0, 0x1e7c8,
1454                 0x1e808, 0x1e80c,
1455                 0x1e840, 0x1e844,
1456                 0x1e84c, 0x1e84c,
1457                 0x1ea84, 0x1ea90,
1458                 0x1eac0, 0x1eac0,
1459                 0x1eae0, 0x1eae0,
1460                 0x1eb00, 0x1eb84,
1461                 0x1ebc0, 0x1ebc8,
1462                 0x1ec08, 0x1ec0c,
1463                 0x1ec40, 0x1ec44,
1464                 0x1ec4c, 0x1ec4c,
1465                 0x1ee84, 0x1ee90,
1466                 0x1eec0, 0x1eec0,
1467                 0x1eee0, 0x1eee0,
1468                 0x1ef00, 0x1ef84,
1469                 0x1efc0, 0x1efc8,
1470                 0x1f008, 0x1f00c,
1471                 0x1f040, 0x1f044,
1472                 0x1f04c, 0x1f04c,
1473                 0x1f284, 0x1f290,
1474                 0x1f2c0, 0x1f2c0,
1475                 0x1f2e0, 0x1f2e0,
1476                 0x1f300, 0x1f384,
1477                 0x1f3c0, 0x1f3c8,
1478                 0x1f408, 0x1f40c,
1479                 0x1f440, 0x1f444,
1480                 0x1f44c, 0x1f44c,
1481                 0x1f684, 0x1f690,
1482                 0x1f6c0, 0x1f6c0,
1483                 0x1f6e0, 0x1f6e0,
1484                 0x1f700, 0x1f784,
1485                 0x1f7c0, 0x1f7c8,
1486                 0x1f808, 0x1f80c,
1487                 0x1f840, 0x1f844,
1488                 0x1f84c, 0x1f84c,
1489                 0x1fa84, 0x1fa90,
1490                 0x1fac0, 0x1fac0,
1491                 0x1fae0, 0x1fae0,
1492                 0x1fb00, 0x1fb84,
1493                 0x1fbc0, 0x1fbc8,
1494                 0x1fc08, 0x1fc0c,
1495                 0x1fc40, 0x1fc44,
1496                 0x1fc4c, 0x1fc4c,
1497                 0x1fe84, 0x1fe90,
1498                 0x1fec0, 0x1fec0,
1499                 0x1fee0, 0x1fee0,
1500                 0x1ff00, 0x1ff84,
1501                 0x1ffc0, 0x1ffc8,
1502                 0x30000, 0x30030,
1503                 0x30100, 0x30144,
1504                 0x30190, 0x301a0,
1505                 0x301a8, 0x301b8,
1506                 0x301c4, 0x301c8,
1507                 0x301d0, 0x301d0,
1508                 0x30200, 0x30318,
1509                 0x30400, 0x304b4,
1510                 0x304c0, 0x3052c,
1511                 0x30540, 0x3061c,
1512                 0x30800, 0x30828,
1513                 0x30834, 0x30834,
1514                 0x308c0, 0x30908,
1515                 0x30910, 0x309ac,
1516                 0x30a00, 0x30a14,
1517                 0x30a1c, 0x30a2c,
1518                 0x30a44, 0x30a50,
1519                 0x30a74, 0x30a74,
1520                 0x30a7c, 0x30afc,
1521                 0x30b08, 0x30c24,
1522                 0x30d00, 0x30d00,
1523                 0x30d08, 0x30d14,
1524                 0x30d1c, 0x30d20,
1525                 0x30d3c, 0x30d3c,
1526                 0x30d48, 0x30d50,
1527                 0x31200, 0x3120c,
1528                 0x31220, 0x31220,
1529                 0x31240, 0x31240,
1530                 0x31600, 0x3160c,
1531                 0x31a00, 0x31a1c,
1532                 0x31e00, 0x31e20,
1533                 0x31e38, 0x31e3c,
1534                 0x31e80, 0x31e80,
1535                 0x31e88, 0x31ea8,
1536                 0x31eb0, 0x31eb4,
1537                 0x31ec8, 0x31ed4,
1538                 0x31fb8, 0x32004,
1539                 0x32200, 0x32200,
1540                 0x32208, 0x32240,
1541                 0x32248, 0x32280,
1542                 0x32288, 0x322c0,
1543                 0x322c8, 0x322fc,
1544                 0x32600, 0x32630,
1545                 0x32a00, 0x32abc,
1546                 0x32b00, 0x32b10,
1547                 0x32b20, 0x32b30,
1548                 0x32b40, 0x32b50,
1549                 0x32b60, 0x32b70,
1550                 0x33000, 0x33028,
1551                 0x33030, 0x33048,
1552                 0x33060, 0x33068,
1553                 0x33070, 0x3309c,
1554                 0x330f0, 0x33128,
1555                 0x33130, 0x33148,
1556                 0x33160, 0x33168,
1557                 0x33170, 0x3319c,
1558                 0x331f0, 0x33238,
1559                 0x33240, 0x33240,
1560                 0x33248, 0x33250,
1561                 0x3325c, 0x33264,
1562                 0x33270, 0x332b8,
1563                 0x332c0, 0x332e4,
1564                 0x332f8, 0x33338,
1565                 0x33340, 0x33340,
1566                 0x33348, 0x33350,
1567                 0x3335c, 0x33364,
1568                 0x33370, 0x333b8,
1569                 0x333c0, 0x333e4,
1570                 0x333f8, 0x33428,
1571                 0x33430, 0x33448,
1572                 0x33460, 0x33468,
1573                 0x33470, 0x3349c,
1574                 0x334f0, 0x33528,
1575                 0x33530, 0x33548,
1576                 0x33560, 0x33568,
1577                 0x33570, 0x3359c,
1578                 0x335f0, 0x33638,
1579                 0x33640, 0x33640,
1580                 0x33648, 0x33650,
1581                 0x3365c, 0x33664,
1582                 0x33670, 0x336b8,
1583                 0x336c0, 0x336e4,
1584                 0x336f8, 0x33738,
1585                 0x33740, 0x33740,
1586                 0x33748, 0x33750,
1587                 0x3375c, 0x33764,
1588                 0x33770, 0x337b8,
1589                 0x337c0, 0x337e4,
1590                 0x337f8, 0x337fc,
1591                 0x33814, 0x33814,
1592                 0x3382c, 0x3382c,
1593                 0x33880, 0x3388c,
1594                 0x338e8, 0x338ec,
1595                 0x33900, 0x33928,
1596                 0x33930, 0x33948,
1597                 0x33960, 0x33968,
1598                 0x33970, 0x3399c,
1599                 0x339f0, 0x33a38,
1600                 0x33a40, 0x33a40,
1601                 0x33a48, 0x33a50,
1602                 0x33a5c, 0x33a64,
1603                 0x33a70, 0x33ab8,
1604                 0x33ac0, 0x33ae4,
1605                 0x33af8, 0x33b10,
1606                 0x33b28, 0x33b28,
1607                 0x33b3c, 0x33b50,
1608                 0x33bf0, 0x33c10,
1609                 0x33c28, 0x33c28,
1610                 0x33c3c, 0x33c50,
1611                 0x33cf0, 0x33cfc,
1612                 0x34000, 0x34030,
1613                 0x34100, 0x34144,
1614                 0x34190, 0x341a0,
1615                 0x341a8, 0x341b8,
1616                 0x341c4, 0x341c8,
1617                 0x341d0, 0x341d0,
1618                 0x34200, 0x34318,
1619                 0x34400, 0x344b4,
1620                 0x344c0, 0x3452c,
1621                 0x34540, 0x3461c,
1622                 0x34800, 0x34828,
1623                 0x34834, 0x34834,
1624                 0x348c0, 0x34908,
1625                 0x34910, 0x349ac,
1626                 0x34a00, 0x34a14,
1627                 0x34a1c, 0x34a2c,
1628                 0x34a44, 0x34a50,
1629                 0x34a74, 0x34a74,
1630                 0x34a7c, 0x34afc,
1631                 0x34b08, 0x34c24,
1632                 0x34d00, 0x34d00,
1633                 0x34d08, 0x34d14,
1634                 0x34d1c, 0x34d20,
1635                 0x34d3c, 0x34d3c,
1636                 0x34d48, 0x34d50,
1637                 0x35200, 0x3520c,
1638                 0x35220, 0x35220,
1639                 0x35240, 0x35240,
1640                 0x35600, 0x3560c,
1641                 0x35a00, 0x35a1c,
1642                 0x35e00, 0x35e20,
1643                 0x35e38, 0x35e3c,
1644                 0x35e80, 0x35e80,
1645                 0x35e88, 0x35ea8,
1646                 0x35eb0, 0x35eb4,
1647                 0x35ec8, 0x35ed4,
1648                 0x35fb8, 0x36004,
1649                 0x36200, 0x36200,
1650                 0x36208, 0x36240,
1651                 0x36248, 0x36280,
1652                 0x36288, 0x362c0,
1653                 0x362c8, 0x362fc,
1654                 0x36600, 0x36630,
1655                 0x36a00, 0x36abc,
1656                 0x36b00, 0x36b10,
1657                 0x36b20, 0x36b30,
1658                 0x36b40, 0x36b50,
1659                 0x36b60, 0x36b70,
1660                 0x37000, 0x37028,
1661                 0x37030, 0x37048,
1662                 0x37060, 0x37068,
1663                 0x37070, 0x3709c,
1664                 0x370f0, 0x37128,
1665                 0x37130, 0x37148,
1666                 0x37160, 0x37168,
1667                 0x37170, 0x3719c,
1668                 0x371f0, 0x37238,
1669                 0x37240, 0x37240,
1670                 0x37248, 0x37250,
1671                 0x3725c, 0x37264,
1672                 0x37270, 0x372b8,
1673                 0x372c0, 0x372e4,
1674                 0x372f8, 0x37338,
1675                 0x37340, 0x37340,
1676                 0x37348, 0x37350,
1677                 0x3735c, 0x37364,
1678                 0x37370, 0x373b8,
1679                 0x373c0, 0x373e4,
1680                 0x373f8, 0x37428,
1681                 0x37430, 0x37448,
1682                 0x37460, 0x37468,
1683                 0x37470, 0x3749c,
1684                 0x374f0, 0x37528,
1685                 0x37530, 0x37548,
1686                 0x37560, 0x37568,
1687                 0x37570, 0x3759c,
1688                 0x375f0, 0x37638,
1689                 0x37640, 0x37640,
1690                 0x37648, 0x37650,
1691                 0x3765c, 0x37664,
1692                 0x37670, 0x376b8,
1693                 0x376c0, 0x376e4,
1694                 0x376f8, 0x37738,
1695                 0x37740, 0x37740,
1696                 0x37748, 0x37750,
1697                 0x3775c, 0x37764,
1698                 0x37770, 0x377b8,
1699                 0x377c0, 0x377e4,
1700                 0x377f8, 0x377fc,
1701                 0x37814, 0x37814,
1702                 0x3782c, 0x3782c,
1703                 0x37880, 0x3788c,
1704                 0x378e8, 0x378ec,
1705                 0x37900, 0x37928,
1706                 0x37930, 0x37948,
1707                 0x37960, 0x37968,
1708                 0x37970, 0x3799c,
1709                 0x379f0, 0x37a38,
1710                 0x37a40, 0x37a40,
1711                 0x37a48, 0x37a50,
1712                 0x37a5c, 0x37a64,
1713                 0x37a70, 0x37ab8,
1714                 0x37ac0, 0x37ae4,
1715                 0x37af8, 0x37b10,
1716                 0x37b28, 0x37b28,
1717                 0x37b3c, 0x37b50,
1718                 0x37bf0, 0x37c10,
1719                 0x37c28, 0x37c28,
1720                 0x37c3c, 0x37c50,
1721                 0x37cf0, 0x37cfc,
1722                 0x38000, 0x38030,
1723                 0x38100, 0x38144,
1724                 0x38190, 0x381a0,
1725                 0x381a8, 0x381b8,
1726                 0x381c4, 0x381c8,
1727                 0x381d0, 0x381d0,
1728                 0x38200, 0x38318,
1729                 0x38400, 0x384b4,
1730                 0x384c0, 0x3852c,
1731                 0x38540, 0x3861c,
1732                 0x38800, 0x38828,
1733                 0x38834, 0x38834,
1734                 0x388c0, 0x38908,
1735                 0x38910, 0x389ac,
1736                 0x38a00, 0x38a14,
1737                 0x38a1c, 0x38a2c,
1738                 0x38a44, 0x38a50,
1739                 0x38a74, 0x38a74,
1740                 0x38a7c, 0x38afc,
1741                 0x38b08, 0x38c24,
1742                 0x38d00, 0x38d00,
1743                 0x38d08, 0x38d14,
1744                 0x38d1c, 0x38d20,
1745                 0x38d3c, 0x38d3c,
1746                 0x38d48, 0x38d50,
1747                 0x39200, 0x3920c,
1748                 0x39220, 0x39220,
1749                 0x39240, 0x39240,
1750                 0x39600, 0x3960c,
1751                 0x39a00, 0x39a1c,
1752                 0x39e00, 0x39e20,
1753                 0x39e38, 0x39e3c,
1754                 0x39e80, 0x39e80,
1755                 0x39e88, 0x39ea8,
1756                 0x39eb0, 0x39eb4,
1757                 0x39ec8, 0x39ed4,
1758                 0x39fb8, 0x3a004,
1759                 0x3a200, 0x3a200,
1760                 0x3a208, 0x3a240,
1761                 0x3a248, 0x3a280,
1762                 0x3a288, 0x3a2c0,
1763                 0x3a2c8, 0x3a2fc,
1764                 0x3a600, 0x3a630,
1765                 0x3aa00, 0x3aabc,
1766                 0x3ab00, 0x3ab10,
1767                 0x3ab20, 0x3ab30,
1768                 0x3ab40, 0x3ab50,
1769                 0x3ab60, 0x3ab70,
1770                 0x3b000, 0x3b028,
1771                 0x3b030, 0x3b048,
1772                 0x3b060, 0x3b068,
1773                 0x3b070, 0x3b09c,
1774                 0x3b0f0, 0x3b128,
1775                 0x3b130, 0x3b148,
1776                 0x3b160, 0x3b168,
1777                 0x3b170, 0x3b19c,
1778                 0x3b1f0, 0x3b238,
1779                 0x3b240, 0x3b240,
1780                 0x3b248, 0x3b250,
1781                 0x3b25c, 0x3b264,
1782                 0x3b270, 0x3b2b8,
1783                 0x3b2c0, 0x3b2e4,
1784                 0x3b2f8, 0x3b338,
1785                 0x3b340, 0x3b340,
1786                 0x3b348, 0x3b350,
1787                 0x3b35c, 0x3b364,
1788                 0x3b370, 0x3b3b8,
1789                 0x3b3c0, 0x3b3e4,
1790                 0x3b3f8, 0x3b428,
1791                 0x3b430, 0x3b448,
1792                 0x3b460, 0x3b468,
1793                 0x3b470, 0x3b49c,
1794                 0x3b4f0, 0x3b528,
1795                 0x3b530, 0x3b548,
1796                 0x3b560, 0x3b568,
1797                 0x3b570, 0x3b59c,
1798                 0x3b5f0, 0x3b638,
1799                 0x3b640, 0x3b640,
1800                 0x3b648, 0x3b650,
1801                 0x3b65c, 0x3b664,
1802                 0x3b670, 0x3b6b8,
1803                 0x3b6c0, 0x3b6e4,
1804                 0x3b6f8, 0x3b738,
1805                 0x3b740, 0x3b740,
1806                 0x3b748, 0x3b750,
1807                 0x3b75c, 0x3b764,
1808                 0x3b770, 0x3b7b8,
1809                 0x3b7c0, 0x3b7e4,
1810                 0x3b7f8, 0x3b7fc,
1811                 0x3b814, 0x3b814,
1812                 0x3b82c, 0x3b82c,
1813                 0x3b880, 0x3b88c,
1814                 0x3b8e8, 0x3b8ec,
1815                 0x3b900, 0x3b928,
1816                 0x3b930, 0x3b948,
1817                 0x3b960, 0x3b968,
1818                 0x3b970, 0x3b99c,
1819                 0x3b9f0, 0x3ba38,
1820                 0x3ba40, 0x3ba40,
1821                 0x3ba48, 0x3ba50,
1822                 0x3ba5c, 0x3ba64,
1823                 0x3ba70, 0x3bab8,
1824                 0x3bac0, 0x3bae4,
1825                 0x3baf8, 0x3bb10,
1826                 0x3bb28, 0x3bb28,
1827                 0x3bb3c, 0x3bb50,
1828                 0x3bbf0, 0x3bc10,
1829                 0x3bc28, 0x3bc28,
1830                 0x3bc3c, 0x3bc50,
1831                 0x3bcf0, 0x3bcfc,
1832                 0x3c000, 0x3c030,
1833                 0x3c100, 0x3c144,
1834                 0x3c190, 0x3c1a0,
1835                 0x3c1a8, 0x3c1b8,
1836                 0x3c1c4, 0x3c1c8,
1837                 0x3c1d0, 0x3c1d0,
1838                 0x3c200, 0x3c318,
1839                 0x3c400, 0x3c4b4,
1840                 0x3c4c0, 0x3c52c,
1841                 0x3c540, 0x3c61c,
1842                 0x3c800, 0x3c828,
1843                 0x3c834, 0x3c834,
1844                 0x3c8c0, 0x3c908,
1845                 0x3c910, 0x3c9ac,
1846                 0x3ca00, 0x3ca14,
1847                 0x3ca1c, 0x3ca2c,
1848                 0x3ca44, 0x3ca50,
1849                 0x3ca74, 0x3ca74,
1850                 0x3ca7c, 0x3cafc,
1851                 0x3cb08, 0x3cc24,
1852                 0x3cd00, 0x3cd00,
1853                 0x3cd08, 0x3cd14,
1854                 0x3cd1c, 0x3cd20,
1855                 0x3cd3c, 0x3cd3c,
1856                 0x3cd48, 0x3cd50,
1857                 0x3d200, 0x3d20c,
1858                 0x3d220, 0x3d220,
1859                 0x3d240, 0x3d240,
1860                 0x3d600, 0x3d60c,
1861                 0x3da00, 0x3da1c,
1862                 0x3de00, 0x3de20,
1863                 0x3de38, 0x3de3c,
1864                 0x3de80, 0x3de80,
1865                 0x3de88, 0x3dea8,
1866                 0x3deb0, 0x3deb4,
1867                 0x3dec8, 0x3ded4,
1868                 0x3dfb8, 0x3e004,
1869                 0x3e200, 0x3e200,
1870                 0x3e208, 0x3e240,
1871                 0x3e248, 0x3e280,
1872                 0x3e288, 0x3e2c0,
1873                 0x3e2c8, 0x3e2fc,
1874                 0x3e600, 0x3e630,
1875                 0x3ea00, 0x3eabc,
1876                 0x3eb00, 0x3eb10,
1877                 0x3eb20, 0x3eb30,
1878                 0x3eb40, 0x3eb50,
1879                 0x3eb60, 0x3eb70,
1880                 0x3f000, 0x3f028,
1881                 0x3f030, 0x3f048,
1882                 0x3f060, 0x3f068,
1883                 0x3f070, 0x3f09c,
1884                 0x3f0f0, 0x3f128,
1885                 0x3f130, 0x3f148,
1886                 0x3f160, 0x3f168,
1887                 0x3f170, 0x3f19c,
1888                 0x3f1f0, 0x3f238,
1889                 0x3f240, 0x3f240,
1890                 0x3f248, 0x3f250,
1891                 0x3f25c, 0x3f264,
1892                 0x3f270, 0x3f2b8,
1893                 0x3f2c0, 0x3f2e4,
1894                 0x3f2f8, 0x3f338,
1895                 0x3f340, 0x3f340,
1896                 0x3f348, 0x3f350,
1897                 0x3f35c, 0x3f364,
1898                 0x3f370, 0x3f3b8,
1899                 0x3f3c0, 0x3f3e4,
1900                 0x3f3f8, 0x3f428,
1901                 0x3f430, 0x3f448,
1902                 0x3f460, 0x3f468,
1903                 0x3f470, 0x3f49c,
1904                 0x3f4f0, 0x3f528,
1905                 0x3f530, 0x3f548,
1906                 0x3f560, 0x3f568,
1907                 0x3f570, 0x3f59c,
1908                 0x3f5f0, 0x3f638,
1909                 0x3f640, 0x3f640,
1910                 0x3f648, 0x3f650,
1911                 0x3f65c, 0x3f664,
1912                 0x3f670, 0x3f6b8,
1913                 0x3f6c0, 0x3f6e4,
1914                 0x3f6f8, 0x3f738,
1915                 0x3f740, 0x3f740,
1916                 0x3f748, 0x3f750,
1917                 0x3f75c, 0x3f764,
1918                 0x3f770, 0x3f7b8,
1919                 0x3f7c0, 0x3f7e4,
1920                 0x3f7f8, 0x3f7fc,
1921                 0x3f814, 0x3f814,
1922                 0x3f82c, 0x3f82c,
1923                 0x3f880, 0x3f88c,
1924                 0x3f8e8, 0x3f8ec,
1925                 0x3f900, 0x3f928,
1926                 0x3f930, 0x3f948,
1927                 0x3f960, 0x3f968,
1928                 0x3f970, 0x3f99c,
1929                 0x3f9f0, 0x3fa38,
1930                 0x3fa40, 0x3fa40,
1931                 0x3fa48, 0x3fa50,
1932                 0x3fa5c, 0x3fa64,
1933                 0x3fa70, 0x3fab8,
1934                 0x3fac0, 0x3fae4,
1935                 0x3faf8, 0x3fb10,
1936                 0x3fb28, 0x3fb28,
1937                 0x3fb3c, 0x3fb50,
1938                 0x3fbf0, 0x3fc10,
1939                 0x3fc28, 0x3fc28,
1940                 0x3fc3c, 0x3fc50,
1941                 0x3fcf0, 0x3fcfc,
1942                 0x40000, 0x4000c,
1943                 0x40040, 0x40050,
1944                 0x40060, 0x40068,
1945                 0x4007c, 0x4008c,
1946                 0x40094, 0x400b0,
1947                 0x400c0, 0x40144,
1948                 0x40180, 0x4018c,
1949                 0x40200, 0x40254,
1950                 0x40260, 0x40264,
1951                 0x40270, 0x40288,
1952                 0x40290, 0x40298,
1953                 0x402ac, 0x402c8,
1954                 0x402d0, 0x402e0,
1955                 0x402f0, 0x402f0,
1956                 0x40300, 0x4033c,
1957                 0x403f8, 0x403fc,
1958                 0x41304, 0x413c4,
1959                 0x41400, 0x4140c,
1960                 0x41414, 0x4141c,
1961                 0x41480, 0x414d0,
1962                 0x44000, 0x44054,
1963                 0x4405c, 0x44078,
1964                 0x440c0, 0x44174,
1965                 0x44180, 0x441ac,
1966                 0x441b4, 0x441b8,
1967                 0x441c0, 0x44254,
1968                 0x4425c, 0x44278,
1969                 0x442c0, 0x44374,
1970                 0x44380, 0x443ac,
1971                 0x443b4, 0x443b8,
1972                 0x443c0, 0x44454,
1973                 0x4445c, 0x44478,
1974                 0x444c0, 0x44574,
1975                 0x44580, 0x445ac,
1976                 0x445b4, 0x445b8,
1977                 0x445c0, 0x44654,
1978                 0x4465c, 0x44678,
1979                 0x446c0, 0x44774,
1980                 0x44780, 0x447ac,
1981                 0x447b4, 0x447b8,
1982                 0x447c0, 0x44854,
1983                 0x4485c, 0x44878,
1984                 0x448c0, 0x44974,
1985                 0x44980, 0x449ac,
1986                 0x449b4, 0x449b8,
1987                 0x449c0, 0x449fc,
1988                 0x45000, 0x45004,
1989                 0x45010, 0x45030,
1990                 0x45040, 0x45060,
1991                 0x45068, 0x45068,
1992                 0x45080, 0x45084,
1993                 0x450a0, 0x450b0,
1994                 0x45200, 0x45204,
1995                 0x45210, 0x45230,
1996                 0x45240, 0x45260,
1997                 0x45268, 0x45268,
1998                 0x45280, 0x45284,
1999                 0x452a0, 0x452b0,
2000                 0x460c0, 0x460e4,
2001                 0x47000, 0x4703c,
2002                 0x47044, 0x4708c,
2003                 0x47200, 0x47250,
2004                 0x47400, 0x47408,
2005                 0x47414, 0x47420,
2006                 0x47600, 0x47618,
2007                 0x47800, 0x47814,
2008                 0x48000, 0x4800c,
2009                 0x48040, 0x48050,
2010                 0x48060, 0x48068,
2011                 0x4807c, 0x4808c,
2012                 0x48094, 0x480b0,
2013                 0x480c0, 0x48144,
2014                 0x48180, 0x4818c,
2015                 0x48200, 0x48254,
2016                 0x48260, 0x48264,
2017                 0x48270, 0x48288,
2018                 0x48290, 0x48298,
2019                 0x482ac, 0x482c8,
2020                 0x482d0, 0x482e0,
2021                 0x482f0, 0x482f0,
2022                 0x48300, 0x4833c,
2023                 0x483f8, 0x483fc,
2024                 0x49304, 0x493c4,
2025                 0x49400, 0x4940c,
2026                 0x49414, 0x4941c,
2027                 0x49480, 0x494d0,
2028                 0x4c000, 0x4c054,
2029                 0x4c05c, 0x4c078,
2030                 0x4c0c0, 0x4c174,
2031                 0x4c180, 0x4c1ac,
2032                 0x4c1b4, 0x4c1b8,
2033                 0x4c1c0, 0x4c254,
2034                 0x4c25c, 0x4c278,
2035                 0x4c2c0, 0x4c374,
2036                 0x4c380, 0x4c3ac,
2037                 0x4c3b4, 0x4c3b8,
2038                 0x4c3c0, 0x4c454,
2039                 0x4c45c, 0x4c478,
2040                 0x4c4c0, 0x4c574,
2041                 0x4c580, 0x4c5ac,
2042                 0x4c5b4, 0x4c5b8,
2043                 0x4c5c0, 0x4c654,
2044                 0x4c65c, 0x4c678,
2045                 0x4c6c0, 0x4c774,
2046                 0x4c780, 0x4c7ac,
2047                 0x4c7b4, 0x4c7b8,
2048                 0x4c7c0, 0x4c854,
2049                 0x4c85c, 0x4c878,
2050                 0x4c8c0, 0x4c974,
2051                 0x4c980, 0x4c9ac,
2052                 0x4c9b4, 0x4c9b8,
2053                 0x4c9c0, 0x4c9fc,
2054                 0x4d000, 0x4d004,
2055                 0x4d010, 0x4d030,
2056                 0x4d040, 0x4d060,
2057                 0x4d068, 0x4d068,
2058                 0x4d080, 0x4d084,
2059                 0x4d0a0, 0x4d0b0,
2060                 0x4d200, 0x4d204,
2061                 0x4d210, 0x4d230,
2062                 0x4d240, 0x4d260,
2063                 0x4d268, 0x4d268,
2064                 0x4d280, 0x4d284,
2065                 0x4d2a0, 0x4d2b0,
2066                 0x4e0c0, 0x4e0e4,
2067                 0x4f000, 0x4f03c,
2068                 0x4f044, 0x4f08c,
2069                 0x4f200, 0x4f250,
2070                 0x4f400, 0x4f408,
2071                 0x4f414, 0x4f420,
2072                 0x4f600, 0x4f618,
2073                 0x4f800, 0x4f814,
2074                 0x50000, 0x50084,
2075                 0x50090, 0x500cc,
2076                 0x50400, 0x50400,
2077                 0x50800, 0x50884,
2078                 0x50890, 0x508cc,
2079                 0x50c00, 0x50c00,
2080                 0x51000, 0x5101c,
2081                 0x51300, 0x51308,
2082         };
2083
2084         static const unsigned int t6_reg_ranges[] = {
2085                 0x1008, 0x101c,
2086                 0x1024, 0x10a8,
2087                 0x10b4, 0x10f8,
2088                 0x1100, 0x1114,
2089                 0x111c, 0x112c,
2090                 0x1138, 0x113c,
2091                 0x1144, 0x114c,
2092                 0x1180, 0x1184,
2093                 0x1190, 0x1194,
2094                 0x11a0, 0x11a4,
2095                 0x11b0, 0x11b4,
2096                 0x11fc, 0x1274,
2097                 0x1280, 0x133c,
2098                 0x1800, 0x18fc,
2099                 0x3000, 0x302c,
2100                 0x3060, 0x30b0,
2101                 0x30b8, 0x30d8,
2102                 0x30e0, 0x30fc,
2103                 0x3140, 0x357c,
2104                 0x35a8, 0x35cc,
2105                 0x35ec, 0x35ec,
2106                 0x3600, 0x5624,
2107                 0x56cc, 0x56ec,
2108                 0x56f4, 0x5720,
2109                 0x5728, 0x575c,
2110                 0x580c, 0x5814,
2111                 0x5890, 0x589c,
2112                 0x58a4, 0x58ac,
2113                 0x58b8, 0x58bc,
2114                 0x5940, 0x595c,
2115                 0x5980, 0x598c,
2116                 0x59b0, 0x59c8,
2117                 0x59d0, 0x59dc,
2118                 0x59fc, 0x5a18,
2119                 0x5a60, 0x5a6c,
2120                 0x5a80, 0x5a8c,
2121                 0x5a94, 0x5a9c,
2122                 0x5b94, 0x5bfc,
2123                 0x5c10, 0x5e48,
2124                 0x5e50, 0x5e94,
2125                 0x5ea0, 0x5eb0,
2126                 0x5ec0, 0x5ec0,
2127                 0x5ec8, 0x5ed0,
2128                 0x5ee0, 0x5ee0,
2129                 0x5ef0, 0x5ef0,
2130                 0x5f00, 0x5f00,
2131                 0x6000, 0x6020,
2132                 0x6028, 0x6040,
2133                 0x6058, 0x609c,
2134                 0x60a8, 0x619c,
2135                 0x7700, 0x7798,
2136                 0x77c0, 0x7880,
2137                 0x78cc, 0x78fc,
2138                 0x7b00, 0x7b58,
2139                 0x7b60, 0x7b84,
2140                 0x7b8c, 0x7c54,
2141                 0x7d00, 0x7d38,
2142                 0x7d40, 0x7d84,
2143                 0x7d8c, 0x7ddc,
2144                 0x7de4, 0x7e04,
2145                 0x7e10, 0x7e1c,
2146                 0x7e24, 0x7e38,
2147                 0x7e40, 0x7e44,
2148                 0x7e4c, 0x7e78,
2149                 0x7e80, 0x7edc,
2150                 0x7ee8, 0x7efc,
2151                 0x8dc0, 0x8de4,
2152                 0x8df8, 0x8e04,
2153                 0x8e10, 0x8e84,
2154                 0x8ea0, 0x8f88,
2155                 0x8fb8, 0x9058,
2156                 0x9060, 0x9060,
2157                 0x9068, 0x90f8,
2158                 0x9100, 0x9124,
2159                 0x9400, 0x9470,
2160                 0x9600, 0x9600,
2161                 0x9608, 0x9638,
2162                 0x9640, 0x9704,
2163                 0x9710, 0x971c,
2164                 0x9800, 0x9808,
2165                 0x9820, 0x983c,
2166                 0x9850, 0x9864,
2167                 0x9c00, 0x9c6c,
2168                 0x9c80, 0x9cec,
2169                 0x9d00, 0x9d6c,
2170                 0x9d80, 0x9dec,
2171                 0x9e00, 0x9e6c,
2172                 0x9e80, 0x9eec,
2173                 0x9f00, 0x9f6c,
2174                 0x9f80, 0xa020,
2175                 0xd004, 0xd03c,
2176                 0xd100, 0xd118,
2177                 0xd200, 0xd214,
2178                 0xd220, 0xd234,
2179                 0xd240, 0xd254,
2180                 0xd260, 0xd274,
2181                 0xd280, 0xd294,
2182                 0xd2a0, 0xd2b4,
2183                 0xd2c0, 0xd2d4,
2184                 0xd2e0, 0xd2f4,
2185                 0xd300, 0xd31c,
2186                 0xdfc0, 0xdfe0,
2187                 0xe000, 0xf008,
2188                 0xf010, 0xf018,
2189                 0xf020, 0xf028,
2190                 0x11000, 0x11014,
2191                 0x11048, 0x1106c,
2192                 0x11074, 0x11088,
2193                 0x11098, 0x11120,
2194                 0x1112c, 0x1117c,
2195                 0x11190, 0x112e0,
2196                 0x11300, 0x1130c,
2197                 0x12000, 0x1206c,
2198                 0x19040, 0x1906c,
2199                 0x19078, 0x19080,
2200                 0x1908c, 0x190e8,
2201                 0x190f0, 0x190f8,
2202                 0x19100, 0x19110,
2203                 0x19120, 0x19124,
2204                 0x19150, 0x19194,
2205                 0x1919c, 0x191b0,
2206                 0x191d0, 0x191e8,
2207                 0x19238, 0x19290,
2208                 0x192a4, 0x192b0,
2209                 0x192bc, 0x192bc,
2210                 0x19348, 0x1934c,
2211                 0x193f8, 0x19418,
2212                 0x19420, 0x19428,
2213                 0x19430, 0x19444,
2214                 0x1944c, 0x1946c,
2215                 0x19474, 0x19474,
2216                 0x19490, 0x194cc,
2217                 0x194f0, 0x194f8,
2218                 0x19c00, 0x19c48,
2219                 0x19c50, 0x19c80,
2220                 0x19c94, 0x19c98,
2221                 0x19ca0, 0x19cbc,
2222                 0x19ce4, 0x19ce4,
2223                 0x19cf0, 0x19cf8,
2224                 0x19d00, 0x19d28,
2225                 0x19d50, 0x19d78,
2226                 0x19d94, 0x19d98,
2227                 0x19da0, 0x19dc8,
2228                 0x19df0, 0x19e10,
2229                 0x19e50, 0x19e6c,
2230                 0x19ea0, 0x19ebc,
2231                 0x19ec4, 0x19ef4,
2232                 0x19f04, 0x19f2c,
2233                 0x19f34, 0x19f34,
2234                 0x19f40, 0x19f50,
2235                 0x19f90, 0x19fac,
2236                 0x19fc4, 0x19fc8,
2237                 0x19fd0, 0x19fe4,
2238                 0x1a000, 0x1a004,
2239                 0x1a010, 0x1a06c,
2240                 0x1a0b0, 0x1a0e4,
2241                 0x1a0ec, 0x1a0f8,
2242                 0x1a100, 0x1a108,
2243                 0x1a114, 0x1a120,
2244                 0x1a128, 0x1a130,
2245                 0x1a138, 0x1a138,
2246                 0x1a190, 0x1a1c4,
2247                 0x1a1fc, 0x1a1fc,
2248                 0x1e008, 0x1e00c,
2249                 0x1e040, 0x1e044,
2250                 0x1e04c, 0x1e04c,
2251                 0x1e284, 0x1e290,
2252                 0x1e2c0, 0x1e2c0,
2253                 0x1e2e0, 0x1e2e0,
2254                 0x1e300, 0x1e384,
2255                 0x1e3c0, 0x1e3c8,
2256                 0x1e408, 0x1e40c,
2257                 0x1e440, 0x1e444,
2258                 0x1e44c, 0x1e44c,
2259                 0x1e684, 0x1e690,
2260                 0x1e6c0, 0x1e6c0,
2261                 0x1e6e0, 0x1e6e0,
2262                 0x1e700, 0x1e784,
2263                 0x1e7c0, 0x1e7c8,
2264                 0x1e808, 0x1e80c,
2265                 0x1e840, 0x1e844,
2266                 0x1e84c, 0x1e84c,
2267                 0x1ea84, 0x1ea90,
2268                 0x1eac0, 0x1eac0,
2269                 0x1eae0, 0x1eae0,
2270                 0x1eb00, 0x1eb84,
2271                 0x1ebc0, 0x1ebc8,
2272                 0x1ec08, 0x1ec0c,
2273                 0x1ec40, 0x1ec44,
2274                 0x1ec4c, 0x1ec4c,
2275                 0x1ee84, 0x1ee90,
2276                 0x1eec0, 0x1eec0,
2277                 0x1eee0, 0x1eee0,
2278                 0x1ef00, 0x1ef84,
2279                 0x1efc0, 0x1efc8,
2280                 0x1f008, 0x1f00c,
2281                 0x1f040, 0x1f044,
2282                 0x1f04c, 0x1f04c,
2283                 0x1f284, 0x1f290,
2284                 0x1f2c0, 0x1f2c0,
2285                 0x1f2e0, 0x1f2e0,
2286                 0x1f300, 0x1f384,
2287                 0x1f3c0, 0x1f3c8,
2288                 0x1f408, 0x1f40c,
2289                 0x1f440, 0x1f444,
2290                 0x1f44c, 0x1f44c,
2291                 0x1f684, 0x1f690,
2292                 0x1f6c0, 0x1f6c0,
2293                 0x1f6e0, 0x1f6e0,
2294                 0x1f700, 0x1f784,
2295                 0x1f7c0, 0x1f7c8,
2296                 0x1f808, 0x1f80c,
2297                 0x1f840, 0x1f844,
2298                 0x1f84c, 0x1f84c,
2299                 0x1fa84, 0x1fa90,
2300                 0x1fac0, 0x1fac0,
2301                 0x1fae0, 0x1fae0,
2302                 0x1fb00, 0x1fb84,
2303                 0x1fbc0, 0x1fbc8,
2304                 0x1fc08, 0x1fc0c,
2305                 0x1fc40, 0x1fc44,
2306                 0x1fc4c, 0x1fc4c,
2307                 0x1fe84, 0x1fe90,
2308                 0x1fec0, 0x1fec0,
2309                 0x1fee0, 0x1fee0,
2310                 0x1ff00, 0x1ff84,
2311                 0x1ffc0, 0x1ffc8,
2312                 0x30000, 0x30030,
2313                 0x30100, 0x30168,
2314                 0x30190, 0x301a0,
2315                 0x301a8, 0x301b8,
2316                 0x301c4, 0x301c8,
2317                 0x301d0, 0x301d0,
2318                 0x30200, 0x30320,
2319                 0x30400, 0x304b4,
2320                 0x304c0, 0x3052c,
2321                 0x30540, 0x3061c,
2322                 0x30800, 0x308a0,
2323                 0x308c0, 0x30908,
2324                 0x30910, 0x309b8,
2325                 0x30a00, 0x30a04,
2326                 0x30a0c, 0x30a14,
2327                 0x30a1c, 0x30a2c,
2328                 0x30a44, 0x30a50,
2329                 0x30a74, 0x30a74,
2330                 0x30a7c, 0x30afc,
2331                 0x30b08, 0x30c24,
2332                 0x30d00, 0x30d14,
2333                 0x30d1c, 0x30d3c,
2334                 0x30d44, 0x30d4c,
2335                 0x30d54, 0x30d74,
2336                 0x30d7c, 0x30d7c,
2337                 0x30de0, 0x30de0,
2338                 0x30e00, 0x30ed4,
2339                 0x30f00, 0x30fa4,
2340                 0x30fc0, 0x30fc4,
2341                 0x31000, 0x31004,
2342                 0x31080, 0x310fc,
2343                 0x31208, 0x31220,
2344                 0x3123c, 0x31254,
2345                 0x31300, 0x31300,
2346                 0x31308, 0x3131c,
2347                 0x31338, 0x3133c,
2348                 0x31380, 0x31380,
2349                 0x31388, 0x313a8,
2350                 0x313b4, 0x313b4,
2351                 0x31400, 0x31420,
2352                 0x31438, 0x3143c,
2353                 0x31480, 0x31480,
2354                 0x314a8, 0x314a8,
2355                 0x314b0, 0x314b4,
2356                 0x314c8, 0x314d4,
2357                 0x31a40, 0x31a4c,
2358                 0x31af0, 0x31b20,
2359                 0x31b38, 0x31b3c,
2360                 0x31b80, 0x31b80,
2361                 0x31ba8, 0x31ba8,
2362                 0x31bb0, 0x31bb4,
2363                 0x31bc8, 0x31bd4,
2364                 0x32140, 0x3218c,
2365                 0x321f0, 0x321f4,
2366                 0x32200, 0x32200,
2367                 0x32218, 0x32218,
2368                 0x32400, 0x32400,
2369                 0x32408, 0x3241c,
2370                 0x32618, 0x32620,
2371                 0x32664, 0x32664,
2372                 0x326a8, 0x326a8,
2373                 0x326ec, 0x326ec,
2374                 0x32a00, 0x32abc,
2375                 0x32b00, 0x32b18,
2376                 0x32b20, 0x32b38,
2377                 0x32b40, 0x32b58,
2378                 0x32b60, 0x32b78,
2379                 0x32c00, 0x32c00,
2380                 0x32c08, 0x32c3c,
2381                 0x33000, 0x3302c,
2382                 0x33034, 0x33050,
2383                 0x33058, 0x33058,
2384                 0x33060, 0x3308c,
2385                 0x3309c, 0x330ac,
2386                 0x330c0, 0x330c0,
2387                 0x330c8, 0x330d0,
2388                 0x330d8, 0x330e0,
2389                 0x330ec, 0x3312c,
2390                 0x33134, 0x33150,
2391                 0x33158, 0x33158,
2392                 0x33160, 0x3318c,
2393                 0x3319c, 0x331ac,
2394                 0x331c0, 0x331c0,
2395                 0x331c8, 0x331d0,
2396                 0x331d8, 0x331e0,
2397                 0x331ec, 0x33290,
2398                 0x33298, 0x332c4,
2399                 0x332e4, 0x33390,
2400                 0x33398, 0x333c4,
2401                 0x333e4, 0x3342c,
2402                 0x33434, 0x33450,
2403                 0x33458, 0x33458,
2404                 0x33460, 0x3348c,
2405                 0x3349c, 0x334ac,
2406                 0x334c0, 0x334c0,
2407                 0x334c8, 0x334d0,
2408                 0x334d8, 0x334e0,
2409                 0x334ec, 0x3352c,
2410                 0x33534, 0x33550,
2411                 0x33558, 0x33558,
2412                 0x33560, 0x3358c,
2413                 0x3359c, 0x335ac,
2414                 0x335c0, 0x335c0,
2415                 0x335c8, 0x335d0,
2416                 0x335d8, 0x335e0,
2417                 0x335ec, 0x33690,
2418                 0x33698, 0x336c4,
2419                 0x336e4, 0x33790,
2420                 0x33798, 0x337c4,
2421                 0x337e4, 0x337fc,
2422                 0x33814, 0x33814,
2423                 0x33854, 0x33868,
2424                 0x33880, 0x3388c,
2425                 0x338c0, 0x338d0,
2426                 0x338e8, 0x338ec,
2427                 0x33900, 0x3392c,
2428                 0x33934, 0x33950,
2429                 0x33958, 0x33958,
2430                 0x33960, 0x3398c,
2431                 0x3399c, 0x339ac,
2432                 0x339c0, 0x339c0,
2433                 0x339c8, 0x339d0,
2434                 0x339d8, 0x339e0,
2435                 0x339ec, 0x33a90,
2436                 0x33a98, 0x33ac4,
2437                 0x33ae4, 0x33b10,
2438                 0x33b24, 0x33b28,
2439                 0x33b38, 0x33b50,
2440                 0x33bf0, 0x33c10,
2441                 0x33c24, 0x33c28,
2442                 0x33c38, 0x33c50,
2443                 0x33cf0, 0x33cfc,
2444                 0x34000, 0x34030,
2445                 0x34100, 0x34168,
2446                 0x34190, 0x341a0,
2447                 0x341a8, 0x341b8,
2448                 0x341c4, 0x341c8,
2449                 0x341d0, 0x341d0,
2450                 0x34200, 0x34320,
2451                 0x34400, 0x344b4,
2452                 0x344c0, 0x3452c,
2453                 0x34540, 0x3461c,
2454                 0x34800, 0x348a0,
2455                 0x348c0, 0x34908,
2456                 0x34910, 0x349b8,
2457                 0x34a00, 0x34a04,
2458                 0x34a0c, 0x34a14,
2459                 0x34a1c, 0x34a2c,
2460                 0x34a44, 0x34a50,
2461                 0x34a74, 0x34a74,
2462                 0x34a7c, 0x34afc,
2463                 0x34b08, 0x34c24,
2464                 0x34d00, 0x34d14,
2465                 0x34d1c, 0x34d3c,
2466                 0x34d44, 0x34d4c,
2467                 0x34d54, 0x34d74,
2468                 0x34d7c, 0x34d7c,
2469                 0x34de0, 0x34de0,
2470                 0x34e00, 0x34ed4,
2471                 0x34f00, 0x34fa4,
2472                 0x34fc0, 0x34fc4,
2473                 0x35000, 0x35004,
2474                 0x35080, 0x350fc,
2475                 0x35208, 0x35220,
2476                 0x3523c, 0x35254,
2477                 0x35300, 0x35300,
2478                 0x35308, 0x3531c,
2479                 0x35338, 0x3533c,
2480                 0x35380, 0x35380,
2481                 0x35388, 0x353a8,
2482                 0x353b4, 0x353b4,
2483                 0x35400, 0x35420,
2484                 0x35438, 0x3543c,
2485                 0x35480, 0x35480,
2486                 0x354a8, 0x354a8,
2487                 0x354b0, 0x354b4,
2488                 0x354c8, 0x354d4,
2489                 0x35a40, 0x35a4c,
2490                 0x35af0, 0x35b20,
2491                 0x35b38, 0x35b3c,
2492                 0x35b80, 0x35b80,
2493                 0x35ba8, 0x35ba8,
2494                 0x35bb0, 0x35bb4,
2495                 0x35bc8, 0x35bd4,
2496                 0x36140, 0x3618c,
2497                 0x361f0, 0x361f4,
2498                 0x36200, 0x36200,
2499                 0x36218, 0x36218,
2500                 0x36400, 0x36400,
2501                 0x36408, 0x3641c,
2502                 0x36618, 0x36620,
2503                 0x36664, 0x36664,
2504                 0x366a8, 0x366a8,
2505                 0x366ec, 0x366ec,
2506                 0x36a00, 0x36abc,
2507                 0x36b00, 0x36b18,
2508                 0x36b20, 0x36b38,
2509                 0x36b40, 0x36b58,
2510                 0x36b60, 0x36b78,
2511                 0x36c00, 0x36c00,
2512                 0x36c08, 0x36c3c,
2513                 0x37000, 0x3702c,
2514                 0x37034, 0x37050,
2515                 0x37058, 0x37058,
2516                 0x37060, 0x3708c,
2517                 0x3709c, 0x370ac,
2518                 0x370c0, 0x370c0,
2519                 0x370c8, 0x370d0,
2520                 0x370d8, 0x370e0,
2521                 0x370ec, 0x3712c,
2522                 0x37134, 0x37150,
2523                 0x37158, 0x37158,
2524                 0x37160, 0x3718c,
2525                 0x3719c, 0x371ac,
2526                 0x371c0, 0x371c0,
2527                 0x371c8, 0x371d0,
2528                 0x371d8, 0x371e0,
2529                 0x371ec, 0x37290,
2530                 0x37298, 0x372c4,
2531                 0x372e4, 0x37390,
2532                 0x37398, 0x373c4,
2533                 0x373e4, 0x3742c,
2534                 0x37434, 0x37450,
2535                 0x37458, 0x37458,
2536                 0x37460, 0x3748c,
2537                 0x3749c, 0x374ac,
2538                 0x374c0, 0x374c0,
2539                 0x374c8, 0x374d0,
2540                 0x374d8, 0x374e0,
2541                 0x374ec, 0x3752c,
2542                 0x37534, 0x37550,
2543                 0x37558, 0x37558,
2544                 0x37560, 0x3758c,
2545                 0x3759c, 0x375ac,
2546                 0x375c0, 0x375c0,
2547                 0x375c8, 0x375d0,
2548                 0x375d8, 0x375e0,
2549                 0x375ec, 0x37690,
2550                 0x37698, 0x376c4,
2551                 0x376e4, 0x37790,
2552                 0x37798, 0x377c4,
2553                 0x377e4, 0x377fc,
2554                 0x37814, 0x37814,
2555                 0x37854, 0x37868,
2556                 0x37880, 0x3788c,
2557                 0x378c0, 0x378d0,
2558                 0x378e8, 0x378ec,
2559                 0x37900, 0x3792c,
2560                 0x37934, 0x37950,
2561                 0x37958, 0x37958,
2562                 0x37960, 0x3798c,
2563                 0x3799c, 0x379ac,
2564                 0x379c0, 0x379c0,
2565                 0x379c8, 0x379d0,
2566                 0x379d8, 0x379e0,
2567                 0x379ec, 0x37a90,
2568                 0x37a98, 0x37ac4,
2569                 0x37ae4, 0x37b10,
2570                 0x37b24, 0x37b28,
2571                 0x37b38, 0x37b50,
2572                 0x37bf0, 0x37c10,
2573                 0x37c24, 0x37c28,
2574                 0x37c38, 0x37c50,
2575                 0x37cf0, 0x37cfc,
2576                 0x40040, 0x40040,
2577                 0x40080, 0x40084,
2578                 0x40100, 0x40100,
2579                 0x40140, 0x401bc,
2580                 0x40200, 0x40214,
2581                 0x40228, 0x40228,
2582                 0x40240, 0x40258,
2583                 0x40280, 0x40280,
2584                 0x40304, 0x40304,
2585                 0x40330, 0x4033c,
2586                 0x41304, 0x413c8,
2587                 0x413d0, 0x413dc,
2588                 0x413f0, 0x413f0,
2589                 0x41400, 0x4140c,
2590                 0x41414, 0x4141c,
2591                 0x41480, 0x414d0,
2592                 0x44000, 0x4407c,
2593                 0x440c0, 0x441ac,
2594                 0x441b4, 0x4427c,
2595                 0x442c0, 0x443ac,
2596                 0x443b4, 0x4447c,
2597                 0x444c0, 0x445ac,
2598                 0x445b4, 0x4467c,
2599                 0x446c0, 0x447ac,
2600                 0x447b4, 0x4487c,
2601                 0x448c0, 0x449ac,
2602                 0x449b4, 0x44a7c,
2603                 0x44ac0, 0x44bac,
2604                 0x44bb4, 0x44c7c,
2605                 0x44cc0, 0x44dac,
2606                 0x44db4, 0x44e7c,
2607                 0x44ec0, 0x44fac,
2608                 0x44fb4, 0x4507c,
2609                 0x450c0, 0x451ac,
2610                 0x451b4, 0x451fc,
2611                 0x45800, 0x45804,
2612                 0x45810, 0x45830,
2613                 0x45840, 0x45860,
2614                 0x45868, 0x45868,
2615                 0x45880, 0x45884,
2616                 0x458a0, 0x458b0,
2617                 0x45a00, 0x45a04,
2618                 0x45a10, 0x45a30,
2619                 0x45a40, 0x45a60,
2620                 0x45a68, 0x45a68,
2621                 0x45a80, 0x45a84,
2622                 0x45aa0, 0x45ab0,
2623                 0x460c0, 0x460e4,
2624                 0x47000, 0x4703c,
2625                 0x47044, 0x4708c,
2626                 0x47200, 0x47250,
2627                 0x47400, 0x47408,
2628                 0x47414, 0x47420,
2629                 0x47600, 0x47618,
2630                 0x47800, 0x47814,
2631                 0x47820, 0x4782c,
2632                 0x50000, 0x50084,
2633                 0x50090, 0x500cc,
2634                 0x50300, 0x50384,
2635                 0x50400, 0x50400,
2636                 0x50800, 0x50884,
2637                 0x50890, 0x508cc,
2638                 0x50b00, 0x50b84,
2639                 0x50c00, 0x50c00,
2640                 0x51000, 0x51020,
2641                 0x51028, 0x510b0,
2642                 0x51300, 0x51324,
2643         };
2644
2645         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2646         const unsigned int *reg_ranges;
2647         int reg_ranges_size, range;
2648         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2649
2650         /* Select the right set of register ranges to dump depending on the
2651          * adapter chip type.
2652          */
2653         switch (chip_version) {
2654         case CHELSIO_T4:
2655                 reg_ranges = t4_reg_ranges;
2656                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2657                 break;
2658
2659         case CHELSIO_T5:
2660                 reg_ranges = t5_reg_ranges;
2661                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2662                 break;
2663
2664         case CHELSIO_T6:
2665                 reg_ranges = t6_reg_ranges;
2666                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2667                 break;
2668
2669         default:
2670                 dev_err(adap->pdev_dev,
2671                         "Unsupported chip version %d\n", chip_version);
2672                 return;
2673         }
2674
2675         /* Clear the register buffer and insert the appropriate register
2676          * values selected by the above register ranges.
2677          */
2678         memset(buf, 0, buf_size);
2679         for (range = 0; range < reg_ranges_size; range += 2) {
2680                 unsigned int reg = reg_ranges[range];
2681                 unsigned int last_reg = reg_ranges[range + 1];
2682                 u32 *bufp = (u32 *)((char *)buf + reg);
2683
2684                 /* Iterate across the register range filling in the register
2685                  * buffer but don't write past the end of the register buffer.
2686                  */
2687                 while (reg <= last_reg && bufp < buf_end) {
2688                         *bufp++ = t4_read_reg(adap, reg);
2689                         reg += sizeof(u32);
2690                 }
2691         }
2692 }
2693
2694 #define EEPROM_STAT_ADDR   0x7bfc
2695 #define VPD_BASE           0x400
2696 #define VPD_BASE_OLD       0
2697 #define VPD_LEN            1024
2698 #define CHELSIO_VPD_UNIQUE_ID 0x82
2699
2700 /**
2701  * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2702  * @phys_addr: the physical EEPROM address
2703  * @fn: the PCI function number
2704  * @sz: size of function-specific area
2705  *
2706  * Translate a physical EEPROM address to virtual.  The first 1K is
2707  * accessed through virtual addresses starting at 31K, the rest is
2708  * accessed through virtual addresses starting at 0.
2709  *
2710  * The mapping is as follows:
2711  * [0..1K) -> [31K..32K)
2712  * [1K..1K+A) -> [31K-A..31K)
2713  * [1K+A..ES) -> [0..ES-A-1K)
2714  *
2715  * where A = @fn * @sz, and ES = EEPROM size.
2716  */
2717 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2718 {
2719         fn *= sz;
2720         if (phys_addr < 1024)
2721                 return phys_addr + (31 << 10);
2722         if (phys_addr < 1024 + fn)
2723                 return 31744 - fn + phys_addr - 1024;
2724         if (phys_addr < EEPROMSIZE)
2725                 return phys_addr - 1024 - fn;
2726         return -EINVAL;
2727 }
2728
2729 /**
2730  *      t4_seeprom_wp - enable/disable EEPROM write protection
2731  *      @adapter: the adapter
2732  *      @enable: whether to enable or disable write protection
2733  *
2734  *      Enables or disables write protection on the serial EEPROM.
2735  */
2736 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2737 {
2738         unsigned int v = enable ? 0xc : 0;
2739         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2740         return ret < 0 ? ret : 0;
2741 }
2742
2743 /**
2744  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2745  *      @adapter: adapter to read
2746  *      @p: where to store the parameters
2747  *
2748  *      Reads card parameters stored in VPD EEPROM.
2749  */
2750 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2751 {
2752         int i, ret = 0, addr;
2753         int ec, sn, pn, na;
2754         u8 *vpd, csum;
2755         unsigned int vpdr_len, kw_offset, id_len;
2756
2757         vpd = vmalloc(VPD_LEN);
2758         if (!vpd)
2759                 return -ENOMEM;
2760
2761         /* Card information normally starts at VPD_BASE but early cards had
2762          * it at 0.
2763          */
2764         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2765         if (ret < 0)
2766                 goto out;
2767
2768         /* The VPD shall have a unique identifier specified by the PCI SIG.
2769          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2770          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2771          * is expected to automatically put this entry at the
2772          * beginning of the VPD.
2773          */
2774         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2775
2776         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2777         if (ret < 0)
2778                 goto out;
2779
2780         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2781                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2782                 ret = -EINVAL;
2783                 goto out;
2784         }
2785
2786         id_len = pci_vpd_lrdt_size(vpd);
2787         if (id_len > ID_LEN)
2788                 id_len = ID_LEN;
2789
2790         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2791         if (i < 0) {
2792                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2793                 ret = -EINVAL;
2794                 goto out;
2795         }
2796
2797         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2798         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2799         if (vpdr_len + kw_offset > VPD_LEN) {
2800                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2801                 ret = -EINVAL;
2802                 goto out;
2803         }
2804
2805 #define FIND_VPD_KW(var, name) do { \
2806         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2807         if (var < 0) { \
2808                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2809                 ret = -EINVAL; \
2810                 goto out; \
2811         } \
2812         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2813 } while (0)
2814
2815         FIND_VPD_KW(i, "RV");
2816         for (csum = 0; i >= 0; i--)
2817                 csum += vpd[i];
2818
2819         if (csum) {
2820                 dev_err(adapter->pdev_dev,
2821                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2822                 ret = -EINVAL;
2823                 goto out;
2824         }
2825
2826         FIND_VPD_KW(ec, "EC");
2827         FIND_VPD_KW(sn, "SN");
2828         FIND_VPD_KW(pn, "PN");
2829         FIND_VPD_KW(na, "NA");
2830 #undef FIND_VPD_KW
2831
2832         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2833         strim(p->id);
2834         memcpy(p->ec, vpd + ec, EC_LEN);
2835         strim(p->ec);
2836         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2837         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2838         strim(p->sn);
2839         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2840         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2841         strim(p->pn);
2842         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2843         strim((char *)p->na);
2844
2845 out:
2846         vfree(vpd);
2847         return ret < 0 ? ret : 0;
2848 }
2849
2850 /**
2851  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2852  *      @adapter: adapter to read
2853  *      @p: where to store the parameters
2854  *
2855  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2856  *      Clock.  This can only be called after a connection to the firmware
2857  *      is established.
2858  */
2859 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2860 {
2861         u32 cclk_param, cclk_val;
2862         int ret;
2863
2864         /* Grab the raw VPD parameters.
2865          */
2866         ret = t4_get_raw_vpd_params(adapter, p);
2867         if (ret)
2868                 return ret;
2869
2870         /* Ask firmware for the Core Clock since it knows how to translate the
2871          * Reference Clock ('V2') VPD field into a Core Clock value ...
2872          */
2873         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2874                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2875         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2876                               1, &cclk_param, &cclk_val);
2877
2878         if (ret)
2879                 return ret;
2880         p->cclk = cclk_val;
2881
2882         return 0;
2883 }
2884
2885 /**
2886  *      t4_get_pfres - retrieve VF resource limits
2887  *      @adapter: the adapter
2888  *
2889  *      Retrieves configured resource limits and capabilities for a physical
2890  *      function.  The results are stored in @adapter->pfres.
2891  */
2892 int t4_get_pfres(struct adapter *adapter)
2893 {
2894         struct pf_resources *pfres = &adapter->params.pfres;
2895         struct fw_pfvf_cmd cmd, rpl;
2896         int v;
2897         u32 word;
2898
2899         /* Execute PFVF Read command to get VF resource limits; bail out early
2900          * with error on command failure.
2901          */
2902         memset(&cmd, 0, sizeof(cmd));
2903         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2904                                     FW_CMD_REQUEST_F |
2905                                     FW_CMD_READ_F |
2906                                     FW_PFVF_CMD_PFN_V(adapter->pf) |
2907                                     FW_PFVF_CMD_VFN_V(0));
2908         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2909         v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2910         if (v != FW_SUCCESS)
2911                 return v;
2912
2913         /* Extract PF resource limits and return success.
2914          */
2915         word = be32_to_cpu(rpl.niqflint_niq);
2916         pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2917         pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2918
2919         word = be32_to_cpu(rpl.type_to_neq);
2920         pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2921         pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2922
2923         word = be32_to_cpu(rpl.tc_to_nexactf);
2924         pfres->tc = FW_PFVF_CMD_TC_G(word);
2925         pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2926         pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2927
2928         word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2929         pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2930         pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2931         pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2932
2933         return 0;
2934 }
2935
2936 /* serial flash and firmware constants */
2937 enum {
2938         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2939
2940         /* flash command opcodes */
2941         SF_PROG_PAGE    = 2,          /* program page */
2942         SF_WR_DISABLE   = 4,          /* disable writes */
2943         SF_RD_STATUS    = 5,          /* read status register */
2944         SF_WR_ENABLE    = 6,          /* enable writes */
2945         SF_RD_DATA_FAST = 0xb,        /* read flash */
2946         SF_RD_ID        = 0x9f,       /* read ID */
2947         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2948 };
2949
2950 /**
2951  *      sf1_read - read data from the serial flash
2952  *      @adapter: the adapter
2953  *      @byte_cnt: number of bytes to read
2954  *      @cont: whether another operation will be chained
2955  *      @lock: whether to lock SF for PL access only
2956  *      @valp: where to store the read data
2957  *
2958  *      Reads up to 4 bytes of data from the serial flash.  The location of
2959  *      the read needs to be specified prior to calling this by issuing the
2960  *      appropriate commands to the serial flash.
2961  */
2962 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2963                     int lock, u32 *valp)
2964 {
2965         int ret;
2966
2967         if (!byte_cnt || byte_cnt > 4)
2968                 return -EINVAL;
2969         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2970                 return -EBUSY;
2971         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2972                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2973         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2974         if (!ret)
2975                 *valp = t4_read_reg(adapter, SF_DATA_A);
2976         return ret;
2977 }
2978
2979 /**
2980  *      sf1_write - write data to the serial flash
2981  *      @adapter: the adapter
2982  *      @byte_cnt: number of bytes to write
2983  *      @cont: whether another operation will be chained
2984  *      @lock: whether to lock SF for PL access only
2985  *      @val: value to write
2986  *
2987  *      Writes up to 4 bytes of data to the serial flash.  The location of
2988  *      the write needs to be specified prior to calling this by issuing the
2989  *      appropriate commands to the serial flash.
2990  */
2991 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2992                      int lock, u32 val)
2993 {
2994         if (!byte_cnt || byte_cnt > 4)
2995                 return -EINVAL;
2996         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2997                 return -EBUSY;
2998         t4_write_reg(adapter, SF_DATA_A, val);
2999         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
3000                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
3001         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
3002 }
3003
3004 /**
3005  *      flash_wait_op - wait for a flash operation to complete
3006  *      @adapter: the adapter
3007  *      @attempts: max number of polls of the status register
3008  *      @delay: delay between polls in ms
3009  *
3010  *      Wait for a flash operation to complete by polling the status register.
3011  */
3012 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3013 {
3014         int ret;
3015         u32 status;
3016
3017         while (1) {
3018                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3019                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3020                         return ret;
3021                 if (!(status & 1))
3022                         return 0;
3023                 if (--attempts == 0)
3024                         return -EAGAIN;
3025                 if (delay)
3026                         msleep(delay);
3027         }
3028 }
3029
3030 /**
3031  *      t4_read_flash - read words from serial flash
3032  *      @adapter: the adapter
3033  *      @addr: the start address for the read
3034  *      @nwords: how many 32-bit words to read
3035  *      @data: where to store the read data
3036  *      @byte_oriented: whether to store data as bytes or as words
3037  *
3038  *      Read the specified number of 32-bit words from the serial flash.
3039  *      If @byte_oriented is set the read data is stored as a byte array
3040  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
3041  *      natural endianness.
3042  */
3043 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3044                   unsigned int nwords, u32 *data, int byte_oriented)
3045 {
3046         int ret;
3047
3048         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3049                 return -EINVAL;
3050
3051         addr = swab32(addr) | SF_RD_DATA_FAST;
3052
3053         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3054             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3055                 return ret;
3056
3057         for ( ; nwords; nwords--, data++) {
3058                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3059                 if (nwords == 1)
3060                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3061                 if (ret)
3062                         return ret;
3063                 if (byte_oriented)
3064                         *data = (__force __u32)(cpu_to_be32(*data));
3065         }
3066         return 0;
3067 }
3068
3069 /**
3070  *      t4_write_flash - write up to a page of data to the serial flash
3071  *      @adapter: the adapter
3072  *      @addr: the start address to write
3073  *      @n: length of data to write in bytes
3074  *      @data: the data to write
3075  *
3076  *      Writes up to a page of data (256 bytes) to the serial flash starting
3077  *      at the given address.  All the data must be written to the same page.
3078  */
3079 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3080                           unsigned int n, const u8 *data)
3081 {
3082         int ret;
3083         u32 buf[64];
3084         unsigned int i, c, left, val, offset = addr & 0xff;
3085
3086         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3087                 return -EINVAL;
3088
3089         val = swab32(addr) | SF_PROG_PAGE;
3090
3091         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3092             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3093                 goto unlock;
3094
3095         for (left = n; left; left -= c) {
3096                 c = min(left, 4U);
3097                 for (val = 0, i = 0; i < c; ++i)
3098                         val = (val << 8) + *data++;
3099
3100                 ret = sf1_write(adapter, c, c != left, 1, val);
3101                 if (ret)
3102                         goto unlock;
3103         }
3104         ret = flash_wait_op(adapter, 8, 1);
3105         if (ret)
3106                 goto unlock;
3107
3108         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3109
3110         /* Read the page to verify the write succeeded */
3111         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3112         if (ret)
3113                 return ret;
3114
3115         if (memcmp(data - n, (u8 *)buf + offset, n)) {
3116                 dev_err(adapter->pdev_dev,
3117                         "failed to correctly write the flash page at %#x\n",
3118                         addr);
3119                 return -EIO;
3120         }
3121         return 0;
3122
3123 unlock:
3124         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3125         return ret;
3126 }
3127
3128 /**
3129  *      t4_get_fw_version - read the firmware version
3130  *      @adapter: the adapter
3131  *      @vers: where to place the version
3132  *
3133  *      Reads the FW version from flash.
3134  */
3135 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3136 {
3137         return t4_read_flash(adapter, FLASH_FW_START +
3138                              offsetof(struct fw_hdr, fw_ver), 1,
3139                              vers, 0);
3140 }
3141
3142 /**
3143  *      t4_get_bs_version - read the firmware bootstrap version
3144  *      @adapter: the adapter
3145  *      @vers: where to place the version
3146  *
3147  *      Reads the FW Bootstrap version from flash.
3148  */
3149 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3150 {
3151         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3152                              offsetof(struct fw_hdr, fw_ver), 1,
3153                              vers, 0);
3154 }
3155
3156 /**
3157  *      t4_get_tp_version - read the TP microcode version
3158  *      @adapter: the adapter
3159  *      @vers: where to place the version
3160  *
3161  *      Reads the TP microcode version from flash.
3162  */
3163 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3164 {
3165         return t4_read_flash(adapter, FLASH_FW_START +
3166                              offsetof(struct fw_hdr, tp_microcode_ver),
3167                              1, vers, 0);
3168 }
3169
3170 /**
3171  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3172  *      @adapter: the adapter
3173  *      @vers: where to place the version
3174  *
3175  *      Reads the Expansion ROM header from FLASH and returns the version
3176  *      number (if present) through the @vers return value pointer.  We return
3177  *      this in the Firmware Version Format since it's convenient.  Return
3178  *      0 on success, -ENOENT if no Expansion ROM is present.
3179  */
3180 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3181 {
3182         struct exprom_header {
3183                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3184                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3185         } *hdr;
3186         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3187                                            sizeof(u32))];
3188         int ret;
3189
3190         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3191                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3192                             0);
3193         if (ret)
3194                 return ret;
3195
3196         hdr = (struct exprom_header *)exprom_header_buf;
3197         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3198                 return -ENOENT;
3199
3200         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3201                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3202                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3203                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3204         return 0;
3205 }
3206
3207 /**
3208  *      t4_get_vpd_version - return the VPD version
3209  *      @adapter: the adapter
3210  *      @vers: where to place the version
3211  *
3212  *      Reads the VPD via the Firmware interface (thus this can only be called
3213  *      once we're ready to issue Firmware commands).  The format of the
3214  *      VPD version is adapter specific.  Returns 0 on success, an error on
3215  *      failure.
3216  *
3217  *      Note that early versions of the Firmware didn't include the ability
3218  *      to retrieve the VPD version, so we zero-out the return-value parameter
3219  *      in that case to avoid leaving it with garbage in it.
3220  *
3221  *      Also note that the Firmware will return its cached copy of the VPD
3222  *      Revision ID, not the actual Revision ID as written in the Serial
3223  *      EEPROM.  This is only an issue if a new VPD has been written and the
3224  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3225  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3226  *      if the Host Driver will be performing a full adapter initialization.
3227  */
3228 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3229 {
3230         u32 vpdrev_param;
3231         int ret;
3232
3233         vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3234                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3235         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3236                               1, &vpdrev_param, vers);
3237         if (ret)
3238                 *vers = 0;
3239         return ret;
3240 }
3241
3242 /**
3243  *      t4_get_scfg_version - return the Serial Configuration version
3244  *      @adapter: the adapter
3245  *      @vers: where to place the version
3246  *
3247  *      Reads the Serial Configuration Version via the Firmware interface
3248  *      (thus this can only be called once we're ready to issue Firmware
3249  *      commands).  The format of the Serial Configuration version is
3250  *      adapter specific.  Returns 0 on success, an error on failure.
3251  *
3252  *      Note that early versions of the Firmware didn't include the ability
3253  *      to retrieve the Serial Configuration version, so we zero-out the
3254  *      return-value parameter in that case to avoid leaving it with
3255  *      garbage in it.
3256  *
3257  *      Also note that the Firmware will return its cached copy of the Serial
3258  *      Initialization Revision ID, not the actual Revision ID as written in
3259  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3260  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3261  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3262  *      been issued if the Host Driver will be performing a full adapter
3263  *      initialization.
3264  */
3265 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3266 {
3267         u32 scfgrev_param;
3268         int ret;
3269
3270         scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3271                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3272         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3273                               1, &scfgrev_param, vers);
3274         if (ret)
3275                 *vers = 0;
3276         return ret;
3277 }
3278
3279 /**
3280  *      t4_get_version_info - extract various chip/firmware version information
3281  *      @adapter: the adapter
3282  *
3283  *      Reads various chip/firmware version numbers and stores them into the
3284  *      adapter Adapter Parameters structure.  If any of the efforts fails
3285  *      the first failure will be returned, but all of the version numbers
3286  *      will be read.
3287  */
3288 int t4_get_version_info(struct adapter *adapter)
3289 {
3290         int ret = 0;
3291
3292         #define FIRST_RET(__getvinfo) \
3293         do { \
3294                 int __ret = __getvinfo; \
3295                 if (__ret && !ret) \
3296                         ret = __ret; \
3297         } while (0)
3298
3299         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3300         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3301         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3302         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3303         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3304         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3305
3306         #undef FIRST_RET
3307         return ret;
3308 }
3309
3310 /**
3311  *      t4_dump_version_info - dump all of the adapter configuration IDs
3312  *      @adapter: the adapter
3313  *
3314  *      Dumps all of the various bits of adapter configuration version/revision
3315  *      IDs information.  This is typically called at some point after
3316  *      t4_get_version_info() has been called.
3317  */
3318 void t4_dump_version_info(struct adapter *adapter)
3319 {
3320         /* Device information */
3321         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3322                  adapter->params.vpd.id,
3323                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
3324         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3325                  adapter->params.vpd.sn, adapter->params.vpd.pn);
3326
3327         /* Firmware Version */
3328         if (!adapter->params.fw_vers)
3329                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3330         else
3331                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3332                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3333                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3334                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3335                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3336
3337         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3338          * Firmware, so dev_info() is more appropriate here.)
3339          */
3340         if (!adapter->params.bs_vers)
3341                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3342         else
3343                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3344                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3345                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3346                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3347                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3348
3349         /* TP Microcode Version */
3350         if (!adapter->params.tp_vers)
3351                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3352         else
3353                 dev_info(adapter->pdev_dev,
3354                          "TP Microcode version: %u.%u.%u.%u\n",
3355                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3356                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3357                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3358                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3359
3360         /* Expansion ROM version */
3361         if (!adapter->params.er_vers)
3362                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3363         else
3364                 dev_info(adapter->pdev_dev,
3365                          "Expansion ROM version: %u.%u.%u.%u\n",
3366                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3367                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3368                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3369                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3370
3371         /* Serial Configuration version */
3372         dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3373                  adapter->params.scfg_vers);
3374
3375         /* VPD Version */
3376         dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3377                  adapter->params.vpd_vers);
3378 }
3379
3380 /**
3381  *      t4_check_fw_version - check if the FW is supported with this driver
3382  *      @adap: the adapter
3383  *
3384  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3385  *      if there's exact match, a negative error if the version could not be
3386  *      read or there's a major version mismatch
3387  */
3388 int t4_check_fw_version(struct adapter *adap)
3389 {
3390         int i, ret, major, minor, micro;
3391         int exp_major, exp_minor, exp_micro;
3392         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3393
3394         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3395         /* Try multiple times before returning error */
3396         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3397                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3398
3399         if (ret)
3400                 return ret;
3401
3402         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3403         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3404         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3405
3406         switch (chip_version) {
3407         case CHELSIO_T4:
3408                 exp_major = T4FW_MIN_VERSION_MAJOR;
3409                 exp_minor = T4FW_MIN_VERSION_MINOR;
3410                 exp_micro = T4FW_MIN_VERSION_MICRO;
3411                 break;
3412         case CHELSIO_T5:
3413                 exp_major = T5FW_MIN_VERSION_MAJOR;
3414                 exp_minor = T5FW_MIN_VERSION_MINOR;
3415                 exp_micro = T5FW_MIN_VERSION_MICRO;
3416                 break;
3417         case CHELSIO_T6:
3418                 exp_major = T6FW_MIN_VERSION_MAJOR;
3419                 exp_minor = T6FW_MIN_VERSION_MINOR;
3420                 exp_micro = T6FW_MIN_VERSION_MICRO;
3421                 break;
3422         default:
3423                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3424                         adap->chip);
3425                 return -EINVAL;
3426         }
3427
3428         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3429             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3430                 dev_err(adap->pdev_dev,
3431                         "Card has firmware version %u.%u.%u, minimum "
3432                         "supported firmware is %u.%u.%u.\n", major, minor,
3433                         micro, exp_major, exp_minor, exp_micro);
3434                 return -EFAULT;
3435         }
3436         return 0;
3437 }
3438
3439 /* Is the given firmware API compatible with the one the driver was compiled
3440  * with?
3441  */
3442 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3443 {
3444
3445         /* short circuit if it's the exact same firmware version */
3446         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3447                 return 1;
3448
3449 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3450         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3451             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3452                 return 1;
3453 #undef SAME_INTF
3454
3455         return 0;
3456 }
3457
3458 /* The firmware in the filesystem is usable, but should it be installed?
3459  * This routine explains itself in detail if it indicates the filesystem
3460  * firmware should be installed.
3461  */
3462 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3463                                 int k, int c)
3464 {
3465         const char *reason;
3466
3467         if (!card_fw_usable) {
3468                 reason = "incompatible or unusable";
3469                 goto install;
3470         }
3471
3472         if (k > c) {
3473                 reason = "older than the version supported with this driver";
3474                 goto install;
3475         }
3476
3477         return 0;
3478
3479 install:
3480         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3481                 "installing firmware %u.%u.%u.%u on card.\n",
3482                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3483                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3484                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3485                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3486
3487         return 1;
3488 }
3489
3490 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3491                const u8 *fw_data, unsigned int fw_size,
3492                struct fw_hdr *card_fw, enum dev_state state,
3493                int *reset)
3494 {
3495         int ret, card_fw_usable, fs_fw_usable;
3496         const struct fw_hdr *fs_fw;
3497         const struct fw_hdr *drv_fw;
3498
3499         drv_fw = &fw_info->fw_hdr;
3500
3501         /* Read the header of the firmware on the card */
3502         ret = -t4_read_flash(adap, FLASH_FW_START,
3503                             sizeof(*card_fw) / sizeof(uint32_t),
3504                             (uint32_t *)card_fw, 1);
3505         if (ret == 0) {
3506                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3507         } else {
3508                 dev_err(adap->pdev_dev,
3509                         "Unable to read card's firmware header: %d\n", ret);
3510                 card_fw_usable = 0;
3511         }
3512
3513         if (fw_data != NULL) {
3514                 fs_fw = (const void *)fw_data;
3515                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3516         } else {
3517                 fs_fw = NULL;
3518                 fs_fw_usable = 0;
3519         }
3520
3521         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3522             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3523                 /* Common case: the firmware on the card is an exact match and
3524                  * the filesystem one is an exact match too, or the filesystem
3525                  * one is absent/incompatible.
3526                  */
3527         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3528                    should_install_fs_fw(adap, card_fw_usable,
3529                                         be32_to_cpu(fs_fw->fw_ver),
3530                                         be32_to_cpu(card_fw->fw_ver))) {
3531                 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3532                                      fw_size, 0);
3533                 if (ret != 0) {
3534                         dev_err(adap->pdev_dev,
3535                                 "failed to install firmware: %d\n", ret);
3536                         goto bye;
3537                 }
3538
3539                 /* Installed successfully, update the cached header too. */
3540                 *card_fw = *fs_fw;
3541                 card_fw_usable = 1;
3542                 *reset = 0;     /* already reset as part of load_fw */
3543         }
3544
3545         if (!card_fw_usable) {
3546                 uint32_t d, c, k;
3547
3548                 d = be32_to_cpu(drv_fw->fw_ver);
3549                 c = be32_to_cpu(card_fw->fw_ver);
3550                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3551
3552                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3553                         "chip state %d, "
3554                         "driver compiled with %d.%d.%d.%d, "
3555                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3556                         state,
3557                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3558                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3559                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3560                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3561                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3562                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3563                 ret = EINVAL;
3564                 goto bye;
3565         }
3566
3567         /* We're using whatever's on the card and it's known to be good. */
3568         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3569         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3570
3571 bye:
3572         return ret;
3573 }
3574
3575 /**
3576  *      t4_flash_erase_sectors - erase a range of flash sectors
3577  *      @adapter: the adapter
3578  *      @start: the first sector to erase
3579  *      @end: the last sector to erase
3580  *
3581  *      Erases the sectors in the given inclusive range.
3582  */
3583 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3584 {
3585         int ret = 0;
3586
3587         if (end >= adapter->params.sf_nsec)
3588                 return -EINVAL;
3589
3590         while (start <= end) {
3591                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3592                     (ret = sf1_write(adapter, 4, 0, 1,
3593                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3594                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3595                         dev_err(adapter->pdev_dev,
3596                                 "erase of flash sector %d failed, error %d\n",
3597                                 start, ret);
3598                         break;
3599                 }
3600                 start++;
3601         }
3602         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3603         return ret;
3604 }
3605
3606 /**
3607  *      t4_flash_cfg_addr - return the address of the flash configuration file
3608  *      @adapter: the adapter
3609  *
3610  *      Return the address within the flash where the Firmware Configuration
3611  *      File is stored.
3612  */
3613 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3614 {
3615         if (adapter->params.sf_size == 0x100000)
3616                 return FLASH_FPGA_CFG_START;
3617         else
3618                 return FLASH_CFG_START;
3619 }
3620
3621 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3622  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3623  * and emit an error message for mismatched firmware to save our caller the
3624  * effort ...
3625  */
3626 static bool t4_fw_matches_chip(const struct adapter *adap,
3627                                const struct fw_hdr *hdr)
3628 {
3629         /* The expression below will return FALSE for any unsupported adapter
3630          * which will keep us "honest" in the future ...
3631          */
3632         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3633             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3634             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3635                 return true;
3636
3637         dev_err(adap->pdev_dev,
3638                 "FW image (%d) is not suitable for this adapter (%d)\n",
3639                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3640         return false;
3641 }
3642
3643 /**
3644  *      t4_load_fw - download firmware
3645  *      @adap: the adapter
3646  *      @fw_data: the firmware image to write
3647  *      @size: image size
3648  *
3649  *      Write the supplied firmware image to the card's serial flash.
3650  */
3651 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3652 {
3653         u32 csum;
3654         int ret, addr;
3655         unsigned int i;
3656         u8 first_page[SF_PAGE_SIZE];
3657         const __be32 *p = (const __be32 *)fw_data;
3658         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3659         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3660         unsigned int fw_start_sec = FLASH_FW_START_SEC;
3661         unsigned int fw_size = FLASH_FW_MAX_SIZE;
3662         unsigned int fw_start = FLASH_FW_START;
3663
3664         if (!size) {
3665                 dev_err(adap->pdev_dev, "FW image has no data\n");
3666                 return -EINVAL;
3667         }
3668         if (size & 511) {
3669                 dev_err(adap->pdev_dev,
3670                         "FW image size not multiple of 512 bytes\n");
3671                 return -EINVAL;
3672         }
3673         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3674                 dev_err(adap->pdev_dev,
3675                         "FW image size differs from size in FW header\n");
3676                 return -EINVAL;
3677         }
3678         if (size > fw_size) {
3679                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3680                         fw_size);
3681                 return -EFBIG;
3682         }
3683         if (!t4_fw_matches_chip(adap, hdr))
3684                 return -EINVAL;
3685
3686         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3687                 csum += be32_to_cpu(p[i]);
3688
3689         if (csum != 0xffffffff) {
3690                 dev_err(adap->pdev_dev,
3691                         "corrupted firmware image, checksum %#x\n", csum);
3692                 return -EINVAL;
3693         }
3694
3695         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3696         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3697         if (ret)
3698                 goto out;
3699
3700         /*
3701          * We write the correct version at the end so the driver can see a bad
3702          * version if the FW write fails.  Start by writing a copy of the
3703          * first page with a bad version.
3704          */
3705         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3706         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3707         ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page);
3708         if (ret)
3709                 goto out;
3710
3711         addr = fw_start;
3712         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3713                 addr += SF_PAGE_SIZE;
3714                 fw_data += SF_PAGE_SIZE;
3715                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3716                 if (ret)
3717                         goto out;
3718         }
3719
3720         ret = t4_write_flash(adap,
3721                              fw_start + offsetof(struct fw_hdr, fw_ver),
3722                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3723 out:
3724         if (ret)
3725                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3726                         ret);
3727         else
3728                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3729         return ret;
3730 }
3731
3732 /**
3733  *      t4_phy_fw_ver - return current PHY firmware version
3734  *      @adap: the adapter
3735  *      @phy_fw_ver: return value buffer for PHY firmware version
3736  *
3737  *      Returns the current version of external PHY firmware on the
3738  *      adapter.
3739  */
3740 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3741 {
3742         u32 param, val;
3743         int ret;
3744
3745         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3746                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3747                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3748                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3749         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3750                               &param, &val);
3751         if (ret)
3752                 return ret;
3753         *phy_fw_ver = val;
3754         return 0;
3755 }
3756
3757 /**
3758  *      t4_load_phy_fw - download port PHY firmware
3759  *      @adap: the adapter
3760  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3761  *      @win_lock: the lock to use to guard the memory copy
3762  *      @phy_fw_version: function to check PHY firmware versions
3763  *      @phy_fw_data: the PHY firmware image to write
3764  *      @phy_fw_size: image size
3765  *
3766  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3767  *      @phy_fw_version is supplied, then it will be used to determine if
3768  *      it's necessary to perform the transfer by comparing the version
3769  *      of any existing adapter PHY firmware with that of the passed in
3770  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3771  *      around the call to t4_memory_rw() which transfers the PHY firmware
3772  *      to the adapter.
3773  *
3774  *      A negative error number will be returned if an error occurs.  If
3775  *      version number support is available and there's no need to upgrade
3776  *      the firmware, 0 will be returned.  If firmware is successfully
3777  *      transferred to the adapter, 1 will be returned.
3778  *
3779  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3780  *      a result, a RESET of the adapter would cause that RAM to lose its
3781  *      contents.  Thus, loading PHY firmware on such adapters must happen
3782  *      after any FW_RESET_CMDs ...
3783  */
3784 int t4_load_phy_fw(struct adapter *adap,
3785                    int win, spinlock_t *win_lock,
3786                    int (*phy_fw_version)(const u8 *, size_t),
3787                    const u8 *phy_fw_data, size_t phy_fw_size)
3788 {
3789         unsigned long mtype = 0, maddr = 0;
3790         u32 param, val;
3791         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3792         int ret;
3793
3794         /* If we have version number support, then check to see if the adapter
3795          * already has up-to-date PHY firmware loaded.
3796          */
3797         if (phy_fw_version) {
3798                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3799                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3800                 if (ret < 0)
3801                         return ret;
3802
3803                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3804                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3805                                 "version %#x\n", cur_phy_fw_ver);
3806                         return 0;
3807                 }
3808         }
3809
3810         /* Ask the firmware where it wants us to copy the PHY firmware image.
3811          * The size of the file requires a special version of the READ command
3812          * which will pass the file size via the values field in PARAMS_CMD and
3813          * retrieve the return value from firmware and place it in the same
3814          * buffer values
3815          */
3816         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3817                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3818                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3819                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3820         val = phy_fw_size;
3821         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3822                                  &param, &val, 1, true);
3823         if (ret < 0)
3824                 return ret;
3825         mtype = val >> 8;
3826         maddr = (val & 0xff) << 16;
3827
3828         /* Copy the supplied PHY Firmware image to the adapter memory location
3829          * allocated by the adapter firmware.
3830          */
3831         if (win_lock)
3832                 spin_lock_bh(win_lock);
3833         ret = t4_memory_rw(adap, win, mtype, maddr,
3834                            phy_fw_size, (__be32 *)phy_fw_data,
3835                            T4_MEMORY_WRITE);
3836         if (win_lock)
3837                 spin_unlock_bh(win_lock);
3838         if (ret)
3839                 return ret;
3840
3841         /* Tell the firmware that the PHY firmware image has been written to
3842          * RAM and it can now start copying it over to the PHYs.  The chip
3843          * firmware will RESET the affected PHYs as part of this operation
3844          * leaving them running the new PHY firmware image.
3845          */
3846         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3847                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3848                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3849                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3850         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3851                                     &param, &val, 30000);
3852
3853         /* If we have version number support, then check to see that the new
3854          * firmware got loaded properly.
3855          */
3856         if (phy_fw_version) {
3857                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3858                 if (ret < 0)
3859                         return ret;
3860
3861                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3862                         CH_WARN(adap, "PHY Firmware did not update: "
3863                                 "version on adapter %#x, "
3864                                 "version flashed %#x\n",
3865                                 cur_phy_fw_ver, new_phy_fw_vers);
3866                         return -ENXIO;
3867                 }
3868         }
3869
3870         return 1;
3871 }
3872
3873 /**
3874  *      t4_fwcache - firmware cache operation
3875  *      @adap: the adapter
3876  *      @op  : the operation (flush or flush and invalidate)
3877  */
3878 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3879 {
3880         struct fw_params_cmd c;
3881
3882         memset(&c, 0, sizeof(c));
3883         c.op_to_vfn =
3884                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3885                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3886                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3887                             FW_PARAMS_CMD_VFN_V(0));
3888         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3889         c.param[0].mnem =
3890                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3891                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3892         c.param[0].val = cpu_to_be32(op);
3893
3894         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3895 }
3896
3897 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3898                         unsigned int *pif_req_wrptr,
3899                         unsigned int *pif_rsp_wrptr)
3900 {
3901         int i, j;
3902         u32 cfg, val, req, rsp;
3903
3904         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3905         if (cfg & LADBGEN_F)
3906                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3907
3908         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3909         req = POLADBGWRPTR_G(val);
3910         rsp = PILADBGWRPTR_G(val);
3911         if (pif_req_wrptr)
3912                 *pif_req_wrptr = req;
3913         if (pif_rsp_wrptr)
3914                 *pif_rsp_wrptr = rsp;
3915
3916         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3917                 for (j = 0; j < 6; j++) {
3918                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3919                                      PILADBGRDPTR_V(rsp));
3920                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3921                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3922                         req++;
3923                         rsp++;
3924                 }
3925                 req = (req + 2) & POLADBGRDPTR_M;
3926                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3927         }
3928         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3929 }
3930
3931 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3932 {
3933         u32 cfg;
3934         int i, j, idx;
3935
3936         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3937         if (cfg & LADBGEN_F)
3938                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3939
3940         for (i = 0; i < CIM_MALA_SIZE; i++) {
3941                 for (j = 0; j < 5; j++) {
3942                         idx = 8 * i + j;
3943                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3944                                      PILADBGRDPTR_V(idx));
3945                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3946                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3947                 }
3948         }
3949         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3950 }
3951
3952 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3953 {
3954         unsigned int i, j;
3955
3956         for (i = 0; i < 8; i++) {
3957                 u32 *p = la_buf + i;
3958
3959                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3960                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3961                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3962                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3963                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3964         }
3965 }
3966
3967 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3968  * Capabilities which we control with separate controls -- see, for instance,
3969  * Pause Frames and Forward Error Correction.  In order to determine what the
3970  * full set of Advertised Port Capabilities are, the base Advertised Port
3971  * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3972  * Port Capabilities associated with those other controls.  See
3973  * t4_link_acaps() for how this is done.
3974  */
3975 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3976                      FW_PORT_CAP32_ANEG)
3977
3978 /**
3979  *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3980  *      @caps16: a 16-bit Port Capabilities value
3981  *
3982  *      Returns the equivalent 32-bit Port Capabilities value.
3983  */
3984 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3985 {
3986         fw_port_cap32_t caps32 = 0;
3987
3988         #define CAP16_TO_CAP32(__cap) \
3989                 do { \
3990                         if (caps16 & FW_PORT_CAP_##__cap) \
3991                                 caps32 |= FW_PORT_CAP32_##__cap; \
3992                 } while (0)
3993
3994         CAP16_TO_CAP32(SPEED_100M);
3995         CAP16_TO_CAP32(SPEED_1G);
3996         CAP16_TO_CAP32(SPEED_25G);
3997         CAP16_TO_CAP32(SPEED_10G);
3998         CAP16_TO_CAP32(SPEED_40G);
3999         CAP16_TO_CAP32(SPEED_100G);
4000         CAP16_TO_CAP32(FC_RX);
4001         CAP16_TO_CAP32(FC_TX);
4002         CAP16_TO_CAP32(ANEG);
4003         CAP16_TO_CAP32(FORCE_PAUSE);
4004         CAP16_TO_CAP32(MDIAUTO);
4005         CAP16_TO_CAP32(MDISTRAIGHT);
4006         CAP16_TO_CAP32(FEC_RS);
4007         CAP16_TO_CAP32(FEC_BASER_RS);
4008         CAP16_TO_CAP32(802_3_PAUSE);
4009         CAP16_TO_CAP32(802_3_ASM_DIR);
4010
4011         #undef CAP16_TO_CAP32
4012
4013         return caps32;
4014 }
4015
4016 /**
4017  *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4018  *      @caps32: a 32-bit Port Capabilities value
4019  *
4020  *      Returns the equivalent 16-bit Port Capabilities value.  Note that
4021  *      not all 32-bit Port Capabilities can be represented in the 16-bit
4022  *      Port Capabilities and some fields/values may not make it.
4023  */
4024 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
4025 {
4026         fw_port_cap16_t caps16 = 0;
4027
4028         #define CAP32_TO_CAP16(__cap) \
4029                 do { \
4030                         if (caps32 & FW_PORT_CAP32_##__cap) \
4031                                 caps16 |= FW_PORT_CAP_##__cap; \
4032                 } while (0)
4033
4034         CAP32_TO_CAP16(SPEED_100M);
4035         CAP32_TO_CAP16(SPEED_1G);
4036         CAP32_TO_CAP16(SPEED_10G);
4037         CAP32_TO_CAP16(SPEED_25G);
4038         CAP32_TO_CAP16(SPEED_40G);
4039         CAP32_TO_CAP16(SPEED_100G);
4040         CAP32_TO_CAP16(FC_RX);
4041         CAP32_TO_CAP16(FC_TX);
4042         CAP32_TO_CAP16(802_3_PAUSE);
4043         CAP32_TO_CAP16(802_3_ASM_DIR);
4044         CAP32_TO_CAP16(ANEG);
4045         CAP32_TO_CAP16(FORCE_PAUSE);
4046         CAP32_TO_CAP16(MDIAUTO);
4047         CAP32_TO_CAP16(MDISTRAIGHT);
4048         CAP32_TO_CAP16(FEC_RS);
4049         CAP32_TO_CAP16(FEC_BASER_RS);
4050
4051         #undef CAP32_TO_CAP16
4052
4053         return caps16;
4054 }
4055
4056 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4057 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4058 {
4059         enum cc_pause cc_pause = 0;
4060
4061         if (fw_pause & FW_PORT_CAP32_FC_RX)
4062                 cc_pause |= PAUSE_RX;
4063         if (fw_pause & FW_PORT_CAP32_FC_TX)
4064                 cc_pause |= PAUSE_TX;
4065
4066         return cc_pause;
4067 }
4068
4069 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4070 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4071 {
4072         /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4073          * commands, etc.
4074          */
4075         fw_port_cap32_t fw_pause = 0;
4076
4077         if (cc_pause & PAUSE_RX)
4078                 fw_pause |= FW_PORT_CAP32_FC_RX;
4079         if (cc_pause & PAUSE_TX)
4080                 fw_pause |= FW_PORT_CAP32_FC_TX;
4081         if (!(cc_pause & PAUSE_AUTONEG))
4082                 fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4083
4084         /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4085          * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4086          * Note that these bits are ignored in L1 Configure commands.
4087          */
4088         if (cc_pause & PAUSE_RX) {
4089                 if (cc_pause & PAUSE_TX)
4090                         fw_pause |= FW_PORT_CAP32_802_3_PAUSE;
4091                 else
4092                         fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR |
4093                                     FW_PORT_CAP32_802_3_PAUSE;
4094         } else if (cc_pause & PAUSE_TX) {
4095                 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR;
4096         }
4097
4098         return fw_pause;
4099 }
4100
4101 /* Translate Firmware Forward Error Correction specification to Common Code */
4102 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4103 {
4104         enum cc_fec cc_fec = 0;
4105
4106         if (fw_fec & FW_PORT_CAP32_FEC_RS)
4107                 cc_fec |= FEC_RS;
4108         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4109                 cc_fec |= FEC_BASER_RS;
4110
4111         return cc_fec;
4112 }
4113
4114 /* Translate Common Code Forward Error Correction specification to Firmware */
4115 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4116 {
4117         fw_port_cap32_t fw_fec = 0;
4118
4119         if (cc_fec & FEC_RS)
4120                 fw_fec |= FW_PORT_CAP32_FEC_RS;
4121         if (cc_fec & FEC_BASER_RS)
4122                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4123
4124         return fw_fec;
4125 }
4126
4127 /**
4128  *      t4_link_acaps - compute Link Advertised Port Capabilities
4129  *      @adapter: the adapter
4130  *      @port: the Port ID
4131  *      @lc: the Port's Link Configuration
4132  *
4133  *      Synthesize the Advertised Port Capabilities we'll be using based on
4134  *      the base Advertised Port Capabilities (which have been filtered by
4135  *      ADVERT_MASK) plus the individual controls for things like Pause
4136  *      Frames, Forward Error Correction, MDI, etc.
4137  */
4138 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
4139                               struct link_config *lc)
4140 {
4141         fw_port_cap32_t fw_fc, fw_fec, acaps;
4142         unsigned int fw_mdi;
4143         char cc_fec;
4144
4145         fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4146
4147         /* Convert driver coding of Pause Frame Flow Control settings into the
4148          * Firmware's API.
4149          */
4150         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4151
4152         /* Convert Common Code Forward Error Control settings into the
4153          * Firmware's API.  If the current Requested FEC has "Automatic"
4154          * (IEEE 802.3) specified, then we use whatever the Firmware
4155          * sent us as part of its IEEE 802.3-based interpretation of
4156          * the Transceiver Module EPROM FEC parameters.  Otherwise we
4157          * use whatever is in the current Requested FEC settings.
4158          */
4159         if (lc->requested_fec & FEC_AUTO)
4160                 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4161         else
4162                 cc_fec = lc->requested_fec;
4163         fw_fec = cc_to_fwcap_fec(cc_fec);
4164
4165         /* Figure out what our Requested Port Capabilities are going to be.
4166          * Note parallel structure in t4_handle_get_port_info() and
4167          * init_link_config().
4168          */
4169         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4170                 acaps = lc->acaps | fw_fc | fw_fec;
4171                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4172                 lc->fec = cc_fec;
4173         } else if (lc->autoneg == AUTONEG_DISABLE) {
4174                 acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4175                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4176                 lc->fec = cc_fec;
4177         } else {
4178                 acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
4179         }
4180
4181         /* Some Requested Port Capabilities are trivially wrong if they exceed
4182          * the Physical Port Capabilities.  We can check that here and provide
4183          * moderately useful feedback in the system log.
4184          *
4185          * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4186          * we need to exclude this from this check in order to maintain
4187          * compatibility ...
4188          */
4189         if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4190                 dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4191                         acaps, lc->pcaps);
4192                 return -EINVAL;
4193         }
4194
4195         return acaps;
4196 }
4197
4198 /**
4199  *      t4_link_l1cfg_core - apply link configuration to MAC/PHY
4200  *      @adapter: the adapter
4201  *      @mbox: the Firmware Mailbox to use
4202  *      @port: the Port ID
4203  *      @lc: the Port's Link Configuration
4204  *      @sleep_ok: if true we may sleep while awaiting command completion
4205  *      @timeout: time to wait for command to finish before timing out
4206  *              (negative implies @sleep_ok=false)
4207  *
4208  *      Set up a port's MAC and PHY according to a desired link configuration.
4209  *      - If the PHY can auto-negotiate first decide what to advertise, then
4210  *        enable/disable auto-negotiation as desired, and reset.
4211  *      - If the PHY does not auto-negotiate just reset it.
4212  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4213  *        otherwise do it later based on the outcome of auto-negotiation.
4214  */
4215 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4216                        unsigned int port, struct link_config *lc,
4217                        u8 sleep_ok, int timeout)
4218 {
4219         unsigned int fw_caps = adapter->params.fw_caps_support;
4220         struct fw_port_cmd cmd;
4221         fw_port_cap32_t rcap;
4222         int ret;
4223
4224         if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
4225             lc->autoneg == AUTONEG_ENABLE) {
4226                 return -EINVAL;
4227         }
4228
4229         /* Compute our Requested Port Capabilities and send that on to the
4230          * Firmware.
4231          */
4232         rcap = t4_link_acaps(adapter, port, lc);
4233         memset(&cmd, 0, sizeof(cmd));
4234         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4235                                        FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4236                                        FW_PORT_CMD_PORTID_V(port));
4237         cmd.action_to_len16 =
4238                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4239                                                  ? FW_PORT_ACTION_L1_CFG
4240                                                  : FW_PORT_ACTION_L1_CFG32) |
4241                                                  FW_LEN16(cmd));
4242         if (fw_caps == FW_CAPS16)
4243                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4244         else
4245                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4246
4247         ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4248                                       sleep_ok, timeout);
4249
4250         /* Unfortunately, even if the Requested Port Capabilities "fit" within
4251          * the Physical Port Capabilities, some combinations of features may
4252          * still not be legal.  For example, 40Gb/s and Reed-Solomon Forward
4253          * Error Correction.  So if the Firmware rejects the L1 Configure
4254          * request, flag that here.
4255          */
4256         if (ret) {
4257                 dev_err(adapter->pdev_dev,
4258                         "Requested Port Capabilities %#x rejected, error %d\n",
4259                         rcap, -ret);
4260                 return ret;
4261         }
4262         return 0;
4263 }
4264
4265 /**
4266  *      t4_restart_aneg - restart autonegotiation
4267  *      @adap: the adapter
4268  *      @mbox: mbox to use for the FW command
4269  *      @port: the port id
4270  *
4271  *      Restarts autonegotiation for the selected port.
4272  */
4273 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4274 {
4275         unsigned int fw_caps = adap->params.fw_caps_support;
4276         struct fw_port_cmd c;
4277
4278         memset(&c, 0, sizeof(c));
4279         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4280                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4281                                      FW_PORT_CMD_PORTID_V(port));
4282         c.action_to_len16 =
4283                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4284                                                  ? FW_PORT_ACTION_L1_CFG
4285                                                  : FW_PORT_ACTION_L1_CFG32) |
4286                             FW_LEN16(c));
4287         if (fw_caps == FW_CAPS16)
4288                 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4289         else
4290                 c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
4291         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4292 }
4293
4294 typedef void (*int_handler_t)(struct adapter *adap);
4295
4296 struct intr_info {
4297         unsigned int mask;       /* bits to check in interrupt status */
4298         const char *msg;         /* message to print or NULL */
4299         short stat_idx;          /* stat counter to increment or -1 */
4300         unsigned short fatal;    /* whether the condition reported is fatal */
4301         int_handler_t int_handler; /* platform-specific int handler */
4302 };
4303
4304 /**
4305  *      t4_handle_intr_status - table driven interrupt handler
4306  *      @adapter: the adapter that generated the interrupt
4307  *      @reg: the interrupt status register to process
4308  *      @acts: table of interrupt actions
4309  *
4310  *      A table driven interrupt handler that applies a set of masks to an
4311  *      interrupt status word and performs the corresponding actions if the
4312  *      interrupts described by the mask have occurred.  The actions include
4313  *      optionally emitting a warning or alert message.  The table is terminated
4314  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4315  *      conditions.
4316  */
4317 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4318                                  const struct intr_info *acts)
4319 {
4320         int fatal = 0;
4321         unsigned int mask = 0;
4322         unsigned int status = t4_read_reg(adapter, reg);
4323
4324         for ( ; acts->mask; ++acts) {
4325                 if (!(status & acts->mask))
4326                         continue;
4327                 if (acts->fatal) {
4328                         fatal++;
4329                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4330                                   status & acts->mask);
4331                 } else if (acts->msg && printk_ratelimit())
4332                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4333                                  status & acts->mask);
4334                 if (acts->int_handler)
4335                         acts->int_handler(adapter);
4336                 mask |= acts->mask;
4337         }
4338         status &= mask;
4339         if (status)                           /* clear processed interrupts */
4340                 t4_write_reg(adapter, reg, status);
4341         return fatal;
4342 }
4343
4344 /*
4345  * Interrupt handler for the PCIE module.
4346  */
4347 static void pcie_intr_handler(struct adapter *adapter)
4348 {
4349         static const struct intr_info sysbus_intr_info[] = {
4350                 { RNPP_F, "RXNP array parity error", -1, 1 },
4351                 { RPCP_F, "RXPC array parity error", -1, 1 },
4352                 { RCIP_F, "RXCIF array parity error", -1, 1 },
4353                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4354                 { RFTP_F, "RXFT array parity error", -1, 1 },
4355                 { 0 }
4356         };
4357         static const struct intr_info pcie_port_intr_info[] = {
4358                 { TPCP_F, "TXPC array parity error", -1, 1 },
4359                 { TNPP_F, "TXNP array parity error", -1, 1 },
4360                 { TFTP_F, "TXFT array parity error", -1, 1 },
4361                 { TCAP_F, "TXCA array parity error", -1, 1 },
4362                 { TCIP_F, "TXCIF array parity error", -1, 1 },
4363                 { RCAP_F, "RXCA array parity error", -1, 1 },
4364                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4365                 { RDPE_F, "Rx data parity error", -1, 1 },
4366                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4367                 { 0 }
4368         };
4369         static const struct intr_info pcie_intr_info[] = {
4370                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4371                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4372                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4373                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4374                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4375                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4376                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4377                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4378                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4379                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4380                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4381                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4382                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4383                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4384                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4385                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4386                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4387                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4388                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4389                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4390                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4391                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4392                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4393                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4394                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4395                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4396                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4397                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4398                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4399                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4400                   -1, 0 },
4401                 { 0 }
4402         };
4403
4404         static struct intr_info t5_pcie_intr_info[] = {
4405                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4406                   -1, 1 },
4407                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4408                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4409                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4410                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4411                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4412                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4413                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4414                   -1, 1 },
4415                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4416                   -1, 1 },
4417                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4418                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4419                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4420                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4421                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4422                   -1, 1 },
4423                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4424                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4425                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4426                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4427                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4428                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4429                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4430                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4431                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4432                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4433                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4434                   -1, 1 },
4435                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4436                   -1, 1 },
4437                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4438                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4439                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4440                 { READRSPERR_F, "Outbound read error", -1, 0 },
4441                 { 0 }
4442         };
4443
4444         int fat;
4445
4446         if (is_t4(adapter->params.chip))
4447                 fat = t4_handle_intr_status(adapter,
4448                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4449                                 sysbus_intr_info) +
4450                         t4_handle_intr_status(adapter,
4451                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4452                                         pcie_port_intr_info) +
4453                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4454                                               pcie_intr_info);
4455         else
4456                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4457                                             t5_pcie_intr_info);
4458
4459         if (fat)
4460                 t4_fatal_err(adapter);
4461 }
4462
4463 /*
4464  * TP interrupt handler.
4465  */
4466 static void tp_intr_handler(struct adapter *adapter)
4467 {
4468         static const struct intr_info tp_intr_info[] = {
4469                 { 0x3fffffff, "TP parity error", -1, 1 },
4470                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4471                 { 0 }
4472         };
4473
4474         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4475                 t4_fatal_err(adapter);
4476 }
4477
4478 /*
4479  * SGE interrupt handler.
4480  */
4481 static void sge_intr_handler(struct adapter *adapter)
4482 {
4483         u64 v;
4484         u32 err;
4485
4486         static const struct intr_info sge_intr_info[] = {
4487                 { ERR_CPL_EXCEED_IQE_SIZE_F,
4488                   "SGE received CPL exceeding IQE size", -1, 1 },
4489                 { ERR_INVALID_CIDX_INC_F,
4490                   "SGE GTS CIDX increment too large", -1, 0 },
4491                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4492                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4493                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4494                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
4495                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4496                   0 },
4497                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4498                   0 },
4499                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4500                   0 },
4501                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4502                   0 },
4503                 { ERR_ING_CTXT_PRIO_F,
4504                   "SGE too many priority ingress contexts", -1, 0 },
4505                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4506                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4507                 { 0 }
4508         };
4509
4510         static struct intr_info t4t5_sge_intr_info[] = {
4511                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4512                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4513                 { ERR_EGR_CTXT_PRIO_F,
4514                   "SGE too many priority egress contexts", -1, 0 },
4515                 { 0 }
4516         };
4517
4518         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4519                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4520         if (v) {
4521                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4522                                 (unsigned long long)v);
4523                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4524                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4525         }
4526
4527         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4528         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4529                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4530                                            t4t5_sge_intr_info);
4531
4532         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4533         if (err & ERROR_QID_VALID_F) {
4534                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4535                         ERROR_QID_G(err));
4536                 if (err & UNCAPTURED_ERROR_F)
4537                         dev_err(adapter->pdev_dev,
4538                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4539                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4540                              UNCAPTURED_ERROR_F);
4541         }
4542
4543         if (v != 0)
4544                 t4_fatal_err(adapter);
4545 }
4546
4547 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4548                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4549 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4550                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4551
4552 /*
4553  * CIM interrupt handler.
4554  */
4555 static void cim_intr_handler(struct adapter *adapter)
4556 {
4557         static const struct intr_info cim_intr_info[] = {
4558                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4559                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4560                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4561                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4562                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4563                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4564                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4565                 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4566                 { 0 }
4567         };
4568         static const struct intr_info cim_upintr_info[] = {
4569                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4570                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4571                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4572                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4573                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4574                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4575                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4576                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4577                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4578                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4579                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4580                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4581                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4582                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4583                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4584                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4585                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4586                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4587                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4588                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4589                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4590                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4591                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4592                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4593                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4594                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4595                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4596                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4597                 { 0 }
4598         };
4599
4600         u32 val, fw_err;
4601         int fat;
4602
4603         fw_err = t4_read_reg(adapter, PCIE_FW_A);
4604         if (fw_err & PCIE_FW_ERR_F)
4605                 t4_report_fw_error(adapter);
4606
4607         /* When the Firmware detects an internal error which normally
4608          * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4609          * in order to make sure the Host sees the Firmware Crash.  So
4610          * if we have a Timer0 interrupt and don't see a Firmware Crash,
4611          * ignore the Timer0 interrupt.
4612          */
4613
4614         val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4615         if (val & TIMER0INT_F)
4616                 if (!(fw_err & PCIE_FW_ERR_F) ||
4617                     (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4618                         t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4619                                      TIMER0INT_F);
4620
4621         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4622                                     cim_intr_info) +
4623               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4624                                     cim_upintr_info);
4625         if (fat)
4626                 t4_fatal_err(adapter);
4627 }
4628
4629 /*
4630  * ULP RX interrupt handler.
4631  */
4632 static void ulprx_intr_handler(struct adapter *adapter)
4633 {
4634         static const struct intr_info ulprx_intr_info[] = {
4635                 { 0x1800000, "ULPRX context error", -1, 1 },
4636                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4637                 { 0 }
4638         };
4639
4640         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4641                 t4_fatal_err(adapter);
4642 }
4643
4644 /*
4645  * ULP TX interrupt handler.
4646  */
4647 static void ulptx_intr_handler(struct adapter *adapter)
4648 {
4649         static const struct intr_info ulptx_intr_info[] = {
4650                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4651                   0 },
4652                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4653                   0 },
4654                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4655                   0 },
4656                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4657                   0 },
4658                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4659                 { 0 }
4660         };
4661
4662         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4663                 t4_fatal_err(adapter);
4664 }
4665
4666 /*
4667  * PM TX interrupt handler.
4668  */
4669 static void pmtx_intr_handler(struct adapter *adapter)
4670 {
4671         static const struct intr_info pmtx_intr_info[] = {
4672                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4673                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4674                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4675                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4676                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4677                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4678                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4679                   -1, 1 },
4680                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4681                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4682                 { 0 }
4683         };
4684
4685         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4686                 t4_fatal_err(adapter);
4687 }
4688
4689 /*
4690  * PM RX interrupt handler.
4691  */
4692 static void pmrx_intr_handler(struct adapter *adapter)
4693 {
4694         static const struct intr_info pmrx_intr_info[] = {
4695                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4696                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4697                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4698                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4699                   -1, 1 },
4700                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4701                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4702                 { 0 }
4703         };
4704
4705         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4706                 t4_fatal_err(adapter);
4707 }
4708
4709 /*
4710  * CPL switch interrupt handler.
4711  */
4712 static void cplsw_intr_handler(struct adapter *adapter)
4713 {
4714         static const struct intr_info cplsw_intr_info[] = {
4715                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4716                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4717                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4718                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4719                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4720                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4721                 { 0 }
4722         };
4723
4724         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4725                 t4_fatal_err(adapter);
4726 }
4727
4728 /*
4729  * LE interrupt handler.
4730  */
4731 static void le_intr_handler(struct adapter *adap)
4732 {
4733         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4734         static const struct intr_info le_intr_info[] = {
4735                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4736                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4737                 { PARITYERR_F, "LE parity error", -1, 1 },
4738                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4739                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4740                 { 0 }
4741         };
4742
4743         static struct intr_info t6_le_intr_info[] = {
4744                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4745                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4746                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4747                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4748                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4749                 { 0 }
4750         };
4751
4752         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4753                                   (chip <= CHELSIO_T5) ?
4754                                   le_intr_info : t6_le_intr_info))
4755                 t4_fatal_err(adap);
4756 }
4757
4758 /*
4759  * MPS interrupt handler.
4760  */
4761 static void mps_intr_handler(struct adapter *adapter)
4762 {
4763         static const struct intr_info mps_rx_intr_info[] = {
4764                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4765                 { 0 }
4766         };
4767         static const struct intr_info mps_tx_intr_info[] = {
4768                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4769                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4770                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4771                   -1, 1 },
4772                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4773                   -1, 1 },
4774                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4775                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4776                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4777                 { 0 }
4778         };
4779         static const struct intr_info t6_mps_tx_intr_info[] = {
4780                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4781                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4782                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4783                   -1, 1 },
4784                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4785                   -1, 1 },
4786                 /* MPS Tx Bubble is normal for T6 */
4787                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4788                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4789                 { 0 }
4790         };
4791         static const struct intr_info mps_trc_intr_info[] = {
4792                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4793                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4794                   -1, 1 },
4795                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4796                 { 0 }
4797         };
4798         static const struct intr_info mps_stat_sram_intr_info[] = {
4799                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4800                 { 0 }
4801         };
4802         static const struct intr_info mps_stat_tx_intr_info[] = {
4803                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4804                 { 0 }
4805         };
4806         static const struct intr_info mps_stat_rx_intr_info[] = {
4807                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4808                 { 0 }
4809         };
4810         static const struct intr_info mps_cls_intr_info[] = {
4811                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4812                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4813                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4814                 { 0 }
4815         };
4816
4817         int fat;
4818
4819         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4820                                     mps_rx_intr_info) +
4821               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4822                                     is_t6(adapter->params.chip)
4823                                     ? t6_mps_tx_intr_info
4824                                     : mps_tx_intr_info) +
4825               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4826                                     mps_trc_intr_info) +
4827               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4828                                     mps_stat_sram_intr_info) +
4829               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4830                                     mps_stat_tx_intr_info) +
4831               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4832                                     mps_stat_rx_intr_info) +
4833               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4834                                     mps_cls_intr_info);
4835
4836         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4837         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4838         if (fat)
4839                 t4_fatal_err(adapter);
4840 }
4841
4842 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4843                       ECC_UE_INT_CAUSE_F)
4844
4845 /*
4846  * EDC/MC interrupt handler.
4847  */
4848 static void mem_intr_handler(struct adapter *adapter, int idx)
4849 {
4850         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4851
4852         unsigned int addr, cnt_addr, v;
4853
4854         if (idx <= MEM_EDC1) {
4855                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4856                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4857         } else if (idx == MEM_MC) {
4858                 if (is_t4(adapter->params.chip)) {
4859                         addr = MC_INT_CAUSE_A;
4860                         cnt_addr = MC_ECC_STATUS_A;
4861                 } else {
4862                         addr = MC_P_INT_CAUSE_A;
4863                         cnt_addr = MC_P_ECC_STATUS_A;
4864                 }
4865         } else {
4866                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4867                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4868         }
4869
4870         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4871         if (v & PERR_INT_CAUSE_F)
4872                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4873                           name[idx]);
4874         if (v & ECC_CE_INT_CAUSE_F) {
4875                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4876
4877                 t4_edc_err_read(adapter, idx);
4878
4879                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4880                 if (printk_ratelimit())
4881                         dev_warn(adapter->pdev_dev,
4882                                  "%u %s correctable ECC data error%s\n",
4883                                  cnt, name[idx], cnt > 1 ? "s" : "");
4884         }
4885         if (v & ECC_UE_INT_CAUSE_F)
4886                 dev_alert(adapter->pdev_dev,
4887                           "%s uncorrectable ECC data error\n", name[idx]);
4888
4889         t4_write_reg(adapter, addr, v);
4890         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4891                 t4_fatal_err(adapter);
4892 }
4893
4894 /*
4895  * MA interrupt handler.
4896  */
4897 static void ma_intr_handler(struct adapter *adap)
4898 {
4899         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4900
4901         if (status & MEM_PERR_INT_CAUSE_F) {
4902                 dev_alert(adap->pdev_dev,
4903                           "MA parity error, parity status %#x\n",
4904                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4905                 if (is_t5(adap->params.chip))
4906                         dev_alert(adap->pdev_dev,
4907                                   "MA parity error, parity status %#x\n",
4908                                   t4_read_reg(adap,
4909                                               MA_PARITY_ERROR_STATUS2_A));
4910         }
4911         if (status & MEM_WRAP_INT_CAUSE_F) {
4912                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4913                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4914                           "client %u to address %#x\n",
4915                           MEM_WRAP_CLIENT_NUM_G(v),
4916                           MEM_WRAP_ADDRESS_G(v) << 4);
4917         }
4918         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4919         t4_fatal_err(adap);
4920 }
4921
4922 /*
4923  * SMB interrupt handler.
4924  */
4925 static void smb_intr_handler(struct adapter *adap)
4926 {
4927         static const struct intr_info smb_intr_info[] = {
4928                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4929                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4930                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4931                 { 0 }
4932         };
4933
4934         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4935                 t4_fatal_err(adap);
4936 }
4937
4938 /*
4939  * NC-SI interrupt handler.
4940  */
4941 static void ncsi_intr_handler(struct adapter *adap)
4942 {
4943         static const struct intr_info ncsi_intr_info[] = {
4944                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4945                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4946                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4947                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4948                 { 0 }
4949         };
4950
4951         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4952                 t4_fatal_err(adap);
4953 }
4954
4955 /*
4956  * XGMAC interrupt handler.
4957  */
4958 static void xgmac_intr_handler(struct adapter *adap, int port)
4959 {
4960         u32 v, int_cause_reg;
4961
4962         if (is_t4(adap->params.chip))
4963                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4964         else
4965                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4966
4967         v = t4_read_reg(adap, int_cause_reg);
4968
4969         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4970         if (!v)
4971                 return;
4972
4973         if (v & TXFIFO_PRTY_ERR_F)
4974                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4975                           port);
4976         if (v & RXFIFO_PRTY_ERR_F)
4977                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4978                           port);
4979         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4980         t4_fatal_err(adap);
4981 }
4982
4983 /*
4984  * PL interrupt handler.
4985  */
4986 static void pl_intr_handler(struct adapter *adap)
4987 {
4988         static const struct intr_info pl_intr_info[] = {
4989                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4990                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4991                 { 0 }
4992         };
4993
4994         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4995                 t4_fatal_err(adap);
4996 }
4997
4998 #define PF_INTR_MASK (PFSW_F)
4999 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
5000                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5001                 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5002
5003 /**
5004  *      t4_slow_intr_handler - control path interrupt handler
5005  *      @adapter: the adapter
5006  *
5007  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
5008  *      The designation 'slow' is because it involves register reads, while
5009  *      data interrupts typically don't involve any MMIOs.
5010  */
5011 int t4_slow_intr_handler(struct adapter *adapter)
5012 {
5013         /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5014          * set when the corresponding PL_INT_ENABLE bit isn't set.  It's
5015          * easiest just to mask that case here.
5016          */
5017         u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
5018         u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
5019         u32 cause = raw_cause & enable;
5020
5021         if (!(cause & GLBL_INTR_MASK))
5022                 return 0;
5023         if (cause & CIM_F)
5024                 cim_intr_handler(adapter);
5025         if (cause & MPS_F)
5026                 mps_intr_handler(adapter);
5027         if (cause & NCSI_F)
5028                 ncsi_intr_handler(adapter);
5029         if (cause & PL_F)
5030                 pl_intr_handler(adapter);
5031         if (cause & SMB_F)
5032                 smb_intr_handler(adapter);
5033         if (cause & XGMAC0_F)
5034                 xgmac_intr_handler(adapter, 0);
5035         if (cause & XGMAC1_F)
5036                 xgmac_intr_handler(adapter, 1);
5037         if (cause & XGMAC_KR0_F)
5038                 xgmac_intr_handler(adapter, 2);
5039         if (cause & XGMAC_KR1_F)
5040                 xgmac_intr_handler(adapter, 3);
5041         if (cause & PCIE_F)
5042                 pcie_intr_handler(adapter);
5043         if (cause & MC_F)
5044                 mem_intr_handler(adapter, MEM_MC);
5045         if (is_t5(adapter->params.chip) && (cause & MC1_F))
5046                 mem_intr_handler(adapter, MEM_MC1);
5047         if (cause & EDC0_F)
5048                 mem_intr_handler(adapter, MEM_EDC0);
5049         if (cause & EDC1_F)
5050                 mem_intr_handler(adapter, MEM_EDC1);
5051         if (cause & LE_F)
5052                 le_intr_handler(adapter);
5053         if (cause & TP_F)
5054                 tp_intr_handler(adapter);
5055         if (cause & MA_F)
5056                 ma_intr_handler(adapter);
5057         if (cause & PM_TX_F)
5058                 pmtx_intr_handler(adapter);
5059         if (cause & PM_RX_F)
5060                 pmrx_intr_handler(adapter);
5061         if (cause & ULP_RX_F)
5062                 ulprx_intr_handler(adapter);
5063         if (cause & CPL_SWITCH_F)
5064                 cplsw_intr_handler(adapter);
5065         if (cause & SGE_F)
5066                 sge_intr_handler(adapter);
5067         if (cause & ULP_TX_F)
5068                 ulptx_intr_handler(adapter);
5069
5070         /* Clear the interrupts just processed for which we are the master. */
5071         t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
5072         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
5073         return 1;
5074 }
5075
5076 /**
5077  *      t4_intr_enable - enable interrupts
5078  *      @adapter: the adapter whose interrupts should be enabled
5079  *
5080  *      Enable PF-specific interrupts for the calling function and the top-level
5081  *      interrupt concentrator for global interrupts.  Interrupts are already
5082  *      enabled at each module, here we just enable the roots of the interrupt
5083  *      hierarchies.
5084  *
5085  *      Note: this function should be called only when the driver manages
5086  *      non PF-specific interrupts from the various HW modules.  Only one PCI
5087  *      function at a time should be doing this.
5088  */
5089 void t4_intr_enable(struct adapter *adapter)
5090 {
5091         u32 val = 0;
5092         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5093         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5094                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5095
5096         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
5097                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
5098         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
5099                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
5100                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
5101                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
5102                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
5103                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
5104                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
5105         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
5106         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
5107 }
5108
5109 /**
5110  *      t4_intr_disable - disable interrupts
5111  *      @adapter: the adapter whose interrupts should be disabled
5112  *
5113  *      Disable interrupts.  We only disable the top-level interrupt
5114  *      concentrators.  The caller must be a PCI function managing global
5115  *      interrupts.
5116  */
5117 void t4_intr_disable(struct adapter *adapter)
5118 {
5119         u32 whoami, pf;
5120
5121         if (pci_channel_offline(adapter->pdev))
5122                 return;
5123
5124         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5125         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5126                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5127
5128         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
5129         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5130 }
5131
5132 unsigned int t4_chip_rss_size(struct adapter *adap)
5133 {
5134         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5135                 return RSS_NENTRIES;
5136         else
5137                 return T6_RSS_NENTRIES;
5138 }
5139
5140 /**
5141  *      t4_config_rss_range - configure a portion of the RSS mapping table
5142  *      @adapter: the adapter
5143  *      @mbox: mbox to use for the FW command
5144  *      @viid: virtual interface whose RSS subtable is to be written
5145  *      @start: start entry in the table to write
5146  *      @n: how many table entries to write
5147  *      @rspq: values for the response queue lookup table
5148  *      @nrspq: number of values in @rspq
5149  *
5150  *      Programs the selected part of the VI's RSS mapping table with the
5151  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
5152  *      until the full table range is populated.
5153  *
5154  *      The caller must ensure the values in @rspq are in the range allowed for
5155  *      @viid.
5156  */
5157 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5158                         int start, int n, const u16 *rspq, unsigned int nrspq)
5159 {
5160         int ret;
5161         const u16 *rsp = rspq;
5162         const u16 *rsp_end = rspq + nrspq;
5163         struct fw_rss_ind_tbl_cmd cmd;
5164
5165         memset(&cmd, 0, sizeof(cmd));
5166         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5167                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5168                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
5169         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5170
5171         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5172         while (n > 0) {
5173                 int nq = min(n, 32);
5174                 __be32 *qp = &cmd.iq0_to_iq2;
5175
5176                 cmd.niqid = cpu_to_be16(nq);
5177                 cmd.startidx = cpu_to_be16(start);
5178
5179                 start += nq;
5180                 n -= nq;
5181
5182                 while (nq > 0) {
5183                         unsigned int v;
5184
5185                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5186                         if (++rsp >= rsp_end)
5187                                 rsp = rspq;
5188                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5189                         if (++rsp >= rsp_end)
5190                                 rsp = rspq;
5191                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5192                         if (++rsp >= rsp_end)
5193                                 rsp = rspq;
5194
5195                         *qp++ = cpu_to_be32(v);
5196                         nq -= 3;
5197                 }
5198
5199                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5200                 if (ret)
5201                         return ret;
5202         }
5203         return 0;
5204 }
5205
5206 /**
5207  *      t4_config_glbl_rss - configure the global RSS mode
5208  *      @adapter: the adapter
5209  *      @mbox: mbox to use for the FW command
5210  *      @mode: global RSS mode
5211  *      @flags: mode-specific flags
5212  *
5213  *      Sets the global RSS mode.
5214  */
5215 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5216                        unsigned int flags)
5217 {
5218         struct fw_rss_glb_config_cmd c;
5219
5220         memset(&c, 0, sizeof(c));
5221         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5222                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5223         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5224         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5225                 c.u.manual.mode_pkd =
5226                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5227         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5228                 c.u.basicvirtual.mode_pkd =
5229                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5230                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5231         } else
5232                 return -EINVAL;
5233         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5234 }
5235
5236 /**
5237  *      t4_config_vi_rss - configure per VI RSS settings
5238  *      @adapter: the adapter
5239  *      @mbox: mbox to use for the FW command
5240  *      @viid: the VI id
5241  *      @flags: RSS flags
5242  *      @defq: id of the default RSS queue for the VI.
5243  *
5244  *      Configures VI-specific RSS properties.
5245  */
5246 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5247                      unsigned int flags, unsigned int defq)
5248 {
5249         struct fw_rss_vi_config_cmd c;
5250
5251         memset(&c, 0, sizeof(c));
5252         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5253                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5254                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5255         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5256         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5257                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5258         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5259 }
5260
5261 /* Read an RSS table row */
5262 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5263 {
5264         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5265         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5266                                    5, 0, val);
5267 }
5268
5269 /**
5270  *      t4_read_rss - read the contents of the RSS mapping table
5271  *      @adapter: the adapter
5272  *      @map: holds the contents of the RSS mapping table
5273  *
5274  *      Reads the contents of the RSS hash->queue mapping table.
5275  */
5276 int t4_read_rss(struct adapter *adapter, u16 *map)
5277 {
5278         int i, ret, nentries;
5279         u32 val;
5280
5281         nentries = t4_chip_rss_size(adapter);
5282         for (i = 0; i < nentries / 2; ++i) {
5283                 ret = rd_rss_row(adapter, i, &val);
5284                 if (ret)
5285                         return ret;
5286                 *map++ = LKPTBLQUEUE0_G(val);
5287                 *map++ = LKPTBLQUEUE1_G(val);
5288         }
5289         return 0;
5290 }
5291
5292 static unsigned int t4_use_ldst(struct adapter *adap)
5293 {
5294         return (adap->flags & CXGB4_FW_OK) && !adap->use_bd;
5295 }
5296
5297 /**
5298  * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5299  * @adap: the adapter
5300  * @cmd: TP fw ldst address space type
5301  * @vals: where the indirect register values are stored/written
5302  * @nregs: how many indirect registers to read/write
5303  * @start_idx: index of first indirect register to read/write
5304  * @rw: Read (1) or Write (0)
5305  * @sleep_ok: if true we may sleep while awaiting command completion
5306  *
5307  * Access TP indirect registers through LDST
5308  */
5309 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5310                             unsigned int nregs, unsigned int start_index,
5311                             unsigned int rw, bool sleep_ok)
5312 {
5313         int ret = 0;
5314         unsigned int i;
5315         struct fw_ldst_cmd c;
5316
5317         for (i = 0; i < nregs; i++) {
5318                 memset(&c, 0, sizeof(c));
5319                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5320                                                 FW_CMD_REQUEST_F |
5321                                                 (rw ? FW_CMD_READ_F :
5322                                                       FW_CMD_WRITE_F) |
5323                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
5324                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5325
5326                 c.u.addrval.addr = cpu_to_be32(start_index + i);
5327                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5328                 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5329                                       sleep_ok);
5330                 if (ret)
5331                         return ret;
5332
5333                 if (rw)
5334                         vals[i] = be32_to_cpu(c.u.addrval.val);
5335         }
5336         return 0;
5337 }
5338
5339 /**
5340  * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5341  * @adap: the adapter
5342  * @reg_addr: Address Register
5343  * @reg_data: Data register
5344  * @buff: where the indirect register values are stored/written
5345  * @nregs: how many indirect registers to read/write
5346  * @start_index: index of first indirect register to read/write
5347  * @rw: READ(1) or WRITE(0)
5348  * @sleep_ok: if true we may sleep while awaiting command completion
5349  *
5350  * Read/Write TP indirect registers through LDST if possible.
5351  * Else, use backdoor access
5352  **/
5353 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5354                               u32 *buff, u32 nregs, u32 start_index, int rw,
5355                               bool sleep_ok)
5356 {
5357         int rc = -EINVAL;
5358         int cmd;
5359
5360         switch (reg_addr) {
5361         case TP_PIO_ADDR_A:
5362                 cmd = FW_LDST_ADDRSPC_TP_PIO;
5363                 break;
5364         case TP_TM_PIO_ADDR_A:
5365                 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5366                 break;
5367         case TP_MIB_INDEX_A:
5368                 cmd = FW_LDST_ADDRSPC_TP_MIB;
5369                 break;
5370         default:
5371                 goto indirect_access;
5372         }
5373
5374         if (t4_use_ldst(adap))
5375                 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5376                                       sleep_ok);
5377
5378 indirect_access:
5379
5380         if (rc) {
5381                 if (rw)
5382                         t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5383                                          start_index);
5384                 else
5385                         t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5386                                           start_index);
5387         }
5388 }
5389
5390 /**
5391  * t4_tp_pio_read - Read TP PIO registers
5392  * @adap: the adapter
5393  * @buff: where the indirect register values are written
5394  * @nregs: how many indirect registers to read
5395  * @start_index: index of first indirect register to read
5396  * @sleep_ok: if true we may sleep while awaiting command completion
5397  *
5398  * Read TP PIO Registers
5399  **/
5400 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5401                     u32 start_index, bool sleep_ok)
5402 {
5403         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5404                           start_index, 1, sleep_ok);
5405 }
5406
5407 /**
5408  * t4_tp_pio_write - Write TP PIO registers
5409  * @adap: the adapter
5410  * @buff: where the indirect register values are stored
5411  * @nregs: how many indirect registers to write
5412  * @start_index: index of first indirect register to write
5413  * @sleep_ok: if true we may sleep while awaiting command completion
5414  *
5415  * Write TP PIO Registers
5416  **/
5417 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5418                             u32 start_index, bool sleep_ok)
5419 {
5420         t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5421                           start_index, 0, sleep_ok);
5422 }
5423
5424 /**
5425  * t4_tp_tm_pio_read - Read TP TM PIO registers
5426  * @adap: the adapter
5427  * @buff: where the indirect register values are written
5428  * @nregs: how many indirect registers to read
5429  * @start_index: index of first indirect register to read
5430  * @sleep_ok: if true we may sleep while awaiting command completion
5431  *
5432  * Read TP TM PIO Registers
5433  **/
5434 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5435                        u32 start_index, bool sleep_ok)
5436 {
5437         t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5438                           nregs, start_index, 1, sleep_ok);
5439 }
5440
5441 /**
5442  * t4_tp_mib_read - Read TP MIB registers
5443  * @adap: the adapter
5444  * @buff: where the indirect register values are written
5445  * @nregs: how many indirect registers to read
5446  * @start_index: index of first indirect register to read
5447  * @sleep_ok: if true we may sleep while awaiting command completion
5448  *
5449  * Read TP MIB Registers
5450  **/
5451 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5452                     bool sleep_ok)
5453 {
5454         t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5455                           start_index, 1, sleep_ok);
5456 }
5457
5458 /**
5459  *      t4_read_rss_key - read the global RSS key
5460  *      @adap: the adapter
5461  *      @key: 10-entry array holding the 320-bit RSS key
5462  *      @sleep_ok: if true we may sleep while awaiting command completion
5463  *
5464  *      Reads the global 320-bit RSS key.
5465  */
5466 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5467 {
5468         t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5469 }
5470
5471 /**
5472  *      t4_write_rss_key - program one of the RSS keys
5473  *      @adap: the adapter
5474  *      @key: 10-entry array holding the 320-bit RSS key
5475  *      @idx: which RSS key to write
5476  *      @sleep_ok: if true we may sleep while awaiting command completion
5477  *
5478  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5479  *      0..15 the corresponding entry in the RSS key table is written,
5480  *      otherwise the global RSS key is written.
5481  */
5482 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5483                       bool sleep_ok)
5484 {
5485         u8 rss_key_addr_cnt = 16;
5486         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5487
5488         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5489          * allows access to key addresses 16-63 by using KeyWrAddrX
5490          * as index[5:4](upper 2) into key table
5491          */
5492         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5493             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5494                 rss_key_addr_cnt = 32;
5495
5496         t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5497
5498         if (idx >= 0 && idx < rss_key_addr_cnt) {
5499                 if (rss_key_addr_cnt > 16)
5500                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5501                                      KEYWRADDRX_V(idx >> 4) |
5502                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
5503                 else
5504                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5505                                      KEYWRADDR_V(idx) | KEYWREN_F);
5506         }
5507 }
5508
5509 /**
5510  *      t4_read_rss_pf_config - read PF RSS Configuration Table
5511  *      @adapter: the adapter
5512  *      @index: the entry in the PF RSS table to read
5513  *      @valp: where to store the returned value
5514  *      @sleep_ok: if true we may sleep while awaiting command completion
5515  *
5516  *      Reads the PF RSS Configuration Table at the specified index and returns
5517  *      the value found there.
5518  */
5519 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5520                            u32 *valp, bool sleep_ok)
5521 {
5522         t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5523 }
5524
5525 /**
5526  *      t4_read_rss_vf_config - read VF RSS Configuration Table
5527  *      @adapter: the adapter
5528  *      @index: the entry in the VF RSS table to read
5529  *      @vfl: where to store the returned VFL
5530  *      @vfh: where to store the returned VFH
5531  *      @sleep_ok: if true we may sleep while awaiting command completion
5532  *
5533  *      Reads the VF RSS Configuration Table at the specified index and returns
5534  *      the (VFL, VFH) values found there.
5535  */
5536 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5537                            u32 *vfl, u32 *vfh, bool sleep_ok)
5538 {
5539         u32 vrt, mask, data;
5540
5541         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5542                 mask = VFWRADDR_V(VFWRADDR_M);
5543                 data = VFWRADDR_V(index);
5544         } else {
5545                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5546                  data = T6_VFWRADDR_V(index);
5547         }
5548
5549         /* Request that the index'th VF Table values be read into VFL/VFH.
5550          */
5551         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5552         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5553         vrt |= data | VFRDEN_F;
5554         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5555
5556         /* Grab the VFL/VFH values ...
5557          */
5558         t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5559         t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5560 }
5561
5562 /**
5563  *      t4_read_rss_pf_map - read PF RSS Map
5564  *      @adapter: the adapter
5565  *      @sleep_ok: if true we may sleep while awaiting command completion
5566  *
5567  *      Reads the PF RSS Map register and returns its value.
5568  */
5569 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5570 {
5571         u32 pfmap;
5572
5573         t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5574         return pfmap;
5575 }
5576
5577 /**
5578  *      t4_read_rss_pf_mask - read PF RSS Mask
5579  *      @adapter: the adapter
5580  *      @sleep_ok: if true we may sleep while awaiting command completion
5581  *
5582  *      Reads the PF RSS Mask register and returns its value.
5583  */
5584 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5585 {
5586         u32 pfmask;
5587
5588         t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5589         return pfmask;
5590 }
5591
5592 /**
5593  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5594  *      @adap: the adapter
5595  *      @v4: holds the TCP/IP counter values
5596  *      @v6: holds the TCP/IPv6 counter values
5597  *      @sleep_ok: if true we may sleep while awaiting command completion
5598  *
5599  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5600  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5601  */
5602 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5603                          struct tp_tcp_stats *v6, bool sleep_ok)
5604 {
5605         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5606
5607 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5608 #define STAT(x)     val[STAT_IDX(x)]
5609 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5610
5611         if (v4) {
5612                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5613                                TP_MIB_TCP_OUT_RST_A, sleep_ok);
5614                 v4->tcp_out_rsts = STAT(OUT_RST);
5615                 v4->tcp_in_segs  = STAT64(IN_SEG);
5616                 v4->tcp_out_segs = STAT64(OUT_SEG);
5617                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5618         }
5619         if (v6) {
5620                 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5621                                TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5622                 v6->tcp_out_rsts = STAT(OUT_RST);
5623                 v6->tcp_in_segs  = STAT64(IN_SEG);
5624                 v6->tcp_out_segs = STAT64(OUT_SEG);
5625                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5626         }
5627 #undef STAT64
5628 #undef STAT
5629 #undef STAT_IDX
5630 }
5631
5632 /**
5633  *      t4_tp_get_err_stats - read TP's error MIB counters
5634  *      @adap: the adapter
5635  *      @st: holds the counter values
5636  *      @sleep_ok: if true we may sleep while awaiting command completion
5637  *
5638  *      Returns the values of TP's error counters.
5639  */
5640 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5641                          bool sleep_ok)
5642 {
5643         int nchan = adap->params.arch.nchan;
5644
5645         t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5646                        sleep_ok);
5647         t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5648                        sleep_ok);
5649         t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5650                        sleep_ok);
5651         t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5652                        TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5653         t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5654                        TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5655         t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5656                        sleep_ok);
5657         t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5658                        TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5659         t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5660                        TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5661         t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5662                        sleep_ok);
5663 }
5664
5665 /**
5666  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5667  *      @adap: the adapter
5668  *      @st: holds the counter values
5669  *      @sleep_ok: if true we may sleep while awaiting command completion
5670  *
5671  *      Returns the values of TP's CPL counters.
5672  */
5673 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5674                          bool sleep_ok)
5675 {
5676         int nchan = adap->params.arch.nchan;
5677
5678         t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5679
5680         t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5681 }
5682
5683 /**
5684  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5685  *      @adap: the adapter
5686  *      @st: holds the counter values
5687  *      @sleep_ok: if true we may sleep while awaiting command completion
5688  *
5689  *      Returns the values of TP's RDMA counters.
5690  */
5691 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5692                           bool sleep_ok)
5693 {
5694         t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5695                        sleep_ok);
5696 }
5697
5698 /**
5699  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5700  *      @adap: the adapter
5701  *      @idx: the port index
5702  *      @st: holds the counter values
5703  *      @sleep_ok: if true we may sleep while awaiting command completion
5704  *
5705  *      Returns the values of TP's FCoE counters for the selected port.
5706  */
5707 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5708                        struct tp_fcoe_stats *st, bool sleep_ok)
5709 {
5710         u32 val[2];
5711
5712         t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5713                        sleep_ok);
5714
5715         t4_tp_mib_read(adap, &st->frames_drop, 1,
5716                        TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5717
5718         t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5719                        sleep_ok);
5720
5721         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5722 }
5723
5724 /**
5725  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5726  *      @adap: the adapter
5727  *      @st: holds the counter values
5728  *      @sleep_ok: if true we may sleep while awaiting command completion
5729  *
5730  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5731  */
5732 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5733                       bool sleep_ok)
5734 {
5735         u32 val[4];
5736
5737         t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5738         st->frames = val[0];
5739         st->drops = val[1];
5740         st->octets = ((u64)val[2] << 32) | val[3];
5741 }
5742
5743 /**
5744  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5745  *      @adap: the adapter
5746  *      @mtus: where to store the MTU values
5747  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5748  *
5749  *      Reads the HW path MTU table.
5750  */
5751 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5752 {
5753         u32 v;
5754         int i;
5755
5756         for (i = 0; i < NMTUS; ++i) {
5757                 t4_write_reg(adap, TP_MTU_TABLE_A,
5758                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5759                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5760                 mtus[i] = MTUVALUE_G(v);
5761                 if (mtu_log)
5762                         mtu_log[i] = MTUWIDTH_G(v);
5763         }
5764 }
5765
5766 /**
5767  *      t4_read_cong_tbl - reads the congestion control table
5768  *      @adap: the adapter
5769  *      @incr: where to store the alpha values
5770  *
5771  *      Reads the additive increments programmed into the HW congestion
5772  *      control table.
5773  */
5774 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5775 {
5776         unsigned int mtu, w;
5777
5778         for (mtu = 0; mtu < NMTUS; ++mtu)
5779                 for (w = 0; w < NCCTRL_WIN; ++w) {
5780                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5781                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5782                         incr[mtu][w] = (u16)t4_read_reg(adap,
5783                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5784                 }
5785 }
5786
5787 /**
5788  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5789  *      @adap: the adapter
5790  *      @addr: the indirect TP register address
5791  *      @mask: specifies the field within the register to modify
5792  *      @val: new value for the field
5793  *
5794  *      Sets a field of an indirect TP register to the given value.
5795  */
5796 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5797                             unsigned int mask, unsigned int val)
5798 {
5799         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5800         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5801         t4_write_reg(adap, TP_PIO_DATA_A, val);
5802 }
5803
5804 /**
5805  *      init_cong_ctrl - initialize congestion control parameters
5806  *      @a: the alpha values for congestion control
5807  *      @b: the beta values for congestion control
5808  *
5809  *      Initialize the congestion control parameters.
5810  */
5811 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5812 {
5813         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5814         a[9] = 2;
5815         a[10] = 3;
5816         a[11] = 4;
5817         a[12] = 5;
5818         a[13] = 6;
5819         a[14] = 7;
5820         a[15] = 8;
5821         a[16] = 9;
5822         a[17] = 10;
5823         a[18] = 14;
5824         a[19] = 17;
5825         a[20] = 21;
5826         a[21] = 25;
5827         a[22] = 30;
5828         a[23] = 35;
5829         a[24] = 45;
5830         a[25] = 60;
5831         a[26] = 80;
5832         a[27] = 100;
5833         a[28] = 200;
5834         a[29] = 300;
5835         a[30] = 400;
5836         a[31] = 500;
5837
5838         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5839         b[9] = b[10] = 1;
5840         b[11] = b[12] = 2;
5841         b[13] = b[14] = b[15] = b[16] = 3;
5842         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5843         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5844         b[28] = b[29] = 6;
5845         b[30] = b[31] = 7;
5846 }
5847
5848 /* The minimum additive increment value for the congestion control table */
5849 #define CC_MIN_INCR 2U
5850
5851 /**
5852  *      t4_load_mtus - write the MTU and congestion control HW tables
5853  *      @adap: the adapter
5854  *      @mtus: the values for the MTU table
5855  *      @alpha: the values for the congestion control alpha parameter
5856  *      @beta: the values for the congestion control beta parameter
5857  *
5858  *      Write the HW MTU table with the supplied MTUs and the high-speed
5859  *      congestion control table with the supplied alpha, beta, and MTUs.
5860  *      We write the two tables together because the additive increments
5861  *      depend on the MTUs.
5862  */
5863 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5864                   const unsigned short *alpha, const unsigned short *beta)
5865 {
5866         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5867                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5868                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5869                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5870         };
5871
5872         unsigned int i, w;
5873
5874         for (i = 0; i < NMTUS; ++i) {
5875                 unsigned int mtu = mtus[i];
5876                 unsigned int log2 = fls(mtu);
5877
5878                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5879                         log2--;
5880                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5881                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5882
5883                 for (w = 0; w < NCCTRL_WIN; ++w) {
5884                         unsigned int inc;
5885
5886                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5887                                   CC_MIN_INCR);
5888
5889                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5890                                      (w << 16) | (beta[w] << 13) | inc);
5891                 }
5892         }
5893 }
5894
5895 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5896  * clocks.  The formula is
5897  *
5898  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5899  *
5900  * which is equivalent to
5901  *
5902  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5903  */
5904 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5905 {
5906         u64 v = bytes256 * adap->params.vpd.cclk;
5907
5908         return v * 62 + v / 2;
5909 }
5910
5911 /**
5912  *      t4_get_chan_txrate - get the current per channel Tx rates
5913  *      @adap: the adapter
5914  *      @nic_rate: rates for NIC traffic
5915  *      @ofld_rate: rates for offloaded traffic
5916  *
5917  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5918  *      for each channel.
5919  */
5920 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5921 {
5922         u32 v;
5923
5924         v = t4_read_reg(adap, TP_TX_TRATE_A);
5925         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5926         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5927         if (adap->params.arch.nchan == NCHAN) {
5928                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5929                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5930         }
5931
5932         v = t4_read_reg(adap, TP_TX_ORATE_A);
5933         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5934         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5935         if (adap->params.arch.nchan == NCHAN) {
5936                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5937                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5938         }
5939 }
5940
5941 /**
5942  *      t4_set_trace_filter - configure one of the tracing filters
5943  *      @adap: the adapter
5944  *      @tp: the desired trace filter parameters
5945  *      @idx: which filter to configure
5946  *      @enable: whether to enable or disable the filter
5947  *
5948  *      Configures one of the tracing filters available in HW.  If @enable is
5949  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5950  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5951  */
5952 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5953                         int idx, int enable)
5954 {
5955         int i, ofst = idx * 4;
5956         u32 data_reg, mask_reg, cfg;
5957
5958         if (!enable) {
5959                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5960                 return 0;
5961         }
5962
5963         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5964         if (cfg & TRCMULTIFILTER_F) {
5965                 /* If multiple tracers are enabled, then maximum
5966                  * capture size is 2.5KB (FIFO size of a single channel)
5967                  * minus 2 flits for CPL_TRACE_PKT header.
5968                  */
5969                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5970                         return -EINVAL;
5971         } else {
5972                 /* If multiple tracers are disabled, to avoid deadlocks
5973                  * maximum packet capture size of 9600 bytes is recommended.
5974                  * Also in this mode, only trace0 can be enabled and running.
5975                  */
5976                 if (tp->snap_len > 9600 || idx)
5977                         return -EINVAL;
5978         }
5979
5980         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5981             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5982             tp->min_len > TFMINPKTSIZE_M)
5983                 return -EINVAL;
5984
5985         /* stop the tracer we'll be changing */
5986         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5987
5988         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5989         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5990         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5991
5992         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5993                 t4_write_reg(adap, data_reg, tp->data[i]);
5994                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5995         }
5996         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5997                      TFCAPTUREMAX_V(tp->snap_len) |
5998                      TFMINPKTSIZE_V(tp->min_len));
5999         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
6000                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
6001                      (is_t4(adap->params.chip) ?
6002                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
6003                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
6004                      T5_TFINVERTMATCH_V(tp->invert)));
6005
6006         return 0;
6007 }
6008
6009 /**
6010  *      t4_get_trace_filter - query one of the tracing filters
6011  *      @adap: the adapter
6012  *      @tp: the current trace filter parameters
6013  *      @idx: which trace filter to query
6014  *      @enabled: non-zero if the filter is enabled
6015  *
6016  *      Returns the current settings of one of the HW tracing filters.
6017  */
6018 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6019                          int *enabled)
6020 {
6021         u32 ctla, ctlb;
6022         int i, ofst = idx * 4;
6023         u32 data_reg, mask_reg;
6024
6025         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6026         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6027
6028         if (is_t4(adap->params.chip)) {
6029                 *enabled = !!(ctla & TFEN_F);
6030                 tp->port =  TFPORT_G(ctla);
6031                 tp->invert = !!(ctla & TFINVERTMATCH_F);
6032         } else {
6033                 *enabled = !!(ctla & T5_TFEN_F);
6034                 tp->port = T5_TFPORT_G(ctla);
6035                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
6036         }
6037         tp->snap_len = TFCAPTUREMAX_G(ctlb);
6038         tp->min_len = TFMINPKTSIZE_G(ctlb);
6039         tp->skip_ofst = TFOFFSET_G(ctla);
6040         tp->skip_len = TFLENGTH_G(ctla);
6041
6042         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
6043         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
6044         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
6045
6046         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6047                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6048                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6049         }
6050 }
6051
6052 /**
6053  *      t4_pmtx_get_stats - returns the HW stats from PMTX
6054  *      @adap: the adapter
6055  *      @cnt: where to store the count statistics
6056  *      @cycles: where to store the cycle statistics
6057  *
6058  *      Returns performance statistics from PMTX.
6059  */
6060 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6061 {
6062         int i;
6063         u32 data[2];
6064
6065         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6066                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
6067                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6068                 if (is_t4(adap->params.chip)) {
6069                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
6070                 } else {
6071                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
6072                                          PM_TX_DBG_DATA_A, data, 2,
6073                                          PM_TX_DBG_STAT_MSB_A);
6074                         cycles[i] = (((u64)data[0] << 32) | data[1]);
6075                 }
6076         }
6077 }
6078
6079 /**
6080  *      t4_pmrx_get_stats - returns the HW stats from PMRX
6081  *      @adap: the adapter
6082  *      @cnt: where to store the count statistics
6083  *      @cycles: where to store the cycle statistics
6084  *
6085  *      Returns performance statistics from PMRX.
6086  */
6087 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6088 {
6089         int i;
6090         u32 data[2];
6091
6092         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6093                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6094                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6095                 if (is_t4(adap->params.chip)) {
6096                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6097                 } else {
6098                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6099                                          PM_RX_DBG_DATA_A, data, 2,
6100                                          PM_RX_DBG_STAT_MSB_A);
6101                         cycles[i] = (((u64)data[0] << 32) | data[1]);
6102                 }
6103         }
6104 }
6105
6106 /**
6107  *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6108  *      @adap: the adapter
6109  *      @pidx: the port index
6110  *
6111  *      Computes and returns a bitmap indicating which MPS buffer groups are
6112  *      associated with the given Port.  Bit i is set if buffer group i is
6113  *      used by the Port.
6114  */
6115 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
6116                                               int pidx)
6117 {
6118         unsigned int chip_version, nports;
6119
6120         chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6121         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6122
6123         switch (chip_version) {
6124         case CHELSIO_T4:
6125         case CHELSIO_T5:
6126                 switch (nports) {
6127                 case 1: return 0xf;
6128                 case 2: return 3 << (2 * pidx);
6129                 case 4: return 1 << pidx;
6130                 }
6131                 break;
6132
6133         case CHELSIO_T6:
6134                 switch (nports) {
6135                 case 2: return 1 << (2 * pidx);
6136                 }
6137                 break;
6138         }
6139
6140         dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6141                 chip_version, nports);
6142
6143         return 0;
6144 }
6145
6146 /**
6147  *      t4_get_mps_bg_map - return the buffer groups associated with a port
6148  *      @adapter: the adapter
6149  *      @pidx: the port index
6150  *
6151  *      Returns a bitmap indicating which MPS buffer groups are associated
6152  *      with the given Port.  Bit i is set if buffer group i is used by the
6153  *      Port.
6154  */
6155 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6156 {
6157         u8 *mps_bg_map;
6158         unsigned int nports;
6159
6160         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6161         if (pidx >= nports) {
6162                 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6163                         pidx, nports);
6164                 return 0;
6165         }
6166
6167         /* If we've already retrieved/computed this, just return the result.
6168          */
6169         mps_bg_map = adapter->params.mps_bg_map;
6170         if (mps_bg_map[pidx])
6171                 return mps_bg_map[pidx];
6172
6173         /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6174          * If we're talking to such Firmware, let it tell us.  If the new
6175          * API isn't supported, revert back to old hardcoded way.  The value
6176          * obtained from Firmware is encoded in below format:
6177          *
6178          * val = (( MPSBGMAP[Port 3] << 24 ) |
6179          *        ( MPSBGMAP[Port 2] << 16 ) |
6180          *        ( MPSBGMAP[Port 1] <<  8 ) |
6181          *        ( MPSBGMAP[Port 0] <<  0 ))
6182          */
6183         if (adapter->flags & CXGB4_FW_OK) {
6184                 u32 param, val;
6185                 int ret;
6186
6187                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6188                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6189                 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6190                                          0, 1, &param, &val);
6191                 if (!ret) {
6192                         int p;
6193
6194                         /* Store the BG Map for all of the Ports in order to
6195                          * avoid more calls to the Firmware in the future.
6196                          */
6197                         for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6198                                 mps_bg_map[p] = val & 0xff;
6199
6200                         return mps_bg_map[pidx];
6201                 }
6202         }
6203
6204         /* Either we're not talking to the Firmware or we're dealing with
6205          * older Firmware which doesn't support the new API to get the MPS
6206          * Buffer Group Map.  Fall back to computing it ourselves.
6207          */
6208         mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6209         return mps_bg_map[pidx];
6210 }
6211
6212 /**
6213  *      t4_get_tp_e2c_map - return the E2C channel map associated with a port
6214  *      @adapter: the adapter
6215  *      @pidx: the port index
6216  */
6217 static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
6218 {
6219         unsigned int nports;
6220         u32 param, val = 0;
6221         int ret;
6222
6223         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6224         if (pidx >= nports) {
6225                 CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
6226                         pidx, nports);
6227                 return 0;
6228         }
6229
6230         /* FW version >= 1.16.44.0 can determine E2C channel map using
6231          * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6232          */
6233         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6234                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
6235         ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6236                                  0, 1, &param, &val);
6237         if (!ret)
6238                 return (val >> (8 * pidx)) & 0xff;
6239
6240         return 0;
6241 }
6242
6243 /**
6244  *      t4_get_tp_ch_map - return TP ingress channels associated with a port
6245  *      @adapter: the adapter
6246  *      @pidx: the port index
6247  *
6248  *      Returns a bitmap indicating which TP Ingress Channels are associated
6249  *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
6250  *      the Port.
6251  */
6252 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6253 {
6254         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6255         unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6256
6257         if (pidx >= nports) {
6258                 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6259                          pidx, nports);
6260                 return 0;
6261         }
6262
6263         switch (chip_version) {
6264         case CHELSIO_T4:
6265         case CHELSIO_T5:
6266                 /* Note that this happens to be the same values as the MPS
6267                  * Buffer Group Map for these Chips.  But we replicate the code
6268                  * here because they're really separate concepts.
6269                  */
6270                 switch (nports) {
6271                 case 1: return 0xf;
6272                 case 2: return 3 << (2 * pidx);
6273                 case 4: return 1 << pidx;
6274                 }
6275                 break;
6276
6277         case CHELSIO_T6:
6278                 switch (nports) {
6279                 case 1:
6280                 case 2: return 1 << pidx;
6281                 }
6282                 break;
6283         }
6284
6285         dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6286                 chip_version, nports);
6287         return 0;
6288 }
6289
6290 /**
6291  *      t4_get_port_type_description - return Port Type string description
6292  *      @port_type: firmware Port Type enumeration
6293  */
6294 const char *t4_get_port_type_description(enum fw_port_type port_type)
6295 {
6296         static const char *const port_type_description[] = {
6297                 "Fiber_XFI",
6298                 "Fiber_XAUI",
6299                 "BT_SGMII",
6300                 "BT_XFI",
6301                 "BT_XAUI",
6302                 "KX4",
6303                 "CX4",
6304                 "KX",
6305                 "KR",
6306                 "SFP",
6307                 "BP_AP",
6308                 "BP4_AP",
6309                 "QSFP_10G",
6310                 "QSA",
6311                 "QSFP",
6312                 "BP40_BA",
6313                 "KR4_100G",
6314                 "CR4_QSFP",
6315                 "CR_QSFP",
6316                 "CR2_QSFP",
6317                 "SFP28",
6318                 "KR_SFP28",
6319                 "KR_XLAUI"
6320         };
6321
6322         if (port_type < ARRAY_SIZE(port_type_description))
6323                 return port_type_description[port_type];
6324         return "UNKNOWN";
6325 }
6326
6327 /**
6328  *      t4_get_port_stats_offset - collect port stats relative to a previous
6329  *                                 snapshot
6330  *      @adap: The adapter
6331  *      @idx: The port
6332  *      @stats: Current stats to fill
6333  *      @offset: Previous stats snapshot
6334  */
6335 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6336                               struct port_stats *stats,
6337                               struct port_stats *offset)
6338 {
6339         u64 *s, *o;
6340         int i;
6341
6342         t4_get_port_stats(adap, idx, stats);
6343         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6344                         i < (sizeof(struct port_stats) / sizeof(u64));
6345                         i++, s++, o++)
6346                 *s -= *o;
6347 }
6348
6349 /**
6350  *      t4_get_port_stats - collect port statistics
6351  *      @adap: the adapter
6352  *      @idx: the port index
6353  *      @p: the stats structure to fill
6354  *
6355  *      Collect statistics related to the given port from HW.
6356  */
6357 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6358 {
6359         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6360         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6361
6362 #define GET_STAT(name) \
6363         t4_read_reg64(adap, \
6364         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6365         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6366 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6367
6368         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
6369         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
6370         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
6371         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
6372         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
6373         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
6374         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
6375         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
6376         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
6377         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
6378         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
6379         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6380         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
6381         p->tx_drop             = GET_STAT(TX_PORT_DROP);
6382         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
6383         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
6384         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
6385         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
6386         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
6387         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
6388         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
6389         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
6390         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
6391
6392         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6393                 if (stat_ctl & COUNTPAUSESTATTX_F)
6394                         p->tx_frames_64 -= p->tx_pause;
6395                 if (stat_ctl & COUNTPAUSEMCTX_F)
6396                         p->tx_mcast_frames -= p->tx_pause;
6397         }
6398         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6399         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6400         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6401         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6402         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6403         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6404         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6405         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6406         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6407         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6408         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6409         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6410         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6411         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6412         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6413         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6414         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6415         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6416         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6417         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6418         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6419         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6420         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6421         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6422         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6423         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6424         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6425
6426         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6427                 if (stat_ctl & COUNTPAUSESTATRX_F)
6428                         p->rx_frames_64 -= p->rx_pause;
6429                 if (stat_ctl & COUNTPAUSEMCRX_F)
6430                         p->rx_mcast_frames -= p->rx_pause;
6431         }
6432
6433         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6434         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6435         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6436         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6437         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6438         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6439         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6440         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6441
6442 #undef GET_STAT
6443 #undef GET_STAT_COM
6444 }
6445
6446 /**
6447  *      t4_get_lb_stats - collect loopback port statistics
6448  *      @adap: the adapter
6449  *      @idx: the loopback port index
6450  *      @p: the stats structure to fill
6451  *
6452  *      Return HW statistics for the given loopback port.
6453  */
6454 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6455 {
6456         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6457
6458 #define GET_STAT(name) \
6459         t4_read_reg64(adap, \
6460         (is_t4(adap->params.chip) ? \
6461         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6462         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6463 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6464
6465         p->octets           = GET_STAT(BYTES);
6466         p->frames           = GET_STAT(FRAMES);
6467         p->bcast_frames     = GET_STAT(BCAST);
6468         p->mcast_frames     = GET_STAT(MCAST);
6469         p->ucast_frames     = GET_STAT(UCAST);
6470         p->error_frames     = GET_STAT(ERROR);
6471
6472         p->frames_64        = GET_STAT(64B);
6473         p->frames_65_127    = GET_STAT(65B_127B);
6474         p->frames_128_255   = GET_STAT(128B_255B);
6475         p->frames_256_511   = GET_STAT(256B_511B);
6476         p->frames_512_1023  = GET_STAT(512B_1023B);
6477         p->frames_1024_1518 = GET_STAT(1024B_1518B);
6478         p->frames_1519_max  = GET_STAT(1519B_MAX);
6479         p->drop             = GET_STAT(DROP_FRAMES);
6480
6481         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6482         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6483         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6484         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6485         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6486         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6487         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6488         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6489
6490 #undef GET_STAT
6491 #undef GET_STAT_COM
6492 }
6493
6494 /*     t4_mk_filtdelwr - create a delete filter WR
6495  *     @ftid: the filter ID
6496  *     @wr: the filter work request to populate
6497  *     @qid: ingress queue to receive the delete notification
6498  *
6499  *     Creates a filter work request to delete the supplied filter.  If @qid is
6500  *     negative the delete notification is suppressed.
6501  */
6502 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6503 {
6504         memset(wr, 0, sizeof(*wr));
6505         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6506         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6507         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6508                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
6509         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6510         if (qid >= 0)
6511                 wr->rx_chan_rx_rpl_iq =
6512                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6513 }
6514
6515 #define INIT_CMD(var, cmd, rd_wr) do { \
6516         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6517                                         FW_CMD_REQUEST_F | \
6518                                         FW_CMD_##rd_wr##_F); \
6519         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6520 } while (0)
6521
6522 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6523                           u32 addr, u32 val)
6524 {
6525         u32 ldst_addrspace;
6526         struct fw_ldst_cmd c;
6527
6528         memset(&c, 0, sizeof(c));
6529         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6530         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6531                                         FW_CMD_REQUEST_F |
6532                                         FW_CMD_WRITE_F |
6533                                         ldst_addrspace);
6534         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6535         c.u.addrval.addr = cpu_to_be32(addr);
6536         c.u.addrval.val = cpu_to_be32(val);
6537
6538         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6539 }
6540
6541 /**
6542  *      t4_mdio_rd - read a PHY register through MDIO
6543  *      @adap: the adapter
6544  *      @mbox: mailbox to use for the FW command
6545  *      @phy_addr: the PHY address
6546  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6547  *      @reg: the register to read
6548  *      @valp: where to store the value
6549  *
6550  *      Issues a FW command through the given mailbox to read a PHY register.
6551  */
6552 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6553                unsigned int mmd, unsigned int reg, u16 *valp)
6554 {
6555         int ret;
6556         u32 ldst_addrspace;
6557         struct fw_ldst_cmd c;
6558
6559         memset(&c, 0, sizeof(c));
6560         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6561         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6562                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6563                                         ldst_addrspace);
6564         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6565         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6566                                          FW_LDST_CMD_MMD_V(mmd));
6567         c.u.mdio.raddr = cpu_to_be16(reg);
6568
6569         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6570         if (ret == 0)
6571                 *valp = be16_to_cpu(c.u.mdio.rval);
6572         return ret;
6573 }
6574
6575 /**
6576  *      t4_mdio_wr - write a PHY register through MDIO
6577  *      @adap: the adapter
6578  *      @mbox: mailbox to use for the FW command
6579  *      @phy_addr: the PHY address
6580  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6581  *      @reg: the register to write
6582  *      @valp: value to write
6583  *
6584  *      Issues a FW command through the given mailbox to write a PHY register.
6585  */
6586 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6587                unsigned int mmd, unsigned int reg, u16 val)
6588 {
6589         u32 ldst_addrspace;
6590         struct fw_ldst_cmd c;
6591
6592         memset(&c, 0, sizeof(c));
6593         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6594         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6595                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6596                                         ldst_addrspace);
6597         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6598         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6599                                          FW_LDST_CMD_MMD_V(mmd));
6600         c.u.mdio.raddr = cpu_to_be16(reg);
6601         c.u.mdio.rval = cpu_to_be16(val);
6602
6603         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6604 }
6605
6606 /**
6607  *      t4_sge_decode_idma_state - decode the idma state
6608  *      @adap: the adapter
6609  *      @state: the state idma is stuck in
6610  */
6611 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6612 {
6613         static const char * const t4_decode[] = {
6614                 "IDMA_IDLE",
6615                 "IDMA_PUSH_MORE_CPL_FIFO",
6616                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6617                 "Not used",
6618                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6619                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6620                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6621                 "IDMA_SEND_FIFO_TO_IMSG",
6622                 "IDMA_FL_REQ_DATA_FL_PREP",
6623                 "IDMA_FL_REQ_DATA_FL",
6624                 "IDMA_FL_DROP",
6625                 "IDMA_FL_H_REQ_HEADER_FL",
6626                 "IDMA_FL_H_SEND_PCIEHDR",
6627                 "IDMA_FL_H_PUSH_CPL_FIFO",
6628                 "IDMA_FL_H_SEND_CPL",
6629                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6630                 "IDMA_FL_H_SEND_IP_HDR",
6631                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6632                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6633                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6634                 "IDMA_FL_D_SEND_PCIEHDR",
6635                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6636                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6637                 "IDMA_FL_SEND_PCIEHDR",
6638                 "IDMA_FL_PUSH_CPL_FIFO",
6639                 "IDMA_FL_SEND_CPL",
6640                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6641                 "IDMA_FL_SEND_PAYLOAD",
6642                 "IDMA_FL_REQ_NEXT_DATA_FL",
6643                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6644                 "IDMA_FL_SEND_PADDING",
6645                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6646                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6647                 "IDMA_FL_REQ_DATAFL_DONE",
6648                 "IDMA_FL_REQ_HEADERFL_DONE",
6649         };
6650         static const char * const t5_decode[] = {
6651                 "IDMA_IDLE",
6652                 "IDMA_ALMOST_IDLE",
6653                 "IDMA_PUSH_MORE_CPL_FIFO",
6654                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6655                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6656                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6657                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6658                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6659                 "IDMA_SEND_FIFO_TO_IMSG",
6660                 "IDMA_FL_REQ_DATA_FL",
6661                 "IDMA_FL_DROP",
6662                 "IDMA_FL_DROP_SEND_INC",
6663                 "IDMA_FL_H_REQ_HEADER_FL",
6664                 "IDMA_FL_H_SEND_PCIEHDR",
6665                 "IDMA_FL_H_PUSH_CPL_FIFO",
6666                 "IDMA_FL_H_SEND_CPL",
6667                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6668                 "IDMA_FL_H_SEND_IP_HDR",
6669                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6670                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6671                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6672                 "IDMA_FL_D_SEND_PCIEHDR",
6673                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6674                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6675                 "IDMA_FL_SEND_PCIEHDR",
6676                 "IDMA_FL_PUSH_CPL_FIFO",
6677                 "IDMA_FL_SEND_CPL",
6678                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6679                 "IDMA_FL_SEND_PAYLOAD",
6680                 "IDMA_FL_REQ_NEXT_DATA_FL",
6681                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6682                 "IDMA_FL_SEND_PADDING",
6683                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6684         };
6685         static const char * const t6_decode[] = {
6686                 "IDMA_IDLE",
6687                 "IDMA_PUSH_MORE_CPL_FIFO",
6688                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6689                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6690                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6691                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6692                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6693                 "IDMA_FL_REQ_DATA_FL",
6694                 "IDMA_FL_DROP",
6695                 "IDMA_FL_DROP_SEND_INC",
6696                 "IDMA_FL_H_REQ_HEADER_FL",
6697                 "IDMA_FL_H_SEND_PCIEHDR",
6698                 "IDMA_FL_H_PUSH_CPL_FIFO",
6699                 "IDMA_FL_H_SEND_CPL",
6700                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6701                 "IDMA_FL_H_SEND_IP_HDR",
6702                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6703                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6704                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6705                 "IDMA_FL_D_SEND_PCIEHDR",
6706                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6707                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6708                 "IDMA_FL_SEND_PCIEHDR",
6709                 "IDMA_FL_PUSH_CPL_FIFO",
6710                 "IDMA_FL_SEND_CPL",
6711                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6712                 "IDMA_FL_SEND_PAYLOAD",
6713                 "IDMA_FL_REQ_NEXT_DATA_FL",
6714                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6715                 "IDMA_FL_SEND_PADDING",
6716                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6717         };
6718         static const u32 sge_regs[] = {
6719                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6720                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6721                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6722         };
6723         const char **sge_idma_decode;
6724         int sge_idma_decode_nstates;
6725         int i;
6726         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6727
6728         /* Select the right set of decode strings to dump depending on the
6729          * adapter chip type.
6730          */
6731         switch (chip_version) {
6732         case CHELSIO_T4:
6733                 sge_idma_decode = (const char **)t4_decode;
6734                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6735                 break;
6736
6737         case CHELSIO_T5:
6738                 sge_idma_decode = (const char **)t5_decode;
6739                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6740                 break;
6741
6742         case CHELSIO_T6:
6743                 sge_idma_decode = (const char **)t6_decode;
6744                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6745                 break;
6746
6747         default:
6748                 dev_err(adapter->pdev_dev,
6749                         "Unsupported chip version %d\n", chip_version);
6750                 return;
6751         }
6752
6753         if (is_t4(adapter->params.chip)) {
6754                 sge_idma_decode = (const char **)t4_decode;
6755                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6756         } else {
6757                 sge_idma_decode = (const char **)t5_decode;
6758                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6759         }
6760
6761         if (state < sge_idma_decode_nstates)
6762                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6763         else
6764                 CH_WARN(adapter, "idma state %d unknown\n", state);
6765
6766         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6767                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6768                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6769 }
6770
6771 /**
6772  *      t4_sge_ctxt_flush - flush the SGE context cache
6773  *      @adap: the adapter
6774  *      @mbox: mailbox to use for the FW command
6775  *      @ctx_type: Egress or Ingress
6776  *
6777  *      Issues a FW command through the given mailbox to flush the
6778  *      SGE context cache.
6779  */
6780 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6781 {
6782         int ret;
6783         u32 ldst_addrspace;
6784         struct fw_ldst_cmd c;
6785
6786         memset(&c, 0, sizeof(c));
6787         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6788                                                  FW_LDST_ADDRSPC_SGE_EGRC :
6789                                                  FW_LDST_ADDRSPC_SGE_INGC);
6790         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6791                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6792                                         ldst_addrspace);
6793         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6794         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6795
6796         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6797         return ret;
6798 }
6799
6800 /**
6801  *      t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6802  *      @adap - the adapter
6803  *      @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6804  *      @dbqtimers: SGE Doorbell Queue Timer table
6805  *
6806  *      Reads the SGE Doorbell Queue Timer values into the provided table.
6807  *      Returns 0 on success (Firmware and Hardware support this feature),
6808  *      an error on failure.
6809  */
6810 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
6811                           u16 *dbqtimers)
6812 {
6813         int ret, dbqtimerix;
6814
6815         ret = 0;
6816         dbqtimerix = 0;
6817         while (dbqtimerix < ndbqtimers) {
6818                 int nparams, param;
6819                 u32 params[7], vals[7];
6820
6821                 nparams = ndbqtimers - dbqtimerix;
6822                 if (nparams > ARRAY_SIZE(params))
6823                         nparams = ARRAY_SIZE(params);
6824
6825                 for (param = 0; param < nparams; param++)
6826                         params[param] =
6827                           (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6828                            FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER) |
6829                            FW_PARAMS_PARAM_Y_V(dbqtimerix + param));
6830                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
6831                                       nparams, params, vals);
6832                 if (ret)
6833                         break;
6834
6835                 for (param = 0; param < nparams; param++)
6836                         dbqtimers[dbqtimerix++] = vals[param];
6837         }
6838         return ret;
6839 }
6840
6841 /**
6842  *      t4_fw_hello - establish communication with FW
6843  *      @adap: the adapter
6844  *      @mbox: mailbox to use for the FW command
6845  *      @evt_mbox: mailbox to receive async FW events
6846  *      @master: specifies the caller's willingness to be the device master
6847  *      @state: returns the current device state (if non-NULL)
6848  *
6849  *      Issues a command to establish communication with FW.  Returns either
6850  *      an error (negative integer) or the mailbox of the Master PF.
6851  */
6852 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6853                 enum dev_master master, enum dev_state *state)
6854 {
6855         int ret;
6856         struct fw_hello_cmd c;
6857         u32 v;
6858         unsigned int master_mbox;
6859         int retries = FW_CMD_HELLO_RETRIES;
6860
6861 retry:
6862         memset(&c, 0, sizeof(c));
6863         INIT_CMD(c, HELLO, WRITE);
6864         c.err_to_clearinit = cpu_to_be32(
6865                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6866                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6867                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6868                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
6869                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6870                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6871                 FW_HELLO_CMD_CLEARINIT_F);
6872
6873         /*
6874          * Issue the HELLO command to the firmware.  If it's not successful
6875          * but indicates that we got a "busy" or "timeout" condition, retry
6876          * the HELLO until we exhaust our retry limit.  If we do exceed our
6877          * retry limit, check to see if the firmware left us any error
6878          * information and report that if so.
6879          */
6880         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6881         if (ret < 0) {
6882                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6883                         goto retry;
6884                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6885                         t4_report_fw_error(adap);
6886                 return ret;
6887         }
6888
6889         v = be32_to_cpu(c.err_to_clearinit);
6890         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6891         if (state) {
6892                 if (v & FW_HELLO_CMD_ERR_F)
6893                         *state = DEV_STATE_ERR;
6894                 else if (v & FW_HELLO_CMD_INIT_F)
6895                         *state = DEV_STATE_INIT;
6896                 else
6897                         *state = DEV_STATE_UNINIT;
6898         }
6899
6900         /*
6901          * If we're not the Master PF then we need to wait around for the
6902          * Master PF Driver to finish setting up the adapter.
6903          *
6904          * Note that we also do this wait if we're a non-Master-capable PF and
6905          * there is no current Master PF; a Master PF may show up momentarily
6906          * and we wouldn't want to fail pointlessly.  (This can happen when an
6907          * OS loads lots of different drivers rapidly at the same time).  In
6908          * this case, the Master PF returned by the firmware will be
6909          * PCIE_FW_MASTER_M so the test below will work ...
6910          */
6911         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6912             master_mbox != mbox) {
6913                 int waiting = FW_CMD_HELLO_TIMEOUT;
6914
6915                 /*
6916                  * Wait for the firmware to either indicate an error or
6917                  * initialized state.  If we see either of these we bail out
6918                  * and report the issue to the caller.  If we exhaust the
6919                  * "hello timeout" and we haven't exhausted our retries, try
6920                  * again.  Otherwise bail with a timeout error.
6921                  */
6922                 for (;;) {
6923                         u32 pcie_fw;
6924
6925                         msleep(50);
6926                         waiting -= 50;
6927
6928                         /*
6929                          * If neither Error nor Initialized are indicated
6930                          * by the firmware keep waiting till we exhaust our
6931                          * timeout ... and then retry if we haven't exhausted
6932                          * our retries ...
6933                          */
6934                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6935                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6936                                 if (waiting <= 0) {
6937                                         if (retries-- > 0)
6938                                                 goto retry;
6939
6940                                         return -ETIMEDOUT;
6941                                 }
6942                                 continue;
6943                         }
6944
6945                         /*
6946                          * We either have an Error or Initialized condition
6947                          * report errors preferentially.
6948                          */
6949                         if (state) {
6950                                 if (pcie_fw & PCIE_FW_ERR_F)
6951                                         *state = DEV_STATE_ERR;
6952                                 else if (pcie_fw & PCIE_FW_INIT_F)
6953                                         *state = DEV_STATE_INIT;
6954                         }
6955
6956                         /*
6957                          * If we arrived before a Master PF was selected and
6958                          * there's not a valid Master PF, grab its identity
6959                          * for our caller.
6960                          */
6961                         if (master_mbox == PCIE_FW_MASTER_M &&
6962                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6963                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6964                         break;
6965                 }
6966         }
6967
6968         return master_mbox;
6969 }
6970
6971 /**
6972  *      t4_fw_bye - end communication with FW
6973  *      @adap: the adapter
6974  *      @mbox: mailbox to use for the FW command
6975  *
6976  *      Issues a command to terminate communication with FW.
6977  */
6978 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6979 {
6980         struct fw_bye_cmd c;
6981
6982         memset(&c, 0, sizeof(c));
6983         INIT_CMD(c, BYE, WRITE);
6984         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6985 }
6986
6987 /**
6988  *      t4_init_cmd - ask FW to initialize the device
6989  *      @adap: the adapter
6990  *      @mbox: mailbox to use for the FW command
6991  *
6992  *      Issues a command to FW to partially initialize the device.  This
6993  *      performs initialization that generally doesn't depend on user input.
6994  */
6995 int t4_early_init(struct adapter *adap, unsigned int mbox)
6996 {
6997         struct fw_initialize_cmd c;
6998
6999         memset(&c, 0, sizeof(c));
7000         INIT_CMD(c, INITIALIZE, WRITE);
7001         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7002 }
7003
7004 /**
7005  *      t4_fw_reset - issue a reset to FW
7006  *      @adap: the adapter
7007  *      @mbox: mailbox to use for the FW command
7008  *      @reset: specifies the type of reset to perform
7009  *
7010  *      Issues a reset command of the specified type to FW.
7011  */
7012 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7013 {
7014         struct fw_reset_cmd c;
7015
7016         memset(&c, 0, sizeof(c));
7017         INIT_CMD(c, RESET, WRITE);
7018         c.val = cpu_to_be32(reset);
7019         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7020 }
7021
7022 /**
7023  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7024  *      @adap: the adapter
7025  *      @mbox: mailbox to use for the FW RESET command (if desired)
7026  *      @force: force uP into RESET even if FW RESET command fails
7027  *
7028  *      Issues a RESET command to firmware (if desired) with a HALT indication
7029  *      and then puts the microprocessor into RESET state.  The RESET command
7030  *      will only be issued if a legitimate mailbox is provided (mbox <=
7031  *      PCIE_FW_MASTER_M).
7032  *
7033  *      This is generally used in order for the host to safely manipulate the
7034  *      adapter without fear of conflicting with whatever the firmware might
7035  *      be doing.  The only way out of this state is to RESTART the firmware
7036  *      ...
7037  */
7038 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7039 {
7040         int ret = 0;
7041
7042         /*
7043          * If a legitimate mailbox is provided, issue a RESET command
7044          * with a HALT indication.
7045          */
7046         if (mbox <= PCIE_FW_MASTER_M) {
7047                 struct fw_reset_cmd c;
7048
7049                 memset(&c, 0, sizeof(c));
7050                 INIT_CMD(c, RESET, WRITE);
7051                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
7052                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
7053                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7054         }
7055
7056         /*
7057          * Normally we won't complete the operation if the firmware RESET
7058          * command fails but if our caller insists we'll go ahead and put the
7059          * uP into RESET.  This can be useful if the firmware is hung or even
7060          * missing ...  We'll have to take the risk of putting the uP into
7061          * RESET without the cooperation of firmware in that case.
7062          *
7063          * We also force the firmware's HALT flag to be on in case we bypassed
7064          * the firmware RESET command above or we're dealing with old firmware
7065          * which doesn't have the HALT capability.  This will serve as a flag
7066          * for the incoming firmware to know that it's coming out of a HALT
7067          * rather than a RESET ... if it's new enough to understand that ...
7068          */
7069         if (ret == 0 || force) {
7070                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
7071                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
7072                                  PCIE_FW_HALT_F);
7073         }
7074
7075         /*
7076          * And we always return the result of the firmware RESET command
7077          * even when we force the uP into RESET ...
7078          */
7079         return ret;
7080 }
7081
7082 /**
7083  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
7084  *      @adap: the adapter
7085  *      @reset: if we want to do a RESET to restart things
7086  *
7087  *      Restart firmware previously halted by t4_fw_halt().  On successful
7088  *      return the previous PF Master remains as the new PF Master and there
7089  *      is no need to issue a new HELLO command, etc.
7090  *
7091  *      We do this in two ways:
7092  *
7093  *       1. If we're dealing with newer firmware we'll simply want to take
7094  *          the chip's microprocessor out of RESET.  This will cause the
7095  *          firmware to start up from its start vector.  And then we'll loop
7096  *          until the firmware indicates it's started again (PCIE_FW.HALT
7097  *          reset to 0) or we timeout.
7098  *
7099  *       2. If we're dealing with older firmware then we'll need to RESET
7100  *          the chip since older firmware won't recognize the PCIE_FW.HALT
7101  *          flag and automatically RESET itself on startup.
7102  */
7103 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
7104 {
7105         if (reset) {
7106                 /*
7107                  * Since we're directing the RESET instead of the firmware
7108                  * doing it automatically, we need to clear the PCIE_FW.HALT
7109                  * bit.
7110                  */
7111                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
7112
7113                 /*
7114                  * If we've been given a valid mailbox, first try to get the
7115                  * firmware to do the RESET.  If that works, great and we can
7116                  * return success.  Otherwise, if we haven't been given a
7117                  * valid mailbox or the RESET command failed, fall back to
7118                  * hitting the chip with a hammer.
7119                  */
7120                 if (mbox <= PCIE_FW_MASTER_M) {
7121                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7122                         msleep(100);
7123                         if (t4_fw_reset(adap, mbox,
7124                                         PIORST_F | PIORSTMODE_F) == 0)
7125                                 return 0;
7126                 }
7127
7128                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
7129                 msleep(2000);
7130         } else {
7131                 int ms;
7132
7133                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7134                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7135                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7136                                 return 0;
7137                         msleep(100);
7138                         ms += 100;
7139                 }
7140                 return -ETIMEDOUT;
7141         }
7142         return 0;
7143 }
7144
7145 /**
7146  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7147  *      @adap: the adapter
7148  *      @mbox: mailbox to use for the FW RESET command (if desired)
7149  *      @fw_data: the firmware image to write
7150  *      @size: image size
7151  *      @force: force upgrade even if firmware doesn't cooperate
7152  *
7153  *      Perform all of the steps necessary for upgrading an adapter's
7154  *      firmware image.  Normally this requires the cooperation of the
7155  *      existing firmware in order to halt all existing activities
7156  *      but if an invalid mailbox token is passed in we skip that step
7157  *      (though we'll still put the adapter microprocessor into RESET in
7158  *      that case).
7159  *
7160  *      On successful return the new firmware will have been loaded and
7161  *      the adapter will have been fully RESET losing all previous setup
7162  *      state.  On unsuccessful return the adapter may be completely hosed ...
7163  *      positive errno indicates that the adapter is ~probably~ intact, a
7164  *      negative errno indicates that things are looking bad ...
7165  */
7166 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7167                   const u8 *fw_data, unsigned int size, int force)
7168 {
7169         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7170         int reset, ret;
7171
7172         if (!t4_fw_matches_chip(adap, fw_hdr))
7173                 return -EINVAL;
7174
7175         /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7176          * set wont be sent when we are flashing FW.
7177          */
7178         adap->flags &= ~CXGB4_FW_OK;
7179
7180         ret = t4_fw_halt(adap, mbox, force);
7181         if (ret < 0 && !force)
7182                 goto out;
7183
7184         ret = t4_load_fw(adap, fw_data, size);
7185         if (ret < 0)
7186                 goto out;
7187
7188         /*
7189          * If there was a Firmware Configuration File stored in FLASH,
7190          * there's a good chance that it won't be compatible with the new
7191          * Firmware.  In order to prevent difficult to diagnose adapter
7192          * initialization issues, we clear out the Firmware Configuration File
7193          * portion of the FLASH .  The user will need to re-FLASH a new
7194          * Firmware Configuration File which is compatible with the new
7195          * Firmware if that's desired.
7196          */
7197         (void)t4_load_cfg(adap, NULL, 0);
7198
7199         /*
7200          * Older versions of the firmware don't understand the new
7201          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7202          * restart.  So for newly loaded older firmware we'll have to do the
7203          * RESET for it so it starts up on a clean slate.  We can tell if
7204          * the newly loaded firmware will handle this right by checking
7205          * its header flags to see if it advertises the capability.
7206          */
7207         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7208         ret = t4_fw_restart(adap, mbox, reset);
7209
7210         /* Grab potentially new Firmware Device Log parameters so we can see
7211          * how healthy the new Firmware is.  It's okay to contact the new
7212          * Firmware for these parameters even though, as far as it's
7213          * concerned, we've never said "HELLO" to it ...
7214          */
7215         (void)t4_init_devlog_params(adap);
7216 out:
7217         adap->flags |= CXGB4_FW_OK;
7218         return ret;
7219 }
7220
7221 /**
7222  *      t4_fl_pkt_align - return the fl packet alignment
7223  *      @adap: the adapter
7224  *
7225  *      T4 has a single field to specify the packing and padding boundary.
7226  *      T5 onwards has separate fields for this and hence the alignment for
7227  *      next packet offset is maximum of these two.
7228  *
7229  */
7230 int t4_fl_pkt_align(struct adapter *adap)
7231 {
7232         u32 sge_control, sge_control2;
7233         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7234
7235         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7236
7237         /* T4 uses a single control field to specify both the PCIe Padding and
7238          * Packing Boundary.  T5 introduced the ability to specify these
7239          * separately.  The actual Ingress Packet Data alignment boundary
7240          * within Packed Buffer Mode is the maximum of these two
7241          * specifications.  (Note that it makes no real practical sense to
7242          * have the Padding Boundary be larger than the Packing Boundary but you
7243          * could set the chip up that way and, in fact, legacy T4 code would
7244          * end doing this because it would initialize the Padding Boundary and
7245          * leave the Packing Boundary initialized to 0 (16 bytes).)
7246          * Padding Boundary values in T6 starts from 8B,
7247          * where as it is 32B for T4 and T5.
7248          */
7249         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7250                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7251         else
7252                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7253
7254         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7255
7256         fl_align = ingpadboundary;
7257         if (!is_t4(adap->params.chip)) {
7258                 /* T5 has a weird interpretation of one of the PCIe Packing
7259                  * Boundary values.  No idea why ...
7260                  */
7261                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7262                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7263                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7264                         ingpackboundary = 16;
7265                 else
7266                         ingpackboundary = 1 << (ingpackboundary +
7267                                                 INGPACKBOUNDARY_SHIFT_X);
7268
7269                 fl_align = max(ingpadboundary, ingpackboundary);
7270         }
7271         return fl_align;
7272 }
7273
7274 /**
7275  *      t4_fixup_host_params - fix up host-dependent parameters
7276  *      @adap: the adapter
7277  *      @page_size: the host's Base Page Size
7278  *      @cache_line_size: the host's Cache Line Size
7279  *
7280  *      Various registers in T4 contain values which are dependent on the
7281  *      host's Base Page and Cache Line Sizes.  This function will fix all of
7282  *      those registers with the appropriate values as passed in ...
7283  */
7284 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7285                          unsigned int cache_line_size)
7286 {
7287         unsigned int page_shift = fls(page_size) - 1;
7288         unsigned int sge_hps = page_shift - 10;
7289         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7290         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7291         unsigned int fl_align_log = fls(fl_align) - 1;
7292
7293         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7294                      HOSTPAGESIZEPF0_V(sge_hps) |
7295                      HOSTPAGESIZEPF1_V(sge_hps) |
7296                      HOSTPAGESIZEPF2_V(sge_hps) |
7297                      HOSTPAGESIZEPF3_V(sge_hps) |
7298                      HOSTPAGESIZEPF4_V(sge_hps) |
7299                      HOSTPAGESIZEPF5_V(sge_hps) |
7300                      HOSTPAGESIZEPF6_V(sge_hps) |
7301                      HOSTPAGESIZEPF7_V(sge_hps));
7302
7303         if (is_t4(adap->params.chip)) {
7304                 t4_set_reg_field(adap, SGE_CONTROL_A,
7305                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7306                                  EGRSTATUSPAGESIZE_F,
7307                                  INGPADBOUNDARY_V(fl_align_log -
7308                                                   INGPADBOUNDARY_SHIFT_X) |
7309                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7310         } else {
7311                 unsigned int pack_align;
7312                 unsigned int ingpad, ingpack;
7313
7314                 /* T5 introduced the separation of the Free List Padding and
7315                  * Packing Boundaries.  Thus, we can select a smaller Padding
7316                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
7317                  * Bandwidth, and use a Packing Boundary which is large enough
7318                  * to avoid false sharing between CPUs, etc.
7319                  *
7320                  * For the PCI Link, the smaller the Padding Boundary the
7321                  * better.  For the Memory Controller, a smaller Padding
7322                  * Boundary is better until we cross under the Memory Line
7323                  * Size (the minimum unit of transfer to/from Memory).  If we
7324                  * have a Padding Boundary which is smaller than the Memory
7325                  * Line Size, that'll involve a Read-Modify-Write cycle on the
7326                  * Memory Controller which is never good.
7327                  */
7328
7329                 /* We want the Packing Boundary to be based on the Cache Line
7330                  * Size in order to help avoid False Sharing performance
7331                  * issues between CPUs, etc.  We also want the Packing
7332                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
7333                  * get best performance when the Packing Boundary is a
7334                  * multiple of the Maximum Payload Size.
7335                  */
7336                 pack_align = fl_align;
7337                 if (pci_is_pcie(adap->pdev)) {
7338                         unsigned int mps, mps_log;
7339                         u16 devctl;
7340
7341                         /* The PCIe Device Control Maximum Payload Size field
7342                          * [bits 7:5] encodes sizes as powers of 2 starting at
7343                          * 128 bytes.
7344                          */
7345                         pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL,
7346                                                   &devctl);
7347                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7348                         mps = 1 << mps_log;
7349                         if (mps > pack_align)
7350                                 pack_align = mps;
7351                 }
7352
7353                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7354                  * value for the Packing Boundary.  This corresponds to 16
7355                  * bytes instead of the expected 32 bytes.  So if we want 32
7356                  * bytes, the best we can really do is 64 bytes ...
7357                  */
7358                 if (pack_align <= 16) {
7359                         ingpack = INGPACKBOUNDARY_16B_X;
7360                         fl_align = 16;
7361                 } else if (pack_align == 32) {
7362                         ingpack = INGPACKBOUNDARY_64B_X;
7363                         fl_align = 64;
7364                 } else {
7365                         unsigned int pack_align_log = fls(pack_align) - 1;
7366
7367                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7368                         fl_align = pack_align;
7369                 }
7370
7371                 /* Use the smallest Ingress Padding which isn't smaller than
7372                  * the Memory Controller Read/Write Size.  We'll take that as
7373                  * being 8 bytes since we don't know of any system with a
7374                  * wider Memory Controller Bus Width.
7375                  */
7376                 if (is_t5(adap->params.chip))
7377                         ingpad = INGPADBOUNDARY_32B_X;
7378                 else
7379                         ingpad = T6_INGPADBOUNDARY_8B_X;
7380
7381                 t4_set_reg_field(adap, SGE_CONTROL_A,
7382                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7383                                  EGRSTATUSPAGESIZE_F,
7384                                  INGPADBOUNDARY_V(ingpad) |
7385                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
7386                 t4_set_reg_field(adap, SGE_CONTROL2_A,
7387                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7388                                  INGPACKBOUNDARY_V(ingpack));
7389         }
7390         /*
7391          * Adjust various SGE Free List Host Buffer Sizes.
7392          *
7393          * This is something of a crock since we're using fixed indices into
7394          * the array which are also known by the sge.c code and the T4
7395          * Firmware Configuration File.  We need to come up with a much better
7396          * approach to managing this array.  For now, the first four entries
7397          * are:
7398          *
7399          *   0: Host Page Size
7400          *   1: 64KB
7401          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7402          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7403          *
7404          * For the single-MTU buffers in unpacked mode we need to include
7405          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7406          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7407          * Padding boundary.  All of these are accommodated in the Factory
7408          * Default Firmware Configuration File but we need to adjust it for
7409          * this host's cache line size.
7410          */
7411         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7412         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7413                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7414                      & ~(fl_align-1));
7415         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7416                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7417                      & ~(fl_align-1));
7418
7419         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7420
7421         return 0;
7422 }
7423
7424 /**
7425  *      t4_fw_initialize - ask FW to initialize the device
7426  *      @adap: the adapter
7427  *      @mbox: mailbox to use for the FW command
7428  *
7429  *      Issues a command to FW to partially initialize the device.  This
7430  *      performs initialization that generally doesn't depend on user input.
7431  */
7432 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7433 {
7434         struct fw_initialize_cmd c;
7435
7436         memset(&c, 0, sizeof(c));
7437         INIT_CMD(c, INITIALIZE, WRITE);
7438         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7439 }
7440
7441 /**
7442  *      t4_query_params_rw - query FW or device parameters
7443  *      @adap: the adapter
7444  *      @mbox: mailbox to use for the FW command
7445  *      @pf: the PF
7446  *      @vf: the VF
7447  *      @nparams: the number of parameters
7448  *      @params: the parameter names
7449  *      @val: the parameter values
7450  *      @rw: Write and read flag
7451  *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7452  *
7453  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7454  *      queried at once.
7455  */
7456 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7457                        unsigned int vf, unsigned int nparams, const u32 *params,
7458                        u32 *val, int rw, bool sleep_ok)
7459 {
7460         int i, ret;
7461         struct fw_params_cmd c;
7462         __be32 *p = &c.param[0].mnem;
7463
7464         if (nparams > 7)
7465                 return -EINVAL;
7466
7467         memset(&c, 0, sizeof(c));
7468         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7469                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
7470                                   FW_PARAMS_CMD_PFN_V(pf) |
7471                                   FW_PARAMS_CMD_VFN_V(vf));
7472         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7473
7474         for (i = 0; i < nparams; i++) {
7475                 *p++ = cpu_to_be32(*params++);
7476                 if (rw)
7477                         *p = cpu_to_be32(*(val + i));
7478                 p++;
7479         }
7480
7481         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7482         if (ret == 0)
7483                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7484                         *val++ = be32_to_cpu(*p);
7485         return ret;
7486 }
7487
7488 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7489                     unsigned int vf, unsigned int nparams, const u32 *params,
7490                     u32 *val)
7491 {
7492         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7493                                   true);
7494 }
7495
7496 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7497                        unsigned int vf, unsigned int nparams, const u32 *params,
7498                        u32 *val)
7499 {
7500         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7501                                   false);
7502 }
7503
7504 /**
7505  *      t4_set_params_timeout - sets FW or device parameters
7506  *      @adap: the adapter
7507  *      @mbox: mailbox to use for the FW command
7508  *      @pf: the PF
7509  *      @vf: the VF
7510  *      @nparams: the number of parameters
7511  *      @params: the parameter names
7512  *      @val: the parameter values
7513  *      @timeout: the timeout time
7514  *
7515  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7516  *      specified at once.
7517  */
7518 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7519                           unsigned int pf, unsigned int vf,
7520                           unsigned int nparams, const u32 *params,
7521                           const u32 *val, int timeout)
7522 {
7523         struct fw_params_cmd c;
7524         __be32 *p = &c.param[0].mnem;
7525
7526         if (nparams > 7)
7527                 return -EINVAL;
7528
7529         memset(&c, 0, sizeof(c));
7530         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7531                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7532                                   FW_PARAMS_CMD_PFN_V(pf) |
7533                                   FW_PARAMS_CMD_VFN_V(vf));
7534         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7535
7536         while (nparams--) {
7537                 *p++ = cpu_to_be32(*params++);
7538                 *p++ = cpu_to_be32(*val++);
7539         }
7540
7541         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7542 }
7543
7544 /**
7545  *      t4_set_params - sets FW or device parameters
7546  *      @adap: the adapter
7547  *      @mbox: mailbox to use for the FW command
7548  *      @pf: the PF
7549  *      @vf: the VF
7550  *      @nparams: the number of parameters
7551  *      @params: the parameter names
7552  *      @val: the parameter values
7553  *
7554  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7555  *      specified at once.
7556  */
7557 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7558                   unsigned int vf, unsigned int nparams, const u32 *params,
7559                   const u32 *val)
7560 {
7561         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7562                                      FW_CMD_MAX_TIMEOUT);
7563 }
7564
7565 /**
7566  *      t4_cfg_pfvf - configure PF/VF resource limits
7567  *      @adap: the adapter
7568  *      @mbox: mailbox to use for the FW command
7569  *      @pf: the PF being configured
7570  *      @vf: the VF being configured
7571  *      @txq: the max number of egress queues
7572  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7573  *      @rxqi: the max number of interrupt-capable ingress queues
7574  *      @rxq: the max number of interruptless ingress queues
7575  *      @tc: the PCI traffic class
7576  *      @vi: the max number of virtual interfaces
7577  *      @cmask: the channel access rights mask for the PF/VF
7578  *      @pmask: the port access rights mask for the PF/VF
7579  *      @nexact: the maximum number of exact MPS filters
7580  *      @rcaps: read capabilities
7581  *      @wxcaps: write/execute capabilities
7582  *
7583  *      Configures resource limits and capabilities for a physical or virtual
7584  *      function.
7585  */
7586 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7587                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7588                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7589                 unsigned int vi, unsigned int cmask, unsigned int pmask,
7590                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7591 {
7592         struct fw_pfvf_cmd c;
7593
7594         memset(&c, 0, sizeof(c));
7595         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7596                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7597                                   FW_PFVF_CMD_VFN_V(vf));
7598         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7599         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7600                                      FW_PFVF_CMD_NIQ_V(rxq));
7601         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7602                                     FW_PFVF_CMD_PMASK_V(pmask) |
7603                                     FW_PFVF_CMD_NEQ_V(txq));
7604         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7605                                       FW_PFVF_CMD_NVI_V(vi) |
7606                                       FW_PFVF_CMD_NEXACTF_V(nexact));
7607         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7608                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7609                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7610         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7611 }
7612
7613 /**
7614  *      t4_alloc_vi - allocate a virtual interface
7615  *      @adap: the adapter
7616  *      @mbox: mailbox to use for the FW command
7617  *      @port: physical port associated with the VI
7618  *      @pf: the PF owning the VI
7619  *      @vf: the VF owning the VI
7620  *      @nmac: number of MAC addresses needed (1 to 5)
7621  *      @mac: the MAC addresses of the VI
7622  *      @rss_size: size of RSS table slice associated with this VI
7623  *
7624  *      Allocates a virtual interface for the given physical port.  If @mac is
7625  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7626  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7627  *      stored consecutively so the space needed is @nmac * 6 bytes.
7628  *      Returns a negative error number or the non-negative VI id.
7629  */
7630 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7631                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7632                 unsigned int *rss_size, u8 *vivld, u8 *vin)
7633 {
7634         int ret;
7635         struct fw_vi_cmd c;
7636
7637         memset(&c, 0, sizeof(c));
7638         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7639                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7640                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7641         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7642         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7643         c.nmac = nmac - 1;
7644
7645         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7646         if (ret)
7647                 return ret;
7648
7649         if (mac) {
7650                 memcpy(mac, c.mac, sizeof(c.mac));
7651                 switch (nmac) {
7652                 case 5:
7653                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7654                         /* Fall through */
7655                 case 4:
7656                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7657                         /* Fall through */
7658                 case 3:
7659                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7660                         /* Fall through */
7661                 case 2:
7662                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7663                 }
7664         }
7665         if (rss_size)
7666                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7667
7668         if (vivld)
7669                 *vivld = FW_VI_CMD_VFVLD_G(be32_to_cpu(c.alloc_to_len16));
7670
7671         if (vin)
7672                 *vin = FW_VI_CMD_VIN_G(be32_to_cpu(c.alloc_to_len16));
7673
7674         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7675 }
7676
7677 /**
7678  *      t4_free_vi - free a virtual interface
7679  *      @adap: the adapter
7680  *      @mbox: mailbox to use for the FW command
7681  *      @pf: the PF owning the VI
7682  *      @vf: the VF owning the VI
7683  *      @viid: virtual interface identifiler
7684  *
7685  *      Free a previously allocated virtual interface.
7686  */
7687 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7688                unsigned int vf, unsigned int viid)
7689 {
7690         struct fw_vi_cmd c;
7691
7692         memset(&c, 0, sizeof(c));
7693         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7694                                   FW_CMD_REQUEST_F |
7695                                   FW_CMD_EXEC_F |
7696                                   FW_VI_CMD_PFN_V(pf) |
7697                                   FW_VI_CMD_VFN_V(vf));
7698         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7699         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7700
7701         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7702 }
7703
7704 /**
7705  *      t4_set_rxmode - set Rx properties of a virtual interface
7706  *      @adap: the adapter
7707  *      @mbox: mailbox to use for the FW command
7708  *      @viid: the VI id
7709  *      @mtu: the new MTU or -1
7710  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7711  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7712  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7713  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7714  *      @sleep_ok: if true we may sleep while awaiting command completion
7715  *
7716  *      Sets Rx properties of a virtual interface.
7717  */
7718 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7719                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
7720                   bool sleep_ok)
7721 {
7722         struct fw_vi_rxmode_cmd c;
7723
7724         /* convert to FW values */
7725         if (mtu < 0)
7726                 mtu = FW_RXMODE_MTU_NO_CHG;
7727         if (promisc < 0)
7728                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7729         if (all_multi < 0)
7730                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7731         if (bcast < 0)
7732                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7733         if (vlanex < 0)
7734                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7735
7736         memset(&c, 0, sizeof(c));
7737         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7738                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7739                                    FW_VI_RXMODE_CMD_VIID_V(viid));
7740         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7741         c.mtu_to_vlanexen =
7742                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7743                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7744                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7745                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7746                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7747         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7748 }
7749
7750 /**
7751  *      t4_free_encap_mac_filt - frees MPS entry at given index
7752  *      @adap: the adapter
7753  *      @viid: the VI id
7754  *      @idx: index of MPS entry to be freed
7755  *      @sleep_ok: call is allowed to sleep
7756  *
7757  *      Frees the MPS entry at supplied index
7758  *
7759  *      Returns a negative error number or zero on success
7760  */
7761 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7762                            int idx, bool sleep_ok)
7763 {
7764         struct fw_vi_mac_exact *p;
7765         u8 addr[] = {0, 0, 0, 0, 0, 0};
7766         struct fw_vi_mac_cmd c;
7767         int ret = 0;
7768         u32 exact;
7769
7770         memset(&c, 0, sizeof(c));
7771         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7772                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7773                                    FW_CMD_EXEC_V(0) |
7774                                    FW_VI_MAC_CMD_VIID_V(viid));
7775         exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7776         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7777                                           exact |
7778                                           FW_CMD_LEN16_V(1));
7779         p = c.u.exact;
7780         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7781                                       FW_VI_MAC_CMD_IDX_V(idx));
7782         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7783         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7784         return ret;
7785 }
7786
7787 /**
7788  *      t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7789  *      @adap: the adapter
7790  *      @viid: the VI id
7791  *      @addr: the MAC address
7792  *      @mask: the mask
7793  *      @idx: index of the entry in mps tcam
7794  *      @lookup_type: MAC address for inner (1) or outer (0) header
7795  *      @port_id: the port index
7796  *      @sleep_ok: call is allowed to sleep
7797  *
7798  *      Removes the mac entry at the specified index using raw mac interface.
7799  *
7800  *      Returns a negative error number on failure.
7801  */
7802 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7803                          const u8 *addr, const u8 *mask, unsigned int idx,
7804                          u8 lookup_type, u8 port_id, bool sleep_ok)
7805 {
7806         struct fw_vi_mac_cmd c;
7807         struct fw_vi_mac_raw *p = &c.u.raw;
7808         u32 val;
7809
7810         memset(&c, 0, sizeof(c));
7811         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7812                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7813                                    FW_CMD_EXEC_V(0) |
7814                                    FW_VI_MAC_CMD_VIID_V(viid));
7815         val = FW_CMD_LEN16_V(1) |
7816               FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7817         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7818                                           FW_CMD_LEN16_V(val));
7819
7820         p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7821                                      FW_VI_MAC_ID_BASED_FREE);
7822
7823         /* Lookup Type. Outer header: 0, Inner header: 1 */
7824         p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7825                                    DATAPORTNUM_V(port_id));
7826         /* Lookup mask and port mask */
7827         p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7828                                     DATAPORTNUM_V(DATAPORTNUM_M));
7829
7830         /* Copy the address and the mask */
7831         memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7832         memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7833
7834         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7835 }
7836
7837 /**
7838  *      t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7839  *      @adap: the adapter
7840  *      @viid: the VI id
7841  *      @mac: the MAC address
7842  *      @mask: the mask
7843  *      @vni: the VNI id for the tunnel protocol
7844  *      @vni_mask: mask for the VNI id
7845  *      @dip_hit: to enable DIP match for the MPS entry
7846  *      @lookup_type: MAC address for inner (1) or outer (0) header
7847  *      @sleep_ok: call is allowed to sleep
7848  *
7849  *      Allocates an MPS entry with specified MAC address and VNI value.
7850  *
7851  *      Returns a negative error number or the allocated index for this mac.
7852  */
7853 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7854                             const u8 *addr, const u8 *mask, unsigned int vni,
7855                             unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7856                             bool sleep_ok)
7857 {
7858         struct fw_vi_mac_cmd c;
7859         struct fw_vi_mac_vni *p = c.u.exact_vni;
7860         int ret = 0;
7861         u32 val;
7862
7863         memset(&c, 0, sizeof(c));
7864         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7865                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7866                                    FW_VI_MAC_CMD_VIID_V(viid));
7867         val = FW_CMD_LEN16_V(1) |
7868               FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7869         c.freemacs_to_len16 = cpu_to_be32(val);
7870         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7871                                       FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7872         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7873         memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7874
7875         p->lookup_type_to_vni =
7876                 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7877                             FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7878                             FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7879         p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7880         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7881         if (ret == 0)
7882                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7883         return ret;
7884 }
7885
7886 /**
7887  *      t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7888  *      @adap: the adapter
7889  *      @viid: the VI id
7890  *      @mac: the MAC address
7891  *      @mask: the mask
7892  *      @idx: index at which to add this entry
7893  *      @port_id: the port index
7894  *      @lookup_type: MAC address for inner (1) or outer (0) header
7895  *      @sleep_ok: call is allowed to sleep
7896  *
7897  *      Adds the mac entry at the specified index using raw mac interface.
7898  *
7899  *      Returns a negative error number or the allocated index for this mac.
7900  */
7901 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7902                           const u8 *addr, const u8 *mask, unsigned int idx,
7903                           u8 lookup_type, u8 port_id, bool sleep_ok)
7904 {
7905         int ret = 0;
7906         struct fw_vi_mac_cmd c;
7907         struct fw_vi_mac_raw *p = &c.u.raw;
7908         u32 val;
7909
7910         memset(&c, 0, sizeof(c));
7911         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7912                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7913                                    FW_VI_MAC_CMD_VIID_V(viid));
7914         val = FW_CMD_LEN16_V(1) |
7915               FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7916         c.freemacs_to_len16 = cpu_to_be32(val);
7917
7918         /* Specify that this is an inner mac address */
7919         p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7920
7921         /* Lookup Type. Outer header: 0, Inner header: 1 */
7922         p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7923                                    DATAPORTNUM_V(port_id));
7924         /* Lookup mask and port mask */
7925         p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7926                                     DATAPORTNUM_V(DATAPORTNUM_M));
7927
7928         /* Copy the address and the mask */
7929         memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7930         memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7931
7932         ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7933         if (ret == 0) {
7934                 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7935                 if (ret != idx)
7936                         ret = -ENOMEM;
7937         }
7938
7939         return ret;
7940 }
7941
7942 /**
7943  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7944  *      @adap: the adapter
7945  *      @mbox: mailbox to use for the FW command
7946  *      @viid: the VI id
7947  *      @free: if true any existing filters for this VI id are first removed
7948  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7949  *      @addr: the MAC address(es)
7950  *      @idx: where to store the index of each allocated filter
7951  *      @hash: pointer to hash address filter bitmap
7952  *      @sleep_ok: call is allowed to sleep
7953  *
7954  *      Allocates an exact-match filter for each of the supplied addresses and
7955  *      sets it to the corresponding address.  If @idx is not %NULL it should
7956  *      have at least @naddr entries, each of which will be set to the index of
7957  *      the filter allocated for the corresponding MAC address.  If a filter
7958  *      could not be allocated for an address its index is set to 0xffff.
7959  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7960  *      are hashed and update the hash filter bitmap pointed at by @hash.
7961  *
7962  *      Returns a negative error number or the number of filters allocated.
7963  */
7964 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7965                       unsigned int viid, bool free, unsigned int naddr,
7966                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7967 {
7968         int offset, ret = 0;
7969         struct fw_vi_mac_cmd c;
7970         unsigned int nfilters = 0;
7971         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7972         unsigned int rem = naddr;
7973
7974         if (naddr > max_naddr)
7975                 return -EINVAL;
7976
7977         for (offset = 0; offset < naddr ; /**/) {
7978                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7979                                          rem : ARRAY_SIZE(c.u.exact));
7980                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7981                                                      u.exact[fw_naddr]), 16);
7982                 struct fw_vi_mac_exact *p;
7983                 int i;
7984
7985                 memset(&c, 0, sizeof(c));
7986                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7987                                            FW_CMD_REQUEST_F |
7988                                            FW_CMD_WRITE_F |
7989                                            FW_CMD_EXEC_V(free) |
7990                                            FW_VI_MAC_CMD_VIID_V(viid));
7991                 c.freemacs_to_len16 =
7992                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7993                                     FW_CMD_LEN16_V(len16));
7994
7995                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7996                         p->valid_to_idx =
7997                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7998                                             FW_VI_MAC_CMD_IDX_V(
7999                                                     FW_VI_MAC_ADD_MAC));
8000                         memcpy(p->macaddr, addr[offset + i],
8001                                sizeof(p->macaddr));
8002                 }
8003
8004                 /* It's okay if we run out of space in our MAC address arena.
8005                  * Some of the addresses we submit may get stored so we need
8006                  * to run through the reply to see what the results were ...
8007                  */
8008                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8009                 if (ret && ret != -FW_ENOMEM)
8010                         break;
8011
8012                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8013                         u16 index = FW_VI_MAC_CMD_IDX_G(
8014                                         be16_to_cpu(p->valid_to_idx));
8015
8016                         if (idx)
8017                                 idx[offset + i] = (index >= max_naddr ?
8018                                                    0xffff : index);
8019                         if (index < max_naddr)
8020                                 nfilters++;
8021                         else if (hash)
8022                                 *hash |= (1ULL <<
8023                                           hash_mac_addr(addr[offset + i]));
8024                 }
8025
8026                 free = false;
8027                 offset += fw_naddr;
8028                 rem -= fw_naddr;
8029         }
8030
8031         if (ret == 0 || ret == -FW_ENOMEM)
8032                 ret = nfilters;
8033         return ret;
8034 }
8035
8036 /**
8037  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
8038  *      @adap: the adapter
8039  *      @mbox: mailbox to use for the FW command
8040  *      @viid: the VI id
8041  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
8042  *      @addr: the MAC address(es)
8043  *      @sleep_ok: call is allowed to sleep
8044  *
8045  *      Frees the exact-match filter for each of the supplied addresses
8046  *
8047  *      Returns a negative error number or the number of filters freed.
8048  */
8049 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8050                      unsigned int viid, unsigned int naddr,
8051                      const u8 **addr, bool sleep_ok)
8052 {
8053         int offset, ret = 0;
8054         struct fw_vi_mac_cmd c;
8055         unsigned int nfilters = 0;
8056         unsigned int max_naddr = is_t4(adap->params.chip) ?
8057                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
8058                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8059         unsigned int rem = naddr;
8060
8061         if (naddr > max_naddr)
8062                 return -EINVAL;
8063
8064         for (offset = 0; offset < (int)naddr ; /**/) {
8065                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8066                                          ? rem
8067                                          : ARRAY_SIZE(c.u.exact));
8068                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8069                                                      u.exact[fw_naddr]), 16);
8070                 struct fw_vi_mac_exact *p;
8071                 int i;
8072
8073                 memset(&c, 0, sizeof(c));
8074                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8075                                      FW_CMD_REQUEST_F |
8076                                      FW_CMD_WRITE_F |
8077                                      FW_CMD_EXEC_V(0) |
8078                                      FW_VI_MAC_CMD_VIID_V(viid));
8079                 c.freemacs_to_len16 =
8080                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8081                                             FW_CMD_LEN16_V(len16));
8082
8083                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8084                         p->valid_to_idx = cpu_to_be16(
8085                                 FW_VI_MAC_CMD_VALID_F |
8086                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
8087                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8088                 }
8089
8090                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8091                 if (ret)
8092                         break;
8093
8094                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8095                         u16 index = FW_VI_MAC_CMD_IDX_G(
8096                                                 be16_to_cpu(p->valid_to_idx));
8097
8098                         if (index < max_naddr)
8099                                 nfilters++;
8100                 }
8101
8102                 offset += fw_naddr;
8103                 rem -= fw_naddr;
8104         }
8105
8106         if (ret == 0)
8107                 ret = nfilters;
8108         return ret;
8109 }
8110
8111 /**
8112  *      t4_change_mac - modifies the exact-match filter for a MAC address
8113  *      @adap: the adapter
8114  *      @mbox: mailbox to use for the FW command
8115  *      @viid: the VI id
8116  *      @idx: index of existing filter for old value of MAC address, or -1
8117  *      @addr: the new MAC address value
8118  *      @persist: whether a new MAC allocation should be persistent
8119  *      @add_smt: if true also add the address to the HW SMT
8120  *
8121  *      Modifies an exact-match filter and sets it to the new MAC address.
8122  *      Note that in general it is not possible to modify the value of a given
8123  *      filter so the generic way to modify an address filter is to free the one
8124  *      being used by the old address value and allocate a new filter for the
8125  *      new address value.  @idx can be -1 if the address is a new addition.
8126  *
8127  *      Returns a negative error number or the index of the filter with the new
8128  *      MAC value.
8129  */
8130 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8131                   int idx, const u8 *addr, bool persist, u8 *smt_idx)
8132 {
8133         int ret, mode;
8134         struct fw_vi_mac_cmd c;
8135         struct fw_vi_mac_exact *p = c.u.exact;
8136         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
8137
8138         if (idx < 0)                             /* new allocation */
8139                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8140         mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8141
8142         memset(&c, 0, sizeof(c));
8143         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8144                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8145                                    FW_VI_MAC_CMD_VIID_V(viid));
8146         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
8147         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8148                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
8149                                       FW_VI_MAC_CMD_IDX_V(idx));
8150         memcpy(p->macaddr, addr, sizeof(p->macaddr));
8151
8152         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8153         if (ret == 0) {
8154                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
8155                 if (ret >= max_mac_addr)
8156                         ret = -ENOMEM;
8157                 if (smt_idx) {
8158                         if (adap->params.viid_smt_extn_support) {
8159                                 *smt_idx = FW_VI_MAC_CMD_SMTID_G
8160                                                     (be32_to_cpu(c.op_to_viid));
8161                         } else {
8162                                 /* In T4/T5, SMT contains 256 SMAC entries
8163                                  * organized in 128 rows of 2 entries each.
8164                                  * In T6, SMT contains 256 SMAC entries in
8165                                  * 256 rows.
8166                                  */
8167                                 if (CHELSIO_CHIP_VERSION(adap->params.chip) <=
8168                                                                      CHELSIO_T5)
8169                                         *smt_idx = (viid & FW_VIID_VIN_M) << 1;
8170                                 else
8171                                         *smt_idx = (viid & FW_VIID_VIN_M);
8172                         }
8173                 }
8174         }
8175         return ret;
8176 }
8177
8178 /**
8179  *      t4_set_addr_hash - program the MAC inexact-match hash filter
8180  *      @adap: the adapter
8181  *      @mbox: mailbox to use for the FW command
8182  *      @viid: the VI id
8183  *      @ucast: whether the hash filter should also match unicast addresses
8184  *      @vec: the value to be written to the hash filter
8185  *      @sleep_ok: call is allowed to sleep
8186  *
8187  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
8188  */
8189 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8190                      bool ucast, u64 vec, bool sleep_ok)
8191 {
8192         struct fw_vi_mac_cmd c;
8193
8194         memset(&c, 0, sizeof(c));
8195         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8196                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8197                                    FW_VI_ENABLE_CMD_VIID_V(viid));
8198         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
8199                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
8200                                           FW_CMD_LEN16_V(1));
8201         c.u.hash.hashvec = cpu_to_be64(vec);
8202         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8203 }
8204
8205 /**
8206  *      t4_enable_vi_params - enable/disable a virtual interface
8207  *      @adap: the adapter
8208  *      @mbox: mailbox to use for the FW command
8209  *      @viid: the VI id
8210  *      @rx_en: 1=enable Rx, 0=disable Rx
8211  *      @tx_en: 1=enable Tx, 0=disable Tx
8212  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8213  *
8214  *      Enables/disables a virtual interface.  Note that setting DCB Enable
8215  *      only makes sense when enabling a Virtual Interface ...
8216  */
8217 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8218                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8219 {
8220         struct fw_vi_enable_cmd c;
8221
8222         memset(&c, 0, sizeof(c));
8223         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8224                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8225                                    FW_VI_ENABLE_CMD_VIID_V(viid));
8226         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8227                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8228                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8229                                      FW_LEN16(c));
8230         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8231 }
8232
8233 /**
8234  *      t4_enable_vi - enable/disable a virtual interface
8235  *      @adap: the adapter
8236  *      @mbox: mailbox to use for the FW command
8237  *      @viid: the VI id
8238  *      @rx_en: 1=enable Rx, 0=disable Rx
8239  *      @tx_en: 1=enable Tx, 0=disable Tx
8240  *
8241  *      Enables/disables a virtual interface.
8242  */
8243 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8244                  bool rx_en, bool tx_en)
8245 {
8246         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8247 }
8248
8249 /**
8250  *      t4_enable_pi_params - enable/disable a Port's Virtual Interface
8251  *      @adap: the adapter
8252  *      @mbox: mailbox to use for the FW command
8253  *      @pi: the Port Information structure
8254  *      @rx_en: 1=enable Rx, 0=disable Rx
8255  *      @tx_en: 1=enable Tx, 0=disable Tx
8256  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8257  *
8258  *      Enables/disables a Port's Virtual Interface.  Note that setting DCB
8259  *      Enable only makes sense when enabling a Virtual Interface ...
8260  *      If the Virtual Interface enable/disable operation is successful,
8261  *      we notify the OS-specific code of a potential Link Status change
8262  *      via the OS Contract API t4_os_link_changed().
8263  */
8264 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8265                         struct port_info *pi,
8266                         bool rx_en, bool tx_en, bool dcb_en)
8267 {
8268         int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8269                                       rx_en, tx_en, dcb_en);
8270         if (ret)
8271                 return ret;
8272         t4_os_link_changed(adap, pi->port_id,
8273                            rx_en && tx_en && pi->link_cfg.link_ok);
8274         return 0;
8275 }
8276
8277 /**
8278  *      t4_identify_port - identify a VI's port by blinking its LED
8279  *      @adap: the adapter
8280  *      @mbox: mailbox to use for the FW command
8281  *      @viid: the VI id
8282  *      @nblinks: how many times to blink LED at 2.5 Hz
8283  *
8284  *      Identifies a VI's port by blinking its LED.
8285  */
8286 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8287                      unsigned int nblinks)
8288 {
8289         struct fw_vi_enable_cmd c;
8290
8291         memset(&c, 0, sizeof(c));
8292         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8293                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8294                                    FW_VI_ENABLE_CMD_VIID_V(viid));
8295         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8296         c.blinkdur = cpu_to_be16(nblinks);
8297         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8298 }
8299
8300 /**
8301  *      t4_iq_stop - stop an ingress queue and its FLs
8302  *      @adap: the adapter
8303  *      @mbox: mailbox to use for the FW command
8304  *      @pf: the PF owning the queues
8305  *      @vf: the VF owning the queues
8306  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8307  *      @iqid: ingress queue id
8308  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
8309  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
8310  *
8311  *      Stops an ingress queue and its associated FLs, if any.  This causes
8312  *      any current or future data/messages destined for these queues to be
8313  *      tossed.
8314  */
8315 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8316                unsigned int vf, unsigned int iqtype, unsigned int iqid,
8317                unsigned int fl0id, unsigned int fl1id)
8318 {
8319         struct fw_iq_cmd c;
8320
8321         memset(&c, 0, sizeof(c));
8322         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8323                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8324                                   FW_IQ_CMD_VFN_V(vf));
8325         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8326         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8327         c.iqid = cpu_to_be16(iqid);
8328         c.fl0id = cpu_to_be16(fl0id);
8329         c.fl1id = cpu_to_be16(fl1id);
8330         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8331 }
8332
8333 /**
8334  *      t4_iq_free - free an ingress queue and its FLs
8335  *      @adap: the adapter
8336  *      @mbox: mailbox to use for the FW command
8337  *      @pf: the PF owning the queues
8338  *      @vf: the VF owning the queues
8339  *      @iqtype: the ingress queue type
8340  *      @iqid: ingress queue id
8341  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
8342  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
8343  *
8344  *      Frees an ingress queue and its associated FLs, if any.
8345  */
8346 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8347                unsigned int vf, unsigned int iqtype, unsigned int iqid,
8348                unsigned int fl0id, unsigned int fl1id)
8349 {
8350         struct fw_iq_cmd c;
8351
8352         memset(&c, 0, sizeof(c));
8353         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8354                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8355                                   FW_IQ_CMD_VFN_V(vf));
8356         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8357         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8358         c.iqid = cpu_to_be16(iqid);
8359         c.fl0id = cpu_to_be16(fl0id);
8360         c.fl1id = cpu_to_be16(fl1id);
8361         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8362 }
8363
8364 /**
8365  *      t4_eth_eq_free - free an Ethernet egress queue
8366  *      @adap: the adapter
8367  *      @mbox: mailbox to use for the FW command
8368  *      @pf: the PF owning the queue
8369  *      @vf: the VF owning the queue
8370  *      @eqid: egress queue id
8371  *
8372  *      Frees an Ethernet egress queue.
8373  */
8374 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8375                    unsigned int vf, unsigned int eqid)
8376 {
8377         struct fw_eq_eth_cmd c;
8378
8379         memset(&c, 0, sizeof(c));
8380         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8381                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8382                                   FW_EQ_ETH_CMD_PFN_V(pf) |
8383                                   FW_EQ_ETH_CMD_VFN_V(vf));
8384         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8385         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8386         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8387 }
8388
8389 /**
8390  *      t4_ctrl_eq_free - free a control egress queue
8391  *      @adap: the adapter
8392  *      @mbox: mailbox to use for the FW command
8393  *      @pf: the PF owning the queue
8394  *      @vf: the VF owning the queue
8395  *      @eqid: egress queue id
8396  *
8397  *      Frees a control egress queue.
8398  */
8399 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8400                     unsigned int vf, unsigned int eqid)
8401 {
8402         struct fw_eq_ctrl_cmd c;
8403
8404         memset(&c, 0, sizeof(c));
8405         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8406                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8407                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
8408                                   FW_EQ_CTRL_CMD_VFN_V(vf));
8409         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8410         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8411         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8412 }
8413
8414 /**
8415  *      t4_ofld_eq_free - free an offload egress queue
8416  *      @adap: the adapter
8417  *      @mbox: mailbox to use for the FW command
8418  *      @pf: the PF owning the queue
8419  *      @vf: the VF owning the queue
8420  *      @eqid: egress queue id
8421  *
8422  *      Frees a control egress queue.
8423  */
8424 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8425                     unsigned int vf, unsigned int eqid)
8426 {
8427         struct fw_eq_ofld_cmd c;
8428
8429         memset(&c, 0, sizeof(c));
8430         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8431                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8432                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
8433                                   FW_EQ_OFLD_CMD_VFN_V(vf));
8434         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8435         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8436         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8437 }
8438
8439 /**
8440  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
8441  *      @adap: the adapter
8442  *      @link_down_rc: Link Down Reason Code
8443  *
8444  *      Returns a string representation of the Link Down Reason Code.
8445  */
8446 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8447 {
8448         static const char * const reason[] = {
8449                 "Link Down",
8450                 "Remote Fault",
8451                 "Auto-negotiation Failure",
8452                 "Reserved",
8453                 "Insufficient Airflow",
8454                 "Unable To Determine Reason",
8455                 "No RX Signal Detected",
8456                 "Reserved",
8457         };
8458
8459         if (link_down_rc >= ARRAY_SIZE(reason))
8460                 return "Bad Reason Code";
8461
8462         return reason[link_down_rc];
8463 }
8464
8465 /**
8466  * Return the highest speed set in the port capabilities, in Mb/s.
8467  */
8468 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8469 {
8470         #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8471                 do { \
8472                         if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8473                                 return __speed; \
8474                 } while (0)
8475
8476         TEST_SPEED_RETURN(400G, 400000);
8477         TEST_SPEED_RETURN(200G, 200000);
8478         TEST_SPEED_RETURN(100G, 100000);
8479         TEST_SPEED_RETURN(50G,   50000);
8480         TEST_SPEED_RETURN(40G,   40000);
8481         TEST_SPEED_RETURN(25G,   25000);
8482         TEST_SPEED_RETURN(10G,   10000);
8483         TEST_SPEED_RETURN(1G,     1000);
8484         TEST_SPEED_RETURN(100M,    100);
8485
8486         #undef TEST_SPEED_RETURN
8487
8488         return 0;
8489 }
8490
8491 /**
8492  *      fwcap_to_fwspeed - return highest speed in Port Capabilities
8493  *      @acaps: advertised Port Capabilities
8494  *
8495  *      Get the highest speed for the port from the advertised Port
8496  *      Capabilities.  It will be either the highest speed from the list of
8497  *      speeds or whatever user has set using ethtool.
8498  */
8499 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8500 {
8501         #define TEST_SPEED_RETURN(__caps_speed) \
8502                 do { \
8503                         if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8504                                 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8505                 } while (0)
8506
8507         TEST_SPEED_RETURN(400G);
8508         TEST_SPEED_RETURN(200G);
8509         TEST_SPEED_RETURN(100G);
8510         TEST_SPEED_RETURN(50G);
8511         TEST_SPEED_RETURN(40G);
8512         TEST_SPEED_RETURN(25G);
8513         TEST_SPEED_RETURN(10G);
8514         TEST_SPEED_RETURN(1G);
8515         TEST_SPEED_RETURN(100M);
8516
8517         #undef TEST_SPEED_RETURN
8518
8519         return 0;
8520 }
8521
8522 /**
8523  *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8524  *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8525  *
8526  *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8527  *      32-bit Port Capabilities value.
8528  */
8529 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8530 {
8531         fw_port_cap32_t linkattr = 0;
8532
8533         /* Unfortunately the format of the Link Status in the old
8534          * 16-bit Port Information message isn't the same as the
8535          * 16-bit Port Capabilities bitfield used everywhere else ...
8536          */
8537         if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8538                 linkattr |= FW_PORT_CAP32_FC_RX;
8539         if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8540                 linkattr |= FW_PORT_CAP32_FC_TX;
8541         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8542                 linkattr |= FW_PORT_CAP32_SPEED_100M;
8543         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8544                 linkattr |= FW_PORT_CAP32_SPEED_1G;
8545         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8546                 linkattr |= FW_PORT_CAP32_SPEED_10G;
8547         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8548                 linkattr |= FW_PORT_CAP32_SPEED_25G;
8549         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8550                 linkattr |= FW_PORT_CAP32_SPEED_40G;
8551         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8552                 linkattr |= FW_PORT_CAP32_SPEED_100G;
8553
8554         return linkattr;
8555 }
8556
8557 /**
8558  *      t4_handle_get_port_info - process a FW reply message
8559  *      @pi: the port info
8560  *      @rpl: start of the FW message
8561  *
8562  *      Processes a GET_PORT_INFO FW reply message.
8563  */
8564 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8565 {
8566         const struct fw_port_cmd *cmd = (const void *)rpl;
8567         fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8568         struct link_config *lc = &pi->link_cfg;
8569         struct adapter *adapter = pi->adapter;
8570         unsigned int speed, fc, fec, adv_fc;
8571         enum fw_port_module_type mod_type;
8572         int action, link_ok, linkdnrc;
8573         enum fw_port_type port_type;
8574
8575         /* Extract the various fields from the Port Information message.
8576          */
8577         action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8578         switch (action) {
8579         case FW_PORT_ACTION_GET_PORT_INFO: {
8580                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8581
8582                 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8583                 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8584                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8585                 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8586                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8587                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8588                 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8589                 linkattr = lstatus_to_fwcap(lstatus);
8590                 break;
8591         }
8592
8593         case FW_PORT_ACTION_GET_PORT_INFO32: {
8594                 u32 lstatus32;
8595
8596                 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8597                 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8598                 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8599                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8600                 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8601                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8602                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8603                 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8604                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8605                 break;
8606         }
8607
8608         default:
8609                 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8610                         be32_to_cpu(cmd->action_to_len16));
8611                 return;
8612         }
8613
8614         fec = fwcap_to_cc_fec(acaps);
8615         adv_fc = fwcap_to_cc_pause(acaps);
8616         fc = fwcap_to_cc_pause(linkattr);
8617         speed = fwcap_to_speed(linkattr);
8618
8619         /* Reset state for communicating new Transceiver Module status and
8620          * whether the OS-dependent layer wants us to redo the current
8621          * "sticky" L1 Configure Link Parameters.
8622          */
8623         lc->new_module = false;
8624         lc->redo_l1cfg = false;
8625
8626         if (mod_type != pi->mod_type) {
8627                 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8628                  * various fundamental Port Capabilities which used to be
8629                  * immutable can now change radically.  We can now have
8630                  * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8631                  * all change based on what Transceiver Module is inserted.
8632                  * So we need to record the Physical "Port" Capabilities on
8633                  * every Transceiver Module change.
8634                  */
8635                 lc->pcaps = pcaps;
8636
8637                 /* When a new Transceiver Module is inserted, the Firmware
8638                  * will examine its i2c EPROM to determine its type and
8639                  * general operating parameters including things like Forward
8640                  * Error Control, etc.  Various IEEE 802.3 standards dictate
8641                  * how to interpret these i2c values to determine default
8642                  * "sutomatic" settings.  We record these for future use when
8643                  * the user explicitly requests these standards-based values.
8644                  */
8645                 lc->def_acaps = acaps;
8646
8647                 /* Some versions of the early T6 Firmware "cheated" when
8648                  * handling different Transceiver Modules by changing the
8649                  * underlaying Port Type reported to the Host Drivers.  As
8650                  * such we need to capture whatever Port Type the Firmware
8651                  * sends us and record it in case it's different from what we
8652                  * were told earlier.  Unfortunately, since Firmware is
8653                  * forever, we'll need to keep this code here forever, but in
8654                  * later T6 Firmware it should just be an assignment of the
8655                  * same value already recorded.
8656                  */
8657                 pi->port_type = port_type;
8658
8659                 /* Record new Module Type information.
8660                  */
8661                 pi->mod_type = mod_type;
8662
8663                 /* Let the OS-dependent layer know if we have a new
8664                  * Transceiver Module inserted.
8665                  */
8666                 lc->new_module = t4_is_inserted_mod_type(mod_type);
8667
8668                 t4_os_portmod_changed(adapter, pi->port_id);
8669         }
8670
8671         if (link_ok != lc->link_ok || speed != lc->speed ||
8672             fc != lc->fc || adv_fc != lc->advertised_fc ||
8673             fec != lc->fec) {
8674                 /* something changed */
8675                 if (!link_ok && lc->link_ok) {
8676                         lc->link_down_rc = linkdnrc;
8677                         dev_warn_ratelimited(adapter->pdev_dev,
8678                                              "Port %d link down, reason: %s\n",
8679                                              pi->tx_chan,
8680                                              t4_link_down_rc_str(linkdnrc));
8681                 }
8682                 lc->link_ok = link_ok;
8683                 lc->speed = speed;
8684                 lc->advertised_fc = adv_fc;
8685                 lc->fc = fc;
8686                 lc->fec = fec;
8687
8688                 lc->lpacaps = lpacaps;
8689                 lc->acaps = acaps & ADVERT_MASK;
8690
8691                 /* If we're not physically capable of Auto-Negotiation, note
8692                  * this as Auto-Negotiation disabled.  Otherwise, we track
8693                  * what Auto-Negotiation settings we have.  Note parallel
8694                  * structure in t4_link_l1cfg_core() and init_link_config().
8695                  */
8696                 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8697                         lc->autoneg = AUTONEG_DISABLE;
8698                 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8699                         lc->autoneg = AUTONEG_ENABLE;
8700                 } else {
8701                         /* When Autoneg is disabled, user needs to set
8702                          * single speed.
8703                          * Similar to cxgb4_ethtool.c: set_link_ksettings
8704                          */
8705                         lc->acaps = 0;
8706                         lc->speed_caps = fwcap_to_fwspeed(acaps);
8707                         lc->autoneg = AUTONEG_DISABLE;
8708                 }
8709
8710                 t4_os_link_changed(adapter, pi->port_id, link_ok);
8711         }
8712
8713         /* If we have a new Transceiver Module and the OS-dependent code has
8714          * told us that it wants us to redo whatever "sticky" L1 Configuration
8715          * Link Parameters are set, do that now.
8716          */
8717         if (lc->new_module && lc->redo_l1cfg) {
8718                 struct link_config old_lc;
8719                 int ret;
8720
8721                 /* Save the current L1 Configuration and restore it if an
8722                  * error occurs.  We probably should fix the l1_cfg*()
8723                  * routines not to change the link_config when an error
8724                  * occurs ...
8725                  */
8726                 old_lc = *lc;
8727                 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8728                 if (ret) {
8729                         *lc = old_lc;
8730                         dev_warn(adapter->pdev_dev,
8731                                  "Attempt to update new Transceiver Module settings failed\n");
8732                 }
8733         }
8734         lc->new_module = false;
8735         lc->redo_l1cfg = false;
8736 }
8737
8738 /**
8739  *      t4_update_port_info - retrieve and update port information if changed
8740  *      @pi: the port_info
8741  *
8742  *      We issue a Get Port Information Command to the Firmware and, if
8743  *      successful, we check to see if anything is different from what we
8744  *      last recorded and update things accordingly.
8745  */
8746 int t4_update_port_info(struct port_info *pi)
8747 {
8748         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8749         struct fw_port_cmd port_cmd;
8750         int ret;
8751
8752         memset(&port_cmd, 0, sizeof(port_cmd));
8753         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8754                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8755                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8756         port_cmd.action_to_len16 = cpu_to_be32(
8757                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8758                                      ? FW_PORT_ACTION_GET_PORT_INFO
8759                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8760                 FW_LEN16(port_cmd));
8761         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8762                          &port_cmd, sizeof(port_cmd), &port_cmd);
8763         if (ret)
8764                 return ret;
8765
8766         t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8767         return 0;
8768 }
8769
8770 /**
8771  *      t4_get_link_params - retrieve basic link parameters for given port
8772  *      @pi: the port
8773  *      @link_okp: value return pointer for link up/down
8774  *      @speedp: value return pointer for speed (Mb/s)
8775  *      @mtup: value return pointer for mtu
8776  *
8777  *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8778  *      and MTU for a specified port.  A negative error is returned on
8779  *      failure; 0 on success.
8780  */
8781 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8782                        unsigned int *speedp, unsigned int *mtup)
8783 {
8784         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8785         struct fw_port_cmd port_cmd;
8786         unsigned int action, link_ok, mtu;
8787         fw_port_cap32_t linkattr;
8788         int ret;
8789
8790         memset(&port_cmd, 0, sizeof(port_cmd));
8791         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8792                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8793                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8794         action = (fw_caps == FW_CAPS16
8795                   ? FW_PORT_ACTION_GET_PORT_INFO
8796                   : FW_PORT_ACTION_GET_PORT_INFO32);
8797         port_cmd.action_to_len16 = cpu_to_be32(
8798                 FW_PORT_CMD_ACTION_V(action) |
8799                 FW_LEN16(port_cmd));
8800         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8801                          &port_cmd, sizeof(port_cmd), &port_cmd);
8802         if (ret)
8803                 return ret;
8804
8805         if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8806                 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8807
8808                 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8809                 linkattr = lstatus_to_fwcap(lstatus);
8810                 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8811         } else {
8812                 u32 lstatus32 =
8813                            be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8814
8815                 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8816                 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8817                 mtu = FW_PORT_CMD_MTU32_G(
8818                         be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8819         }
8820
8821         *link_okp = link_ok;
8822         *speedp = fwcap_to_speed(linkattr);
8823         *mtup = mtu;
8824
8825         return 0;
8826 }
8827
8828 /**
8829  *      t4_handle_fw_rpl - process a FW reply message
8830  *      @adap: the adapter
8831  *      @rpl: start of the FW message
8832  *
8833  *      Processes a FW message, such as link state change messages.
8834  */
8835 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8836 {
8837         u8 opcode = *(const u8 *)rpl;
8838
8839         /* This might be a port command ... this simplifies the following
8840          * conditionals ...  We can get away with pre-dereferencing
8841          * action_to_len16 because it's in the first 16 bytes and all messages
8842          * will be at least that long.
8843          */
8844         const struct fw_port_cmd *p = (const void *)rpl;
8845         unsigned int action =
8846                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8847
8848         if (opcode == FW_PORT_CMD &&
8849             (action == FW_PORT_ACTION_GET_PORT_INFO ||
8850              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8851                 int i;
8852                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8853                 struct port_info *pi = NULL;
8854
8855                 for_each_port(adap, i) {
8856                         pi = adap2pinfo(adap, i);
8857                         if (pi->tx_chan == chan)
8858                                 break;
8859                 }
8860
8861                 t4_handle_get_port_info(pi, rpl);
8862         } else {
8863                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8864                          opcode);
8865                 return -EINVAL;
8866         }
8867         return 0;
8868 }
8869
8870 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8871 {
8872         u16 val;
8873
8874         if (pci_is_pcie(adapter->pdev)) {
8875                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8876                 p->speed = val & PCI_EXP_LNKSTA_CLS;
8877                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8878         }
8879 }
8880
8881 /**
8882  *      init_link_config - initialize a link's SW state
8883  *      @lc: pointer to structure holding the link state
8884  *      @pcaps: link Port Capabilities
8885  *      @acaps: link current Advertised Port Capabilities
8886  *
8887  *      Initializes the SW state maintained for each link, including the link's
8888  *      capabilities and default speed/flow-control/autonegotiation settings.
8889  */
8890 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8891                              fw_port_cap32_t acaps)
8892 {
8893         lc->pcaps = pcaps;
8894         lc->def_acaps = acaps;
8895         lc->lpacaps = 0;
8896         lc->speed_caps = 0;
8897         lc->speed = 0;
8898         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8899
8900         /* For Forward Error Control, we default to whatever the Firmware
8901          * tells us the Link is currently advertising.
8902          */
8903         lc->requested_fec = FEC_AUTO;
8904         lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8905
8906         /* If the Port is capable of Auto-Negtotiation, initialize it as
8907          * "enabled" and copy over all of the Physical Port Capabilities
8908          * to the Advertised Port Capabilities.  Otherwise mark it as
8909          * Auto-Negotiate disabled and select the highest supported speed
8910          * for the link.  Note parallel structure in t4_link_l1cfg_core()
8911          * and t4_handle_get_port_info().
8912          */
8913         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8914                 lc->acaps = lc->pcaps & ADVERT_MASK;
8915                 lc->autoneg = AUTONEG_ENABLE;
8916                 lc->requested_fc |= PAUSE_AUTONEG;
8917         } else {
8918                 lc->acaps = 0;
8919                 lc->autoneg = AUTONEG_DISABLE;
8920                 lc->speed_caps = fwcap_to_fwspeed(acaps);
8921         }
8922 }
8923
8924 #define CIM_PF_NOACCESS 0xeeeeeeee
8925
8926 int t4_wait_dev_ready(void __iomem *regs)
8927 {
8928         u32 whoami;
8929
8930         whoami = readl(regs + PL_WHOAMI_A);
8931         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8932                 return 0;
8933
8934         msleep(500);
8935         whoami = readl(regs + PL_WHOAMI_A);
8936         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8937 }
8938
8939 struct flash_desc {
8940         u32 vendor_and_model_id;
8941         u32 size_mb;
8942 };
8943
8944 static int t4_get_flash_params(struct adapter *adap)
8945 {
8946         /* Table for non-Numonix supported flash parts.  Numonix parts are left
8947          * to the preexisting code.  All flash parts have 64KB sectors.
8948          */
8949         static struct flash_desc supported_flash[] = {
8950                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8951         };
8952
8953         unsigned int part, manufacturer;
8954         unsigned int density, size = 0;
8955         u32 flashid = 0;
8956         int ret;
8957
8958         /* Issue a Read ID Command to the Flash part.  We decode supported
8959          * Flash parts and their sizes from this.  There's a newer Query
8960          * Command which can retrieve detailed geometry information but many
8961          * Flash parts don't support it.
8962          */
8963
8964         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8965         if (!ret)
8966                 ret = sf1_read(adap, 3, 0, 1, &flashid);
8967         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8968         if (ret)
8969                 return ret;
8970
8971         /* Check to see if it's one of our non-standard supported Flash parts.
8972          */
8973         for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8974                 if (supported_flash[part].vendor_and_model_id == flashid) {
8975                         adap->params.sf_size = supported_flash[part].size_mb;
8976                         adap->params.sf_nsec =
8977                                 adap->params.sf_size / SF_SEC_SIZE;
8978                         goto found;
8979                 }
8980
8981         /* Decode Flash part size.  The code below looks repetitive with
8982          * common encodings, but that's not guaranteed in the JEDEC
8983          * specification for the Read JEDEC ID command.  The only thing that
8984          * we're guaranteed by the JEDEC specification is where the
8985          * Manufacturer ID is in the returned result.  After that each
8986          * Manufacturer ~could~ encode things completely differently.
8987          * Note, all Flash parts must have 64KB sectors.
8988          */
8989         manufacturer = flashid & 0xff;
8990         switch (manufacturer) {
8991         case 0x20: { /* Micron/Numonix */
8992                 /* This Density -> Size decoding table is taken from Micron
8993                  * Data Sheets.
8994                  */
8995                 density = (flashid >> 16) & 0xff;
8996                 switch (density) {
8997                 case 0x14: /* 1MB */
8998                         size = 1 << 20;
8999                         break;
9000                 case 0x15: /* 2MB */
9001                         size = 1 << 21;
9002                         break;
9003                 case 0x16: /* 4MB */
9004                         size = 1 << 22;
9005                         break;
9006                 case 0x17: /* 8MB */
9007                         size = 1 << 23;
9008                         break;
9009                 case 0x18: /* 16MB */
9010                         size = 1 << 24;
9011                         break;
9012                 case 0x19: /* 32MB */
9013                         size = 1 << 25;
9014                         break;
9015                 case 0x20: /* 64MB */
9016                         size = 1 << 26;
9017                         break;
9018                 case 0x21: /* 128MB */
9019                         size = 1 << 27;
9020                         break;
9021                 case 0x22: /* 256MB */
9022                         size = 1 << 28;
9023                         break;
9024                 }
9025                 break;
9026         }
9027         case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9028                 /* This Density -> Size decoding table is taken from ISSI
9029                  * Data Sheets.
9030                  */
9031                 density = (flashid >> 16) & 0xff;
9032                 switch (density) {
9033                 case 0x16: /* 32 MB */
9034                         size = 1 << 25;
9035                         break;
9036                 case 0x17: /* 64MB */
9037                         size = 1 << 26;
9038                         break;
9039                 }
9040                 break;
9041         }
9042         case 0xc2: { /* Macronix */
9043                 /* This Density -> Size decoding table is taken from Macronix
9044                  * Data Sheets.
9045                  */
9046                 density = (flashid >> 16) & 0xff;
9047                 switch (density) {
9048                 case 0x17: /* 8MB */
9049                         size = 1 << 23;
9050                         break;
9051                 case 0x18: /* 16MB */
9052                         size = 1 << 24;
9053                         break;
9054                 }
9055                 break;
9056         }
9057         case 0xef: { /* Winbond */
9058                 /* This Density -> Size decoding table is taken from Winbond
9059                  * Data Sheets.
9060                  */
9061                 density = (flashid >> 16) & 0xff;
9062                 switch (density) {
9063                 case 0x17: /* 8MB */
9064                         size = 1 << 23;
9065                         break;
9066                 case 0x18: /* 16MB */
9067                         size = 1 << 24;
9068                         break;
9069                 }
9070                 break;
9071         }
9072         }
9073
9074         /* If we didn't recognize the FLASH part, that's no real issue: the
9075          * Hardware/Software contract says that Hardware will _*ALWAYS*_
9076          * use a FLASH part which is at least 4MB in size and has 64KB
9077          * sectors.  The unrecognized FLASH part is likely to be much larger
9078          * than 4MB, but that's all we really need.
9079          */
9080         if (size == 0) {
9081                 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9082                          flashid);
9083                 size = 1 << 22;
9084         }
9085
9086         /* Store decoded Flash size and fall through into vetting code. */
9087         adap->params.sf_size = size;
9088         adap->params.sf_nsec = size / SF_SEC_SIZE;
9089
9090 found:
9091         if (adap->params.sf_size < FLASH_MIN_SIZE)
9092                 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9093                          flashid, adap->params.sf_size, FLASH_MIN_SIZE);
9094         return 0;
9095 }
9096
9097 /**
9098  *      t4_prep_adapter - prepare SW and HW for operation
9099  *      @adapter: the adapter
9100  *      @reset: if true perform a HW reset
9101  *
9102  *      Initialize adapter SW state for the various HW modules, set initial
9103  *      values for some adapter tunables, take PHYs out of reset, and
9104  *      initialize the MDIO interface.
9105  */
9106 int t4_prep_adapter(struct adapter *adapter)
9107 {
9108         int ret, ver;
9109         uint16_t device_id;
9110         u32 pl_rev;
9111
9112         get_pci_mode(adapter, &adapter->params.pci);
9113         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
9114
9115         ret = t4_get_flash_params(adapter);
9116         if (ret < 0) {
9117                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
9118                 return ret;
9119         }
9120
9121         /* Retrieve adapter's device ID
9122          */
9123         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
9124         ver = device_id >> 12;
9125         adapter->params.chip = 0;
9126         switch (ver) {
9127         case CHELSIO_T4:
9128                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
9129                 adapter->params.arch.sge_fl_db = DBPRIO_F;
9130                 adapter->params.arch.mps_tcam_size =
9131                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
9132                 adapter->params.arch.mps_rplc_size = 128;
9133                 adapter->params.arch.nchan = NCHAN;
9134                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9135                 adapter->params.arch.vfcount = 128;
9136                 /* Congestion map is for 4 channels so that
9137                  * MPS can have 4 priority per port.
9138                  */
9139                 adapter->params.arch.cng_ch_bits_log = 2;
9140                 break;
9141         case CHELSIO_T5:
9142                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
9143                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
9144                 adapter->params.arch.mps_tcam_size =
9145                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9146                 adapter->params.arch.mps_rplc_size = 128;
9147                 adapter->params.arch.nchan = NCHAN;
9148                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9149                 adapter->params.arch.vfcount = 128;
9150                 adapter->params.arch.cng_ch_bits_log = 2;
9151                 break;
9152         case CHELSIO_T6:
9153                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
9154                 adapter->params.arch.sge_fl_db = 0;
9155                 adapter->params.arch.mps_tcam_size =
9156                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9157                 adapter->params.arch.mps_rplc_size = 256;
9158                 adapter->params.arch.nchan = 2;
9159                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
9160                 adapter->params.arch.vfcount = 256;
9161                 /* Congestion map will be for 2 channels so that
9162                  * MPS can have 8 priority per port.
9163                  */
9164                 adapter->params.arch.cng_ch_bits_log = 3;
9165                 break;
9166         default:
9167                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
9168                         device_id);
9169                 return -EINVAL;
9170         }
9171
9172         adapter->params.cim_la_size = CIMLA_SIZE;
9173         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9174
9175         /*
9176          * Default port for debugging in case we can't reach FW.
9177          */
9178         adapter->params.nports = 1;
9179         adapter->params.portvec = 1;
9180         adapter->params.vpd.cclk = 50000;
9181
9182         /* Set PCIe completion timeout to 4 seconds. */
9183         pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
9184                                            PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
9185         return 0;
9186 }
9187
9188 /**
9189  *      t4_shutdown_adapter - shut down adapter, host & wire
9190  *      @adapter: the adapter
9191  *
9192  *      Perform an emergency shutdown of the adapter and stop it from
9193  *      continuing any further communication on the ports or DMA to the
9194  *      host.  This is typically used when the adapter and/or firmware
9195  *      have crashed and we want to prevent any further accidental
9196  *      communication with the rest of the world.  This will also force
9197  *      the port Link Status to go down -- if register writes work --
9198  *      which should help our peers figure out that we're down.
9199  */
9200 int t4_shutdown_adapter(struct adapter *adapter)
9201 {
9202         int port;
9203
9204         t4_intr_disable(adapter);
9205         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
9206         for_each_port(adapter, port) {
9207                 u32 a_port_cfg = is_t4(adapter->params.chip) ?
9208                                        PORT_REG(port, XGMAC_PORT_CFG_A) :
9209                                        T5_PORT_REG(port, MAC_PORT_CFG_A);
9210
9211                 t4_write_reg(adapter, a_port_cfg,
9212                              t4_read_reg(adapter, a_port_cfg)
9213                              & ~SIGNAL_DET_V(1));
9214         }
9215         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
9216
9217         return 0;
9218 }
9219
9220 /**
9221  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9222  *      @adapter: the adapter
9223  *      @qid: the Queue ID
9224  *      @qtype: the Ingress or Egress type for @qid
9225  *      @user: true if this request is for a user mode queue
9226  *      @pbar2_qoffset: BAR2 Queue Offset
9227  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9228  *
9229  *      Returns the BAR2 SGE Queue Registers information associated with the
9230  *      indicated Absolute Queue ID.  These are passed back in return value
9231  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9232  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9233  *
9234  *      This may return an error which indicates that BAR2 SGE Queue
9235  *      registers aren't available.  If an error is not returned, then the
9236  *      following values are returned:
9237  *
9238  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9239  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9240  *
9241  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9242  *      require the "Inferred Queue ID" ability may be used.  E.g. the
9243  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9244  *      then these "Inferred Queue ID" register may not be used.
9245  */
9246 int t4_bar2_sge_qregs(struct adapter *adapter,
9247                       unsigned int qid,
9248                       enum t4_bar2_qtype qtype,
9249                       int user,
9250                       u64 *pbar2_qoffset,
9251                       unsigned int *pbar2_qid)
9252 {
9253         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9254         u64 bar2_page_offset, bar2_qoffset;
9255         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9256
9257         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9258         if (!user && is_t4(adapter->params.chip))
9259                 return -EINVAL;
9260
9261         /* Get our SGE Page Size parameters.
9262          */
9263         page_shift = adapter->params.sge.hps + 10;
9264         page_size = 1 << page_shift;
9265
9266         /* Get the right Queues per Page parameters for our Queue.
9267          */
9268         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9269                      ? adapter->params.sge.eq_qpp
9270                      : adapter->params.sge.iq_qpp);
9271         qpp_mask = (1 << qpp_shift) - 1;
9272
9273         /*  Calculate the basics of the BAR2 SGE Queue register area:
9274          *  o The BAR2 page the Queue registers will be in.
9275          *  o The BAR2 Queue ID.
9276          *  o The BAR2 Queue ID Offset into the BAR2 page.
9277          */
9278         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9279         bar2_qid = qid & qpp_mask;
9280         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9281
9282         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9283          * hardware will infer the Absolute Queue ID simply from the writes to
9284          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9285          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
9286          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9287          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9288          * from the BAR2 Page and BAR2 Queue ID.
9289          *
9290          * One important censequence of this is that some BAR2 SGE registers
9291          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9292          * there.  But other registers synthesize the SGE Queue ID purely
9293          * from the writes to the registers -- the Write Combined Doorbell
9294          * Buffer is a good example.  These BAR2 SGE Registers are only
9295          * available for those BAR2 SGE Register areas where the SGE Absolute
9296          * Queue ID can be inferred from simple writes.
9297          */
9298         bar2_qoffset = bar2_page_offset;
9299         bar2_qinferred = (bar2_qid_offset < page_size);
9300         if (bar2_qinferred) {
9301                 bar2_qoffset += bar2_qid_offset;
9302                 bar2_qid = 0;
9303         }
9304
9305         *pbar2_qoffset = bar2_qoffset;
9306         *pbar2_qid = bar2_qid;
9307         return 0;
9308 }
9309
9310 /**
9311  *      t4_init_devlog_params - initialize adapter->params.devlog
9312  *      @adap: the adapter
9313  *
9314  *      Initialize various fields of the adapter's Firmware Device Log
9315  *      Parameters structure.
9316  */
9317 int t4_init_devlog_params(struct adapter *adap)
9318 {
9319         struct devlog_params *dparams = &adap->params.devlog;
9320         u32 pf_dparams;
9321         unsigned int devlog_meminfo;
9322         struct fw_devlog_cmd devlog_cmd;
9323         int ret;
9324
9325         /* If we're dealing with newer firmware, the Device Log Parameters
9326          * are stored in a designated register which allows us to access the
9327          * Device Log even if we can't talk to the firmware.
9328          */
9329         pf_dparams =
9330                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9331         if (pf_dparams) {
9332                 unsigned int nentries, nentries128;
9333
9334                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9335                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9336
9337                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9338                 nentries = (nentries128 + 1) * 128;
9339                 dparams->size = nentries * sizeof(struct fw_devlog_e);
9340
9341                 return 0;
9342         }
9343
9344         /* Otherwise, ask the firmware for it's Device Log Parameters.
9345          */
9346         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9347         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9348                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
9349         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9350         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9351                          &devlog_cmd);
9352         if (ret)
9353                 return ret;
9354
9355         devlog_meminfo =
9356                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9357         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9358         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9359         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9360
9361         return 0;
9362 }
9363
9364 /**
9365  *      t4_init_sge_params - initialize adap->params.sge
9366  *      @adapter: the adapter
9367  *
9368  *      Initialize various fields of the adapter's SGE Parameters structure.
9369  */
9370 int t4_init_sge_params(struct adapter *adapter)
9371 {
9372         struct sge_params *sge_params = &adapter->params.sge;
9373         u32 hps, qpp;
9374         unsigned int s_hps, s_qpp;
9375
9376         /* Extract the SGE Page Size for our PF.
9377          */
9378         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9379         s_hps = (HOSTPAGESIZEPF0_S +
9380                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9381         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9382
9383         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9384          */
9385         s_qpp = (QUEUESPERPAGEPF0_S +
9386                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9387         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9388         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9389         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9390         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9391
9392         return 0;
9393 }
9394
9395 /**
9396  *      t4_init_tp_params - initialize adap->params.tp
9397  *      @adap: the adapter
9398  *      @sleep_ok: if true we may sleep while awaiting command completion
9399  *
9400  *      Initialize various fields of the adapter's TP Parameters structure.
9401  */
9402 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9403 {
9404         u32 param, val, v;
9405         int chan, ret;
9406
9407
9408         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9409         adap->params.tp.tre = TIMERRESOLUTION_G(v);
9410         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9411
9412         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9413         for (chan = 0; chan < NCHAN; chan++)
9414                 adap->params.tp.tx_modq[chan] = chan;
9415
9416         /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9417          * Configuration.
9418          */
9419         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
9420                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER) |
9421                  FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK));
9422
9423         /* Read current value */
9424         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
9425                               &param, &val);
9426         if (ret == 0) {
9427                 dev_info(adap->pdev_dev,
9428                          "Current filter mode/mask 0x%x:0x%x\n",
9429                          FW_PARAMS_PARAM_FILTER_MODE_G(val),
9430                          FW_PARAMS_PARAM_FILTER_MASK_G(val));
9431                 adap->params.tp.vlan_pri_map =
9432                         FW_PARAMS_PARAM_FILTER_MODE_G(val);
9433                 adap->params.tp.filter_mask =
9434                         FW_PARAMS_PARAM_FILTER_MASK_G(val);
9435         } else {
9436                 dev_info(adap->pdev_dev,
9437                          "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9438
9439                 /* Incase of older-fw (which doesn't expose the api
9440                  * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9441                  * the fw api) combination, fall-back to older method of reading
9442                  * the filter mode from indirect-register
9443                  */
9444                 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9445                                TP_VLAN_PRI_MAP_A, sleep_ok);
9446
9447                 /* With the older-fw and newer-driver combination we might run
9448                  * into an issue when user wants to use hash filter region but
9449                  * the filter_mask is zero, in this case filter_mask validation
9450                  * is tough. To avoid that we set the filter_mask same as filter
9451                  * mode, which will behave exactly as the older way of ignoring
9452                  * the filter mask validation.
9453                  */
9454                 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
9455         }
9456
9457         t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9458                        TP_INGRESS_CONFIG_A, sleep_ok);
9459
9460         /* For T6, cache the adapter's compressed error vector
9461          * and passing outer header info for encapsulated packets.
9462          */
9463         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9464                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9465                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9466         }
9467
9468         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9469          * shift positions of several elements of the Compressed Filter Tuple
9470          * for this adapter which we need frequently ...
9471          */
9472         adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9473         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9474         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9475         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9476         adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9477         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9478                                                                PROTOCOL_F);
9479         adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9480                                                                 ETHERTYPE_F);
9481         adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9482                                                                MACMATCH_F);
9483         adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9484                                                                 MPSHITTYPE_F);
9485         adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9486                                                            FRAGMENTATION_F);
9487
9488         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9489          * represents the presence of an Outer VLAN instead of a VNIC ID.
9490          */
9491         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9492                 adap->params.tp.vnic_shift = -1;
9493
9494         v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9495         adap->params.tp.hash_filter_mask = v;
9496         v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9497         adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9498         return 0;
9499 }
9500
9501 /**
9502  *      t4_filter_field_shift - calculate filter field shift
9503  *      @adap: the adapter
9504  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9505  *
9506  *      Return the shift position of a filter field within the Compressed
9507  *      Filter Tuple.  The filter field is specified via its selection bit
9508  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
9509  */
9510 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9511 {
9512         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9513         unsigned int sel;
9514         int field_shift;
9515
9516         if ((filter_mode & filter_sel) == 0)
9517                 return -1;
9518
9519         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9520                 switch (filter_mode & sel) {
9521                 case FCOE_F:
9522                         field_shift += FT_FCOE_W;
9523                         break;
9524                 case PORT_F:
9525                         field_shift += FT_PORT_W;
9526                         break;
9527                 case VNIC_ID_F:
9528                         field_shift += FT_VNIC_ID_W;
9529                         break;
9530                 case VLAN_F:
9531                         field_shift += FT_VLAN_W;
9532                         break;
9533                 case TOS_F:
9534                         field_shift += FT_TOS_W;
9535                         break;
9536                 case PROTOCOL_F:
9537                         field_shift += FT_PROTOCOL_W;
9538                         break;
9539                 case ETHERTYPE_F:
9540                         field_shift += FT_ETHERTYPE_W;
9541                         break;
9542                 case MACMATCH_F:
9543                         field_shift += FT_MACMATCH_W;
9544                         break;
9545                 case MPSHITTYPE_F:
9546                         field_shift += FT_MPSHITTYPE_W;
9547                         break;
9548                 case FRAGMENTATION_F:
9549                         field_shift += FT_FRAGMENTATION_W;
9550                         break;
9551                 }
9552         }
9553         return field_shift;
9554 }
9555
9556 int t4_init_rss_mode(struct adapter *adap, int mbox)
9557 {
9558         int i, ret;
9559         struct fw_rss_vi_config_cmd rvc;
9560
9561         memset(&rvc, 0, sizeof(rvc));
9562
9563         for_each_port(adap, i) {
9564                 struct port_info *p = adap2pinfo(adap, i);
9565
9566                 rvc.op_to_viid =
9567                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9568                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
9569                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9570                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9571                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9572                 if (ret)
9573                         return ret;
9574                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9575         }
9576         return 0;
9577 }
9578
9579 /**
9580  *      t4_init_portinfo - allocate a virtual interface and initialize port_info
9581  *      @pi: the port_info
9582  *      @mbox: mailbox to use for the FW command
9583  *      @port: physical port associated with the VI
9584  *      @pf: the PF owning the VI
9585  *      @vf: the VF owning the VI
9586  *      @mac: the MAC address of the VI
9587  *
9588  *      Allocates a virtual interface for the given physical port.  If @mac is
9589  *      not %NULL it contains the MAC address of the VI as assigned by FW.
9590  *      @mac should be large enough to hold an Ethernet address.
9591  *      Returns < 0 on error.
9592  */
9593 int t4_init_portinfo(struct port_info *pi, int mbox,
9594                      int port, int pf, int vf, u8 mac[])
9595 {
9596         struct adapter *adapter = pi->adapter;
9597         unsigned int fw_caps = adapter->params.fw_caps_support;
9598         struct fw_port_cmd cmd;
9599         unsigned int rss_size;
9600         enum fw_port_type port_type;
9601         int mdio_addr;
9602         fw_port_cap32_t pcaps, acaps;
9603         u8 vivld = 0, vin = 0;
9604         int ret;
9605
9606         /* If we haven't yet determined whether we're talking to Firmware
9607          * which knows the new 32-bit Port Capabilities, it's time to find
9608          * out now.  This will also tell new Firmware to send us Port Status
9609          * Updates using the new 32-bit Port Capabilities version of the
9610          * Port Information message.
9611          */
9612         if (fw_caps == FW_CAPS_UNKNOWN) {
9613                 u32 param, val;
9614
9615                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9616                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9617                 val = 1;
9618                 ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
9619                 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9620                 adapter->params.fw_caps_support = fw_caps;
9621         }
9622
9623         memset(&cmd, 0, sizeof(cmd));
9624         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9625                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
9626                                        FW_PORT_CMD_PORTID_V(port));
9627         cmd.action_to_len16 = cpu_to_be32(
9628                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9629                                      ? FW_PORT_ACTION_GET_PORT_INFO
9630                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
9631                 FW_LEN16(cmd));
9632         ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9633         if (ret)
9634                 return ret;
9635
9636         /* Extract the various fields from the Port Information message.
9637          */
9638         if (fw_caps == FW_CAPS16) {
9639                 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9640
9641                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9642                 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9643                              ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9644                              : -1);
9645                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9646                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9647         } else {
9648                 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9649
9650                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9651                 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9652                              ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9653                              : -1);
9654                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9655                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9656         }
9657
9658         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size,
9659                           &vivld, &vin);
9660         if (ret < 0)
9661                 return ret;
9662
9663         pi->viid = ret;
9664         pi->tx_chan = port;
9665         pi->lport = port;
9666         pi->rss_size = rss_size;
9667         pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
9668
9669         /* If fw supports returning the VIN as part of FW_VI_CMD,
9670          * save the returned values.
9671          */
9672         if (adapter->params.viid_smt_extn_support) {
9673                 pi->vivld = vivld;
9674                 pi->vin = vin;
9675         } else {
9676                 /* Retrieve the values from VIID */
9677                 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
9678                 pi->vin =  FW_VIID_VIN_G(pi->viid);
9679         }
9680
9681         pi->port_type = port_type;
9682         pi->mdio_addr = mdio_addr;
9683         pi->mod_type = FW_PORT_MOD_TYPE_NA;
9684
9685         init_link_config(&pi->link_cfg, pcaps, acaps);
9686         return 0;
9687 }
9688
9689 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9690 {
9691         u8 addr[6];
9692         int ret, i, j = 0;
9693
9694         for_each_port(adap, i) {
9695                 struct port_info *pi = adap2pinfo(adap, i);
9696
9697                 while ((adap->params.portvec & (1 << j)) == 0)
9698                         j++;
9699
9700                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9701                 if (ret)
9702                         return ret;
9703
9704                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9705                 j++;
9706         }
9707         return 0;
9708 }
9709
9710 /**
9711  *      t4_read_cimq_cfg - read CIM queue configuration
9712  *      @adap: the adapter
9713  *      @base: holds the queue base addresses in bytes
9714  *      @size: holds the queue sizes in bytes
9715  *      @thres: holds the queue full thresholds in bytes
9716  *
9717  *      Returns the current configuration of the CIM queues, starting with
9718  *      the IBQs, then the OBQs.
9719  */
9720 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9721 {
9722         unsigned int i, v;
9723         int cim_num_obq = is_t4(adap->params.chip) ?
9724                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9725
9726         for (i = 0; i < CIM_NUM_IBQ; i++) {
9727                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9728                              QUENUMSELECT_V(i));
9729                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9730                 /* value is in 256-byte units */
9731                 *base++ = CIMQBASE_G(v) * 256;
9732                 *size++ = CIMQSIZE_G(v) * 256;
9733                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9734         }
9735         for (i = 0; i < cim_num_obq; i++) {
9736                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9737                              QUENUMSELECT_V(i));
9738                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9739                 /* value is in 256-byte units */
9740                 *base++ = CIMQBASE_G(v) * 256;
9741                 *size++ = CIMQSIZE_G(v) * 256;
9742         }
9743 }
9744
9745 /**
9746  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
9747  *      @adap: the adapter
9748  *      @qid: the queue index
9749  *      @data: where to store the queue contents
9750  *      @n: capacity of @data in 32-bit words
9751  *
9752  *      Reads the contents of the selected CIM queue starting at address 0 up
9753  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9754  *      error and the number of 32-bit words actually read on success.
9755  */
9756 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9757 {
9758         int i, err, attempts;
9759         unsigned int addr;
9760         const unsigned int nwords = CIM_IBQ_SIZE * 4;
9761
9762         if (qid > 5 || (n & 3))
9763                 return -EINVAL;
9764
9765         addr = qid * nwords;
9766         if (n > nwords)
9767                 n = nwords;
9768
9769         /* It might take 3-10ms before the IBQ debug read access is allowed.
9770          * Wait for 1 Sec with a delay of 1 usec.
9771          */
9772         attempts = 1000000;
9773
9774         for (i = 0; i < n; i++, addr++) {
9775                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9776                              IBQDBGEN_F);
9777                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9778                                       attempts, 1);
9779                 if (err)
9780                         return err;
9781                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9782         }
9783         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9784         return i;
9785 }
9786
9787 /**
9788  *      t4_read_cim_obq - read the contents of a CIM outbound queue
9789  *      @adap: the adapter
9790  *      @qid: the queue index
9791  *      @data: where to store the queue contents
9792  *      @n: capacity of @data in 32-bit words
9793  *
9794  *      Reads the contents of the selected CIM queue starting at address 0 up
9795  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9796  *      error and the number of 32-bit words actually read on success.
9797  */
9798 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9799 {
9800         int i, err;
9801         unsigned int addr, v, nwords;
9802         int cim_num_obq = is_t4(adap->params.chip) ?
9803                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9804
9805         if ((qid > (cim_num_obq - 1)) || (n & 3))
9806                 return -EINVAL;
9807
9808         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9809                      QUENUMSELECT_V(qid));
9810         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9811
9812         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
9813         nwords = CIMQSIZE_G(v) * 64;  /* same */
9814         if (n > nwords)
9815                 n = nwords;
9816
9817         for (i = 0; i < n; i++, addr++) {
9818                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9819                              OBQDBGEN_F);
9820                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9821                                       2, 1);
9822                 if (err)
9823                         return err;
9824                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9825         }
9826         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9827         return i;
9828 }
9829
9830 /**
9831  *      t4_cim_read - read a block from CIM internal address space
9832  *      @adap: the adapter
9833  *      @addr: the start address within the CIM address space
9834  *      @n: number of words to read
9835  *      @valp: where to store the result
9836  *
9837  *      Reads a block of 4-byte words from the CIM intenal address space.
9838  */
9839 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9840                 unsigned int *valp)
9841 {
9842         int ret = 0;
9843
9844         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9845                 return -EBUSY;
9846
9847         for ( ; !ret && n--; addr += 4) {
9848                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9849                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9850                                       0, 5, 2);
9851                 if (!ret)
9852                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9853         }
9854         return ret;
9855 }
9856
9857 /**
9858  *      t4_cim_write - write a block into CIM internal address space
9859  *      @adap: the adapter
9860  *      @addr: the start address within the CIM address space
9861  *      @n: number of words to write
9862  *      @valp: set of values to write
9863  *
9864  *      Writes a block of 4-byte words into the CIM intenal address space.
9865  */
9866 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9867                  const unsigned int *valp)
9868 {
9869         int ret = 0;
9870
9871         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9872                 return -EBUSY;
9873
9874         for ( ; !ret && n--; addr += 4) {
9875                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9876                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9877                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9878                                       0, 5, 2);
9879         }
9880         return ret;
9881 }
9882
9883 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9884                          unsigned int val)
9885 {
9886         return t4_cim_write(adap, addr, 1, &val);
9887 }
9888
9889 /**
9890  *      t4_cim_read_la - read CIM LA capture buffer
9891  *      @adap: the adapter
9892  *      @la_buf: where to store the LA data
9893  *      @wrptr: the HW write pointer within the capture buffer
9894  *
9895  *      Reads the contents of the CIM LA buffer with the most recent entry at
9896  *      the end of the returned data and with the entry at @wrptr first.
9897  *      We try to leave the LA in the running state we find it in.
9898  */
9899 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9900 {
9901         int i, ret;
9902         unsigned int cfg, val, idx;
9903
9904         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9905         if (ret)
9906                 return ret;
9907
9908         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9909                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9910                 if (ret)
9911                         return ret;
9912         }
9913
9914         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9915         if (ret)
9916                 goto restart;
9917
9918         idx = UPDBGLAWRPTR_G(val);
9919         if (wrptr)
9920                 *wrptr = idx;
9921
9922         for (i = 0; i < adap->params.cim_la_size; i++) {
9923                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9924                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9925                 if (ret)
9926                         break;
9927                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9928                 if (ret)
9929                         break;
9930                 if (val & UPDBGLARDEN_F) {
9931                         ret = -ETIMEDOUT;
9932                         break;
9933                 }
9934                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9935                 if (ret)
9936                         break;
9937
9938                 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9939                  * identify the 32-bit portion of the full 312-bit data
9940                  */
9941                 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9942                         idx = (idx & 0xff0) + 0x10;
9943                 else
9944                         idx++;
9945                 /* address can't exceed 0xfff */
9946                 idx &= UPDBGLARDPTR_M;
9947         }
9948 restart:
9949         if (cfg & UPDBGLAEN_F) {
9950                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9951                                       cfg & ~UPDBGLARDEN_F);
9952                 if (!ret)
9953                         ret = r;
9954         }
9955         return ret;
9956 }
9957
9958 /**
9959  *      t4_tp_read_la - read TP LA capture buffer
9960  *      @adap: the adapter
9961  *      @la_buf: where to store the LA data
9962  *      @wrptr: the HW write pointer within the capture buffer
9963  *
9964  *      Reads the contents of the TP LA buffer with the most recent entry at
9965  *      the end of the returned data and with the entry at @wrptr first.
9966  *      We leave the LA in the running state we find it in.
9967  */
9968 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9969 {
9970         bool last_incomplete;
9971         unsigned int i, cfg, val, idx;
9972
9973         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9974         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
9975                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9976                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9977
9978         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9979         idx = DBGLAWPTR_G(val);
9980         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9981         if (last_incomplete)
9982                 idx = (idx + 1) & DBGLARPTR_M;
9983         if (wrptr)
9984                 *wrptr = idx;
9985
9986         val &= 0xffff;
9987         val &= ~DBGLARPTR_V(DBGLARPTR_M);
9988         val |= adap->params.tp.la_mask;
9989
9990         for (i = 0; i < TPLA_SIZE; i++) {
9991                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9992                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9993                 idx = (idx + 1) & DBGLARPTR_M;
9994         }
9995
9996         /* Wipe out last entry if it isn't valid */
9997         if (last_incomplete)
9998                 la_buf[TPLA_SIZE - 1] = ~0ULL;
9999
10000         if (cfg & DBGLAENABLE_F)                    /* restore running state */
10001                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10002                              cfg | adap->params.tp.la_mask);
10003 }
10004
10005 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10006  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
10007  * state for more than the Warning Threshold then we'll issue a warning about
10008  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
10009  * appears to be hung every Warning Repeat second till the situation clears.
10010  * If the situation clears, we'll note that as well.
10011  */
10012 #define SGE_IDMA_WARN_THRESH 1
10013 #define SGE_IDMA_WARN_REPEAT 300
10014
10015 /**
10016  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10017  *      @adapter: the adapter
10018  *      @idma: the adapter IDMA Monitor state
10019  *
10020  *      Initialize the state of an SGE Ingress DMA Monitor.
10021  */
10022 void t4_idma_monitor_init(struct adapter *adapter,
10023                           struct sge_idma_monitor_state *idma)
10024 {
10025         /* Initialize the state variables for detecting an SGE Ingress DMA
10026          * hang.  The SGE has internal counters which count up on each clock
10027          * tick whenever the SGE finds its Ingress DMA State Engines in the
10028          * same state they were on the previous clock tick.  The clock used is
10029          * the Core Clock so we have a limit on the maximum "time" they can
10030          * record; typically a very small number of seconds.  For instance,
10031          * with a 600MHz Core Clock, we can only count up to a bit more than
10032          * 7s.  So we'll synthesize a larger counter in order to not run the
10033          * risk of having the "timers" overflow and give us the flexibility to
10034          * maintain a Hung SGE State Machine of our own which operates across
10035          * a longer time frame.
10036          */
10037         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10038         idma->idma_stalled[0] = 0;
10039         idma->idma_stalled[1] = 0;
10040 }
10041
10042 /**
10043  *      t4_idma_monitor - monitor SGE Ingress DMA state
10044  *      @adapter: the adapter
10045  *      @idma: the adapter IDMA Monitor state
10046  *      @hz: number of ticks/second
10047  *      @ticks: number of ticks since the last IDMA Monitor call
10048  */
10049 void t4_idma_monitor(struct adapter *adapter,
10050                      struct sge_idma_monitor_state *idma,
10051                      int hz, int ticks)
10052 {
10053         int i, idma_same_state_cnt[2];
10054
10055          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
10056           * are counters inside the SGE which count up on each clock when the
10057           * SGE finds its Ingress DMA State Engines in the same states they
10058           * were in the previous clock.  The counters will peg out at
10059           * 0xffffffff without wrapping around so once they pass the 1s
10060           * threshold they'll stay above that till the IDMA state changes.
10061           */
10062         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
10063         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
10064         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10065
10066         for (i = 0; i < 2; i++) {
10067                 u32 debug0, debug11;
10068
10069                 /* If the Ingress DMA Same State Counter ("timer") is less
10070                  * than 1s, then we can reset our synthesized Stall Timer and
10071                  * continue.  If we have previously emitted warnings about a
10072                  * potential stalled Ingress Queue, issue a note indicating
10073                  * that the Ingress Queue has resumed forward progress.
10074                  */
10075                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10076                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
10077                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
10078                                          "resumed after %d seconds\n",
10079                                          i, idma->idma_qid[i],
10080                                          idma->idma_stalled[i] / hz);
10081                         idma->idma_stalled[i] = 0;
10082                         continue;
10083                 }
10084
10085                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10086                  * domain.  The first time we get here it'll be because we
10087                  * passed the 1s Threshold; each additional time it'll be
10088                  * because the RX Timer Callback is being fired on its regular
10089                  * schedule.
10090                  *
10091                  * If the stall is below our Potential Hung Ingress Queue
10092                  * Warning Threshold, continue.
10093                  */
10094                 if (idma->idma_stalled[i] == 0) {
10095                         idma->idma_stalled[i] = hz;
10096                         idma->idma_warn[i] = 0;
10097                 } else {
10098                         idma->idma_stalled[i] += ticks;
10099                         idma->idma_warn[i] -= ticks;
10100                 }
10101
10102                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
10103                         continue;
10104
10105                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10106                  */
10107                 if (idma->idma_warn[i] > 0)
10108                         continue;
10109                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
10110
10111                 /* Read and save the SGE IDMA State and Queue ID information.
10112                  * We do this every time in case it changes across time ...
10113                  * can't be too careful ...
10114                  */
10115                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
10116                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10117                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10118
10119                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
10120                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10121                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10122
10123                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
10124                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10125                          i, idma->idma_qid[i], idma->idma_state[i],
10126                          idma->idma_stalled[i] / hz,
10127                          debug0, debug11);
10128                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10129         }
10130 }
10131
10132 /**
10133  *      t4_load_cfg - download config file
10134  *      @adap: the adapter
10135  *      @cfg_data: the cfg text file to write
10136  *      @size: text file size
10137  *
10138  *      Write the supplied config text file to the card's serial flash.
10139  */
10140 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10141 {
10142         int ret, i, n, cfg_addr;
10143         unsigned int addr;
10144         unsigned int flash_cfg_start_sec;
10145         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10146
10147         cfg_addr = t4_flash_cfg_addr(adap);
10148         if (cfg_addr < 0)
10149                 return cfg_addr;
10150
10151         addr = cfg_addr;
10152         flash_cfg_start_sec = addr / SF_SEC_SIZE;
10153
10154         if (size > FLASH_CFG_MAX_SIZE) {
10155                 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
10156                         FLASH_CFG_MAX_SIZE);
10157                 return -EFBIG;
10158         }
10159
10160         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
10161                          sf_sec_size);
10162         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10163                                      flash_cfg_start_sec + i - 1);
10164         /* If size == 0 then we're simply erasing the FLASH sectors associated
10165          * with the on-adapter Firmware Configuration File.
10166          */
10167         if (ret || size == 0)
10168                 goto out;
10169
10170         /* this will write to the flash up to SF_PAGE_SIZE at a time */
10171         for (i = 0; i < size; i += SF_PAGE_SIZE) {
10172                 if ((size - i) <  SF_PAGE_SIZE)
10173                         n = size - i;
10174                 else
10175                         n = SF_PAGE_SIZE;
10176                 ret = t4_write_flash(adap, addr, n, cfg_data);
10177                 if (ret)
10178                         goto out;
10179
10180                 addr += SF_PAGE_SIZE;
10181                 cfg_data += SF_PAGE_SIZE;
10182         }
10183
10184 out:
10185         if (ret)
10186                 dev_err(adap->pdev_dev, "config file %s failed %d\n",
10187                         (size == 0 ? "clear" : "download"), ret);
10188         return ret;
10189 }
10190
10191 /**
10192  *      t4_set_vf_mac - Set MAC address for the specified VF
10193  *      @adapter: The adapter
10194  *      @vf: one of the VFs instantiated by the specified PF
10195  *      @naddr: the number of MAC addresses
10196  *      @addr: the MAC address(es) to be set to the specified VF
10197  */
10198 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
10199                       unsigned int naddr, u8 *addr)
10200 {
10201         struct fw_acl_mac_cmd cmd;
10202
10203         memset(&cmd, 0, sizeof(cmd));
10204         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
10205                                     FW_CMD_REQUEST_F |
10206                                     FW_CMD_WRITE_F |
10207                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
10208                                     FW_ACL_MAC_CMD_VFN_V(vf));
10209
10210         /* Note: Do not enable the ACL */
10211         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10212         cmd.nmac = naddr;
10213
10214         switch (adapter->pf) {
10215         case 3:
10216                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10217                 break;
10218         case 2:
10219                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10220                 break;
10221         case 1:
10222                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10223                 break;
10224         case 0:
10225                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10226                 break;
10227         }
10228
10229         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10230 }
10231
10232 /**
10233  * t4_read_pace_tbl - read the pace table
10234  * @adap: the adapter
10235  * @pace_vals: holds the returned values
10236  *
10237  * Returns the values of TP's pace table in microseconds.
10238  */
10239 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10240 {
10241         unsigned int i, v;
10242
10243         for (i = 0; i < NTX_SCHED; i++) {
10244                 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
10245                 v = t4_read_reg(adap, TP_PACE_TABLE_A);
10246                 pace_vals[i] = dack_ticks_to_usec(adap, v);
10247         }
10248 }
10249
10250 /**
10251  * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10252  * @adap: the adapter
10253  * @sched: the scheduler index
10254  * @kbps: the byte rate in Kbps
10255  * @ipg: the interpacket delay in tenths of nanoseconds
10256  * @sleep_ok: if true we may sleep while awaiting command completion
10257  *
10258  * Return the current configuration of a HW Tx scheduler.
10259  */
10260 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10261                      unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
10262 {
10263         unsigned int v, addr, bpt, cpt;
10264
10265         if (kbps) {
10266                 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
10267                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10268                 if (sched & 1)
10269                         v >>= 16;
10270                 bpt = (v >> 8) & 0xff;
10271                 cpt = v & 0xff;
10272                 if (!cpt) {
10273                         *kbps = 0;      /* scheduler disabled */
10274                 } else {
10275                         v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10276                         *kbps = (v * bpt) / 125;
10277                 }
10278         }
10279         if (ipg) {
10280                 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
10281                 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10282                 if (sched & 1)
10283                         v >>= 16;
10284                 v &= 0xffff;
10285                 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10286         }
10287 }
10288
10289 /* t4_sge_ctxt_rd - read an SGE context through FW
10290  * @adap: the adapter
10291  * @mbox: mailbox to use for the FW command
10292  * @cid: the context id
10293  * @ctype: the context type
10294  * @data: where to store the context data
10295  *
10296  * Issues a FW command through the given mailbox to read an SGE context.
10297  */
10298 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10299                    enum ctxt_type ctype, u32 *data)
10300 {
10301         struct fw_ldst_cmd c;
10302         int ret;
10303
10304         if (ctype == CTXT_FLM)
10305                 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10306         else
10307                 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10308
10309         memset(&c, 0, sizeof(c));
10310         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10311                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
10312                                         FW_LDST_CMD_ADDRSPACE_V(ret));
10313         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10314         c.u.idctxt.physid = cpu_to_be32(cid);
10315
10316         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10317         if (ret == 0) {
10318                 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10319                 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10320                 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10321                 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10322                 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10323                 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10324         }
10325         return ret;
10326 }
10327
10328 /**
10329  * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10330  * @adap: the adapter
10331  * @cid: the context id
10332  * @ctype: the context type
10333  * @data: where to store the context data
10334  *
10335  * Reads an SGE context directly, bypassing FW.  This is only for
10336  * debugging when FW is unavailable.
10337  */
10338 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10339                       enum ctxt_type ctype, u32 *data)
10340 {
10341         int i, ret;
10342
10343         t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10344         ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10345         if (!ret)
10346                 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10347                         *data++ = t4_read_reg(adap, i);
10348         return ret;
10349 }
10350
10351 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
10352                     int rateunit, int ratemode, int channel, int class,
10353                     int minrate, int maxrate, int weight, int pktsize)
10354 {
10355         struct fw_sched_cmd cmd;
10356
10357         memset(&cmd, 0, sizeof(cmd));
10358         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10359                                       FW_CMD_REQUEST_F |
10360                                       FW_CMD_WRITE_F);
10361         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10362
10363         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10364         cmd.u.params.type = type;
10365         cmd.u.params.level = level;
10366         cmd.u.params.mode = mode;
10367         cmd.u.params.ch = channel;
10368         cmd.u.params.cl = class;
10369         cmd.u.params.unit = rateunit;
10370         cmd.u.params.rate = ratemode;
10371         cmd.u.params.min = cpu_to_be32(minrate);
10372         cmd.u.params.max = cpu_to_be32(maxrate);
10373         cmd.u.params.weight = cpu_to_be16(weight);
10374         cmd.u.params.pktsize = cpu_to_be16(pktsize);
10375
10376         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10377                                NULL, 1);
10378 }
10379
10380 /**
10381  *      t4_i2c_rd - read I2C data from adapter
10382  *      @adap: the adapter
10383  *      @port: Port number if per-port device; <0 if not
10384  *      @devid: per-port device ID or absolute device ID
10385  *      @offset: byte offset into device I2C space
10386  *      @len: byte length of I2C space data
10387  *      @buf: buffer in which to return I2C data
10388  *
10389  *      Reads the I2C data from the indicated device and location.
10390  */
10391 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10392               unsigned int devid, unsigned int offset,
10393               unsigned int len, u8 *buf)
10394 {
10395         struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10396         unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10397         int ret = 0;
10398
10399         if (len > I2C_PAGE_SIZE)
10400                 return -EINVAL;
10401
10402         /* Dont allow reads that spans multiple pages */
10403         if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10404                 return -EINVAL;
10405
10406         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10407         ldst_cmd.op_to_addrspace =
10408                 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10409                             FW_CMD_REQUEST_F |
10410                             FW_CMD_READ_F |
10411                             FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10412         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10413         ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10414         ldst_cmd.u.i2c.did = devid;
10415
10416         while (len > 0) {
10417                 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10418
10419                 ldst_cmd.u.i2c.boffset = offset;
10420                 ldst_cmd.u.i2c.blen = i2c_len;
10421
10422                 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10423                                  &ldst_rpl);
10424                 if (ret)
10425                         break;
10426
10427                 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10428                 offset += i2c_len;
10429                 buf += i2c_len;
10430                 len -= i2c_len;
10431         }
10432
10433         return ret;
10434 }
10435
10436 /**
10437  *      t4_set_vlan_acl - Set a VLAN id for the specified VF
10438  *      @adapter: the adapter
10439  *      @mbox: mailbox to use for the FW command
10440  *      @vf: one of the VFs instantiated by the specified PF
10441  *      @vlan: The vlanid to be set
10442  */
10443 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10444                     u16 vlan)
10445 {
10446         struct fw_acl_vlan_cmd vlan_cmd;
10447         unsigned int enable;
10448
10449         enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10450         memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10451         vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10452                                          FW_CMD_REQUEST_F |
10453                                          FW_CMD_WRITE_F |
10454                                          FW_CMD_EXEC_F |
10455                                          FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10456                                          FW_ACL_VLAN_CMD_VFN_V(vf));
10457         vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10458         /* Drop all packets that donot match vlan id */
10459         vlan_cmd.dropnovlan_fm = (enable
10460                                   ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F |
10461                                      FW_ACL_VLAN_CMD_FM_F) : 0);
10462         if (enable != 0) {
10463                 vlan_cmd.nvlan = 1;
10464                 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10465         }
10466
10467         return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
10468 }