1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2016 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 /*! \file liquidio_common.h
19 * \brief Common: Structures and macros used in PCI-NIC package by core and
23 #ifndef __LIQUIDIO_COMMON_H__
24 #define __LIQUIDIO_COMMON_H__
26 #include "octeon_config.h"
28 #define LIQUIDIO_PACKAGE ""
29 #define LIQUIDIO_BASE_MAJOR_VERSION 1
30 #define LIQUIDIO_BASE_MINOR_VERSION 7
31 #define LIQUIDIO_BASE_MICRO_VERSION 0
32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
33 __stringify(LIQUIDIO_BASE_MINOR_VERSION)
34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \
36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \
38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
48 /** Tag types used by Octeon cores in its work. */
49 enum octeon_tag_type {
56 /* pre-defined host->NIC tag values */
57 #define LIO_CONTROL (0x11111110)
58 #define LIO_DATA(i) (0x11111111 + (i))
60 /* Opcodes used by host driver/apps to perform operations on the core.
61 * These are used to identify the major subsystem that the operation
64 #define OPCODE_CORE 0 /* used for generic core operations */
65 #define OPCODE_NIC 1 /* used for NIC operations */
66 /* Subcodes are used by host driver/apps to identify the sub-operation
67 * for the core. They only need to by unique for a given subsystem.
69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
71 /** OPCODE_CORE subcodes. For future use. */
73 /** OPCODE_NIC subcodes */
75 /* This subcode is sent by core PCI driver to indicate cores are ready. */
76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
78 #define OPCODE_NIC_CMD 0x03
79 #define OPCODE_NIC_INFO 0x04
80 #define OPCODE_NIC_PORT_STATS 0x05
81 #define OPCODE_NIC_MDIO45 0x06
82 #define OPCODE_NIC_TIMESTAMP 0x07
83 #define OPCODE_NIC_INTRMOD_CFG 0x08
84 #define OPCODE_NIC_IF_CFG 0x09
85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A
86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B
87 #define OPCODE_NIC_SET_TRUSTED_VF 0x13
88 #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14
89 #define VF_DRV_LOADED 1
90 #define VF_DRV_REMOVED -1
91 #define VF_DRV_MACADDR_CHANGED 2
93 #define OPCODE_NIC_VF_REP_PKT 0x15
94 #define OPCODE_NIC_VF_REP_CMD 0x16
96 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5
98 /* Application codes advertised by the core driver initialization packet. */
99 #define CVM_DRV_APP_START 0x0
100 #define CVM_DRV_NO_APP 0
101 #define CVM_DRV_APP_COUNT 0x2
102 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
103 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
104 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
105 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
107 #define BYTES_PER_DHLEN_UNIT 8
108 #define MAX_REG_CNT 2000000U
109 #define INTRNAMSIZ 32
110 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ)
111 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2)
112 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2)
114 #define SCR2_BIT_FW_LOADED 63
116 /* App specific capabilities from firmware to pf driver */
117 #define LIQUIDIO_TIME_SYNC_CAP 0x1
118 #define LIQUIDIO_SWITCHDEV_CAP 0x2
120 static inline u32 incr_index(u32 index, u32 count, u32 max)
122 if ((index + count) >= max)
123 index = index + count - max;
130 #define OCT_BOARD_NAME 32
131 #define OCT_SERIAL_LEN 64
133 /* Structure used by core driver to send indication that the Octeon
134 * application is ready.
136 struct octeon_core_setup {
139 char boardname[OCT_BOARD_NAME];
141 char board_serial_number[OCT_SERIAL_LEN];
149 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
151 /* The Scatter-Gather List Entry. The scatter or gather component used with
152 * a Octeon input instruction has this format.
154 struct octeon_sg_entry {
155 /** The first 64 bit gives the size of data in each dptr.*/
161 /** The 4 dptr pointers for this entry. */
166 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
168 /* \brief Add size to gather list
169 * @param sg_entry scatter/gather entry
170 * @param size size to add
171 * @param pos position to add it.
173 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
177 #ifdef __BIG_ENDIAN_BITFIELD
178 sg_entry->u.size[pos] = size;
180 sg_entry->u.size[3 - pos] = size;
184 /*------------------------- End Scatter/Gather ---------------------------*/
186 #define OCTNET_FRM_LENGTH_SIZE 8
188 #define OCTNET_FRM_PTP_HEADER_SIZE 8
190 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */
192 #define OCTNET_MIN_FRM_SIZE 64
194 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
196 #define OCTNET_DEFAULT_MTU (1500)
197 #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE)
199 /** NIC Commands are sent using this Octeon Input Queue */
200 #define OCTNET_CMD_Q 0
202 /* NIC Command types */
203 #define OCTNET_CMD_CHANGE_MTU 0x1
204 #define OCTNET_CMD_CHANGE_MACADDR 0x2
205 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
206 #define OCTNET_CMD_RX_CTL 0x4
208 #define OCTNET_CMD_SET_MULTI_LIST 0x5
209 #define OCTNET_CMD_CLEAR_STATS 0x6
211 /* command for setting the speed, duplex & autoneg */
212 #define OCTNET_CMD_SET_SETTINGS 0x7
213 #define OCTNET_CMD_SET_FLOW_CTL 0x8
215 #define OCTNET_CMD_MDIO_READ_WRITE 0x9
216 #define OCTNET_CMD_GPIO_ACCESS 0xA
217 #define OCTNET_CMD_LRO_ENABLE 0xB
218 #define OCTNET_CMD_LRO_DISABLE 0xC
219 #define OCTNET_CMD_SET_RSS 0xD
220 #define OCTNET_CMD_WRITE_SA 0xE
221 #define OCTNET_CMD_DELETE_SA 0xF
222 #define OCTNET_CMD_UPDATE_SA 0x12
224 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
225 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
226 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
227 #define OCTNET_CMD_VERBOSE_ENABLE 0x14
228 #define OCTNET_CMD_VERBOSE_DISABLE 0x15
230 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16
231 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17
232 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18
233 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
235 #define OCTNET_CMD_ID_ACTIVE 0x1a
237 #define OCTNET_CMD_SET_UC_LIST 0x1b
238 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c
240 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f
242 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0
243 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1
244 #define OCTNET_CMD_RXCSUM_ENABLE 0x0
245 #define OCTNET_CMD_RXCSUM_DISABLE 0x1
246 #define OCTNET_CMD_TXCSUM_ENABLE 0x0
247 #define OCTNET_CMD_TXCSUM_DISABLE 0x1
248 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1
249 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0
251 #define LIO_CMD_WAIT_TM 100
253 /* RX(packets coming from wire) Checksum verification flags */
255 #define CNNIC_L4SUM_VERIFIED 0x1
256 #define CNNIC_IPSUM_VERIFIED 0x2
257 #define CNNIC_TUN_CSUM_VERIFIED 0x4
258 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
260 /*LROIPV4 and LROIPV6 Flags*/
261 #define OCTNIC_LROIPV4 0x1
262 #define OCTNIC_LROIPV6 0x2
264 /* Interface flags communicated between host driver and core app. */
265 enum octnet_ifflags {
266 OCTNET_IFFLAG_PROMISC = 0x01,
267 OCTNET_IFFLAG_ALLMULTI = 0x02,
268 OCTNET_IFFLAG_MULTICAST = 0x04,
269 OCTNET_IFFLAG_BROADCAST = 0x08,
270 OCTNET_IFFLAG_UNICAST = 0x10
294 #ifdef __BIG_ENDIAN_BITFIELD
297 u64 more:6; /* How many udd words follow the command */
322 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
324 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
325 #define LIO_SOFTCMDRESP_IH2 40
326 #define LIO_SOFTCMDRESP_IH3 (40 + 8)
328 #define LIO_PCICMD_O2 24
329 #define LIO_PCICMD_O3 (24 + 8)
331 /* Instruction Header(DPI) - for OCTEON-III models */
332 struct octeon_instr_ih3 {
333 #ifdef __BIG_ENDIAN_BITFIELD
338 /** Gather indicator 1=gather*/
341 /** Data length OR no. of entries in gather list */
344 /** Front Data size */
350 /** PKI port kind - PKIND */
360 /** PKI port kind - PKIND */
366 /** Front Data size */
369 /** Data length OR no. of entries in gather list */
372 /** Gather indicator 1=gather*/
381 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
382 /** BIG ENDIAN format. */
383 struct octeon_instr_pki_ih3 {
384 #ifdef __BIG_ENDIAN_BITFIELD
389 /** Raw mode indicator 1 = RAW */
454 /** Raw mode indicator 1 = RAW */
463 /** Instruction Header */
464 struct octeon_instr_ih2 {
465 #ifdef __BIG_ENDIAN_BITFIELD
466 /** Raw mode indicator 1 = RAW */
469 /** Gather indicator 1=gather*/
472 /** Data length OR no. of entries in gather list */
475 /** Front Data size */
478 /** Packet Order / Work Unit selection (1 of 8)*/
481 /** Core group selection (1 of 16) */
484 /** Short Raw Packet Indicator 1=short raw pkt */
499 /** Short Raw Packet Indicator 1=short raw pkt */
502 /** Core group selection (1 of 16) */
505 /** Packet Order / Work Unit selection (1 of 8)*/
508 /** Front Data size */
511 /** Data length OR no. of entries in gather list */
514 /** Gather indicator 1=gather*/
517 /** Raw mode indicator 1 = RAW */
522 /** Input Request Header */
523 struct octeon_instr_irh {
524 #ifdef __BIG_ENDIAN_BITFIELD
531 u64 ossp:32; /* opcode/subcode specific parameters */
533 u64 ossp:32; /* opcode/subcode specific parameters */
543 /** Return Data Parameters */
544 struct octeon_instr_rdp {
545 #ifdef __BIG_ENDIAN_BITFIELD
556 /** Receive Header */
558 #ifdef __BIG_ENDIAN_BITFIELD
563 u64 len:3; /** additional 64-bit words */
565 u64 ossp:32; /** opcode/subcode specific parameters */
570 u64 len:3; /** additional 64-bit words */
574 u64 csum_verified:3; /** checksum verified. */
575 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */
577 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
582 u64 len:3; /** additional 64-bit words */
585 u64 max_nic_ports:10;
593 u64 len:3; /** additional 64-bit words */
601 u64 ossp:32; /** opcode/subcode specific parameters */
603 u64 len:3; /** additional 64-bit words */
608 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
610 u64 has_hwtstamp:1; /** 1 = has hwtstamp */
611 u64 csum_verified:3; /** checksum verified. */
615 u64 len:3; /** additional 64-bit words */
623 u64 max_nic_ports:10;
626 u64 len:3; /** additional 64-bit words */
634 u64 len:3; /** additional 64-bit words */
641 #define OCT_RH_SIZE (sizeof(union octeon_rh))
643 union octnic_packet_params {
646 #ifdef __BIG_ENDIAN_BITFIELD
648 u32 ip_csum:1; /* Perform IP header checksum(s) */
649 /* Perform Outer transport header checksum */
650 u32 transport_csum:1;
651 /* Find tunnel, and perform transport csum. */
653 u32 tsflag:1; /* Timestamp this packet */
654 u32 ipsec_ops:4; /* IPsec operation */
659 u32 transport_csum:1;
666 /** Status of a RGMII Link on Octeon as seen by core driver. */
667 union oct_link_status {
671 #ifdef __BIG_ENDIAN_BITFIELD
698 LIO_PHY_PORT_TP = 0x0,
699 LIO_PHY_PORT_FIBRE = 0x1,
700 LIO_PHY_PORT_UNKNOWN,
703 /** The txpciq info passed to host from the firmware */
709 #ifdef __BIG_ENDIAN_BITFIELD
731 /** The rxpciq info passed to host from the firmware */
737 #ifdef __BIG_ENDIAN_BITFIELD
747 /** Information for a OCTEON ethernet interface shared between core & host. */
748 struct oct_link_info {
749 union oct_link_status link;
752 #ifdef __BIG_ENDIAN_BITFIELD
754 u64 macaddr_is_admin_asgnd:1;
762 u64 macaddr_is_admin_asgnd:1;
766 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
767 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
770 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
772 struct liquidio_if_cfg_info {
773 u64 iqmask; /** mask for IQs enabled for the port */
774 u64 oqmask; /** mask for OQs enabled for the port */
775 struct oct_link_info linfo; /** initial link information */
776 char liquidio_firmware_version[32];
779 /** Stats for each NIC port in RX direction. */
780 struct nic_rx_stats {
781 /* link-level stats */
788 u64 fifo_err; /* Accounts for over/under-run of buffers */
798 u64 fw_total_fwd_bytes;
806 u64 fw_lro_pkts; /* Number of packets that are LROed */
807 u64 fw_lro_octs; /* Number of octets that are LROed */
808 u64 fw_total_lro; /* Number of LRO packets formed */
809 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
810 u64 fw_lro_aborts_port;
811 u64 fw_lro_aborts_seq;
812 u64 fw_lro_aborts_tsval;
813 u64 fw_lro_aborts_timer;
814 /* intrmod: packet forward rate */
818 /** Stats for each NIC port in RX direction. */
819 struct nic_tx_stats {
820 /* link-level stats */
822 u64 total_bytes_sent;
826 u64 one_collision_sent; /* Packets sent after one collision*/
827 u64 multi_collision_sent; /* Packets sent after multiple collision*/
828 u64 max_collision_fail; /* Packets not sent due to max collisions */
829 u64 max_deferral_fail; /* Packets not sent due to max deferrals */
830 u64 fifo_err; /* Accounts for over/under-run of buffers */
832 u64 total_collisions; /* Total number of collisions detected */
837 u64 fw_total_fwd_bytes;
842 u64 fw_tso; /* number of tso requests */
843 u64 fw_tso_fwd; /* number of packets segmented in tso */
848 struct oct_link_stats {
849 struct nic_rx_stats fromwire;
850 struct nic_tx_stats fromhost;
854 static inline int opcode_slow_path(union octeon_rh *rh)
856 u16 subcode1, subcode2;
858 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode);
859 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA);
861 return (subcode2 != subcode1);
864 #define LIO68XX_LED_CTRL_ADDR 0x3501
865 #define LIO68XX_LED_CTRL_CFGON 0x1f
866 #define LIO68XX_LED_CTRL_CFGOFF 0x100
867 #define LIO68XX_LED_BEACON_ADDR 0x3508
868 #define LIO68XX_LED_BEACON_CFGON 0x47fd
869 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
870 #define VITESSE_PHY_GPIO_DRIVEON 0x1
871 #define VITESSE_PHY_GPIO_CFG 0x8
872 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
873 #define VITESSE_PHY_GPIO_HIGH 0x2
874 #define VITESSE_PHY_GPIO_LOW 0x3
875 #define LED_IDENTIFICATION_ON 0x1
876 #define LED_IDENTIFICATION_OFF 0x0
878 struct oct_mdio_cmd {
886 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
888 struct oct_intrmod_cfg {
894 u64 rx_maxcnt_trigger;
895 u64 rx_mincnt_trigger;
896 u64 rx_maxtmr_trigger;
897 u64 rx_mintmr_trigger;
898 u64 tx_mincnt_trigger;
899 u64 tx_maxcnt_trigger;
905 #define BASE_QUEUE_NOT_REQUESTED 65535
907 union oct_nic_if_cfg {
910 #ifdef __BIG_ENDIAN_BITFIELD
926 struct lio_trusted_vf {
929 uint64_t reserved: 55;
933 s64 sec; /* seconds */
934 s64 nsec; /* nanoseconds */
937 struct lio_vf_rep_stats {
947 enum lio_vf_rep_req_type {
949 LIO_VF_REP_REQ_STATE,
951 LIO_VF_REP_REQ_STATS,
952 LIO_VF_REP_REQ_DEVNAME
956 LIO_VF_REP_STATE_DOWN,
960 #define LIO_IF_NAME_SIZE 16
961 struct lio_vf_rep_req {
967 struct lio_vf_rep_name {
968 char name[LIO_IF_NAME_SIZE];
971 struct lio_vf_rep_mtu {
976 struct lio_vf_rep_state {
983 struct lio_vf_rep_resp {