drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_dcb.h"
  64 #include "bnx2x_sp.h"
  65 #define bnx2x_init_block(bp, start, end) \
  66   return (printk(KERN_ERR "%s: Missing Free firmware\n", bp->dev->name),\
  67           -EINVAL)
  68
  69 #include <linux/firmware.h>
  70 #include "bnx2x_fw_file_hdr.h"
  71 /* FW files */
  72 /*(DEBLOBBED)*/
  73 #define FW_FILE_NAME_E1         "/*(DEBLOBBED)*/"
  74 #define FW_FILE_NAME_E1H        "/*(DEBLOBBED)*/"
  75 #define FW_FILE_NAME_E2         "/*(DEBLOBBED)*/"
  76
  77 /* Time in jiffies before concluding the transmitter is hung */
  78 #define TX_TIMEOUT              (5*HZ)
  79
  80 static char version[] =
  81         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  82         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  83
  84 MODULE_AUTHOR("Eliezer Tamir");
  85 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  86                    "BCM57710/57711/57711E/"
  87                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  88                    "57840/57840_MF Driver");
  89 MODULE_LICENSE("GPL");
  90 MODULE_VERSION(DRV_MODULE_VERSION);
  91 /*(DEBLOBBED)*/
  92
  93 int num_queues;
  94 module_param(num_queues, int, 0);
  95 MODULE_PARM_DESC(num_queues,
  96                  " Set number of queues (default is as a number of CPUs)");
  97
  98 static int disable_tpa;
  99 module_param(disable_tpa, int, 0);
 100 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 101
 102 int int_mode;
 103 module_param(int_mode, int, 0);
 104 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 105                                 "(1 INT#x; 2 MSI)");
 106
 107 static int dropless_fc;
 108 module_param(dropless_fc, int, 0);
 109 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 110
 111 static int mrrs = -1;
 112 module_param(mrrs, int, 0);
 113 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 114
 115 static int debug;
 116 module_param(debug, int, 0);
 117 MODULE_PARM_DESC(debug, " Default debug msglevel");
 118
 119 struct workqueue_struct *bnx2x_wq;
 120
 121 struct bnx2x_mac_vals {
 122         u32 xmac_addr;
 123         u32 xmac_val;
 124         u32 emac_addr;
 125         u32 emac_val;
 126         u32 umac_addr;
 127         u32 umac_val;
 128         u32 bmac_addr;
 129         u32 bmac_val[2];
 130 };
 131
 132 enum bnx2x_board_type {
 133         BCM57710 = 0,
 134         BCM57711,
 135         BCM57711E,
 136         BCM57712,
 137         BCM57712_MF,
 138         BCM57712_VF,
 139         BCM57800,
 140         BCM57800_MF,
 141         BCM57800_VF,
 142         BCM57810,
 143         BCM57810_MF,
 144         BCM57810_VF,
 145         BCM57840_4_10,
 146         BCM57840_2_20,
 147         BCM57840_MF,
 148         BCM57840_VF,
 149         BCM57811,
 150         BCM57811_MF,
 151         BCM57840_O,
 152         BCM57840_MFO,
 153         BCM57811_VF
 154 };
 155
 156 /* indexed by board_type, above */
 157 static struct {
 158         char *name;
 159 } board_info[] = {
 160         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 161         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 162         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 163         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 164         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 165         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 166         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 167         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 168         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 169         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 170         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 171         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 173         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 174         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 175         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 176         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 177         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 178         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 179         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 180         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 181 };
 182
 183 #ifndef PCI_DEVICE_ID_NX2_57710
 184 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 185 #endif
 186 #ifndef PCI_DEVICE_ID_NX2_57711
 187 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 188 #endif
 189 #ifndef PCI_DEVICE_ID_NX2_57711E
 190 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57712
 193 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 196 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 199 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57800
 202 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 205 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 208 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57810
 211 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 214 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57840_O
 217 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 220 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 223 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 226 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 229 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 232 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 235 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57811
 238 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 241 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 244 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 245 #endif
 246
 247 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 248         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 249         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 250         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 251         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 269         { 0 }
 270 };
 271
 272 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 273
 274 /* Global resources for unloading a previously loaded device */
 275 #define BNX2X_PREV_WAIT_NEEDED 1
 276 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 277 static LIST_HEAD(bnx2x_prev_list);
 278 /****************************************************************************
 279 * General service functions
 280 ****************************************************************************/
 281
 282 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 283                                        u32 addr, dma_addr_t mapping)
 284 {
 285         REG_WR(bp,  addr, U64_LO(mapping));
 286         REG_WR(bp,  addr + 4, U64_HI(mapping));
 287 }
 288
 289 static void storm_memset_spq_addr(struct bnx2x *bp,
 290                                   dma_addr_t mapping, u16 abs_fid)
 291 {
 292         u32 addr = XSEM_REG_FAST_MEMORY +
 293                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 294
 295         __storm_memset_dma_mapping(bp, addr, mapping);
 296 }
 297
 298 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 299                                   u16 pf_id)
 300 {
 301         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 302                 pf_id);
 303         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 304                 pf_id);
 305         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 306                 pf_id);
 307         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 308                 pf_id);
 309 }
 310
 311 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 312                                  u8 enable)
 313 {
 314         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 315                 enable);
 316         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 317                 enable);
 318         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 319                 enable);
 320         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 321                 enable);
 322 }
 323
 324 static void storm_memset_eq_data(struct bnx2x *bp,
 325                                  struct event_ring_data *eq_data,
 326                                 u16 pfid)
 327 {
 328         size_t size = sizeof(struct event_ring_data);
 329
 330         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 331
 332         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 333 }
 334
 335 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 336                                  u16 pfid)
 337 {
 338         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 339         REG_WR16(bp, addr, eq_prod);
 340 }
 341
 342 /* used only at init
 343  * locking is done by mcp
 344  */
 345 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 346 {
 347         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 348         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 349         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 350                                PCICFG_VENDOR_ID_OFFSET);
 351 }
 352
 353 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 354 {
 355         u32 val;
 356
 357         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 358         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 359         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 360                                PCICFG_VENDOR_ID_OFFSET);
 361
 362         return val;
 363 }
 364
 365 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 366 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 367 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 368 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 369 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 370
 371 static void bnx2x_dp_dmae(struct bnx2x *bp,
 372                           struct dmae_command *dmae, int msglvl)
 373 {
 374         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 375         int i;
 376
 377         switch (dmae->opcode & DMAE_COMMAND_DST) {
 378         case DMAE_CMD_DST_PCI:
 379                 if (src_type == DMAE_CMD_SRC_PCI)
 380                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 381                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 382                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 383                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 384                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 385                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 386                            dmae->comp_val);
 387                 else
 388                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 389                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 390                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 391                            dmae->opcode, dmae->src_addr_lo >> 2,
 392                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 393                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 394                            dmae->comp_val);
 395                 break;
 396         case DMAE_CMD_DST_GRC:
 397                 if (src_type == DMAE_CMD_SRC_PCI)
 398                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 399                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 400                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 401                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 402                            dmae->len, dmae->dst_addr_lo >> 2,
 403                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 404                            dmae->comp_val);
 405                 else
 406                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 407                            "src [%08x], len [%d*4], dst [%08x]\n"
 408                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 409                            dmae->opcode, dmae->src_addr_lo >> 2,
 410                            dmae->len, dmae->dst_addr_lo >> 2,
 411                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 412                            dmae->comp_val);
 413                 break;
 414         default:
 415                 if (src_type == DMAE_CMD_SRC_PCI)
 416                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 417                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 418                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 419                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 420                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 421                            dmae->comp_val);
 422                 else
 423                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 424                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 425                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 426                            dmae->opcode, dmae->src_addr_lo >> 2,
 427                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 428                            dmae->comp_val);
 429                 break;
 430         }
 431
 432         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 433                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 434                    i, *(((u32 *)dmae) + i));
 435 }
 436
 437 /* copy command into DMAE command memory and set DMAE command go */
 438 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 439 {
 440         u32 cmd_offset;
 441         int i;
 442
 443         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 444         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 445                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 446         }
 447         REG_WR(bp, dmae_reg_go_c[idx], 1);
 448 }
 449
 450 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 451 {
 452         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 453                            DMAE_CMD_C_ENABLE);
 454 }
 455
 456 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 457 {
 458         return opcode & ~DMAE_CMD_SRC_RESET;
 459 }
 460
 461 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 462                              bool with_comp, u8 comp_type)
 463 {
 464         u32 opcode = 0;
 465
 466         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 467                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 468
 469         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 470
 471         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 472         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 473                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 474         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 475
 476 #ifdef __BIG_ENDIAN
 477         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 478 #else
 479         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 480 #endif
 481         if (with_comp)
 482                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 483         return opcode;
 484 }
 485
 486 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 487                                       struct dmae_command *dmae,
 488                                       u8 src_type, u8 dst_type)
 489 {
 490         memset(dmae, 0, sizeof(struct dmae_command));
 491
 492         /* set the opcode */
 493         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 494                                          true, DMAE_COMP_PCI);
 495
 496         /* fill in the completion parameters */
 497         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 498         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 499         dmae->comp_val = DMAE_COMP_VAL;
 500 }
 501
 502 /* issue a dmae command over the init-channel and wait for completion */
 503 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 504                                u32 *comp)
 505 {
 506         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 507         int rc = 0;
 508
 509         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 510
 511         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 512          * as long as this code is called both from syscall context and
 513          * from ndo_set_rx_mode() flow that may be called from BH.
 514          */
 515         spin_lock_bh(&bp->dmae_lock);
 516
 517         /* reset completion */
 518         *comp = 0;
 519
 520         /* post the command on the channel used for initializations */
 521         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 522
 523         /* wait for completion */
 524         udelay(5);
 525         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 526
 527                 if (!cnt ||
 528                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 529                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 530                         BNX2X_ERR("DMAE timeout!\n");
 531                         rc = DMAE_TIMEOUT;
 532                         goto unlock;
 533                 }
 534                 cnt--;
 535                 udelay(50);
 536         }
 537         if (*comp & DMAE_PCI_ERR_FLAG) {
 538                 BNX2X_ERR("DMAE PCI error!\n");
 539                 rc = DMAE_PCI_ERROR;
 540         }
 541
 542 unlock:
 543         spin_unlock_bh(&bp->dmae_lock);
 544         return rc;
 545 }
 546
 547 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 548                       u32 len32)
 549 {
 550         int rc;
 551         struct dmae_command dmae;
 552
 553         if (!bp->dmae_ready) {
 554                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 555
 556                 if (CHIP_IS_E1(bp))
 557                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 558                 else
 559                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 560                 return;
 561         }
 562
 563         /* set opcode and fixed command fields */
 564         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 565
 566         /* fill in addresses and len */
 567         dmae.src_addr_lo = U64_LO(dma_addr);
 568         dmae.src_addr_hi = U64_HI(dma_addr);
 569         dmae.dst_addr_lo = dst_addr >> 2;
 570         dmae.dst_addr_hi = 0;
 571         dmae.len = len32;
 572
 573         /* issue the command and wait for completion */
 574         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 575         if (rc) {
 576                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 577                 bnx2x_panic();
 578         }
 579 }
 580
 581 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 582 {
 583         int rc;
 584         struct dmae_command dmae;
 585
 586         if (!bp->dmae_ready) {
 587                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 588                 int i;
 589
 590                 if (CHIP_IS_E1(bp))
 591                         for (i = 0; i < len32; i++)
 592                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 593                 else
 594                         for (i = 0; i < len32; i++)
 595                                 data[i] = REG_RD(bp, src_addr + i*4);
 596
 597                 return;
 598         }
 599
 600         /* set opcode and fixed command fields */
 601         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 602
 603         /* fill in addresses and len */
 604         dmae.src_addr_lo = src_addr >> 2;
 605         dmae.src_addr_hi = 0;
 606         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 607         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 608         dmae.len = len32;
 609
 610         /* issue the command and wait for completion */
 611         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 612         if (rc) {
 613                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 614                 bnx2x_panic();
 615         }
 616 }
 617
 618 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 619                                       u32 addr, u32 len)
 620 {
 621         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 622         int offset = 0;
 623
 624         while (len > dmae_wr_max) {
 625                 bnx2x_write_dmae(bp, phys_addr + offset,
 626                                  addr + offset, dmae_wr_max);
 627                 offset += dmae_wr_max * 4;
 628                 len -= dmae_wr_max;
 629         }
 630
 631         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 632 }
 633
 634 static int bnx2x_mc_assert(struct bnx2x *bp)
 635 {
 636         char last_idx;
 637         int i, rc = 0;
 638         u32 row0, row1, row2, row3;
 639
 640         /* XSTORM */
 641         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 642                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 643         if (last_idx)
 644                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 645
 646         /* print the asserts */
 647         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 648
 649                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 650                               XSTORM_ASSERT_LIST_OFFSET(i));
 651                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 652                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 653                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 654                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 655                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 656                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 657
 658                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 659                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 660                                   i, row3, row2, row1, row0);
 661                         rc++;
 662                 } else {
 663                         break;
 664                 }
 665         }
 666
 667         /* TSTORM */
 668         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 669                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 670         if (last_idx)
 671                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 672
 673         /* print the asserts */
 674         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 675
 676                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 677                               TSTORM_ASSERT_LIST_OFFSET(i));
 678                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 679                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 680                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 681                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 682                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 683                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 684
 685                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 686                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 687                                   i, row3, row2, row1, row0);
 688                         rc++;
 689                 } else {
 690                         break;
 691                 }
 692         }
 693
 694         /* CSTORM */
 695         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 696                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 697         if (last_idx)
 698                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 699
 700         /* print the asserts */
 701         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 702
 703                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 704                               CSTORM_ASSERT_LIST_OFFSET(i));
 705                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 706                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 707                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 708                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 709                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 710                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 711
 712                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 713                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 714                                   i, row3, row2, row1, row0);
 715                         rc++;
 716                 } else {
 717                         break;
 718                 }
 719         }
 720
 721         /* USTORM */
 722         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 723                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 724         if (last_idx)
 725                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 726
 727         /* print the asserts */
 728         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 729
 730                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 731                               USTORM_ASSERT_LIST_OFFSET(i));
 732                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 733                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 734                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 735                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 736                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 737                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 738
 739                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 740                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 741                                   i, row3, row2, row1, row0);
 742                         rc++;
 743                 } else {
 744                         break;
 745                 }
 746         }
 747
 748         return rc;
 749 }
 750
 751 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 752 #define SCRATCH_BUFFER_SIZE(bp) \
 753         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 754
 755 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 756 {
 757         u32 addr, val;
 758         u32 mark, offset;
 759         __be32 data[9];
 760         int word;
 761         u32 trace_shmem_base;
 762         if (BP_NOMCP(bp)) {
 763                 BNX2X_ERR("NO MCP - can not dump\n");
 764                 return;
 765         }
 766         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 767                 (bp->common.bc_ver & 0xff0000) >> 16,
 768                 (bp->common.bc_ver & 0xff00) >> 8,
 769                 (bp->common.bc_ver & 0xff));
 770
 771         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 772         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 773                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 774
 775         if (BP_PATH(bp) == 0)
 776                 trace_shmem_base = bp->common.shmem_base;
 777         else
 778                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 779
 780         /* sanity */
 781         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 782             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 783                                 SCRATCH_BUFFER_SIZE(bp)) {
 784                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 785                           trace_shmem_base);
 786                 return;
 787         }
 788
 789         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 790
 791         /* validate TRCB signature */
 792         mark = REG_RD(bp, addr);
 793         if (mark != MFW_TRACE_SIGNATURE) {
 794                 BNX2X_ERR("Trace buffer signature is missing.");
 795                 return ;
 796         }
 797
 798         /* read cyclic buffer pointer */
 799         addr += 4;
 800         mark = REG_RD(bp, addr);
 801         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 802         if (mark >= trace_shmem_base || mark < addr + 4) {
 803                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 804                 return;
 805         }
 806         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 807
 808         printk("%s", lvl);
 809
 810         /* dump buffer after the mark */
 811         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 812                 for (word = 0; word < 8; word++)
 813                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 814                 data[8] = 0x0;
 815                 pr_cont("%s", (char *)data);
 816         }
 817
 818         /* dump buffer before the mark */
 819         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 820                 for (word = 0; word < 8; word++)
 821                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 822                 data[8] = 0x0;
 823                 pr_cont("%s", (char *)data);
 824         }
 825         printk("%s" "end of fw dump\n", lvl);
 826 }
 827
 828 static void bnx2x_fw_dump(struct bnx2x *bp)
 829 {
 830         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 831 }
 832
 833 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 834 {
 835         int port = BP_PORT(bp);
 836         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 837         u32 val = REG_RD(bp, addr);
 838
 839         /* in E1 we must use only PCI configuration space to disable
 840          * MSI/MSIX capability
 841          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 842          */
 843         if (CHIP_IS_E1(bp)) {
 844                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 845                  * Use mask register to prevent from HC sending interrupts
 846                  * after we exit the function
 847                  */
 848                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 849
 850                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 851                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 852                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 853         } else
 854                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 855                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 856                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 857                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 858
 859         DP(NETIF_MSG_IFDOWN,
 860            "write %x to HC %d (addr 0x%x)\n",
 861            val, port, addr);
 862
 863         /* flush all outstanding writes */
 864         mmiowb();
 865
 866         REG_WR(bp, addr, val);
 867         if (REG_RD(bp, addr) != val)
 868                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 869 }
 870
 871 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 872 {
 873         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 874
 875         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 876                  IGU_PF_CONF_INT_LINE_EN |
 877                  IGU_PF_CONF_ATTN_BIT_EN);
 878
 879         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 880
 881         /* flush all outstanding writes */
 882         mmiowb();
 883
 884         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 885         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 886                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 887 }
 888
 889 static void bnx2x_int_disable(struct bnx2x *bp)
 890 {
 891         if (bp->common.int_block == INT_BLOCK_HC)
 892                 bnx2x_hc_int_disable(bp);
 893         else
 894                 bnx2x_igu_int_disable(bp);
 895 }
 896
 897 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 898 {
 899         int i;
 900         u16 j;
 901         struct hc_sp_status_block_data sp_sb_data;
 902         int func = BP_FUNC(bp);
 903 #ifdef BNX2X_STOP_ON_ERROR
 904         u16 start = 0, end = 0;
 905         u8 cos;
 906 #endif
 907         if (disable_int)
 908                 bnx2x_int_disable(bp);
 909
 910         bp->stats_state = STATS_STATE_DISABLED;
 911         bp->eth_stats.unrecoverable_error++;
 912         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 913
 914         BNX2X_ERR("begin crash dump -----------------\n");
 915
 916         /* Indices */
 917         /* Common */
 918         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 919                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 920                   bp->spq_prod_idx, bp->stats_counter);
 921         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 922                   bp->def_status_blk->atten_status_block.attn_bits,
 923                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 924                   bp->def_status_blk->atten_status_block.status_block_id,
 925                   bp->def_status_blk->atten_status_block.attn_bits_index);
 926         BNX2X_ERR("     def (");
 927         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 928                 pr_cont("0x%x%s",
 929                         bp->def_status_blk->sp_sb.index_values[i],
 930                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 931
 932         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 933                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 934                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 935                         i*sizeof(u32));
 936
 937         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 938                sp_sb_data.igu_sb_id,
 939                sp_sb_data.igu_seg_id,
 940                sp_sb_data.p_func.pf_id,
 941                sp_sb_data.p_func.vnic_id,
 942                sp_sb_data.p_func.vf_id,
 943                sp_sb_data.p_func.vf_valid,
 944                sp_sb_data.state);
 945
 946         for_each_eth_queue(bp, i) {
 947                 struct bnx2x_fastpath *fp = &bp->fp[i];
 948                 int loop;
 949                 struct hc_status_block_data_e2 sb_data_e2;
 950                 struct hc_status_block_data_e1x sb_data_e1x;
 951                 struct hc_status_block_sm  *hc_sm_p =
 952                         CHIP_IS_E1x(bp) ?
 953                         sb_data_e1x.common.state_machine :
 954                         sb_data_e2.common.state_machine;
 955                 struct hc_index_data *hc_index_p =
 956                         CHIP_IS_E1x(bp) ?
 957                         sb_data_e1x.index_data :
 958                         sb_data_e2.index_data;
 959                 u8 data_size, cos;
 960                 u32 *sb_data_p;
 961                 struct bnx2x_fp_txdata txdata;
 962
 963                 /* Rx */
 964                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 965                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 966                           fp->rx_comp_prod,
 967                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 968                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 969                           fp->rx_sge_prod, fp->last_max_sge,
 970                           le16_to_cpu(fp->fp_hc_idx));
 971
 972                 /* Tx */
 973                 for_each_cos_in_tx_queue(fp, cos)
 974                 {
 975                         txdata = *fp->txdata_ptr[cos];
 976                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 977                                   i, txdata.tx_pkt_prod,
 978                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 979                                   txdata.tx_bd_cons,
 980                                   le16_to_cpu(*txdata.tx_cons_sb));
 981                 }
 982
 983                 loop = CHIP_IS_E1x(bp) ?
 984                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 985
 986                 /* host sb data */
 987
 988                 if (IS_FCOE_FP(fp))
 989                         continue;
 990
 991                 BNX2X_ERR("     run indexes (");
 992                 for (j = 0; j < HC_SB_MAX_SM; j++)
 993                         pr_cont("0x%x%s",
 994                                fp->sb_running_index[j],
 995                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 996
 997                 BNX2X_ERR("     indexes (");
 998                 for (j = 0; j < loop; j++)
 999                         pr_cont("0x%x%s",
1000                                fp->sb_index_values[j],
1001                                (j == loop - 1) ? ")" : " ");
1002                 /* fw sb data */
1003                 data_size = CHIP_IS_E1x(bp) ?
1004                         sizeof(struct hc_status_block_data_e1x) :
1005                         sizeof(struct hc_status_block_data_e2);
1006                 data_size /= sizeof(u32);
1007                 sb_data_p = CHIP_IS_E1x(bp) ?
1008                         (u32 *)&sb_data_e1x :
1009                         (u32 *)&sb_data_e2;
1010                 /* copy sb data in here */
1011                 for (j = 0; j < data_size; j++)
1012                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1013                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1014                                 j * sizeof(u32));
1015
1016                 if (!CHIP_IS_E1x(bp)) {
1017                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1018                                 sb_data_e2.common.p_func.pf_id,
1019                                 sb_data_e2.common.p_func.vf_id,
1020                                 sb_data_e2.common.p_func.vf_valid,
1021                                 sb_data_e2.common.p_func.vnic_id,
1022                                 sb_data_e2.common.same_igu_sb_1b,
1023                                 sb_data_e2.common.state);
1024                 } else {
1025                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1026                                 sb_data_e1x.common.p_func.pf_id,
1027                                 sb_data_e1x.common.p_func.vf_id,
1028                                 sb_data_e1x.common.p_func.vf_valid,
1029                                 sb_data_e1x.common.p_func.vnic_id,
1030                                 sb_data_e1x.common.same_igu_sb_1b,
1031                                 sb_data_e1x.common.state);
1032                 }
1033
1034                 /* SB_SMs data */
1035                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1036                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1037                                 j, hc_sm_p[j].__flags,
1038                                 hc_sm_p[j].igu_sb_id,
1039                                 hc_sm_p[j].igu_seg_id,
1040                                 hc_sm_p[j].time_to_expire,
1041                                 hc_sm_p[j].timer_value);
1042                 }
1043
1044                 /* Indices data */
1045                 for (j = 0; j < loop; j++) {
1046                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1047                                hc_index_p[j].flags,
1048                                hc_index_p[j].timeout);
1049                 }
1050         }
1051
1052 #ifdef BNX2X_STOP_ON_ERROR
1053
1054         /* event queue */
1055         BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1056         for (i = 0; i < NUM_EQ_DESC; i++) {
1057                 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1058
1059                 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1060                           i, bp->eq_ring[i].message.opcode,
1061                           bp->eq_ring[i].message.error);
1062                 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1063         }
1064
1065         /* Rings */
1066         /* Rx */
1067         for_each_valid_rx_queue(bp, i) {
1068                 struct bnx2x_fastpath *fp = &bp->fp[i];
1069
1070                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1071                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1072                 for (j = start; j != end; j = RX_BD(j + 1)) {
1073                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1074                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1075
1076                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1077                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1078                 }
1079
1080                 start = RX_SGE(fp->rx_sge_prod);
1081                 end = RX_SGE(fp->last_max_sge);
1082                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1083                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1084                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1085
1086                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1087                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1088                 }
1089
1090                 start = RCQ_BD(fp->rx_comp_cons - 10);
1091                 end = RCQ_BD(fp->rx_comp_cons + 503);
1092                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1093                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1094
1095                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1096                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1097                 }
1098         }
1099
1100         /* Tx */
1101         for_each_valid_tx_queue(bp, i) {
1102                 struct bnx2x_fastpath *fp = &bp->fp[i];
1103                 for_each_cos_in_tx_queue(fp, cos) {
1104                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1105
1106                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1107                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1108                         for (j = start; j != end; j = TX_BD(j + 1)) {
1109                                 struct sw_tx_bd *sw_bd =
1110                                         &txdata->tx_buf_ring[j];
1111
1112                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1113                                           i, cos, j, sw_bd->skb,
1114                                           sw_bd->first_bd);
1115                         }
1116
1117                         start = TX_BD(txdata->tx_bd_cons - 10);
1118                         end = TX_BD(txdata->tx_bd_cons + 254);
1119                         for (j = start; j != end; j = TX_BD(j + 1)) {
1120                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1121
1122                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1123                                           i, cos, j, tx_bd[0], tx_bd[1],
1124                                           tx_bd[2], tx_bd[3]);
1125                         }
1126                 }
1127         }
1128 #endif
1129         bnx2x_fw_dump(bp);
1130         bnx2x_mc_assert(bp);
1131         BNX2X_ERR("end crash dump -----------------\n");
1132 }
1133
1134 /*
1135  * FLR Support for E2
1136  *
1137  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1138  * initialization.
1139  */
1140 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1141 #define FLR_WAIT_INTERVAL       50      /* usec */
1142 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1143
1144 struct pbf_pN_buf_regs {
1145         int pN;
1146         u32 init_crd;
1147         u32 crd;
1148         u32 crd_freed;
1149 };
1150
1151 struct pbf_pN_cmd_regs {
1152         int pN;
1153         u32 lines_occup;
1154         u32 lines_freed;
1155 };
1156
1157 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1158                                      struct pbf_pN_buf_regs *regs,
1159                                      u32 poll_count)
1160 {
1161         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1162         u32 cur_cnt = poll_count;
1163
1164         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1165         crd = crd_start = REG_RD(bp, regs->crd);
1166         init_crd = REG_RD(bp, regs->init_crd);
1167
1168         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1169         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1170         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1171
1172         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1173                (init_crd - crd_start))) {
1174                 if (cur_cnt--) {
1175                         udelay(FLR_WAIT_INTERVAL);
1176                         crd = REG_RD(bp, regs->crd);
1177                         crd_freed = REG_RD(bp, regs->crd_freed);
1178                 } else {
1179                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1180                            regs->pN);
1181                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1182                            regs->pN, crd);
1183                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1184                            regs->pN, crd_freed);
1185                         break;
1186                 }
1187         }
1188         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1189            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1190 }
1191
1192 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1193                                      struct pbf_pN_cmd_regs *regs,
1194                                      u32 poll_count)
1195 {
1196         u32 occup, to_free, freed, freed_start;
1197         u32 cur_cnt = poll_count;
1198
1199         occup = to_free = REG_RD(bp, regs->lines_occup);
1200         freed = freed_start = REG_RD(bp, regs->lines_freed);
1201
1202         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1203         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1204
1205         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1206                 if (cur_cnt--) {
1207                         udelay(FLR_WAIT_INTERVAL);
1208                         occup = REG_RD(bp, regs->lines_occup);
1209                         freed = REG_RD(bp, regs->lines_freed);
1210                 } else {
1211                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1212                            regs->pN);
1213                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1214                            regs->pN, occup);
1215                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1216                            regs->pN, freed);
1217                         break;
1218                 }
1219         }
1220         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1221            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1222 }
1223
1224 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1225                                     u32 expected, u32 poll_count)
1226 {
1227         u32 cur_cnt = poll_count;
1228         u32 val;
1229
1230         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1231                 udelay(FLR_WAIT_INTERVAL);
1232
1233         return val;
1234 }
1235
1236 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1237                                     char *msg, u32 poll_cnt)
1238 {
1239         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1240         if (val != 0) {
1241                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1242                 return 1;
1243         }
1244         return 0;
1245 }
1246
1247 /* Common routines with VF FLR cleanup */
1248 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1249 {
1250         /* adjust polling timeout */
1251         if (CHIP_REV_IS_EMUL(bp))
1252                 return FLR_POLL_CNT * 2000;
1253
1254         if (CHIP_REV_IS_FPGA(bp))
1255                 return FLR_POLL_CNT * 120;
1256
1257         return FLR_POLL_CNT;
1258 }
1259
1260 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1261 {
1262         struct pbf_pN_cmd_regs cmd_regs[] = {
1263                 {0, (CHIP_IS_E3B0(bp)) ?
1264                         PBF_REG_TQ_OCCUPANCY_Q0 :
1265                         PBF_REG_P0_TQ_OCCUPANCY,
1266                     (CHIP_IS_E3B0(bp)) ?
1267                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1268                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1269                 {1, (CHIP_IS_E3B0(bp)) ?
1270                         PBF_REG_TQ_OCCUPANCY_Q1 :
1271                         PBF_REG_P1_TQ_OCCUPANCY,
1272                     (CHIP_IS_E3B0(bp)) ?
1273                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1274                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1275                 {4, (CHIP_IS_E3B0(bp)) ?
1276                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1277                         PBF_REG_P4_TQ_OCCUPANCY,
1278                     (CHIP_IS_E3B0(bp)) ?
1279                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1280                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1281         };
1282
1283         struct pbf_pN_buf_regs buf_regs[] = {
1284                 {0, (CHIP_IS_E3B0(bp)) ?
1285                         PBF_REG_INIT_CRD_Q0 :
1286                         PBF_REG_P0_INIT_CRD ,
1287                     (CHIP_IS_E3B0(bp)) ?
1288                         PBF_REG_CREDIT_Q0 :
1289                         PBF_REG_P0_CREDIT,
1290                     (CHIP_IS_E3B0(bp)) ?
1291                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1292                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1293                 {1, (CHIP_IS_E3B0(bp)) ?
1294                         PBF_REG_INIT_CRD_Q1 :
1295                         PBF_REG_P1_INIT_CRD,
1296                     (CHIP_IS_E3B0(bp)) ?
1297                         PBF_REG_CREDIT_Q1 :
1298                         PBF_REG_P1_CREDIT,
1299                     (CHIP_IS_E3B0(bp)) ?
1300                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1301                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1302                 {4, (CHIP_IS_E3B0(bp)) ?
1303                         PBF_REG_INIT_CRD_LB_Q :
1304                         PBF_REG_P4_INIT_CRD,
1305                     (CHIP_IS_E3B0(bp)) ?
1306                         PBF_REG_CREDIT_LB_Q :
1307                         PBF_REG_P4_CREDIT,
1308                     (CHIP_IS_E3B0(bp)) ?
1309                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1310                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1311         };
1312
1313         int i;
1314
1315         /* Verify the command queues are flushed P0, P1, P4 */
1316         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1317                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1318
1319         /* Verify the transmission buffers are flushed P0, P1, P4 */
1320         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1321                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1322 }
1323
1324 #define OP_GEN_PARAM(param) \
1325         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1326
1327 #define OP_GEN_TYPE(type) \
1328         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1329
1330 #define OP_GEN_AGG_VECT(index) \
1331         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1332
1333 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1334 {
1335         u32 op_gen_command = 0;
1336         u32 comp_addr = BAR_CSTRORM_INTMEM +
1337                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1338         int ret = 0;
1339
1340         if (REG_RD(bp, comp_addr)) {
1341                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1342                 return 1;
1343         }
1344
1345         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1346         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1347         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1348         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1349
1350         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1351         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1352
1353         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1354                 BNX2X_ERR("FW final cleanup did not succeed\n");
1355                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1356                    (REG_RD(bp, comp_addr)));
1357                 bnx2x_panic();
1358                 return 1;
1359         }
1360         /* Zero completion for next FLR */
1361         REG_WR(bp, comp_addr, 0);
1362
1363         return ret;
1364 }
1365
1366 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1367 {
1368         u16 status;
1369
1370         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1371         return status & PCI_EXP_DEVSTA_TRPND;
1372 }
1373
1374 /* PF FLR specific routines
1375 */
1376 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1377 {
1378         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1379         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1380                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1381                         "CFC PF usage counter timed out",
1382                         poll_cnt))
1383                 return 1;
1384
1385         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1386         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1387                         DORQ_REG_PF_USAGE_CNT,
1388                         "DQ PF usage counter timed out",
1389                         poll_cnt))
1390                 return 1;
1391
1392         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1393         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1394                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1395                         "QM PF usage counter timed out",
1396                         poll_cnt))
1397                 return 1;
1398
1399         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1400         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1401                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1402                         "Timers VNIC usage counter timed out",
1403                         poll_cnt))
1404                 return 1;
1405         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1406                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1407                         "Timers NUM_SCANS usage counter timed out",
1408                         poll_cnt))
1409                 return 1;
1410
1411         /* Wait DMAE PF usage counter to zero */
1412         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1413                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1414                         "DMAE command register timed out",
1415                         poll_cnt))
1416                 return 1;
1417
1418         return 0;
1419 }
1420
1421 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1422 {
1423         u32 val;
1424
1425         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1426         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1427
1428         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1429         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1430
1431         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1432         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1433
1434         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1435         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1436
1437         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1438         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1439
1440         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1441         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1442
1443         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1444         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1445
1446         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1447         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1448            val);
1449 }
1450
1451 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1452 {
1453         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1454
1455         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1456
1457         /* Re-enable PF target read access */
1458         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1459
1460         /* Poll HW usage counters */
1461         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1462         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1463                 return -EBUSY;
1464
1465         /* Zero the igu 'trailing edge' and 'leading edge' */
1466
1467         /* Send the FW cleanup command */
1468         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1469                 return -EBUSY;
1470
1471         /* ATC cleanup */
1472
1473         /* Verify TX hw is flushed */
1474         bnx2x_tx_hw_flushed(bp, poll_cnt);
1475
1476         /* Wait 100ms (not adjusted according to platform) */
1477         msleep(100);
1478
1479         /* Verify no pending pci transactions */
1480         if (bnx2x_is_pcie_pending(bp->pdev))
1481                 BNX2X_ERR("PCIE Transactions still pending\n");
1482
1483         /* Debug */
1484         bnx2x_hw_enable_status(bp);
1485
1486         /*
1487          * Master enable - Due to WB DMAE writes performed before this
1488          * register is re-initialized as part of the regular function init
1489          */
1490         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1491
1492         return 0;
1493 }
1494
1495 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1496 {
1497         int port = BP_PORT(bp);
1498         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1499         u32 val = REG_RD(bp, addr);
1500         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1501         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1502         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1503
1504         if (msix) {
1505                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1506                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1507                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1508                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1509                 if (single_msix)
1510                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1511         } else if (msi) {
1512                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1513                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1514                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1515                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1516         } else {
1517                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1518                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1519                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1520                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1521
1522                 if (!CHIP_IS_E1(bp)) {
1523                         DP(NETIF_MSG_IFUP,
1524                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1525
1526                         REG_WR(bp, addr, val);
1527
1528                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1529                 }
1530         }
1531
1532         if (CHIP_IS_E1(bp))
1533                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1534
1535         DP(NETIF_MSG_IFUP,
1536            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1537            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1538
1539         REG_WR(bp, addr, val);
1540         /*
1541          * Ensure that HC_CONFIG is written before leading/trailing edge config
1542          */
1543         mmiowb();
1544         barrier();
1545
1546         if (!CHIP_IS_E1(bp)) {
1547                 /* init leading/trailing edge */
1548                 if (IS_MF(bp)) {
1549                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1550                         if (bp->port.pmf)
1551                                 /* enable nig and gpio3 attention */
1552                                 val |= 0x1100;
1553                 } else
1554                         val = 0xffff;
1555
1556                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1557                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1558         }
1559
1560         /* Make sure that interrupts are indeed enabled from here on */
1561         mmiowb();
1562 }
1563
1564 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1565 {
1566         u32 val;
1567         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1568         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1569         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1570
1571         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1572
1573         if (msix) {
1574                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1575                          IGU_PF_CONF_SINGLE_ISR_EN);
1576                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1577                         IGU_PF_CONF_ATTN_BIT_EN);
1578
1579                 if (single_msix)
1580                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1581         } else if (msi) {
1582                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1583                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1584                         IGU_PF_CONF_ATTN_BIT_EN |
1585                         IGU_PF_CONF_SINGLE_ISR_EN);
1586         } else {
1587                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1588                 val |= (IGU_PF_CONF_INT_LINE_EN |
1589                         IGU_PF_CONF_ATTN_BIT_EN |
1590                         IGU_PF_CONF_SINGLE_ISR_EN);
1591         }
1592
1593         /* Clean previous status - need to configure igu prior to ack*/
1594         if ((!msix) || single_msix) {
1595                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1596                 bnx2x_ack_int(bp);
1597         }
1598
1599         val |= IGU_PF_CONF_FUNC_EN;
1600
1601         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1602            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1603
1604         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1605
1606         if (val & IGU_PF_CONF_INT_LINE_EN)
1607                 pci_intx(bp->pdev, true);
1608
1609         barrier();
1610
1611         /* init leading/trailing edge */
1612         if (IS_MF(bp)) {
1613                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1614                 if (bp->port.pmf)
1615                         /* enable nig and gpio3 attention */
1616                         val |= 0x1100;
1617         } else
1618                 val = 0xffff;
1619
1620         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1621         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1622
1623         /* Make sure that interrupts are indeed enabled from here on */
1624         mmiowb();
1625 }
1626
1627 void bnx2x_int_enable(struct bnx2x *bp)
1628 {
1629         if (bp->common.int_block == INT_BLOCK_HC)
1630                 bnx2x_hc_int_enable(bp);
1631         else
1632                 bnx2x_igu_int_enable(bp);
1633 }
1634
1635 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1636 {
1637         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1638         int i, offset;
1639
1640         if (disable_hw)
1641                 /* prevent the HW from sending interrupts */
1642                 bnx2x_int_disable(bp);
1643
1644         /* make sure all ISRs are done */
1645         if (msix) {
1646                 synchronize_irq(bp->msix_table[0].vector);
1647                 offset = 1;
1648                 if (CNIC_SUPPORT(bp))
1649                         offset++;
1650                 for_each_eth_queue(bp, i)
1651                         synchronize_irq(bp->msix_table[offset++].vector);
1652         } else
1653                 synchronize_irq(bp->pdev->irq);
1654
1655         /* make sure sp_task is not running */
1656         cancel_delayed_work(&bp->sp_task);
1657         cancel_delayed_work(&bp->period_task);
1658         flush_workqueue(bnx2x_wq);
1659 }
1660
1661 /* fast path */
1662
1663 /*
1664  * General service functions
1665  */
1666
1667 /* Return true if succeeded to acquire the lock */
1668 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1669 {
1670         u32 lock_status;
1671         u32 resource_bit = (1 << resource);
1672         int func = BP_FUNC(bp);
1673         u32 hw_lock_control_reg;
1674
1675         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1676            "Trying to take a lock on resource %d\n", resource);
1677
1678         /* Validating that the resource is within range */
1679         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1680                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1681                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1682                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1683                 return false;
1684         }
1685
1686         if (func <= 5)
1687                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1688         else
1689                 hw_lock_control_reg =
1690                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1691
1692         /* Try to acquire the lock */
1693         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1694         lock_status = REG_RD(bp, hw_lock_control_reg);
1695         if (lock_status & resource_bit)
1696                 return true;
1697
1698         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1699            "Failed to get a lock on resource %d\n", resource);
1700         return false;
1701 }
1702
1703 /**
1704  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1705  *
1706  * @bp: driver handle
1707  *
1708  * Returns the recovery leader resource id according to the engine this function
1709  * belongs to. Currently only only 2 engines is supported.
1710  */
1711 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1712 {
1713         if (BP_PATH(bp))
1714                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1715         else
1716                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1717 }
1718
1719 /**
1720  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1721  *
1722  * @bp: driver handle
1723  *
1724  * Tries to acquire a leader lock for current engine.
1725  */
1726 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1727 {
1728         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1729 }
1730
1731 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1732
1733 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1734 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1735 {
1736         /* Set the interrupt occurred bit for the sp-task to recognize it
1737          * must ack the interrupt and transition according to the IGU
1738          * state machine.
1739          */
1740         atomic_set(&bp->interrupt_occurred, 1);
1741
1742         /* The sp_task must execute only after this bit
1743          * is set, otherwise we will get out of sync and miss all
1744          * further interrupts. Hence, the barrier.
1745          */
1746         smp_wmb();
1747
1748         /* schedule sp_task to workqueue */
1749         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1750 }
1751
1752 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1753 {
1754         struct bnx2x *bp = fp->bp;
1755         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1756         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1757         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1758         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1759
1760         DP(BNX2X_MSG_SP,
1761            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1762            fp->index, cid, command, bp->state,
1763            rr_cqe->ramrod_cqe.ramrod_type);
1764
1765         /* If cid is within VF range, replace the slowpath object with the
1766          * one corresponding to this VF
1767          */
1768         if (cid >= BNX2X_FIRST_VF_CID  &&
1769             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1770                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1771
1772         switch (command) {
1773         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1774                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1775                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1776                 break;
1777
1778         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1779                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1780                 drv_cmd = BNX2X_Q_CMD_SETUP;
1781                 break;
1782
1783         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1784                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1785                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1786                 break;
1787
1788         case (RAMROD_CMD_ID_ETH_HALT):
1789                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1790                 drv_cmd = BNX2X_Q_CMD_HALT;
1791                 break;
1792
1793         case (RAMROD_CMD_ID_ETH_TERMINATE):
1794                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1795                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1796                 break;
1797
1798         case (RAMROD_CMD_ID_ETH_EMPTY):
1799                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1800                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1801                 break;
1802
1803         default:
1804                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1805                           command, fp->index);
1806                 return;
1807         }
1808
1809         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1810             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1811                 /* q_obj->complete_cmd() failure means that this was
1812                  * an unexpected completion.
1813                  *
1814                  * In this case we don't want to increase the bp->spq_left
1815                  * because apparently we haven't sent this command the first
1816                  * place.
1817                  */
1818 #ifdef BNX2X_STOP_ON_ERROR
1819                 bnx2x_panic();
1820 #else
1821                 return;
1822 #endif
1823         /* SRIOV: reschedule any 'in_progress' operations */
1824         bnx2x_iov_sp_event(bp, cid, true);
1825
1826         smp_mb__before_atomic_inc();
1827         atomic_inc(&bp->cq_spq_left);
1828         /* push the change in bp->spq_left and towards the memory */
1829         smp_mb__after_atomic_inc();
1830
1831         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1832
1833         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1834             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1835                 /* if Q update ramrod is completed for last Q in AFEX vif set
1836                  * flow, then ACK MCP at the end
1837                  *
1838                  * mark pending ACK to MCP bit.
1839                  * prevent case that both bits are cleared.
1840                  * At the end of load/unload driver checks that
1841                  * sp_state is cleared, and this order prevents
1842                  * races
1843                  */
1844                 smp_mb__before_clear_bit();
1845                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1846                 wmb();
1847                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1848                 smp_mb__after_clear_bit();
1849
1850                 /* schedule the sp task as mcp ack is required */
1851                 bnx2x_schedule_sp_task(bp);
1852         }
1853
1854         return;
1855 }
1856
1857 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1858 {
1859         struct bnx2x *bp = netdev_priv(dev_instance);
1860         u16 status = bnx2x_ack_int(bp);
1861         u16 mask;
1862         int i;
1863         u8 cos;
1864
1865         /* Return here if interrupt is shared and it's not for us */
1866         if (unlikely(status == 0)) {
1867                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1868                 return IRQ_NONE;
1869         }
1870         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1871
1872 #ifdef BNX2X_STOP_ON_ERROR
1873         if (unlikely(bp->panic))
1874                 return IRQ_HANDLED;
1875 #endif
1876
1877         for_each_eth_queue(bp, i) {
1878                 struct bnx2x_fastpath *fp = &bp->fp[i];
1879
1880                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1881                 if (status & mask) {
1882                         /* Handle Rx or Tx according to SB id */
1883                         for_each_cos_in_tx_queue(fp, cos)
1884                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1885                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1886                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1887                         status &= ~mask;
1888                 }
1889         }
1890
1891         if (CNIC_SUPPORT(bp)) {
1892                 mask = 0x2;
1893                 if (status & (mask | 0x1)) {
1894                         struct cnic_ops *c_ops = NULL;
1895
1896                         rcu_read_lock();
1897                         c_ops = rcu_dereference(bp->cnic_ops);
1898                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1899                                       CNIC_DRV_STATE_HANDLES_IRQ))
1900                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1901                         rcu_read_unlock();
1902
1903                         status &= ~mask;
1904                 }
1905         }
1906
1907         if (unlikely(status & 0x1)) {
1908
1909                 /* schedule sp task to perform default status block work, ack
1910                  * attentions and enable interrupts.
1911                  */
1912                 bnx2x_schedule_sp_task(bp);
1913
1914                 status &= ~0x1;
1915                 if (!status)
1916                         return IRQ_HANDLED;
1917         }
1918
1919         if (unlikely(status))
1920                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1921                    status);
1922
1923         return IRQ_HANDLED;
1924 }
1925
1926 /* Link */
1927
1928 /*
1929  * General service functions
1930  */
1931
1932 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1933 {
1934         u32 lock_status;
1935         u32 resource_bit = (1 << resource);
1936         int func = BP_FUNC(bp);
1937         u32 hw_lock_control_reg;
1938         int cnt;
1939
1940         /* Validating that the resource is within range */
1941         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1942                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1943                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1944                 return -EINVAL;
1945         }
1946
1947         if (func <= 5) {
1948                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1949         } else {
1950                 hw_lock_control_reg =
1951                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1952         }
1953
1954         /* Validating that the resource is not already taken */
1955         lock_status = REG_RD(bp, hw_lock_control_reg);
1956         if (lock_status & resource_bit) {
1957                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1958                    lock_status, resource_bit);
1959                 return -EEXIST;
1960         }
1961
1962         /* Try for 5 second every 5ms */
1963         for (cnt = 0; cnt < 1000; cnt++) {
1964                 /* Try to acquire the lock */
1965                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1966                 lock_status = REG_RD(bp, hw_lock_control_reg);
1967                 if (lock_status & resource_bit)
1968                         return 0;
1969
1970                 usleep_range(5000, 10000);
1971         }
1972         BNX2X_ERR("Timeout\n");
1973         return -EAGAIN;
1974 }
1975
1976 int bnx2x_release_leader_lock(struct bnx2x *bp)
1977 {
1978         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1979 }
1980
1981 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1982 {
1983         u32 lock_status;
1984         u32 resource_bit = (1 << resource);
1985         int func = BP_FUNC(bp);
1986         u32 hw_lock_control_reg;
1987
1988         /* Validating that the resource is within range */
1989         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1990                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1991                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1992                 return -EINVAL;
1993         }
1994
1995         if (func <= 5) {
1996                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1997         } else {
1998                 hw_lock_control_reg =
1999                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2000         }
2001
2002         /* Validating that the resource is currently taken */
2003         lock_status = REG_RD(bp, hw_lock_control_reg);
2004         if (!(lock_status & resource_bit)) {
2005                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2006                           lock_status, resource_bit);
2007                 return -EFAULT;
2008         }
2009
2010         REG_WR(bp, hw_lock_control_reg, resource_bit);
2011         return 0;
2012 }
2013
2014 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2015 {
2016         /* The GPIO should be swapped if swap register is set and active */
2017         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2018                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2019         int gpio_shift = gpio_num +
2020                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2021         u32 gpio_mask = (1 << gpio_shift);
2022         u32 gpio_reg;
2023         int value;
2024
2025         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2026                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2027                 return -EINVAL;
2028         }
2029
2030         /* read GPIO value */
2031         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2032
2033         /* get the requested pin value */
2034         if ((gpio_reg & gpio_mask) == gpio_mask)
2035                 value = 1;
2036         else
2037                 value = 0;
2038
2039         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2040
2041         return value;
2042 }
2043
2044 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2045 {
2046         /* The GPIO should be swapped if swap register is set and active */
2047         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2048                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2049         int gpio_shift = gpio_num +
2050                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2051         u32 gpio_mask = (1 << gpio_shift);
2052         u32 gpio_reg;
2053
2054         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2055                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2056                 return -EINVAL;
2057         }
2058
2059         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2060         /* read GPIO and mask except the float bits */
2061         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2062
2063         switch (mode) {
2064         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2065                 DP(NETIF_MSG_LINK,
2066                    "Set GPIO %d (shift %d) -> output low\n",
2067                    gpio_num, gpio_shift);
2068                 /* clear FLOAT and set CLR */
2069                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2070                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2071                 break;
2072
2073         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2074                 DP(NETIF_MSG_LINK,
2075                    "Set GPIO %d (shift %d) -> output high\n",
2076                    gpio_num, gpio_shift);
2077                 /* clear FLOAT and set SET */
2078                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2079                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2080                 break;
2081
2082         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2083                 DP(NETIF_MSG_LINK,
2084                    "Set GPIO %d (shift %d) -> input\n",
2085                    gpio_num, gpio_shift);
2086                 /* set FLOAT */
2087                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2088                 break;
2089
2090         default:
2091                 break;
2092         }
2093
2094         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2095         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2096
2097         return 0;
2098 }
2099
2100 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2101 {
2102         u32 gpio_reg = 0;
2103         int rc = 0;
2104
2105         /* Any port swapping should be handled by caller. */
2106
2107         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2108         /* read GPIO and mask except the float bits */
2109         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2110         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2111         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2112         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2113
2114         switch (mode) {
2115         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2116                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2117                 /* set CLR */
2118                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2119                 break;
2120
2121         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2122                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2123                 /* set SET */
2124                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2125                 break;
2126
2127         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2128                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2129                 /* set FLOAT */
2130                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2131                 break;
2132
2133         default:
2134                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2135                 rc = -EINVAL;
2136                 break;
2137         }
2138
2139         if (rc == 0)
2140                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2141
2142         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2143
2144         return rc;
2145 }
2146
2147 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2148 {
2149         /* The GPIO should be swapped if swap register is set and active */
2150         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2151                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2152         int gpio_shift = gpio_num +
2153                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2154         u32 gpio_mask = (1 << gpio_shift);
2155         u32 gpio_reg;
2156
2157         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2158                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2159                 return -EINVAL;
2160         }
2161
2162         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2163         /* read GPIO int */
2164         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2165
2166         switch (mode) {
2167         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2168                 DP(NETIF_MSG_LINK,
2169                    "Clear GPIO INT %d (shift %d) -> output low\n",
2170                    gpio_num, gpio_shift);
2171                 /* clear SET and set CLR */
2172                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2173                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2174                 break;
2175
2176         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2177                 DP(NETIF_MSG_LINK,
2178                    "Set GPIO INT %d (shift %d) -> output high\n",
2179                    gpio_num, gpio_shift);
2180                 /* clear CLR and set SET */
2181                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2182                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2183                 break;
2184
2185         default:
2186                 break;
2187         }
2188
2189         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2190         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2191
2192         return 0;
2193 }
2194
2195 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2196 {
2197         u32 spio_reg;
2198
2199         /* Only 2 SPIOs are configurable */
2200         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2201                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2202                 return -EINVAL;
2203         }
2204
2205         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2206         /* read SPIO and mask except the float bits */
2207         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2208
2209         switch (mode) {
2210         case MISC_SPIO_OUTPUT_LOW:
2211                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2212                 /* clear FLOAT and set CLR */
2213                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2214                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2215                 break;
2216
2217         case MISC_SPIO_OUTPUT_HIGH:
2218                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2219                 /* clear FLOAT and set SET */
2220                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2221                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2222                 break;
2223
2224         case MISC_SPIO_INPUT_HI_Z:
2225                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2226                 /* set FLOAT */
2227                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2228                 break;
2229
2230         default:
2231                 break;
2232         }
2233
2234         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2235         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2236
2237         return 0;
2238 }
2239
2240 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2241 {
2242         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2243         switch (bp->link_vars.ieee_fc &
2244                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2245         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2246                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2247                                                    ADVERTISED_Pause);
2248                 break;
2249
2250         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2251                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2252                                                   ADVERTISED_Pause);
2253                 break;
2254
2255         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2256                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2257                 break;
2258
2259         default:
2260                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2261                                                    ADVERTISED_Pause);
2262                 break;
2263         }
2264 }
2265
2266 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2267 {
2268         /* Initialize link parameters structure variables
2269          * It is recommended to turn off RX FC for jumbo frames
2270          *  for better performance
2271          */
2272         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2273                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2274         else
2275                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2276 }
2277
2278 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2279 {
2280         u32 pause_enabled = 0;
2281
2282         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2283                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2284                         pause_enabled = 1;
2285
2286                 REG_WR(bp, BAR_USTRORM_INTMEM +
2287                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2288                        pause_enabled);
2289         }
2290
2291         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2292            pause_enabled ? "enabled" : "disabled");
2293 }
2294
2295 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2296 {
2297         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2298         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2299
2300         if (!BP_NOMCP(bp)) {
2301                 bnx2x_set_requested_fc(bp);
2302                 bnx2x_acquire_phy_lock(bp);
2303
2304                 if (load_mode == LOAD_DIAG) {
2305                         struct link_params *lp = &bp->link_params;
2306                         lp->loopback_mode = LOOPBACK_XGXS;
2307                         /* do PHY loopback at 10G speed, if possible */
2308                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2309                                 if (lp->speed_cap_mask[cfx_idx] &
2310                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2311                                         lp->req_line_speed[cfx_idx] =
2312                                         SPEED_10000;
2313                                 else
2314                                         lp->req_line_speed[cfx_idx] =
2315                                         SPEED_1000;
2316                         }
2317                 }
2318
2319                 if (load_mode == LOAD_LOOPBACK_EXT) {
2320                         struct link_params *lp = &bp->link_params;
2321                         lp->loopback_mode = LOOPBACK_EXT;
2322                 }
2323
2324                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2325
2326                 bnx2x_release_phy_lock(bp);
2327
2328                 bnx2x_init_dropless_fc(bp);
2329
2330                 bnx2x_calc_fc_adv(bp);
2331
2332                 if (bp->link_vars.link_up) {
2333                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2334                         bnx2x_link_report(bp);
2335                 }
2336                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2337                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2338                 return rc;
2339         }
2340         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2341         return -EINVAL;
2342 }
2343
2344 void bnx2x_link_set(struct bnx2x *bp)
2345 {
2346         if (!BP_NOMCP(bp)) {
2347                 bnx2x_acquire_phy_lock(bp);
2348                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2349                 bnx2x_release_phy_lock(bp);
2350
2351                 bnx2x_init_dropless_fc(bp);
2352
2353                 bnx2x_calc_fc_adv(bp);
2354         } else
2355                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2356 }
2357
2358 static void bnx2x__link_reset(struct bnx2x *bp)
2359 {
2360         if (!BP_NOMCP(bp)) {
2361                 bnx2x_acquire_phy_lock(bp);
2362                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2363                 bnx2x_release_phy_lock(bp);
2364         } else
2365                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2366 }
2367
2368 void bnx2x_force_link_reset(struct bnx2x *bp)
2369 {
2370         bnx2x_acquire_phy_lock(bp);
2371         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2372         bnx2x_release_phy_lock(bp);
2373 }
2374
2375 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2376 {
2377         u8 rc = 0;
2378
2379         if (!BP_NOMCP(bp)) {
2380                 bnx2x_acquire_phy_lock(bp);
2381                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2382                                      is_serdes);
2383                 bnx2x_release_phy_lock(bp);
2384         } else
2385                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2386
2387         return rc;
2388 }
2389
2390 /* Calculates the sum of vn_min_rates.
2391    It's needed for further normalizing of the min_rates.
2392    Returns:
2393      sum of vn_min_rates.
2394        or
2395      0 - if all the min_rates are 0.
2396      In the later case fairness algorithm should be deactivated.
2397      If not all min_rates are zero then those that are zeroes will be set to 1.
2398  */
2399 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2400                                       struct cmng_init_input *input)
2401 {
2402         int all_zero = 1;
2403         int vn;
2404
2405         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2406                 u32 vn_cfg = bp->mf_config[vn];
2407                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2408                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2409
2410                 /* Skip hidden vns */
2411                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2412                         vn_min_rate = 0;
2413                 /* If min rate is zero - set it to 1 */
2414                 else if (!vn_min_rate)
2415                         vn_min_rate = DEF_MIN_RATE;
2416                 else
2417                         all_zero = 0;
2418
2419                 input->vnic_min_rate[vn] = vn_min_rate;
2420         }
2421
2422         /* if ETS or all min rates are zeros - disable fairness */
2423         if (BNX2X_IS_ETS_ENABLED(bp)) {
2424                 input->flags.cmng_enables &=
2425                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2426                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2427         } else if (all_zero) {
2428                 input->flags.cmng_enables &=
2429                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2430                 DP(NETIF_MSG_IFUP,
2431                    "All MIN values are zeroes fairness will be disabled\n");
2432         } else
2433                 input->flags.cmng_enables |=
2434                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2435 }
2436
2437 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2438                                     struct cmng_init_input *input)
2439 {
2440         u16 vn_max_rate;
2441         u32 vn_cfg = bp->mf_config[vn];
2442
2443         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2444                 vn_max_rate = 0;
2445         else {
2446                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2447
2448                 if (IS_MF_SI(bp)) {
2449                         /* maxCfg in percents of linkspeed */
2450                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2451                 } else /* SD modes */
2452                         /* maxCfg is absolute in 100Mb units */
2453                         vn_max_rate = maxCfg * 100;
2454         }
2455
2456         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2457
2458         input->vnic_max_rate[vn] = vn_max_rate;
2459 }
2460
2461 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2462 {
2463         if (CHIP_REV_IS_SLOW(bp))
2464                 return CMNG_FNS_NONE;
2465         if (IS_MF(bp))
2466                 return CMNG_FNS_MINMAX;
2467
2468         return CMNG_FNS_NONE;
2469 }
2470
2471 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2472 {
2473         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2474
2475         if (BP_NOMCP(bp))
2476                 return; /* what should be the default value in this case */
2477
2478         /* For 2 port configuration the absolute function number formula
2479          * is:
2480          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2481          *
2482          *      and there are 4 functions per port
2483          *
2484          * For 4 port configuration it is
2485          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2486          *
2487          *      and there are 2 functions per port
2488          */
2489         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2490                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2491
2492                 if (func >= E1H_FUNC_MAX)
2493                         break;
2494
2495                 bp->mf_config[vn] =
2496                         MF_CFG_RD(bp, func_mf_config[func].config);
2497         }
2498         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2499                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2500                 bp->flags |= MF_FUNC_DIS;
2501         } else {
2502                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2503                 bp->flags &= ~MF_FUNC_DIS;
2504         }
2505 }
2506
2507 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2508 {
2509         struct cmng_init_input input;
2510         memset(&input, 0, sizeof(struct cmng_init_input));
2511
2512         input.port_rate = bp->link_vars.line_speed;
2513
2514         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2515                 int vn;
2516
2517                 /* read mf conf from shmem */
2518                 if (read_cfg)
2519                         bnx2x_read_mf_cfg(bp);
2520
2521                 /* vn_weight_sum and enable fairness if not 0 */
2522                 bnx2x_calc_vn_min(bp, &input);
2523
2524                 /* calculate and set min-max rate for each vn */
2525                 if (bp->port.pmf)
2526                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2527                                 bnx2x_calc_vn_max(bp, vn, &input);
2528
2529                 /* always enable rate shaping and fairness */
2530                 input.flags.cmng_enables |=
2531                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2532
2533                 bnx2x_init_cmng(&input, &bp->cmng);
2534                 return;
2535         }
2536
2537         /* rate shaping and fairness are disabled */
2538         DP(NETIF_MSG_IFUP,
2539            "rate shaping and fairness are disabled\n");
2540 }
2541
2542 static void storm_memset_cmng(struct bnx2x *bp,
2543                               struct cmng_init *cmng,
2544                               u8 port)
2545 {
2546         int vn;
2547         size_t size = sizeof(struct cmng_struct_per_port);
2548
2549         u32 addr = BAR_XSTRORM_INTMEM +
2550                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2551
2552         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2553
2554         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2555                 int func = func_by_vn(bp, vn);
2556
2557                 addr = BAR_XSTRORM_INTMEM +
2558                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2559                 size = sizeof(struct rate_shaping_vars_per_vn);
2560                 __storm_memset_struct(bp, addr, size,
2561                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2562
2563                 addr = BAR_XSTRORM_INTMEM +
2564                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2565                 size = sizeof(struct fairness_vars_per_vn);
2566                 __storm_memset_struct(bp, addr, size,
2567                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2568         }
2569 }
2570
2571 /* init cmng mode in HW according to local configuration */
2572 void bnx2x_set_local_cmng(struct bnx2x *bp)
2573 {
2574         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2575
2576         if (cmng_fns != CMNG_FNS_NONE) {
2577                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2578                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2579         } else {
2580                 /* rate shaping and fairness are disabled */
2581                 DP(NETIF_MSG_IFUP,
2582                    "single function mode without fairness\n");
2583         }
2584 }
2585
2586 /* This function is called upon link interrupt */
2587 static void bnx2x_link_attn(struct bnx2x *bp)
2588 {
2589         /* Make sure that we are synced with the current statistics */
2590         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2591
2592         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2593
2594         bnx2x_init_dropless_fc(bp);
2595
2596         if (bp->link_vars.link_up) {
2597
2598                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2599                         struct host_port_stats *pstats;
2600
2601                         pstats = bnx2x_sp(bp, port_stats);
2602                         /* reset old mac stats */
2603                         memset(&(pstats->mac_stx[0]), 0,
2604                                sizeof(struct mac_stx));
2605                 }
2606                 if (bp->state == BNX2X_STATE_OPEN)
2607                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2608         }
2609
2610         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2611                 bnx2x_set_local_cmng(bp);
2612
2613         __bnx2x_link_report(bp);
2614
2615         if (IS_MF(bp))
2616                 bnx2x_link_sync_notify(bp);
2617 }
2618
2619 void bnx2x__link_status_update(struct bnx2x *bp)
2620 {
2621         if (bp->state != BNX2X_STATE_OPEN)
2622                 return;
2623
2624         /* read updated dcb configuration */
2625         if (IS_PF(bp)) {
2626                 bnx2x_dcbx_pmf_update(bp);
2627                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2628                 if (bp->link_vars.link_up)
2629                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2630                 else
2631                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2632                         /* indicate link status */
2633                 bnx2x_link_report(bp);
2634
2635         } else { /* VF */
2636                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2637                                           SUPPORTED_10baseT_Full |
2638                                           SUPPORTED_100baseT_Half |
2639                                           SUPPORTED_100baseT_Full |
2640                                           SUPPORTED_1000baseT_Full |
2641                                           SUPPORTED_2500baseX_Full |
2642                                           SUPPORTED_10000baseT_Full |
2643                                           SUPPORTED_TP |
2644                                           SUPPORTED_FIBRE |
2645                                           SUPPORTED_Autoneg |
2646                                           SUPPORTED_Pause |
2647                                           SUPPORTED_Asym_Pause);
2648                 bp->port.advertising[0] = bp->port.supported[0];
2649
2650                 bp->link_params.bp = bp;
2651                 bp->link_params.port = BP_PORT(bp);
2652                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2653                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2654                 bp->link_params.req_line_speed[0] = SPEED_10000;
2655                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2656                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2657                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2658                 bp->link_vars.line_speed = SPEED_10000;
2659                 bp->link_vars.link_status =
2660                         (LINK_STATUS_LINK_UP |
2661                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2662                 bp->link_vars.link_up = 1;
2663                 bp->link_vars.duplex = DUPLEX_FULL;
2664                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2665                 __bnx2x_link_report(bp);
2666                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2667         }
2668 }
2669
2670 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2671                                   u16 vlan_val, u8 allowed_prio)
2672 {
2673         struct bnx2x_func_state_params func_params = {NULL};
2674         struct bnx2x_func_afex_update_params *f_update_params =
2675                 &func_params.params.afex_update;
2676
2677         func_params.f_obj = &bp->func_obj;
2678         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2679
2680         /* no need to wait for RAMROD completion, so don't
2681          * set RAMROD_COMP_WAIT flag
2682          */
2683
2684         f_update_params->vif_id = vifid;
2685         f_update_params->afex_default_vlan = vlan_val;
2686         f_update_params->allowed_priorities = allowed_prio;
2687
2688         /* if ramrod can not be sent, response to MCP immediately */
2689         if (bnx2x_func_state_change(bp, &func_params) < 0)
2690                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2691
2692         return 0;
2693 }
2694
2695 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2696                                           u16 vif_index, u8 func_bit_map)
2697 {
2698         struct bnx2x_func_state_params func_params = {NULL};
2699         struct bnx2x_func_afex_viflists_params *update_params =
2700                 &func_params.params.afex_viflists;
2701         int rc;
2702         u32 drv_msg_code;
2703
2704         /* validate only LIST_SET and LIST_GET are received from switch */
2705         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2706                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2707                           cmd_type);
2708
2709         func_params.f_obj = &bp->func_obj;
2710         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2711
2712         /* set parameters according to cmd_type */
2713         update_params->afex_vif_list_command = cmd_type;
2714         update_params->vif_list_index = vif_index;
2715         update_params->func_bit_map =
2716                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2717         update_params->func_to_clear = 0;
2718         drv_msg_code =
2719                 (cmd_type == VIF_LIST_RULE_GET) ?
2720                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2721                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2722
2723         /* if ramrod can not be sent, respond to MCP immediately for
2724          * SET and GET requests (other are not triggered from MCP)
2725          */
2726         rc = bnx2x_func_state_change(bp, &func_params);
2727         if (rc < 0)
2728                 bnx2x_fw_command(bp, drv_msg_code, 0);
2729
2730         return 0;
2731 }
2732
2733 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2734 {
2735         struct afex_stats afex_stats;
2736         u32 func = BP_ABS_FUNC(bp);
2737         u32 mf_config;
2738         u16 vlan_val;
2739         u32 vlan_prio;
2740         u16 vif_id;
2741         u8 allowed_prio;
2742         u8 vlan_mode;
2743         u32 addr_to_write, vifid, addrs, stats_type, i;
2744
2745         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2746                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2747                 DP(BNX2X_MSG_MCP,
2748                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2749                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2750         }
2751
2752         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2753                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2754                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2755                 DP(BNX2X_MSG_MCP,
2756                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2757                    vifid, addrs);
2758                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2759                                                addrs);
2760         }
2761
2762         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2763                 addr_to_write = SHMEM2_RD(bp,
2764                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2765                 stats_type = SHMEM2_RD(bp,
2766                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2767
2768                 DP(BNX2X_MSG_MCP,
2769                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2770                    addr_to_write);
2771
2772                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2773
2774                 /* write response to scratchpad, for MCP */
2775                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2776                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2777                                *(((u32 *)(&afex_stats))+i));
2778
2779                 /* send ack message to MCP */
2780                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2781         }
2782
2783         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2784                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2785                 bp->mf_config[BP_VN(bp)] = mf_config;
2786                 DP(BNX2X_MSG_MCP,
2787                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2788                    mf_config);
2789
2790                 /* if VIF_SET is "enabled" */
2791                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2792                         /* set rate limit directly to internal RAM */
2793                         struct cmng_init_input cmng_input;
2794                         struct rate_shaping_vars_per_vn m_rs_vn;
2795                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2796                         u32 addr = BAR_XSTRORM_INTMEM +
2797                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2798
2799                         bp->mf_config[BP_VN(bp)] = mf_config;
2800
2801                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2802                         m_rs_vn.vn_counter.rate =
2803                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2804                         m_rs_vn.vn_counter.quota =
2805                                 (m_rs_vn.vn_counter.rate *
2806                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2807
2808                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2809
2810                         /* read relevant values from mf_cfg struct in shmem */
2811                         vif_id =
2812                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2813                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2814                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2815                         vlan_val =
2816                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2817                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2818                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2819                         vlan_prio = (mf_config &
2820                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2821                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2822                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2823                         vlan_mode =
2824                                 (MF_CFG_RD(bp,
2825                                            func_mf_config[func].afex_config) &
2826                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2827                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2828                         allowed_prio =
2829                                 (MF_CFG_RD(bp,
2830                                            func_mf_config[func].afex_config) &
2831                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2832                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2833
2834                         /* send ramrod to FW, return in case of failure */
2835                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2836                                                    allowed_prio))
2837                                 return;
2838
2839                         bp->afex_def_vlan_tag = vlan_val;
2840                         bp->afex_vlan_mode = vlan_mode;
2841                 } else {
2842                         /* notify link down because BP->flags is disabled */
2843                         bnx2x_link_report(bp);
2844
2845                         /* send INVALID VIF ramrod to FW */
2846                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2847
2848                         /* Reset the default afex VLAN */
2849                         bp->afex_def_vlan_tag = -1;
2850                 }
2851         }
2852 }
2853
2854 static void bnx2x_pmf_update(struct bnx2x *bp)
2855 {
2856         int port = BP_PORT(bp);
2857         u32 val;
2858
2859         bp->port.pmf = 1;
2860         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2861
2862         /*
2863          * We need the mb() to ensure the ordering between the writing to
2864          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2865          */
2866         smp_mb();
2867
2868         /* queue a periodic task */
2869         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2870
2871         bnx2x_dcbx_pmf_update(bp);
2872
2873         /* enable nig attention */
2874         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2875         if (bp->common.int_block == INT_BLOCK_HC) {
2876                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2877                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2878         } else if (!CHIP_IS_E1x(bp)) {
2879                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2880                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2881         }
2882
2883         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2884 }
2885
2886 /* end of Link */
2887
2888 /* slow path */
2889
2890 /*
2891  * General service functions
2892  */
2893
2894 /* send the MCP a request, block until there is a reply */
2895 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2896 {
2897         int mb_idx = BP_FW_MB_IDX(bp);
2898         u32 seq;
2899         u32 rc = 0;
2900         u32 cnt = 1;
2901         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2902
2903         mutex_lock(&bp->fw_mb_mutex);
2904         seq = ++bp->fw_seq;
2905         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2906         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2907
2908         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2909                         (command | seq), param);
2910
2911         do {
2912                 /* let the FW do it's magic ... */
2913                 msleep(delay);
2914
2915                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2916
2917                 /* Give the FW up to 5 second (500*10ms) */
2918         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2919
2920         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2921            cnt*delay, rc, seq);
2922
2923         /* is this a reply to our command? */
2924         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2925                 rc &= FW_MSG_CODE_MASK;
2926         else {
2927                 /* FW BUG! */
2928                 BNX2X_ERR("FW failed to respond!\n");
2929                 bnx2x_fw_dump(bp);
2930                 rc = 0;
2931         }
2932         mutex_unlock(&bp->fw_mb_mutex);
2933
2934         return rc;
2935 }
2936
2937 static void storm_memset_func_cfg(struct bnx2x *bp,
2938                                  struct tstorm_eth_function_common_config *tcfg,
2939                                  u16 abs_fid)
2940 {
2941         size_t size = sizeof(struct tstorm_eth_function_common_config);
2942
2943         u32 addr = BAR_TSTRORM_INTMEM +
2944                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2945
2946         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2947 }
2948
2949 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2950 {
2951         if (CHIP_IS_E1x(bp)) {
2952                 struct tstorm_eth_function_common_config tcfg = {0};
2953
2954                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2955         }
2956
2957         /* Enable the function in the FW */
2958         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2959         storm_memset_func_en(bp, p->func_id, 1);
2960
2961         /* spq */
2962         if (p->func_flgs & FUNC_FLG_SPQ) {
2963                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2964                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2965                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2966         }
2967 }
2968
2969 /**
2970  * bnx2x_get_common_flags - Return common flags
2971  *
2972  * @bp          device handle
2973  * @fp          queue handle
2974  * @zero_stats  TRUE if statistics zeroing is needed
2975  *
2976  * Return the flags that are common for the Tx-only and not normal connections.
2977  */
2978 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2979                                             struct bnx2x_fastpath *fp,
2980                                             bool zero_stats)
2981 {
2982         unsigned long flags = 0;
2983
2984         /* PF driver will always initialize the Queue to an ACTIVE state */
2985         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2986
2987         /* tx only connections collect statistics (on the same index as the
2988          * parent connection). The statistics are zeroed when the parent
2989          * connection is initialized.
2990          */
2991
2992         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2993         if (zero_stats)
2994                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2995
2996         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
2997         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
2998
2999 #ifdef BNX2X_STOP_ON_ERROR
3000         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3001 #endif
3002
3003         return flags;
3004 }
3005
3006 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3007                                        struct bnx2x_fastpath *fp,
3008                                        bool leading)
3009 {
3010         unsigned long flags = 0;
3011
3012         /* calculate other queue flags */
3013         if (IS_MF_SD(bp))
3014                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3015
3016         if (IS_FCOE_FP(fp)) {
3017                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3018                 /* For FCoE - force usage of default priority (for afex) */
3019                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3020         }
3021
3022         if (!fp->disable_tpa) {
3023                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3024                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3025                 if (fp->mode == TPA_MODE_GRO)
3026                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3027         }
3028
3029         if (leading) {
3030                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3031                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3032         }
3033
3034         /* Always set HW VLAN stripping */
3035         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3036
3037         /* configure silent vlan removal */
3038         if (IS_MF_AFEX(bp))
3039                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3040
3041         return flags | bnx2x_get_common_flags(bp, fp, true);
3042 }
3043
3044 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3045         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3046         u8 cos)
3047 {
3048         gen_init->stat_id = bnx2x_stats_id(fp);
3049         gen_init->spcl_id = fp->cl_id;
3050
3051         /* Always use mini-jumbo MTU for FCoE L2 ring */
3052         if (IS_FCOE_FP(fp))
3053                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3054         else
3055                 gen_init->mtu = bp->dev->mtu;
3056
3057         gen_init->cos = cos;
3058 }
3059
3060 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3061         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3062         struct bnx2x_rxq_setup_params *rxq_init)
3063 {
3064         u8 max_sge = 0;
3065         u16 sge_sz = 0;
3066         u16 tpa_agg_size = 0;
3067
3068         if (!fp->disable_tpa) {
3069                 pause->sge_th_lo = SGE_TH_LO(bp);
3070                 pause->sge_th_hi = SGE_TH_HI(bp);
3071
3072                 /* validate SGE ring has enough to cross high threshold */
3073                 WARN_ON(bp->dropless_fc &&
3074                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3075                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3076
3077                 tpa_agg_size = TPA_AGG_SIZE;
3078                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3079                         SGE_PAGE_SHIFT;
3080                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3081                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3082                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3083         }
3084
3085         /* pause - not for e1 */
3086         if (!CHIP_IS_E1(bp)) {
3087                 pause->bd_th_lo = BD_TH_LO(bp);
3088                 pause->bd_th_hi = BD_TH_HI(bp);
3089
3090                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3091                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3092                 /*
3093                  * validate that rings have enough entries to cross
3094                  * high thresholds
3095                  */
3096                 WARN_ON(bp->dropless_fc &&
3097                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3098                                 bp->rx_ring_size);
3099                 WARN_ON(bp->dropless_fc &&
3100                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3101                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3102
3103                 pause->pri_map = 1;
3104         }
3105
3106         /* rxq setup */
3107         rxq_init->dscr_map = fp->rx_desc_mapping;
3108         rxq_init->sge_map = fp->rx_sge_mapping;
3109         rxq_init->rcq_map = fp->rx_comp_mapping;
3110         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3111
3112         /* This should be a maximum number of data bytes that may be
3113          * placed on the BD (not including paddings).
3114          */
3115         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3116                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3117
3118         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3119         rxq_init->tpa_agg_sz = tpa_agg_size;
3120         rxq_init->sge_buf_sz = sge_sz;
3121         rxq_init->max_sges_pkt = max_sge;
3122         rxq_init->rss_engine_id = BP_FUNC(bp);
3123         rxq_init->mcast_engine_id = BP_FUNC(bp);
3124
3125         /* Maximum number or simultaneous TPA aggregation for this Queue.
3126          *
3127          * For PF Clients it should be the maximum available number.
3128          * VF driver(s) may want to define it to a smaller value.
3129          */
3130         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3131
3132         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3133         rxq_init->fw_sb_id = fp->fw_sb_id;
3134
3135         if (IS_FCOE_FP(fp))
3136                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3137         else
3138                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3139         /* configure silent vlan removal
3140          * if multi function mode is afex, then mask default vlan
3141          */
3142         if (IS_MF_AFEX(bp)) {
3143                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3144                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3145         }
3146 }
3147
3148 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3149         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3150         u8 cos)
3151 {
3152         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3153         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3154         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3155         txq_init->fw_sb_id = fp->fw_sb_id;
3156
3157         /*
3158          * set the tss leading client id for TX classification ==
3159          * leading RSS client id
3160          */
3161         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3162
3163         if (IS_FCOE_FP(fp)) {
3164                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3165                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3166         }
3167 }
3168
3169 static void bnx2x_pf_init(struct bnx2x *bp)
3170 {
3171         struct bnx2x_func_init_params func_init = {0};
3172         struct event_ring_data eq_data = { {0} };
3173         u16 flags;
3174
3175         if (!CHIP_IS_E1x(bp)) {
3176                 /* reset IGU PF statistics: MSIX + ATTN */
3177                 /* PF */
3178                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3179                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3180                            (CHIP_MODE_IS_4_PORT(bp) ?
3181                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3182                 /* ATTN */
3183                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3184                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3185                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3186                            (CHIP_MODE_IS_4_PORT(bp) ?
3187                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3188         }
3189
3190         /* function setup flags */
3191         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3192
3193         /* This flag is relevant for E1x only.
3194          * E2 doesn't have a TPA configuration in a function level.
3195          */
3196         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3197
3198         func_init.func_flgs = flags;
3199         func_init.pf_id = BP_FUNC(bp);
3200         func_init.func_id = BP_FUNC(bp);
3201         func_init.spq_map = bp->spq_mapping;
3202         func_init.spq_prod = bp->spq_prod_idx;
3203
3204         bnx2x_func_init(bp, &func_init);
3205
3206         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3207
3208         /*
3209          * Congestion management values depend on the link rate
3210          * There is no active link so initial link rate is set to 10 Gbps.
3211          * When the link comes up The congestion management values are
3212          * re-calculated according to the actual link rate.
3213          */
3214         bp->link_vars.line_speed = SPEED_10000;
3215         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3216
3217         /* Only the PMF sets the HW */
3218         if (bp->port.pmf)
3219                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3220
3221         /* init Event Queue - PCI bus guarantees correct endianity*/
3222         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3223         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3224         eq_data.producer = bp->eq_prod;
3225         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3226         eq_data.sb_id = DEF_SB_ID;
3227         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3228 }
3229
3230 static void bnx2x_e1h_disable(struct bnx2x *bp)
3231 {
3232         int port = BP_PORT(bp);
3233
3234         bnx2x_tx_disable(bp);
3235
3236         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3237 }
3238
3239 static void bnx2x_e1h_enable(struct bnx2x *bp)
3240 {
3241         int port = BP_PORT(bp);
3242
3243         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3244
3245         /* Tx queue should be only re-enabled */
3246         netif_tx_wake_all_queues(bp->dev);
3247
3248         /*
3249          * Should not call netif_carrier_on since it will be called if the link
3250          * is up when checking for link state
3251          */
3252 }
3253
3254 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3255
3256 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3257 {
3258         struct eth_stats_info *ether_stat =
3259                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3260         struct bnx2x_vlan_mac_obj *mac_obj =
3261                 &bp->sp_objs->mac_obj;
3262         int i;
3263
3264         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3265                 ETH_STAT_INFO_VERSION_LEN);
3266
3267         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3268          * mac_local field in ether_stat struct. The base address is offset by 2
3269          * bytes to account for the field being 8 bytes but a mac address is
3270          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3271          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3272          * allocated by the ether_stat struct, so the macs will land in their
3273          * proper positions.
3274          */
3275         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3276                 memset(ether_stat->mac_local + i, 0,
3277                        sizeof(ether_stat->mac_local[0]));
3278         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3279                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3280                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3281                                 ETH_ALEN);
3282         ether_stat->mtu_size = bp->dev->mtu;
3283         if (bp->dev->features & NETIF_F_RXCSUM)
3284                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3285         if (bp->dev->features & NETIF_F_TSO)
3286                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3287         ether_stat->feature_flags |= bp->common.boot_mode;
3288
3289         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3290
3291         ether_stat->txq_size = bp->tx_ring_size;
3292         ether_stat->rxq_size = bp->rx_ring_size;
3293 }
3294
3295 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3296 {
3297         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3298         struct fcoe_stats_info *fcoe_stat =
3299                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3300
3301         if (!CNIC_LOADED(bp))
3302                 return;
3303
3304         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3305
3306         fcoe_stat->qos_priority =
3307                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3308
3309         /* insert FCoE stats from ramrod response */
3310         if (!NO_FCOE(bp)) {
3311                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3312                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3313                         tstorm_queue_statistics;
3314
3315                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3316                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3317                         xstorm_queue_statistics;
3318
3319                 struct fcoe_statistics_params *fw_fcoe_stat =
3320                         &bp->fw_stats_data->fcoe;
3321
3322                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3323                           fcoe_stat->rx_bytes_lo,
3324                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3325
3326                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3327                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3328                           fcoe_stat->rx_bytes_lo,
3329                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3330
3331                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3332                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3333                           fcoe_stat->rx_bytes_lo,
3334                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3335
3336                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3337                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3338                           fcoe_stat->rx_bytes_lo,
3339                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3340
3341                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3342                           fcoe_stat->rx_frames_lo,
3343                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3344
3345                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3346                           fcoe_stat->rx_frames_lo,
3347                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3348
3349                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3350                           fcoe_stat->rx_frames_lo,
3351                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3352
3353                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3354                           fcoe_stat->rx_frames_lo,
3355                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3356
3357                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3358                           fcoe_stat->tx_bytes_lo,
3359                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3360
3361                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3362                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3363                           fcoe_stat->tx_bytes_lo,
3364                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3365
3366                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3367                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3368                           fcoe_stat->tx_bytes_lo,
3369                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3370
3371                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3372                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3373                           fcoe_stat->tx_bytes_lo,
3374                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3375
3376                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3377                           fcoe_stat->tx_frames_lo,
3378                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3379
3380                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3381                           fcoe_stat->tx_frames_lo,
3382                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3383
3384                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3385                           fcoe_stat->tx_frames_lo,
3386                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3387
3388                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3389                           fcoe_stat->tx_frames_lo,
3390                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3391         }
3392
3393         /* ask L5 driver to add data to the struct */
3394         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3395 }
3396
3397 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3398 {
3399         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3400         struct iscsi_stats_info *iscsi_stat =
3401                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3402
3403         if (!CNIC_LOADED(bp))
3404                 return;
3405
3406         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3407                ETH_ALEN);
3408
3409         iscsi_stat->qos_priority =
3410                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3411
3412         /* ask L5 driver to add data to the struct */
3413         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3414 }
3415
3416 /* called due to MCP event (on pmf):
3417  *      reread new bandwidth configuration
3418  *      configure FW
3419  *      notify others function about the change
3420  */
3421 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3422 {
3423         if (bp->link_vars.link_up) {
3424                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3425                 bnx2x_link_sync_notify(bp);
3426         }
3427         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3428 }
3429
3430 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3431 {
3432         bnx2x_config_mf_bw(bp);
3433         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3434 }
3435
3436 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3437 {
3438         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3439         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3440 }
3441
3442 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3443 {
3444         enum drv_info_opcode op_code;
3445         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3446
3447         /* if drv_info version supported by MFW doesn't match - send NACK */
3448         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3449                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3450                 return;
3451         }
3452
3453         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3454                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3455
3456         memset(&bp->slowpath->drv_info_to_mcp, 0,
3457                sizeof(union drv_info_to_mcp));
3458
3459         switch (op_code) {
3460         case ETH_STATS_OPCODE:
3461                 bnx2x_drv_info_ether_stat(bp);
3462                 break;
3463         case FCOE_STATS_OPCODE:
3464                 bnx2x_drv_info_fcoe_stat(bp);
3465                 break;
3466         case ISCSI_STATS_OPCODE:
3467                 bnx2x_drv_info_iscsi_stat(bp);
3468                 break;
3469         default:
3470                 /* if op code isn't supported - send NACK */
3471                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3472                 return;
3473         }
3474
3475         /* if we got drv_info attn from MFW then these fields are defined in
3476          * shmem2 for sure
3477          */
3478         SHMEM2_WR(bp, drv_info_host_addr_lo,
3479                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3480         SHMEM2_WR(bp, drv_info_host_addr_hi,
3481                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3482
3483         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3484 }
3485
3486 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3487 {
3488         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3489
3490         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3491
3492                 /*
3493                  * This is the only place besides the function initialization
3494                  * where the bp->flags can change so it is done without any
3495                  * locks
3496                  */
3497                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3498                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3499                         bp->flags |= MF_FUNC_DIS;
3500
3501                         bnx2x_e1h_disable(bp);
3502                 } else {
3503                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3504                         bp->flags &= ~MF_FUNC_DIS;
3505
3506                         bnx2x_e1h_enable(bp);
3507                 }
3508                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3509         }
3510         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3511                 bnx2x_config_mf_bw(bp);
3512                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3513         }
3514
3515         /* Report results to MCP */
3516         if (dcc_event)
3517                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3518         else
3519                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3520 }
3521
3522 /* must be called under the spq lock */
3523 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3524 {
3525         struct eth_spe *next_spe = bp->spq_prod_bd;
3526
3527         if (bp->spq_prod_bd == bp->spq_last_bd) {
3528                 bp->spq_prod_bd = bp->spq;
3529                 bp->spq_prod_idx = 0;
3530                 DP(BNX2X_MSG_SP, "end of spq\n");
3531         } else {
3532                 bp->spq_prod_bd++;
3533                 bp->spq_prod_idx++;
3534         }
3535         return next_spe;
3536 }
3537
3538 /* must be called under the spq lock */
3539 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3540 {
3541         int func = BP_FUNC(bp);
3542
3543         /*
3544          * Make sure that BD data is updated before writing the producer:
3545          * BD data is written to the memory, the producer is read from the
3546          * memory, thus we need a full memory barrier to ensure the ordering.
3547          */
3548         mb();
3549
3550         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3551                  bp->spq_prod_idx);
3552         mmiowb();
3553 }
3554
3555 /**
3556  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3557  *
3558  * @cmd:        command to check
3559  * @cmd_type:   command type
3560  */
3561 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3562 {
3563         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3564             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3565             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3566             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3567             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3568             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3569             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3570                 return true;
3571         else
3572                 return false;
3573 }
3574
3575 /**
3576  * bnx2x_sp_post - place a single command on an SP ring
3577  *
3578  * @bp:         driver handle
3579  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3580  * @cid:        SW CID the command is related to
3581  * @data_hi:    command private data address (high 32 bits)
3582  * @data_lo:    command private data address (low 32 bits)
3583  * @cmd_type:   command type (e.g. NONE, ETH)
3584  *
3585  * SP data is handled as if it's always an address pair, thus data fields are
3586  * not swapped to little endian in upper functions. Instead this function swaps
3587  * data as if it's two u32 fields.
3588  */
3589 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3590                   u32 data_hi, u32 data_lo, int cmd_type)
3591 {
3592         struct eth_spe *spe;
3593         u16 type;
3594         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3595
3596 #ifdef BNX2X_STOP_ON_ERROR
3597         if (unlikely(bp->panic)) {
3598                 BNX2X_ERR("Can't post SP when there is panic\n");
3599                 return -EIO;
3600         }
3601 #endif
3602
3603         spin_lock_bh(&bp->spq_lock);
3604
3605         if (common) {
3606                 if (!atomic_read(&bp->eq_spq_left)) {
3607                         BNX2X_ERR("BUG! EQ ring full!\n");
3608                         spin_unlock_bh(&bp->spq_lock);
3609                         bnx2x_panic();
3610                         return -EBUSY;
3611                 }
3612         } else if (!atomic_read(&bp->cq_spq_left)) {
3613                         BNX2X_ERR("BUG! SPQ ring full!\n");
3614                         spin_unlock_bh(&bp->spq_lock);
3615                         bnx2x_panic();
3616                         return -EBUSY;
3617         }
3618
3619         spe = bnx2x_sp_get_next(bp);
3620
3621         /* CID needs port number to be encoded int it */
3622         spe->hdr.conn_and_cmd_data =
3623                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3624                                     HW_CID(bp, cid));
3625
3626         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3627
3628         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3629                  SPE_HDR_FUNCTION_ID);
3630
3631         spe->hdr.type = cpu_to_le16(type);
3632
3633         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3634         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3635
3636         /*
3637          * It's ok if the actual decrement is issued towards the memory
3638          * somewhere between the spin_lock and spin_unlock. Thus no
3639          * more explicit memory barrier is needed.
3640          */
3641         if (common)
3642                 atomic_dec(&bp->eq_spq_left);
3643         else
3644                 atomic_dec(&bp->cq_spq_left);
3645
3646         DP(BNX2X_MSG_SP,
3647            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3648            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3649            (u32)(U64_LO(bp->spq_mapping) +
3650            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3651            HW_CID(bp, cid), data_hi, data_lo, type,
3652            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3653
3654         bnx2x_sp_prod_update(bp);
3655         spin_unlock_bh(&bp->spq_lock);
3656         return 0;
3657 }
3658
3659 /* acquire split MCP access lock register */
3660 static int bnx2x_acquire_alr(struct bnx2x *bp)
3661 {
3662         u32 j, val;
3663         int rc = 0;
3664
3665         might_sleep();
3666         for (j = 0; j < 1000; j++) {
3667                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3668                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3669                 if (val & MCPR_ACCESS_LOCK_LOCK)
3670                         break;
3671
3672                 usleep_range(5000, 10000);
3673         }
3674         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3675                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3676                 rc = -EBUSY;
3677         }
3678
3679         return rc;
3680 }
3681
3682 /* release split MCP access lock register */
3683 static void bnx2x_release_alr(struct bnx2x *bp)
3684 {
3685         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3686 }
3687
3688 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3689 #define BNX2X_DEF_SB_IDX        0x0002
3690
3691 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3692 {
3693         struct host_sp_status_block *def_sb = bp->def_status_blk;
3694         u16 rc = 0;
3695
3696         barrier(); /* status block is written to by the chip */
3697         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3698                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3699                 rc |= BNX2X_DEF_SB_ATT_IDX;
3700         }
3701
3702         if (bp->def_idx != def_sb->sp_sb.running_index) {
3703                 bp->def_idx = def_sb->sp_sb.running_index;
3704                 rc |= BNX2X_DEF_SB_IDX;
3705         }
3706
3707         /* Do not reorder: indices reading should complete before handling */
3708         barrier();
3709         return rc;
3710 }
3711
3712 /*
3713  * slow path service functions
3714  */
3715
3716 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3717 {
3718         int port = BP_PORT(bp);
3719         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3720                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3721         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3722                                        NIG_REG_MASK_INTERRUPT_PORT0;
3723         u32 aeu_mask;
3724         u32 nig_mask = 0;
3725         u32 reg_addr;
3726
3727         if (bp->attn_state & asserted)
3728                 BNX2X_ERR("IGU ERROR\n");
3729
3730         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3731         aeu_mask = REG_RD(bp, aeu_addr);
3732
3733         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3734            aeu_mask, asserted);
3735         aeu_mask &= ~(asserted & 0x3ff);
3736         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3737
3738         REG_WR(bp, aeu_addr, aeu_mask);
3739         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3740
3741         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3742         bp->attn_state |= asserted;
3743         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3744
3745         if (asserted & ATTN_HARD_WIRED_MASK) {
3746                 if (asserted & ATTN_NIG_FOR_FUNC) {
3747
3748                         bnx2x_acquire_phy_lock(bp);
3749
3750                         /* save nig interrupt mask */
3751                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3752
3753                         /* If nig_mask is not set, no need to call the update
3754                          * function.
3755                          */
3756                         if (nig_mask) {
3757                                 REG_WR(bp, nig_int_mask_addr, 0);
3758
3759                                 bnx2x_link_attn(bp);
3760                         }
3761
3762                         /* handle unicore attn? */
3763                 }
3764                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3765                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3766
3767                 if (asserted & GPIO_2_FUNC)
3768                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3769
3770                 if (asserted & GPIO_3_FUNC)
3771                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3772
3773                 if (asserted & GPIO_4_FUNC)
3774                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3775
3776                 if (port == 0) {
3777                         if (asserted & ATTN_GENERAL_ATTN_1) {
3778                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3779                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3780                         }
3781                         if (asserted & ATTN_GENERAL_ATTN_2) {
3782                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3783                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3784                         }
3785                         if (asserted & ATTN_GENERAL_ATTN_3) {
3786                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3787                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3788                         }
3789                 } else {
3790                         if (asserted & ATTN_GENERAL_ATTN_4) {
3791                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3792                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3793                         }
3794                         if (asserted & ATTN_GENERAL_ATTN_5) {
3795                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3796                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3797                         }
3798                         if (asserted & ATTN_GENERAL_ATTN_6) {
3799                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3800                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3801                         }
3802                 }
3803
3804         } /* if hardwired */
3805
3806         if (bp->common.int_block == INT_BLOCK_HC)
3807                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3808                             COMMAND_REG_ATTN_BITS_SET);
3809         else
3810                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3811
3812         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3813            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3814         REG_WR(bp, reg_addr, asserted);
3815
3816         /* now set back the mask */
3817         if (asserted & ATTN_NIG_FOR_FUNC) {
3818                 /* Verify that IGU ack through BAR was written before restoring
3819                  * NIG mask. This loop should exit after 2-3 iterations max.
3820                  */
3821                 if (bp->common.int_block != INT_BLOCK_HC) {
3822                         u32 cnt = 0, igu_acked;
3823                         do {
3824                                 igu_acked = REG_RD(bp,
3825                                                    IGU_REG_ATTENTION_ACK_BITS);
3826                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3827                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3828                         if (!igu_acked)
3829                                 DP(NETIF_MSG_HW,
3830                                    "Failed to verify IGU ack on time\n");
3831                         barrier();
3832                 }
3833                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3834                 bnx2x_release_phy_lock(bp);
3835         }
3836 }
3837
3838 static void bnx2x_fan_failure(struct bnx2x *bp)
3839 {
3840         int port = BP_PORT(bp);
3841         u32 ext_phy_config;
3842         /* mark the failure */
3843         ext_phy_config =
3844                 SHMEM_RD(bp,
3845                          dev_info.port_hw_config[port].external_phy_config);
3846
3847         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3848         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3849         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3850                  ext_phy_config);
3851
3852         /* log the failure */
3853         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3854                             "Please contact OEM Support for assistance\n");
3855
3856         /* Schedule device reset (unload)
3857          * This is due to some boards consuming sufficient power when driver is
3858          * up to overheat if fan fails.
3859          */
3860         smp_mb__before_clear_bit();
3861         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3862         smp_mb__after_clear_bit();
3863         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3864 }
3865
3866 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3867 {
3868         int port = BP_PORT(bp);
3869         int reg_offset;
3870         u32 val;
3871
3872         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3873                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3874
3875         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3876
3877                 val = REG_RD(bp, reg_offset);
3878                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3879                 REG_WR(bp, reg_offset, val);
3880
3881                 BNX2X_ERR("SPIO5 hw attention\n");
3882
3883                 /* Fan failure attention */
3884                 bnx2x_hw_reset_phy(&bp->link_params);
3885                 bnx2x_fan_failure(bp);
3886         }
3887
3888         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3889                 bnx2x_acquire_phy_lock(bp);
3890                 bnx2x_handle_module_detect_int(&bp->link_params);
3891                 bnx2x_release_phy_lock(bp);
3892         }
3893
3894         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3895
3896                 val = REG_RD(bp, reg_offset);
3897                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3898                 REG_WR(bp, reg_offset, val);
3899
3900                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3901                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3902                 bnx2x_panic();
3903         }
3904 }
3905
3906 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3907 {
3908         u32 val;
3909
3910         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3911
3912                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3913                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3914                 /* DORQ discard attention */
3915                 if (val & 0x2)
3916                         BNX2X_ERR("FATAL error from DORQ\n");
3917         }
3918
3919         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3920
3921                 int port = BP_PORT(bp);
3922                 int reg_offset;
3923
3924                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3925                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3926
3927                 val = REG_RD(bp, reg_offset);
3928                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3929                 REG_WR(bp, reg_offset, val);
3930
3931                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3932                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3933                 bnx2x_panic();
3934         }
3935 }
3936
3937 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3938 {
3939         u32 val;
3940
3941         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3942
3943                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3944                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3945                 /* CFC error attention */
3946                 if (val & 0x2)
3947                         BNX2X_ERR("FATAL error from CFC\n");
3948         }
3949
3950         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3951                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3952                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3953                 /* RQ_USDMDP_FIFO_OVERFLOW */
3954                 if (val & 0x18000)
3955                         BNX2X_ERR("FATAL error from PXP\n");
3956
3957                 if (!CHIP_IS_E1x(bp)) {
3958                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3959                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3960                 }
3961         }
3962
3963         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3964
3965                 int port = BP_PORT(bp);
3966                 int reg_offset;
3967
3968                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3969                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3970
3971                 val = REG_RD(bp, reg_offset);
3972                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3973                 REG_WR(bp, reg_offset, val);
3974
3975                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3976                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3977                 bnx2x_panic();
3978         }
3979 }
3980
3981 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3982 {
3983         u32 val;
3984
3985         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3986
3987                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3988                         int func = BP_FUNC(bp);
3989
3990                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3991                         bnx2x_read_mf_cfg(bp);
3992                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3993                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3994                         val = SHMEM_RD(bp,
3995                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3996                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3997                                 bnx2x_dcc_event(bp,
3998                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3999
4000                         if (val & DRV_STATUS_SET_MF_BW)
4001                                 bnx2x_set_mf_bw(bp);
4002
4003                         if (val & DRV_STATUS_DRV_INFO_REQ)
4004                                 bnx2x_handle_drv_info_req(bp);
4005
4006                         if (val & DRV_STATUS_VF_DISABLED)
4007                                 bnx2x_vf_handle_flr_event(bp);
4008
4009                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4010                                 bnx2x_pmf_update(bp);
4011
4012                         if (bp->port.pmf &&
4013                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4014                                 bp->dcbx_enabled > 0)
4015                                 /* start dcbx state machine */
4016                                 bnx2x_dcbx_set_params(bp,
4017                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4018                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4019                                 bnx2x_handle_afex_cmd(bp,
4020                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4021                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4022                                 bnx2x_handle_eee_event(bp);
4023                         if (bp->link_vars.periodic_flags &
4024                             PERIODIC_FLAGS_LINK_EVENT) {
4025                                 /*  sync with link */
4026                                 bnx2x_acquire_phy_lock(bp);
4027                                 bp->link_vars.periodic_flags &=
4028                                         ~PERIODIC_FLAGS_LINK_EVENT;
4029                                 bnx2x_release_phy_lock(bp);
4030                                 if (IS_MF(bp))
4031                                         bnx2x_link_sync_notify(bp);
4032                                 bnx2x_link_report(bp);
4033                         }
4034                         /* Always call it here: bnx2x_link_report() will
4035                          * prevent the link indication duplication.
4036                          */
4037                         bnx2x__link_status_update(bp);
4038                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4039
4040                         BNX2X_ERR("MC assert!\n");
4041                         bnx2x_mc_assert(bp);
4042                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4043                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4044                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4045                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4046                         bnx2x_panic();
4047
4048                 } else if (attn & BNX2X_MCP_ASSERT) {
4049
4050                         BNX2X_ERR("MCP assert!\n");
4051                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4052                         bnx2x_fw_dump(bp);
4053
4054                 } else
4055                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4056         }
4057
4058         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4059                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4060                 if (attn & BNX2X_GRC_TIMEOUT) {
4061                         val = CHIP_IS_E1(bp) ? 0 :
4062                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4063                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4064                 }
4065                 if (attn & BNX2X_GRC_RSV) {
4066                         val = CHIP_IS_E1(bp) ? 0 :
4067                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4068                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4069                 }
4070                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4071         }
4072 }
4073
4074 /*
4075  * Bits map:
4076  * 0-7   - Engine0 load counter.
4077  * 8-15  - Engine1 load counter.
4078  * 16    - Engine0 RESET_IN_PROGRESS bit.
4079  * 17    - Engine1 RESET_IN_PROGRESS bit.
4080  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4081  *         on the engine
4082  * 19    - Engine1 ONE_IS_LOADED.
4083  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4084  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4085  *         just the one belonging to its engine).
4086  *
4087  */
4088 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4089
4090 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4091 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4092 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4093 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4094 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4095 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4096 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4097
4098 /*
4099  * Set the GLOBAL_RESET bit.
4100  *
4101  * Should be run under rtnl lock
4102  */
4103 void bnx2x_set_reset_global(struct bnx2x *bp)
4104 {
4105         u32 val;
4106         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4107         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4108         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4109         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4110 }
4111
4112 /*
4113  * Clear the GLOBAL_RESET bit.
4114  *
4115  * Should be run under rtnl lock
4116  */
4117 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4118 {
4119         u32 val;
4120         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4121         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4122         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4123         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4124 }
4125
4126 /*
4127  * Checks the GLOBAL_RESET bit.
4128  *
4129  * should be run under rtnl lock
4130  */
4131 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4132 {
4133         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4134
4135         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4136         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4137 }
4138
4139 /*
4140  * Clear RESET_IN_PROGRESS bit for the current engine.
4141  *
4142  * Should be run under rtnl lock
4143  */
4144 static void bnx2x_set_reset_done(struct bnx2x *bp)
4145 {
4146         u32 val;
4147         u32 bit = BP_PATH(bp) ?
4148                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4149         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4150         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4151
4152         /* Clear the bit */
4153         val &= ~bit;
4154         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4155
4156         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4157 }
4158
4159 /*
4160  * Set RESET_IN_PROGRESS for the current engine.
4161  *
4162  * should be run under rtnl lock
4163  */
4164 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4165 {
4166         u32 val;
4167         u32 bit = BP_PATH(bp) ?
4168                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4169         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4170         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4171
4172         /* Set the bit */
4173         val |= bit;
4174         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4175         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4176 }
4177
4178 /*
4179  * Checks the RESET_IN_PROGRESS bit for the given engine.
4180  * should be run under rtnl lock
4181  */
4182 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4183 {
4184         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4185         u32 bit = engine ?
4186                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4187
4188         /* return false if bit is set */
4189         return (val & bit) ? false : true;
4190 }
4191
4192 /*
4193  * set pf load for the current pf.
4194  *
4195  * should be run under rtnl lock
4196  */
4197 void bnx2x_set_pf_load(struct bnx2x *bp)
4198 {
4199         u32 val1, val;
4200         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4201                              BNX2X_PATH0_LOAD_CNT_MASK;
4202         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4203                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4204
4205         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4206         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4207
4208         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4209
4210         /* get the current counter value */
4211         val1 = (val & mask) >> shift;
4212
4213         /* set bit of that PF */
4214         val1 |= (1 << bp->pf_num);
4215
4216         /* clear the old value */
4217         val &= ~mask;
4218
4219         /* set the new one */
4220         val |= ((val1 << shift) & mask);
4221
4222         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4223         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4224 }
4225
4226 /**
4227  * bnx2x_clear_pf_load - clear pf load mark
4228  *
4229  * @bp:         driver handle
4230  *
4231  * Should be run under rtnl lock.
4232  * Decrements the load counter for the current engine. Returns
4233  * whether other functions are still loaded
4234  */
4235 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4236 {
4237         u32 val1, val;
4238         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4239                              BNX2X_PATH0_LOAD_CNT_MASK;
4240         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4241                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4242
4243         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4244         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4245         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4246
4247         /* get the current counter value */
4248         val1 = (val & mask) >> shift;
4249
4250         /* clear bit of that PF */
4251         val1 &= ~(1 << bp->pf_num);
4252
4253         /* clear the old value */
4254         val &= ~mask;
4255
4256         /* set the new one */
4257         val |= ((val1 << shift) & mask);
4258
4259         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4260         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4261         return val1 != 0;
4262 }
4263
4264 /*
4265  * Read the load status for the current engine.
4266  *
4267  * should be run under rtnl lock
4268  */
4269 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4270 {
4271         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4272                              BNX2X_PATH0_LOAD_CNT_MASK);
4273         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4274                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4275         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4276
4277         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4278
4279         val = (val & mask) >> shift;
4280
4281         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4282            engine, val);
4283
4284         return val != 0;
4285 }
4286
4287 static void _print_parity(struct bnx2x *bp, u32 reg)
4288 {
4289         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4290 }
4291
4292 static void _print_next_block(int idx, const char *blk)
4293 {
4294         pr_cont("%s%s", idx ? ", " : "", blk);
4295 }
4296
4297 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4298                                             int *par_num, bool print)
4299 {
4300         u32 cur_bit;
4301         bool res;
4302         int i;
4303
4304         res = false;
4305
4306         for (i = 0; sig; i++) {
4307                 cur_bit = (0x1UL << i);
4308                 if (sig & cur_bit) {
4309                         res |= true; /* Each bit is real error! */
4310
4311                         if (print) {
4312                                 switch (cur_bit) {
4313                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4314                                         _print_next_block((*par_num)++, "BRB");
4315                                         _print_parity(bp,
4316                                                       BRB1_REG_BRB1_PRTY_STS);
4317                                         break;
4318                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4319                                         _print_next_block((*par_num)++,
4320                                                           "PARSER");
4321                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4322                                         break;
4323                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4324                                         _print_next_block((*par_num)++, "TSDM");
4325                                         _print_parity(bp,
4326                                                       TSDM_REG_TSDM_PRTY_STS);
4327                                         break;
4328                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4329                                         _print_next_block((*par_num)++,
4330                                                           "SEARCHER");
4331                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4332                                         break;
4333                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4334                                         _print_next_block((*par_num)++, "TCM");
4335                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4336                                         break;
4337                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4338                                         _print_next_block((*par_num)++,
4339                                                           "TSEMI");
4340                                         _print_parity(bp,
4341                                                       TSEM_REG_TSEM_PRTY_STS_0);
4342                                         _print_parity(bp,
4343                                                       TSEM_REG_TSEM_PRTY_STS_1);
4344                                         break;
4345                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4346                                         _print_next_block((*par_num)++, "XPB");
4347                                         _print_parity(bp, GRCBASE_XPB +
4348                                                           PB_REG_PB_PRTY_STS);
4349                                         break;
4350                                 }
4351                         }
4352
4353                         /* Clear the bit */
4354                         sig &= ~cur_bit;
4355                 }
4356         }
4357
4358         return res;
4359 }
4360
4361 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4362                                             int *par_num, bool *global,
4363                                             bool print)
4364 {
4365         u32 cur_bit;
4366         bool res;
4367         int i;
4368
4369         res = false;
4370
4371         for (i = 0; sig; i++) {
4372                 cur_bit = (0x1UL << i);
4373                 if (sig & cur_bit) {
4374                         res |= true; /* Each bit is real error! */
4375                         switch (cur_bit) {
4376                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4377                                 if (print) {
4378                                         _print_next_block((*par_num)++, "PBF");
4379                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4380                                 }
4381                                 break;
4382                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4383                                 if (print) {
4384                                         _print_next_block((*par_num)++, "QM");
4385                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4386                                 }
4387                                 break;
4388                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4389                                 if (print) {
4390                                         _print_next_block((*par_num)++, "TM");
4391                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4392                                 }
4393                                 break;
4394                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4395                                 if (print) {
4396                                         _print_next_block((*par_num)++, "XSDM");
4397                                         _print_parity(bp,
4398                                                       XSDM_REG_XSDM_PRTY_STS);
4399                                 }
4400                                 break;
4401                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4402                                 if (print) {
4403                                         _print_next_block((*par_num)++, "XCM");
4404                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4405                                 }
4406                                 break;
4407                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4408                                 if (print) {
4409                                         _print_next_block((*par_num)++,
4410                                                           "XSEMI");
4411                                         _print_parity(bp,
4412                                                       XSEM_REG_XSEM_PRTY_STS_0);
4413                                         _print_parity(bp,
4414                                                       XSEM_REG_XSEM_PRTY_STS_1);
4415                                 }
4416                                 break;
4417                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4418                                 if (print) {
4419                                         _print_next_block((*par_num)++,
4420                                                           "DOORBELLQ");
4421                                         _print_parity(bp,
4422                                                       DORQ_REG_DORQ_PRTY_STS);
4423                                 }
4424                                 break;
4425                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4426                                 if (print) {
4427                                         _print_next_block((*par_num)++, "NIG");
4428                                         if (CHIP_IS_E1x(bp)) {
4429                                                 _print_parity(bp,
4430                                                         NIG_REG_NIG_PRTY_STS);
4431                                         } else {
4432                                                 _print_parity(bp,
4433                                                         NIG_REG_NIG_PRTY_STS_0);
4434                                                 _print_parity(bp,
4435                                                         NIG_REG_NIG_PRTY_STS_1);
4436                                         }
4437                                 }
4438                                 break;
4439                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4440                                 if (print)
4441                                         _print_next_block((*par_num)++,
4442                                                           "VAUX PCI CORE");
4443                                 *global = true;
4444                                 break;
4445                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4446                                 if (print) {
4447                                         _print_next_block((*par_num)++,
4448                                                           "DEBUG");
4449                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4450                                 }
4451                                 break;
4452                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4453                                 if (print) {
4454                                         _print_next_block((*par_num)++, "USDM");
4455                                         _print_parity(bp,
4456                                                       USDM_REG_USDM_PRTY_STS);
4457                                 }
4458                                 break;
4459                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4460                                 if (print) {
4461                                         _print_next_block((*par_num)++, "UCM");
4462                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4463                                 }
4464                                 break;
4465                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4466                                 if (print) {
4467                                         _print_next_block((*par_num)++,
4468                                                           "USEMI");
4469                                         _print_parity(bp,
4470                                                       USEM_REG_USEM_PRTY_STS_0);
4471                                         _print_parity(bp,
4472                                                       USEM_REG_USEM_PRTY_STS_1);
4473                                 }
4474                                 break;
4475                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4476                                 if (print) {
4477                                         _print_next_block((*par_num)++, "UPB");
4478                                         _print_parity(bp, GRCBASE_UPB +
4479                                                           PB_REG_PB_PRTY_STS);
4480                                 }
4481                                 break;
4482                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4483                                 if (print) {
4484                                         _print_next_block((*par_num)++, "CSDM");
4485                                         _print_parity(bp,
4486                                                       CSDM_REG_CSDM_PRTY_STS);
4487                                 }
4488                                 break;
4489                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4490                                 if (print) {
4491                                         _print_next_block((*par_num)++, "CCM");
4492                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4493                                 }
4494                                 break;
4495                         }
4496
4497                         /* Clear the bit */
4498                         sig &= ~cur_bit;
4499                 }
4500         }
4501
4502         return res;
4503 }
4504
4505 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4506                                             int *par_num, bool print)
4507 {
4508         u32 cur_bit;
4509         bool res;
4510         int i;
4511
4512         res = false;
4513
4514         for (i = 0; sig; i++) {
4515                 cur_bit = (0x1UL << i);
4516                 if (sig & cur_bit) {
4517                         res |= true; /* Each bit is real error! */
4518                         if (print) {
4519                                 switch (cur_bit) {
4520                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4521                                         _print_next_block((*par_num)++,
4522                                                           "CSEMI");
4523                                         _print_parity(bp,
4524                                                       CSEM_REG_CSEM_PRTY_STS_0);
4525                                         _print_parity(bp,
4526                                                       CSEM_REG_CSEM_PRTY_STS_1);
4527                                         break;
4528                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4529                                         _print_next_block((*par_num)++, "PXP");
4530                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4531                                         _print_parity(bp,
4532                                                       PXP2_REG_PXP2_PRTY_STS_0);
4533                                         _print_parity(bp,
4534                                                       PXP2_REG_PXP2_PRTY_STS_1);
4535                                         break;
4536                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4537                                         _print_next_block((*par_num)++,
4538                                                           "PXPPCICLOCKCLIENT");
4539                                         break;
4540                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4541                                         _print_next_block((*par_num)++, "CFC");
4542                                         _print_parity(bp,
4543                                                       CFC_REG_CFC_PRTY_STS);
4544                                         break;
4545                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4546                                         _print_next_block((*par_num)++, "CDU");
4547                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4548                                         break;
4549                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4550                                         _print_next_block((*par_num)++, "DMAE");
4551                                         _print_parity(bp,
4552                                                       DMAE_REG_DMAE_PRTY_STS);
4553                                         break;
4554                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4555                                         _print_next_block((*par_num)++, "IGU");
4556                                         if (CHIP_IS_E1x(bp))
4557                                                 _print_parity(bp,
4558                                                         HC_REG_HC_PRTY_STS);
4559                                         else
4560                                                 _print_parity(bp,
4561                                                         IGU_REG_IGU_PRTY_STS);
4562                                         break;
4563                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4564                                         _print_next_block((*par_num)++, "MISC");
4565                                         _print_parity(bp,
4566                                                       MISC_REG_MISC_PRTY_STS);
4567                                         break;
4568                                 }
4569                         }
4570
4571                         /* Clear the bit */
4572                         sig &= ~cur_bit;
4573                 }
4574         }
4575
4576         return res;
4577 }
4578
4579 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4580                                             int *par_num, bool *global,
4581                                             bool print)
4582 {
4583         bool res = false;
4584         u32 cur_bit;
4585         int i;
4586
4587         for (i = 0; sig; i++) {
4588                 cur_bit = (0x1UL << i);
4589                 if (sig & cur_bit) {
4590                         switch (cur_bit) {
4591                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4592                                 if (print)
4593                                         _print_next_block((*par_num)++,
4594                                                           "MCP ROM");
4595                                 *global = true;
4596                                 res |= true;
4597                                 break;
4598                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4599                                 if (print)
4600                                         _print_next_block((*par_num)++,
4601                                                           "MCP UMP RX");
4602                                 *global = true;
4603                                 res |= true;
4604                                 break;
4605                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4606                                 if (print)
4607                                         _print_next_block((*par_num)++,
4608                                                           "MCP UMP TX");
4609                                 *global = true;
4610                                 res |= true;
4611                                 break;
4612                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4613                                 if (print)
4614                                         _print_next_block((*par_num)++,
4615                                                           "MCP SCPAD");
4616                                 /* clear latched SCPAD PATIRY from MCP */
4617                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4618                                        1UL << 10);
4619                                 break;
4620                         }
4621
4622                         /* Clear the bit */
4623                         sig &= ~cur_bit;
4624                 }
4625         }
4626
4627         return res;
4628 }
4629
4630 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4631                                             int *par_num, bool print)
4632 {
4633         u32 cur_bit;
4634         bool res;
4635         int i;
4636
4637         res = false;
4638
4639         for (i = 0; sig; i++) {
4640                 cur_bit = (0x1UL << i);
4641                 if (sig & cur_bit) {
4642                         res |= true; /* Each bit is real error! */
4643                         if (print) {
4644                                 switch (cur_bit) {
4645                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4646                                         _print_next_block((*par_num)++,
4647                                                           "PGLUE_B");
4648                                         _print_parity(bp,
4649                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4650                                         break;
4651                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4652                                         _print_next_block((*par_num)++, "ATC");
4653                                         _print_parity(bp,
4654                                                       ATC_REG_ATC_PRTY_STS);
4655                                         break;
4656                                 }
4657                         }
4658                         /* Clear the bit */
4659                         sig &= ~cur_bit;
4660                 }
4661         }
4662
4663         return res;
4664 }
4665
4666 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4667                               u32 *sig)
4668 {
4669         bool res = false;
4670
4671         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4672             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4673             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4674             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4675             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4676                 int par_num = 0;
4677                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4678                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4679                           sig[0] & HW_PRTY_ASSERT_SET_0,
4680                           sig[1] & HW_PRTY_ASSERT_SET_1,
4681                           sig[2] & HW_PRTY_ASSERT_SET_2,
4682                           sig[3] & HW_PRTY_ASSERT_SET_3,
4683                           sig[4] & HW_PRTY_ASSERT_SET_4);
4684                 if (print)
4685                         netdev_err(bp->dev,
4686                                    "Parity errors detected in blocks: ");
4687                 res |= bnx2x_check_blocks_with_parity0(bp,
4688                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4689                 res |= bnx2x_check_blocks_with_parity1(bp,
4690                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4691                 res |= bnx2x_check_blocks_with_parity2(bp,
4692                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4693                 res |= bnx2x_check_blocks_with_parity3(bp,
4694                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4695                 res |= bnx2x_check_blocks_with_parity4(bp,
4696                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4697
4698                 if (print)
4699                         pr_cont("\n");
4700         }
4701
4702         return res;
4703 }
4704
4705 /**
4706  * bnx2x_chk_parity_attn - checks for parity attentions.
4707  *
4708  * @bp:         driver handle
4709  * @global:     true if there was a global attention
4710  * @print:      show parity attention in syslog
4711  */
4712 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4713 {
4714         struct attn_route attn = { {0} };
4715         int port = BP_PORT(bp);
4716
4717         attn.sig[0] = REG_RD(bp,
4718                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4719                              port*4);
4720         attn.sig[1] = REG_RD(bp,
4721                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4722                              port*4);
4723         attn.sig[2] = REG_RD(bp,
4724                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4725                              port*4);
4726         attn.sig[3] = REG_RD(bp,
4727                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4728                              port*4);
4729         /* Since MCP attentions can't be disabled inside the block, we need to
4730          * read AEU registers to see whether they're currently disabled
4731          */
4732         attn.sig[3] &= ((REG_RD(bp,
4733                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4734                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4735                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4736                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4737
4738         if (!CHIP_IS_E1x(bp))
4739                 attn.sig[4] = REG_RD(bp,
4740                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4741                                      port*4);
4742
4743         return bnx2x_parity_attn(bp, global, print, attn.sig);
4744 }
4745
4746 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4747 {
4748         u32 val;
4749         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4750
4751                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4752                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4753                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4754                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4755                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4756                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4757                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4758                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4759                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4760                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4761                 if (val &
4762                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4763                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4764                 if (val &
4765                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4766                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4767                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4768                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4769                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4770                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4771                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4772                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4773         }
4774         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4775                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4776                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4777                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4778                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4779                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4780                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4781                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4782                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4783                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4784                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4785                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4786                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4787                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4788                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4789         }
4790
4791         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4792                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4793                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4794                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4795                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4796         }
4797 }
4798
4799 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4800 {
4801         struct attn_route attn, *group_mask;
4802         int port = BP_PORT(bp);
4803         int index;
4804         u32 reg_addr;
4805         u32 val;
4806         u32 aeu_mask;
4807         bool global = false;
4808
4809         /* need to take HW lock because MCP or other port might also
4810            try to handle this event */
4811         bnx2x_acquire_alr(bp);
4812
4813         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4814 #ifndef BNX2X_STOP_ON_ERROR
4815                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4816                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4817                 /* Disable HW interrupts */
4818                 bnx2x_int_disable(bp);
4819                 /* In case of parity errors don't handle attentions so that
4820                  * other function would "see" parity errors.
4821                  */
4822 #else
4823                 bnx2x_panic();
4824 #endif
4825                 bnx2x_release_alr(bp);
4826                 return;
4827         }
4828
4829         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4830         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4831         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4832         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4833         if (!CHIP_IS_E1x(bp))
4834                 attn.sig[4] =
4835                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4836         else
4837                 attn.sig[4] = 0;
4838
4839         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4840            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4841
4842         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4843                 if (deasserted & (1 << index)) {
4844                         group_mask = &bp->attn_group[index];
4845
4846                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4847                            index,
4848                            group_mask->sig[0], group_mask->sig[1],
4849                            group_mask->sig[2], group_mask->sig[3],
4850                            group_mask->sig[4]);
4851
4852                         bnx2x_attn_int_deasserted4(bp,
4853                                         attn.sig[4] & group_mask->sig[4]);
4854                         bnx2x_attn_int_deasserted3(bp,
4855                                         attn.sig[3] & group_mask->sig[3]);
4856                         bnx2x_attn_int_deasserted1(bp,
4857                                         attn.sig[1] & group_mask->sig[1]);
4858                         bnx2x_attn_int_deasserted2(bp,
4859                                         attn.sig[2] & group_mask->sig[2]);
4860                         bnx2x_attn_int_deasserted0(bp,
4861                                         attn.sig[0] & group_mask->sig[0]);
4862                 }
4863         }
4864
4865         bnx2x_release_alr(bp);
4866
4867         if (bp->common.int_block == INT_BLOCK_HC)
4868                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4869                             COMMAND_REG_ATTN_BITS_CLR);
4870         else
4871                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4872
4873         val = ~deasserted;
4874         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4875            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4876         REG_WR(bp, reg_addr, val);
4877
4878         if (~bp->attn_state & deasserted)
4879                 BNX2X_ERR("IGU ERROR\n");
4880
4881         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4882                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4883
4884         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4885         aeu_mask = REG_RD(bp, reg_addr);
4886
4887         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4888            aeu_mask, deasserted);
4889         aeu_mask |= (deasserted & 0x3ff);
4890         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4891
4892         REG_WR(bp, reg_addr, aeu_mask);
4893         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4894
4895         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4896         bp->attn_state &= ~deasserted;
4897         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4898 }
4899
4900 static void bnx2x_attn_int(struct bnx2x *bp)
4901 {
4902         /* read local copy of bits */
4903         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4904                                                                 attn_bits);
4905         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4906                                                                 attn_bits_ack);
4907         u32 attn_state = bp->attn_state;
4908
4909         /* look for changed bits */
4910         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4911         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4912
4913         DP(NETIF_MSG_HW,
4914            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4915            attn_bits, attn_ack, asserted, deasserted);
4916
4917         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4918                 BNX2X_ERR("BAD attention state\n");
4919
4920         /* handle bits that were raised */
4921         if (asserted)
4922                 bnx2x_attn_int_asserted(bp, asserted);
4923
4924         if (deasserted)
4925                 bnx2x_attn_int_deasserted(bp, deasserted);
4926 }
4927
4928 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4929                       u16 index, u8 op, u8 update)
4930 {
4931         u32 igu_addr = bp->igu_base_addr;
4932         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4933         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4934                              igu_addr);
4935 }
4936
4937 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4938 {
4939         /* No memory barriers */
4940         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4941         mmiowb(); /* keep prod updates ordered */
4942 }
4943
4944 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4945                                       union event_ring_elem *elem)
4946 {
4947         u8 err = elem->message.error;
4948
4949         if (!bp->cnic_eth_dev.starting_cid  ||
4950             (cid < bp->cnic_eth_dev.starting_cid &&
4951             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4952                 return 1;
4953
4954         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4955
4956         if (unlikely(err)) {
4957
4958                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4959                           cid);
4960                 bnx2x_panic_dump(bp, false);
4961         }
4962         bnx2x_cnic_cfc_comp(bp, cid, err);
4963         return 0;
4964 }
4965
4966 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4967 {
4968         struct bnx2x_mcast_ramrod_params rparam;
4969         int rc;
4970
4971         memset(&rparam, 0, sizeof(rparam));
4972
4973         rparam.mcast_obj = &bp->mcast_obj;
4974
4975         netif_addr_lock_bh(bp->dev);
4976
4977         /* Clear pending state for the last command */
4978         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4979
4980         /* If there are pending mcast commands - send them */
4981         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4982                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4983                 if (rc < 0)
4984                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4985                                   rc);
4986         }
4987
4988         netif_addr_unlock_bh(bp->dev);
4989 }
4990
4991 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4992                                             union event_ring_elem *elem)
4993 {
4994         unsigned long ramrod_flags = 0;
4995         int rc = 0;
4996         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4997         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4998
4999         /* Always push next commands out, don't wait here */
5000         __set_bit(RAMROD_CONT, &ramrod_flags);
5001
5002         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5003                             >> BNX2X_SWCID_SHIFT) {
5004         case BNX2X_FILTER_MAC_PENDING:
5005                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5006                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5007                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5008                 else
5009                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5010
5011                 break;
5012         case BNX2X_FILTER_MCAST_PENDING:
5013                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5014                 /* This is only relevant for 57710 where multicast MACs are
5015                  * configured as unicast MACs using the same ramrod.
5016                  */
5017                 bnx2x_handle_mcast_eqe(bp);
5018                 return;
5019         default:
5020                 BNX2X_ERR("Unsupported classification command: %d\n",
5021                           elem->message.data.eth_event.echo);
5022                 return;
5023         }
5024
5025         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5026
5027         if (rc < 0)
5028                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5029         else if (rc > 0)
5030                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5031 }
5032
5033 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5034
5035 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5036 {
5037         netif_addr_lock_bh(bp->dev);
5038
5039         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5040
5041         /* Send rx_mode command again if was requested */
5042         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5043                 bnx2x_set_storm_rx_mode(bp);
5044         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5045                                     &bp->sp_state))
5046                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5047         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5048                                     &bp->sp_state))
5049                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5050
5051         netif_addr_unlock_bh(bp->dev);
5052 }
5053
5054 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5055                                               union event_ring_elem *elem)
5056 {
5057         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5058                 DP(BNX2X_MSG_SP,
5059                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5060                    elem->message.data.vif_list_event.func_bit_map);
5061                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5062                         elem->message.data.vif_list_event.func_bit_map);
5063         } else if (elem->message.data.vif_list_event.echo ==
5064                    VIF_LIST_RULE_SET) {
5065                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5066                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5067         }
5068 }
5069
5070 /* called with rtnl_lock */
5071 static void bnx2x_after_function_update(struct bnx2x *bp)
5072 {
5073         int q, rc;
5074         struct bnx2x_fastpath *fp;
5075         struct bnx2x_queue_state_params queue_params = {NULL};
5076         struct bnx2x_queue_update_params *q_update_params =
5077                 &queue_params.params.update;
5078
5079         /* Send Q update command with afex vlan removal values for all Qs */
5080         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5081
5082         /* set silent vlan removal values according to vlan mode */
5083         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5084                   &q_update_params->update_flags);
5085         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5086                   &q_update_params->update_flags);
5087         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5088
5089         /* in access mode mark mask and value are 0 to strip all vlans */
5090         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5091                 q_update_params->silent_removal_value = 0;
5092                 q_update_params->silent_removal_mask = 0;
5093         } else {
5094                 q_update_params->silent_removal_value =
5095                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5096                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5097         }
5098
5099         for_each_eth_queue(bp, q) {
5100                 /* Set the appropriate Queue object */
5101                 fp = &bp->fp[q];
5102                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5103
5104                 /* send the ramrod */
5105                 rc = bnx2x_queue_state_change(bp, &queue_params);
5106                 if (rc < 0)
5107                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5108                                   q);
5109         }
5110
5111         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5112                 fp = &bp->fp[FCOE_IDX(bp)];
5113                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5114
5115                 /* clear pending completion bit */
5116                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5117
5118                 /* mark latest Q bit */
5119                 smp_mb__before_clear_bit();
5120                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5121                 smp_mb__after_clear_bit();
5122
5123                 /* send Q update ramrod for FCoE Q */
5124                 rc = bnx2x_queue_state_change(bp, &queue_params);
5125                 if (rc < 0)
5126                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5127                                   q);
5128         } else {
5129                 /* If no FCoE ring - ACK MCP now */
5130                 bnx2x_link_report(bp);
5131                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5132         }
5133 }
5134
5135 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5136         struct bnx2x *bp, u32 cid)
5137 {
5138         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5139
5140         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5141                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5142         else
5143                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5144 }
5145
5146 static void bnx2x_eq_int(struct bnx2x *bp)
5147 {
5148         u16 hw_cons, sw_cons, sw_prod;
5149         union event_ring_elem *elem;
5150         u8 echo;
5151         u32 cid;
5152         u8 opcode;
5153         int rc, spqe_cnt = 0;
5154         struct bnx2x_queue_sp_obj *q_obj;
5155         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5156         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5157
5158         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5159
5160         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5161          * when we get the next-page we need to adjust so the loop
5162          * condition below will be met. The next element is the size of a
5163          * regular element and hence incrementing by 1
5164          */
5165         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5166                 hw_cons++;
5167
5168         /* This function may never run in parallel with itself for a
5169          * specific bp, thus there is no need in "paired" read memory
5170          * barrier here.
5171          */
5172         sw_cons = bp->eq_cons;
5173         sw_prod = bp->eq_prod;
5174
5175         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5176                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5177
5178         for (; sw_cons != hw_cons;
5179               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5180
5181                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5182
5183                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5184                 if (!rc) {
5185                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5186                            rc);
5187                         goto next_spqe;
5188                 }
5189
5190                 /* elem CID originates from FW; actually LE */
5191                 cid = SW_CID((__force __le32)
5192                              elem->message.data.cfc_del_event.cid);
5193                 opcode = elem->message.opcode;
5194
5195                 /* handle eq element */
5196                 switch (opcode) {
5197                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5198                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5199                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5200                         continue;
5201
5202                 case EVENT_RING_OPCODE_STAT_QUERY:
5203                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5204                            "got statistics comp event %d\n",
5205                            bp->stats_comp++);
5206                         /* nothing to do with stats comp */
5207                         goto next_spqe;
5208
5209                 case EVENT_RING_OPCODE_CFC_DEL:
5210                         /* handle according to cid range */
5211                         /*
5212                          * we may want to verify here that the bp state is
5213                          * HALTING
5214                          */
5215                         DP(BNX2X_MSG_SP,
5216                            "got delete ramrod for MULTI[%d]\n", cid);
5217
5218                         if (CNIC_LOADED(bp) &&
5219                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5220                                 goto next_spqe;
5221
5222                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5223
5224                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5225                                 break;
5226
5227                         goto next_spqe;
5228
5229                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5230                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5231                         if (f_obj->complete_cmd(bp, f_obj,
5232                                                 BNX2X_F_CMD_TX_STOP))
5233                                 break;
5234                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5235                         goto next_spqe;
5236
5237                 case EVENT_RING_OPCODE_START_TRAFFIC:
5238                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5239                         if (f_obj->complete_cmd(bp, f_obj,
5240                                                 BNX2X_F_CMD_TX_START))
5241                                 break;
5242                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5243                         goto next_spqe;
5244
5245                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5246                         echo = elem->message.data.function_update_event.echo;
5247                         if (echo == SWITCH_UPDATE) {
5248                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5249                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5250                                 if (f_obj->complete_cmd(
5251                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5252                                         break;
5253
5254                         } else {
5255                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5256                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5257                                 f_obj->complete_cmd(bp, f_obj,
5258                                                     BNX2X_F_CMD_AFEX_UPDATE);
5259
5260                                 /* We will perform the Queues update from
5261                                  * sp_rtnl task as all Queue SP operations
5262                                  * should run under rtnl_lock.
5263                                  */
5264                                 smp_mb__before_clear_bit();
5265                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5266                                         &bp->sp_rtnl_state);
5267                                 smp_mb__after_clear_bit();
5268
5269                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5270                         }
5271
5272                         goto next_spqe;
5273
5274                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5275                         f_obj->complete_cmd(bp, f_obj,
5276                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5277                         bnx2x_after_afex_vif_lists(bp, elem);
5278                         goto next_spqe;
5279                 case EVENT_RING_OPCODE_FUNCTION_START:
5280                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5281                            "got FUNC_START ramrod\n");
5282                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5283                                 break;
5284
5285                         goto next_spqe;
5286
5287                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5288                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5289                            "got FUNC_STOP ramrod\n");
5290                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5291                                 break;
5292
5293                         goto next_spqe;
5294                 }
5295
5296                 switch (opcode | bp->state) {
5297                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5298                       BNX2X_STATE_OPEN):
5299                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5300                       BNX2X_STATE_OPENING_WAIT4_PORT):
5301                         cid = elem->message.data.eth_event.echo &
5302                                 BNX2X_SWCID_MASK;
5303                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5304                            cid);
5305                         rss_raw->clear_pending(rss_raw);
5306                         break;
5307
5308                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5309                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5310                 case (EVENT_RING_OPCODE_SET_MAC |
5311                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5312                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5313                       BNX2X_STATE_OPEN):
5314                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5315                       BNX2X_STATE_DIAG):
5316                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5317                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5318                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5319                         bnx2x_handle_classification_eqe(bp, elem);
5320                         break;
5321
5322                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5323                       BNX2X_STATE_OPEN):
5324                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5325                       BNX2X_STATE_DIAG):
5326                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5327                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5328                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5329                         bnx2x_handle_mcast_eqe(bp);
5330                         break;
5331
5332                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5333                       BNX2X_STATE_OPEN):
5334                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5335                       BNX2X_STATE_DIAG):
5336                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5337                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5338                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5339                         bnx2x_handle_rx_mode_eqe(bp);
5340                         break;
5341                 default:
5342                         /* unknown event log error and continue */
5343                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5344                                   elem->message.opcode, bp->state);
5345                 }
5346 next_spqe:
5347                 spqe_cnt++;
5348         } /* for */
5349
5350         smp_mb__before_atomic_inc();
5351         atomic_add(spqe_cnt, &bp->eq_spq_left);
5352
5353         bp->eq_cons = sw_cons;
5354         bp->eq_prod = sw_prod;
5355         /* Make sure that above mem writes were issued towards the memory */
5356         smp_wmb();
5357
5358         /* update producer */
5359         bnx2x_update_eq_prod(bp, bp->eq_prod);
5360 }
5361
5362 static void bnx2x_sp_task(struct work_struct *work)
5363 {
5364         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5365
5366         DP(BNX2X_MSG_SP, "sp task invoked\n");
5367
5368         /* make sure the atomic interrupt_occurred has been written */
5369         smp_rmb();
5370         if (atomic_read(&bp->interrupt_occurred)) {
5371
5372                 /* what work needs to be performed? */
5373                 u16 status = bnx2x_update_dsb_idx(bp);
5374
5375                 DP(BNX2X_MSG_SP, "status %x\n", status);
5376                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5377                 atomic_set(&bp->interrupt_occurred, 0);
5378
5379                 /* HW attentions */
5380                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5381                         bnx2x_attn_int(bp);
5382                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5383                 }
5384
5385                 /* SP events: STAT_QUERY and others */
5386                 if (status & BNX2X_DEF_SB_IDX) {
5387                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5388
5389                 if (FCOE_INIT(bp) &&
5390                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5391                                 /* Prevent local bottom-halves from running as
5392                                  * we are going to change the local NAPI list.
5393                                  */
5394                                 local_bh_disable();
5395                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5396                                 local_bh_enable();
5397                         }
5398
5399                         /* Handle EQ completions */
5400                         bnx2x_eq_int(bp);
5401                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5402                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5403
5404                         status &= ~BNX2X_DEF_SB_IDX;
5405                 }
5406
5407                 /* if status is non zero then perhaps something went wrong */
5408                 if (unlikely(status))
5409                         DP(BNX2X_MSG_SP,
5410                            "got an unknown interrupt! (status 0x%x)\n", status);
5411
5412                 /* ack status block only if something was actually handled */
5413                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5414                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5415         }
5416
5417         /* must be called after the EQ processing (since eq leads to sriov
5418          * ramrod completion flows).
5419          * This flow may have been scheduled by the arrival of a ramrod
5420          * completion, or by the sriov code rescheduling itself.
5421          */
5422         bnx2x_iov_sp_task(bp);
5423
5424         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5425         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5426                                &bp->sp_state)) {
5427                 bnx2x_link_report(bp);
5428                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5429         }
5430 }
5431
5432 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5433 {
5434         struct net_device *dev = dev_instance;
5435         struct bnx2x *bp = netdev_priv(dev);
5436
5437         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5438                      IGU_INT_DISABLE, 0);
5439
5440 #ifdef BNX2X_STOP_ON_ERROR
5441         if (unlikely(bp->panic))
5442                 return IRQ_HANDLED;
5443 #endif
5444
5445         if (CNIC_LOADED(bp)) {
5446                 struct cnic_ops *c_ops;
5447
5448                 rcu_read_lock();
5449                 c_ops = rcu_dereference(bp->cnic_ops);
5450                 if (c_ops)
5451                         c_ops->cnic_handler(bp->cnic_data, NULL);
5452                 rcu_read_unlock();
5453         }
5454
5455         /* schedule sp task to perform default status block work, ack
5456          * attentions and enable interrupts.
5457          */
5458         bnx2x_schedule_sp_task(bp);
5459
5460         return IRQ_HANDLED;
5461 }
5462
5463 /* end of slow path */
5464
5465 void bnx2x_drv_pulse(struct bnx2x *bp)
5466 {
5467         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5468                  bp->fw_drv_pulse_wr_seq);
5469 }
5470
5471 static void bnx2x_timer(unsigned long data)
5472 {
5473         struct bnx2x *bp = (struct bnx2x *) data;
5474
5475         if (!netif_running(bp->dev))
5476                 return;
5477
5478         if (IS_PF(bp) &&
5479             !BP_NOMCP(bp)) {
5480                 int mb_idx = BP_FW_MB_IDX(bp);
5481                 u16 drv_pulse;
5482                 u16 mcp_pulse;
5483
5484                 ++bp->fw_drv_pulse_wr_seq;
5485                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5486                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5487                 bnx2x_drv_pulse(bp);
5488
5489                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5490                              MCP_PULSE_SEQ_MASK);
5491                 /* The delta between driver pulse and mcp response
5492                  * should not get too big. If the MFW is more than 5 pulses
5493                  * behind, we should worry about it enough to generate an error
5494                  * log.
5495                  */
5496                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5497                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5498                                   drv_pulse, mcp_pulse);
5499         }
5500
5501         if (bp->state == BNX2X_STATE_OPEN)
5502                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5503
5504         /* sample pf vf bulletin board for new posts from pf */
5505         if (IS_VF(bp))
5506                 bnx2x_timer_sriov(bp);
5507
5508         mod_timer(&bp->timer, jiffies + bp->current_interval);
5509 }
5510
5511 /* end of Statistics */
5512
5513 /* nic init */
5514
5515 /*
5516  * nic init service functions
5517  */
5518
5519 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5520 {
5521         u32 i;
5522         if (!(len%4) && !(addr%4))
5523                 for (i = 0; i < len; i += 4)
5524                         REG_WR(bp, addr + i, fill);
5525         else
5526                 for (i = 0; i < len; i++)
5527                         REG_WR8(bp, addr + i, fill);
5528 }
5529
5530 /* helper: writes FP SP data to FW - data_size in dwords */
5531 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5532                                 int fw_sb_id,
5533                                 u32 *sb_data_p,
5534                                 u32 data_size)
5535 {
5536         int index;
5537         for (index = 0; index < data_size; index++)
5538                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5539                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5540                         sizeof(u32)*index,
5541                         *(sb_data_p + index));
5542 }
5543
5544 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5545 {
5546         u32 *sb_data_p;
5547         u32 data_size = 0;
5548         struct hc_status_block_data_e2 sb_data_e2;
5549         struct hc_status_block_data_e1x sb_data_e1x;
5550
5551         /* disable the function first */
5552         if (!CHIP_IS_E1x(bp)) {
5553                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5554                 sb_data_e2.common.state = SB_DISABLED;
5555                 sb_data_e2.common.p_func.vf_valid = false;
5556                 sb_data_p = (u32 *)&sb_data_e2;
5557                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5558         } else {
5559                 memset(&sb_data_e1x, 0,
5560                        sizeof(struct hc_status_block_data_e1x));
5561                 sb_data_e1x.common.state = SB_DISABLED;
5562                 sb_data_e1x.common.p_func.vf_valid = false;
5563                 sb_data_p = (u32 *)&sb_data_e1x;
5564                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5565         }
5566         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5567
5568         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5569                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5570                         CSTORM_STATUS_BLOCK_SIZE);
5571         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5572                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5573                         CSTORM_SYNC_BLOCK_SIZE);
5574 }
5575
5576 /* helper:  writes SP SB data to FW */
5577 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5578                 struct hc_sp_status_block_data *sp_sb_data)
5579 {
5580         int func = BP_FUNC(bp);
5581         int i;
5582         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5583                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5584                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5585                         i*sizeof(u32),
5586                         *((u32 *)sp_sb_data + i));
5587 }
5588
5589 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5590 {
5591         int func = BP_FUNC(bp);
5592         struct hc_sp_status_block_data sp_sb_data;
5593         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5594
5595         sp_sb_data.state = SB_DISABLED;
5596         sp_sb_data.p_func.vf_valid = false;
5597
5598         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5599
5600         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5601                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5602                         CSTORM_SP_STATUS_BLOCK_SIZE);
5603         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5604                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5605                         CSTORM_SP_SYNC_BLOCK_SIZE);
5606 }
5607
5608 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5609                                            int igu_sb_id, int igu_seg_id)
5610 {
5611         hc_sm->igu_sb_id = igu_sb_id;
5612         hc_sm->igu_seg_id = igu_seg_id;
5613         hc_sm->timer_value = 0xFF;
5614         hc_sm->time_to_expire = 0xFFFFFFFF;
5615 }
5616
5617 /* allocates state machine ids. */
5618 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5619 {
5620         /* zero out state machine indices */
5621         /* rx indices */
5622         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5623
5624         /* tx indices */
5625         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5626         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5627         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5628         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5629
5630         /* map indices */
5631         /* rx indices */
5632         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5633                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5634
5635         /* tx indices */
5636         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5637                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5638         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5639                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5640         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5641                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5642         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5643                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5644 }
5645
5646 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5647                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5648 {
5649         int igu_seg_id;
5650
5651         struct hc_status_block_data_e2 sb_data_e2;
5652         struct hc_status_block_data_e1x sb_data_e1x;
5653         struct hc_status_block_sm  *hc_sm_p;
5654         int data_size;
5655         u32 *sb_data_p;
5656
5657         if (CHIP_INT_MODE_IS_BC(bp))
5658                 igu_seg_id = HC_SEG_ACCESS_NORM;
5659         else
5660                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5661
5662         bnx2x_zero_fp_sb(bp, fw_sb_id);
5663
5664         if (!CHIP_IS_E1x(bp)) {
5665                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5666                 sb_data_e2.common.state = SB_ENABLED;
5667                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5668                 sb_data_e2.common.p_func.vf_id = vfid;
5669                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5670                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5671                 sb_data_e2.common.same_igu_sb_1b = true;
5672                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5673                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5674                 hc_sm_p = sb_data_e2.common.state_machine;
5675                 sb_data_p = (u32 *)&sb_data_e2;
5676                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5677                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5678         } else {
5679                 memset(&sb_data_e1x, 0,
5680                        sizeof(struct hc_status_block_data_e1x));
5681                 sb_data_e1x.common.state = SB_ENABLED;
5682                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5683                 sb_data_e1x.common.p_func.vf_id = 0xff;
5684                 sb_data_e1x.common.p_func.vf_valid = false;
5685                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5686                 sb_data_e1x.common.same_igu_sb_1b = true;
5687                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5688                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5689                 hc_sm_p = sb_data_e1x.common.state_machine;
5690                 sb_data_p = (u32 *)&sb_data_e1x;
5691                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5692                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5693         }
5694
5695         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5696                                        igu_sb_id, igu_seg_id);
5697         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5698                                        igu_sb_id, igu_seg_id);
5699
5700         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5701
5702         /* write indices to HW - PCI guarantees endianity of regpairs */
5703         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5704 }
5705
5706 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5707                                      u16 tx_usec, u16 rx_usec)
5708 {
5709         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5710                                     false, rx_usec);
5711         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5712                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5713                                        tx_usec);
5714         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5715                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5716                                        tx_usec);
5717         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5718                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5719                                        tx_usec);
5720 }
5721
5722 static void bnx2x_init_def_sb(struct bnx2x *bp)
5723 {
5724         struct host_sp_status_block *def_sb = bp->def_status_blk;
5725         dma_addr_t mapping = bp->def_status_blk_mapping;
5726         int igu_sp_sb_index;
5727         int igu_seg_id;
5728         int port = BP_PORT(bp);
5729         int func = BP_FUNC(bp);
5730         int reg_offset, reg_offset_en5;
5731         u64 section;
5732         int index;
5733         struct hc_sp_status_block_data sp_sb_data;
5734         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5735
5736         if (CHIP_INT_MODE_IS_BC(bp)) {
5737                 igu_sp_sb_index = DEF_SB_IGU_ID;
5738                 igu_seg_id = HC_SEG_ACCESS_DEF;
5739         } else {
5740                 igu_sp_sb_index = bp->igu_dsb_id;
5741                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5742         }
5743
5744         /* ATTN */
5745         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5746                                             atten_status_block);
5747         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5748
5749         bp->attn_state = 0;
5750
5751         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5752                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5753         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5754                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5755         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5756                 int sindex;
5757                 /* take care of sig[0]..sig[4] */
5758                 for (sindex = 0; sindex < 4; sindex++)
5759                         bp->attn_group[index].sig[sindex] =
5760                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5761
5762                 if (!CHIP_IS_E1x(bp))
5763                         /*
5764                          * enable5 is separate from the rest of the registers,
5765                          * and therefore the address skip is 4
5766                          * and not 16 between the different groups
5767                          */
5768                         bp->attn_group[index].sig[4] = REG_RD(bp,
5769                                         reg_offset_en5 + 0x4*index);
5770                 else
5771                         bp->attn_group[index].sig[4] = 0;
5772         }
5773
5774         if (bp->common.int_block == INT_BLOCK_HC) {
5775                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5776                                      HC_REG_ATTN_MSG0_ADDR_L);
5777
5778                 REG_WR(bp, reg_offset, U64_LO(section));
5779                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5780         } else if (!CHIP_IS_E1x(bp)) {
5781                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5782                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5783         }
5784
5785         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5786                                             sp_sb);
5787
5788         bnx2x_zero_sp_sb(bp);
5789
5790         /* PCI guarantees endianity of regpairs */
5791         sp_sb_data.state                = SB_ENABLED;
5792         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5793         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5794         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5795         sp_sb_data.igu_seg_id           = igu_seg_id;
5796         sp_sb_data.p_func.pf_id         = func;
5797         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5798         sp_sb_data.p_func.vf_id         = 0xff;
5799
5800         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5801
5802         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5803 }
5804
5805 void bnx2x_update_coalesce(struct bnx2x *bp)
5806 {
5807         int i;
5808
5809         for_each_eth_queue(bp, i)
5810                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5811                                          bp->tx_ticks, bp->rx_ticks);
5812 }
5813
5814 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5815 {
5816         spin_lock_init(&bp->spq_lock);
5817         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5818
5819         bp->spq_prod_idx = 0;
5820         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5821         bp->spq_prod_bd = bp->spq;
5822         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5823 }
5824
5825 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5826 {
5827         int i;
5828         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5829                 union event_ring_elem *elem =
5830                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5831
5832                 elem->next_page.addr.hi =
5833                         cpu_to_le32(U64_HI(bp->eq_mapping +
5834                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5835                 elem->next_page.addr.lo =
5836                         cpu_to_le32(U64_LO(bp->eq_mapping +
5837                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5838         }
5839         bp->eq_cons = 0;
5840         bp->eq_prod = NUM_EQ_DESC;
5841         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5842         /* we want a warning message before it gets wrought... */
5843         atomic_set(&bp->eq_spq_left,
5844                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5845 }
5846
5847 /* called with netif_addr_lock_bh() */
5848 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5849                         unsigned long rx_mode_flags,
5850                         unsigned long rx_accept_flags,
5851                         unsigned long tx_accept_flags,
5852                         unsigned long ramrod_flags)
5853 {
5854         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5855         int rc;
5856
5857         memset(&ramrod_param, 0, sizeof(ramrod_param));
5858
5859         /* Prepare ramrod parameters */
5860         ramrod_param.cid = 0;
5861         ramrod_param.cl_id = cl_id;
5862         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5863         ramrod_param.func_id = BP_FUNC(bp);
5864
5865         ramrod_param.pstate = &bp->sp_state;
5866         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5867
5868         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5869         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5870
5871         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5872
5873         ramrod_param.ramrod_flags = ramrod_flags;
5874         ramrod_param.rx_mode_flags = rx_mode_flags;
5875
5876         ramrod_param.rx_accept_flags = rx_accept_flags;
5877         ramrod_param.tx_accept_flags = tx_accept_flags;
5878
5879         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5880         if (rc < 0) {
5881                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5882                 return rc;
5883         }
5884
5885         return 0;
5886 }
5887
5888 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5889                                    unsigned long *rx_accept_flags,
5890                                    unsigned long *tx_accept_flags)
5891 {
5892         /* Clear the flags first */
5893         *rx_accept_flags = 0;
5894         *tx_accept_flags = 0;
5895
5896         switch (rx_mode) {
5897         case BNX2X_RX_MODE_NONE:
5898                 /*
5899                  * 'drop all' supersedes any accept flags that may have been
5900                  * passed to the function.
5901                  */
5902                 break;
5903         case BNX2X_RX_MODE_NORMAL:
5904                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5905                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5906                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5907
5908                 /* internal switching mode */
5909                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5910                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5911                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5912
5913                 break;
5914         case BNX2X_RX_MODE_ALLMULTI:
5915                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5916                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5917                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5918
5919                 /* internal switching mode */
5920                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5921                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5922                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5923
5924                 break;
5925         case BNX2X_RX_MODE_PROMISC:
5926                 /* According to definition of SI mode, iface in promisc mode
5927                  * should receive matched and unmatched (in resolution of port)
5928                  * unicast packets.
5929                  */
5930                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5931                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5932                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5933                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5934
5935                 /* internal switching mode */
5936                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5937                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5938
5939                 if (IS_MF_SI(bp))
5940                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5941                 else
5942                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5943
5944                 break;
5945         default:
5946                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5947                 return -EINVAL;
5948         }
5949
5950         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5951         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5952                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5953                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5954         }
5955
5956         return 0;
5957 }
5958
5959 /* called with netif_addr_lock_bh() */
5960 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5961 {
5962         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5963         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5964         int rc;
5965
5966         if (!NO_FCOE(bp))
5967                 /* Configure rx_mode of FCoE Queue */
5968                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5969
5970         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5971                                      &tx_accept_flags);
5972         if (rc)
5973                 return rc;
5974
5975         __set_bit(RAMROD_RX, &ramrod_flags);
5976         __set_bit(RAMROD_TX, &ramrod_flags);
5977
5978         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5979                                    rx_accept_flags, tx_accept_flags,
5980                                    ramrod_flags);
5981 }
5982
5983 static void bnx2x_init_internal_common(struct bnx2x *bp)
5984 {
5985         int i;
5986
5987         if (IS_MF_SI(bp))
5988                 /*
5989                  * In switch independent mode, the TSTORM needs to accept
5990                  * packets that failed classification, since approximate match
5991                  * mac addresses aren't written to NIG LLH
5992                  */
5993                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5994                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5995         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5996                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5997                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5998
5999         /* Zero this manually as its initialization is
6000            currently missing in the initTool */
6001         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6002                 REG_WR(bp, BAR_USTRORM_INTMEM +
6003                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6004         if (!CHIP_IS_E1x(bp)) {
6005                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6006                         CHIP_INT_MODE_IS_BC(bp) ?
6007                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6008         }
6009 }
6010
6011 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6012 {
6013         switch (load_code) {
6014         case FW_MSG_CODE_DRV_LOAD_COMMON:
6015         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6016                 bnx2x_init_internal_common(bp);
6017                 /* no break */
6018
6019         case FW_MSG_CODE_DRV_LOAD_PORT:
6020                 /* nothing to do */
6021                 /* no break */
6022
6023         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6024                 /* internal memory per function is
6025                    initialized inside bnx2x_pf_init */
6026                 break;
6027
6028         default:
6029                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6030                 break;
6031         }
6032 }
6033
6034 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6035 {
6036         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6037 }
6038
6039 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6040 {
6041         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6042 }
6043
6044 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6045 {
6046         if (CHIP_IS_E1x(fp->bp))
6047                 return BP_L_ID(fp->bp) + fp->index;
6048         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6049                 return bnx2x_fp_igu_sb_id(fp);
6050 }
6051
6052 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6053 {
6054         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6055         u8 cos;
6056         unsigned long q_type = 0;
6057         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6058         fp->rx_queue = fp_idx;
6059         fp->cid = fp_idx;
6060         fp->cl_id = bnx2x_fp_cl_id(fp);
6061         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6062         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6063         /* qZone id equals to FW (per path) client id */
6064         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6065
6066         /* init shortcut */
6067         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6068
6069         /* Setup SB indices */
6070         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6071
6072         /* Configure Queue State object */
6073         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6074         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6075
6076         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6077
6078         /* init tx data */
6079         for_each_cos_in_tx_queue(fp, cos) {
6080                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6081                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6082                                   FP_COS_TO_TXQ(fp, cos, bp),
6083                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6084                 cids[cos] = fp->txdata_ptr[cos]->cid;
6085         }
6086
6087         /* nothing more for vf to do here */
6088         if (IS_VF(bp))
6089                 return;
6090
6091         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6092                       fp->fw_sb_id, fp->igu_sb_id);
6093         bnx2x_update_fpsb_idx(fp);
6094         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6095                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6096                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6097
6098         /**
6099          * Configure classification DBs: Always enable Tx switching
6100          */
6101         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6102
6103         DP(NETIF_MSG_IFUP,
6104            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6105            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6106            fp->igu_sb_id);
6107 }
6108
6109 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6110 {
6111         int i;
6112
6113         for (i = 1; i <= NUM_TX_RINGS; i++) {
6114                 struct eth_tx_next_bd *tx_next_bd =
6115                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6116
6117                 tx_next_bd->addr_hi =
6118                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6119                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6120                 tx_next_bd->addr_lo =
6121                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6122                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6123         }
6124
6125         *txdata->tx_cons_sb = cpu_to_le16(0);
6126
6127         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6128         txdata->tx_db.data.zero_fill1 = 0;
6129         txdata->tx_db.data.prod = 0;
6130
6131         txdata->tx_pkt_prod = 0;
6132         txdata->tx_pkt_cons = 0;
6133         txdata->tx_bd_prod = 0;
6134         txdata->tx_bd_cons = 0;
6135         txdata->tx_pkt = 0;
6136 }
6137
6138 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6139 {
6140         int i;
6141
6142         for_each_tx_queue_cnic(bp, i)
6143                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6144 }
6145
6146 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6147 {
6148         int i;
6149         u8 cos;
6150
6151         for_each_eth_queue(bp, i)
6152                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6153                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6154 }
6155
6156 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6157 {
6158         if (!NO_FCOE(bp))
6159                 bnx2x_init_fcoe_fp(bp);
6160
6161         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6162                       BNX2X_VF_ID_INVALID, false,
6163                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6164
6165         /* ensure status block indices were read */
6166         rmb();
6167         bnx2x_init_rx_rings_cnic(bp);
6168         bnx2x_init_tx_rings_cnic(bp);
6169
6170         /* flush all */
6171         mb();
6172         mmiowb();
6173 }
6174
6175 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6176 {
6177         int i;
6178
6179         /* Setup NIC internals and enable interrupts */
6180         for_each_eth_queue(bp, i)
6181                 bnx2x_init_eth_fp(bp, i);
6182
6183         /* ensure status block indices were read */
6184         rmb();
6185         bnx2x_init_rx_rings(bp);
6186         bnx2x_init_tx_rings(bp);
6187
6188         if (IS_PF(bp)) {
6189                 /* Initialize MOD_ABS interrupts */
6190                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6191                                        bp->common.shmem_base,
6192                                        bp->common.shmem2_base, BP_PORT(bp));
6193
6194                 /* initialize the default status block and sp ring */
6195                 bnx2x_init_def_sb(bp);
6196                 bnx2x_update_dsb_idx(bp);
6197                 bnx2x_init_sp_ring(bp);
6198         } else {
6199                 bnx2x_memset_stats(bp);
6200         }
6201 }
6202
6203 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6204 {
6205         bnx2x_init_eq_ring(bp);
6206         bnx2x_init_internal(bp, load_code);
6207         bnx2x_pf_init(bp);
6208         bnx2x_stats_init(bp);
6209
6210         /* flush all before enabling interrupts */
6211         mb();
6212         mmiowb();
6213
6214         bnx2x_int_enable(bp);
6215
6216         /* Check for SPIO5 */
6217         bnx2x_attn_int_deasserted0(bp,
6218                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6219                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6220 }
6221
6222 /* gzip service functions */
6223 static int bnx2x_gunzip_init(struct bnx2x *bp)
6224 {
6225         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6226                                             &bp->gunzip_mapping, GFP_KERNEL);
6227         if (bp->gunzip_buf  == NULL)
6228                 goto gunzip_nomem1;
6229
6230         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6231         if (bp->strm  == NULL)
6232                 goto gunzip_nomem2;
6233
6234         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6235         if (bp->strm->workspace == NULL)
6236                 goto gunzip_nomem3;
6237
6238         return 0;
6239
6240 gunzip_nomem3:
6241         kfree(bp->strm);
6242         bp->strm = NULL;
6243
6244 gunzip_nomem2:
6245         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6246                           bp->gunzip_mapping);
6247         bp->gunzip_buf = NULL;
6248
6249 gunzip_nomem1:
6250         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6251         return -ENOMEM;
6252 }
6253
6254 static void bnx2x_gunzip_end(struct bnx2x *bp)
6255 {
6256         if (bp->strm) {
6257                 vfree(bp->strm->workspace);
6258                 kfree(bp->strm);
6259                 bp->strm = NULL;
6260         }
6261
6262         if (bp->gunzip_buf) {
6263                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6264                                   bp->gunzip_mapping);
6265                 bp->gunzip_buf = NULL;
6266         }
6267 }
6268
6269 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6270 {
6271         int n, rc;
6272
6273         /* check gzip header */
6274         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6275                 BNX2X_ERR("Bad gzip header\n");
6276                 return -EINVAL;
6277         }
6278
6279         n = 10;
6280
6281 #define FNAME                           0x8
6282
6283         if (zbuf[3] & FNAME)
6284                 while ((zbuf[n++] != 0) && (n < len));
6285
6286         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6287         bp->strm->avail_in = len - n;
6288         bp->strm->next_out = bp->gunzip_buf;
6289         bp->strm->avail_out = FW_BUF_SIZE;
6290
6291         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6292         if (rc != Z_OK)
6293                 return rc;
6294
6295         rc = zlib_inflate(bp->strm, Z_FINISH);
6296         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6297                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6298                            bp->strm->msg);
6299
6300         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6301         if (bp->gunzip_outlen & 0x3)
6302                 netdev_err(bp->dev,
6303                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6304                                 bp->gunzip_outlen);
6305         bp->gunzip_outlen >>= 2;
6306
6307         zlib_inflateEnd(bp->strm);
6308
6309         if (rc == Z_STREAM_END)
6310                 return 0;
6311
6312         return rc;
6313 }
6314
6315 /* nic load/unload */
6316
6317 /*
6318  * General service functions
6319  */
6320
6321 /* send a NIG loopback debug packet */
6322 static void bnx2x_lb_pckt(struct bnx2x *bp)
6323 {
6324         u32 wb_write[3];
6325
6326         /* Ethernet source and destination addresses */
6327         wb_write[0] = 0x55555555;
6328         wb_write[1] = 0x55555555;
6329         wb_write[2] = 0x20;             /* SOP */
6330         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6331
6332         /* NON-IP protocol */
6333         wb_write[0] = 0x09000000;
6334         wb_write[1] = 0x55555555;
6335         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6336         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6337 }
6338
6339 /* some of the internal memories
6340  * are not directly readable from the driver
6341  * to test them we send debug packets
6342  */
6343 static int bnx2x_int_mem_test(struct bnx2x *bp)
6344 {
6345         int factor;
6346         int count, i;
6347         u32 val = 0;
6348
6349         if (CHIP_REV_IS_FPGA(bp))
6350                 factor = 120;
6351         else if (CHIP_REV_IS_EMUL(bp))
6352                 factor = 200;
6353         else
6354                 factor = 1;
6355
6356         /* Disable inputs of parser neighbor blocks */
6357         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6358         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6359         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6360         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6361
6362         /*  Write 0 to parser credits for CFC search request */
6363         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6364
6365         /* send Ethernet packet */
6366         bnx2x_lb_pckt(bp);
6367
6368         /* TODO do i reset NIG statistic? */
6369         /* Wait until NIG register shows 1 packet of size 0x10 */
6370         count = 1000 * factor;
6371         while (count) {
6372
6373                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6374                 val = *bnx2x_sp(bp, wb_data[0]);
6375                 if (val == 0x10)
6376                         break;
6377
6378                 usleep_range(10000, 20000);
6379                 count--;
6380         }
6381         if (val != 0x10) {
6382                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6383                 return -1;
6384         }
6385
6386         /* Wait until PRS register shows 1 packet */
6387         count = 1000 * factor;
6388         while (count) {
6389                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6390                 if (val == 1)
6391                         break;
6392
6393                 usleep_range(10000, 20000);
6394                 count--;
6395         }
6396         if (val != 0x1) {
6397                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6398                 return -2;
6399         }
6400
6401         /* Reset and init BRB, PRS */
6402         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6403         msleep(50);
6404         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6405         msleep(50);
6406         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6407         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6408
6409         DP(NETIF_MSG_HW, "part2\n");
6410
6411         /* Disable inputs of parser neighbor blocks */
6412         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6413         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6414         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6415         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6416
6417         /* Write 0 to parser credits for CFC search request */
6418         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6419
6420         /* send 10 Ethernet packets */
6421         for (i = 0; i < 10; i++)
6422                 bnx2x_lb_pckt(bp);
6423
6424         /* Wait until NIG register shows 10 + 1
6425            packets of size 11*0x10 = 0xb0 */
6426         count = 1000 * factor;
6427         while (count) {
6428
6429                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6430                 val = *bnx2x_sp(bp, wb_data[0]);
6431                 if (val == 0xb0)
6432                         break;
6433
6434                 usleep_range(10000, 20000);
6435                 count--;
6436         }
6437         if (val != 0xb0) {
6438                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6439                 return -3;
6440         }
6441
6442         /* Wait until PRS register shows 2 packets */
6443         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6444         if (val != 2)
6445                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6446
6447         /* Write 1 to parser credits for CFC search request */
6448         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6449
6450         /* Wait until PRS register shows 3 packets */
6451         msleep(10 * factor);
6452         /* Wait until NIG register shows 1 packet of size 0x10 */
6453         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6454         if (val != 3)
6455                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6456
6457         /* clear NIG EOP FIFO */
6458         for (i = 0; i < 11; i++)
6459                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6460         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6461         if (val != 1) {
6462                 BNX2X_ERR("clear of NIG failed\n");
6463                 return -4;
6464         }
6465
6466         /* Reset and init BRB, PRS, NIG */
6467         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6468         msleep(50);
6469         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6470         msleep(50);
6471         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6472         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6473         if (!CNIC_SUPPORT(bp))
6474                 /* set NIC mode */
6475                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6476
6477         /* Enable inputs of parser neighbor blocks */
6478         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6479         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6480         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6481         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6482
6483         DP(NETIF_MSG_HW, "done\n");
6484
6485         return 0; /* OK */
6486 }
6487
6488 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6489 {
6490         u32 val;
6491
6492         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6493         if (!CHIP_IS_E1x(bp))
6494                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6495         else
6496                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6497         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6498         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6499         /*
6500          * mask read length error interrupts in brb for parser
6501          * (parsing unit and 'checksum and crc' unit)
6502          * these errors are legal (PU reads fixed length and CAC can cause
6503          * read length error on truncated packets)
6504          */
6505         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6506         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6507         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6508         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6509         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6510         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6511 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6512 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6513         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6514         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6515         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6516 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6517 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6518         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6519         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6520         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6521         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6522 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6523 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6524
6525         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6526                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6527                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6528         if (!CHIP_IS_E1x(bp))
6529                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6530                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6531         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6532
6533         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6534         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6535         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6536 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6537
6538         if (!CHIP_IS_E1x(bp))
6539                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6540                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6541
6542         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6543         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6544 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6545         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6546 }
6547
6548 static void bnx2x_reset_common(struct bnx2x *bp)
6549 {
6550         u32 val = 0x1400;
6551
6552         /* reset_common */
6553         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6554                0xd3ffff7f);
6555
6556         if (CHIP_IS_E3(bp)) {
6557                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6558                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6559         }
6560
6561         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6562 }
6563
6564 static void bnx2x_setup_dmae(struct bnx2x *bp)
6565 {
6566         bp->dmae_ready = 0;
6567         spin_lock_init(&bp->dmae_lock);
6568 }
6569
6570 static void bnx2x_init_pxp(struct bnx2x *bp)
6571 {
6572         u16 devctl;
6573         int r_order, w_order;
6574
6575         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6576         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6577         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6578         if (bp->mrrs == -1)
6579                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6580         else {
6581                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6582                 r_order = bp->mrrs;
6583         }
6584
6585         bnx2x_init_pxp_arb(bp, r_order, w_order);
6586 }
6587
6588 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6589 {
6590         int is_required;
6591         u32 val;
6592         int port;
6593
6594         if (BP_NOMCP(bp))
6595                 return;
6596
6597         is_required = 0;
6598         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6599               SHARED_HW_CFG_FAN_FAILURE_MASK;
6600
6601         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6602                 is_required = 1;
6603
6604         /*
6605          * The fan failure mechanism is usually related to the PHY type since
6606          * the power consumption of the board is affected by the PHY. Currently,
6607          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6608          */
6609         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6610                 for (port = PORT_0; port < PORT_MAX; port++) {
6611                         is_required |=
6612                                 bnx2x_fan_failure_det_req(
6613                                         bp,
6614                                         bp->common.shmem_base,
6615                                         bp->common.shmem2_base,
6616                                         port);
6617                 }
6618
6619         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6620
6621         if (is_required == 0)
6622                 return;
6623
6624         /* Fan failure is indicated by SPIO 5 */
6625         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6626
6627         /* set to active low mode */
6628         val = REG_RD(bp, MISC_REG_SPIO_INT);
6629         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6630         REG_WR(bp, MISC_REG_SPIO_INT, val);
6631
6632         /* enable interrupt to signal the IGU */
6633         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6634         val |= MISC_SPIO_SPIO5;
6635         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6636 }
6637
6638 void bnx2x_pf_disable(struct bnx2x *bp)
6639 {
6640         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6641         val &= ~IGU_PF_CONF_FUNC_EN;
6642
6643         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6644         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6645         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6646 }
6647
6648 static void bnx2x__common_init_phy(struct bnx2x *bp)
6649 {
6650         u32 shmem_base[2], shmem2_base[2];
6651         /* Avoid common init in case MFW supports LFA */
6652         if (SHMEM2_RD(bp, size) >
6653             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6654                 return;
6655         shmem_base[0] =  bp->common.shmem_base;
6656         shmem2_base[0] = bp->common.shmem2_base;
6657         if (!CHIP_IS_E1x(bp)) {
6658                 shmem_base[1] =
6659                         SHMEM2_RD(bp, other_shmem_base_addr);
6660                 shmem2_base[1] =
6661                         SHMEM2_RD(bp, other_shmem2_base_addr);
6662         }
6663         bnx2x_acquire_phy_lock(bp);
6664         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6665                               bp->common.chip_id);
6666         bnx2x_release_phy_lock(bp);
6667 }
6668
6669 /**
6670  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6671  *
6672  * @bp:         driver handle
6673  */
6674 static int bnx2x_init_hw_common(struct bnx2x *bp)
6675 {
6676         u32 val;
6677
6678         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6679
6680         /*
6681          * take the RESET lock to protect undi_unload flow from accessing
6682          * registers while we're resetting the chip
6683          */
6684         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6685
6686         bnx2x_reset_common(bp);
6687         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6688
6689         val = 0xfffc;
6690         if (CHIP_IS_E3(bp)) {
6691                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6692                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6693         }
6694         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6695
6696         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6697
6698         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6699
6700         if (!CHIP_IS_E1x(bp)) {
6701                 u8 abs_func_id;
6702
6703                 /**
6704                  * 4-port mode or 2-port mode we need to turn of master-enable
6705                  * for everyone, after that, turn it back on for self.
6706                  * so, we disregard multi-function or not, and always disable
6707                  * for all functions on the given path, this means 0,2,4,6 for
6708                  * path 0 and 1,3,5,7 for path 1
6709                  */
6710                 for (abs_func_id = BP_PATH(bp);
6711                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6712                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6713                                 REG_WR(bp,
6714                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6715                                     1);
6716                                 continue;
6717                         }
6718
6719                         bnx2x_pretend_func(bp, abs_func_id);
6720                         /* clear pf enable */
6721                         bnx2x_pf_disable(bp);
6722                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6723                 }
6724         }
6725
6726         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6727         if (CHIP_IS_E1(bp)) {
6728                 /* enable HW interrupt from PXP on USDM overflow
6729                    bit 16 on INT_MASK_0 */
6730                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6731         }
6732
6733         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6734         bnx2x_init_pxp(bp);
6735
6736 #ifdef __BIG_ENDIAN
6737         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6738         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6739         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6740         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6741         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6742         /* make sure this value is 0 */
6743         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6744
6745 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6746         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6747         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6748         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6749         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6750 #endif
6751
6752         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6753
6754         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6755                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6756
6757         /* let the HW do it's magic ... */
6758         msleep(100);
6759         /* finish PXP init */
6760         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6761         if (val != 1) {
6762                 BNX2X_ERR("PXP2 CFG failed\n");
6763                 return -EBUSY;
6764         }
6765         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6766         if (val != 1) {
6767                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6768                 return -EBUSY;
6769         }
6770
6771         /* Timers bug workaround E2 only. We need to set the entire ILT to
6772          * have entries with value "0" and valid bit on.
6773          * This needs to be done by the first PF that is loaded in a path
6774          * (i.e. common phase)
6775          */
6776         if (!CHIP_IS_E1x(bp)) {
6777 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6778  * (i.e. vnic3) to start even if it is marked as "scan-off".
6779  * This occurs when a different function (func2,3) is being marked
6780  * as "scan-off". Real-life scenario for example: if a driver is being
6781  * load-unloaded while func6,7 are down. This will cause the timer to access
6782  * the ilt, translate to a logical address and send a request to read/write.
6783  * Since the ilt for the function that is down is not valid, this will cause
6784  * a translation error which is unrecoverable.
6785  * The Workaround is intended to make sure that when this happens nothing fatal
6786  * will occur. The workaround:
6787  *      1.  First PF driver which loads on a path will:
6788  *              a.  After taking the chip out of reset, by using pretend,
6789  *                  it will write "0" to the following registers of
6790  *                  the other vnics.
6791  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6792  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6793  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6794  *                  And for itself it will write '1' to
6795  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6796  *                  dmae-operations (writing to pram for example.)
6797  *                  note: can be done for only function 6,7 but cleaner this
6798  *                        way.
6799  *              b.  Write zero+valid to the entire ILT.
6800  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6801  *                  VNIC3 (of that port). The range allocated will be the
6802  *                  entire ILT. This is needed to prevent  ILT range error.
6803  *      2.  Any PF driver load flow:
6804  *              a.  ILT update with the physical addresses of the allocated
6805  *                  logical pages.
6806  *              b.  Wait 20msec. - note that this timeout is needed to make
6807  *                  sure there are no requests in one of the PXP internal
6808  *                  queues with "old" ILT addresses.
6809  *              c.  PF enable in the PGLC.
6810  *              d.  Clear the was_error of the PF in the PGLC. (could have
6811  *                  occurred while driver was down)
6812  *              e.  PF enable in the CFC (WEAK + STRONG)
6813  *              f.  Timers scan enable
6814  *      3.  PF driver unload flow:
6815  *              a.  Clear the Timers scan_en.
6816  *              b.  Polling for scan_on=0 for that PF.
6817  *              c.  Clear the PF enable bit in the PXP.
6818  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6819  *              e.  Write zero+valid to all ILT entries (The valid bit must
6820  *                  stay set)
6821  *              f.  If this is VNIC 3 of a port then also init
6822  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6823  *                  to the last entry in the ILT.
6824  *
6825  *      Notes:
6826  *      Currently the PF error in the PGLC is non recoverable.
6827  *      In the future the there will be a recovery routine for this error.
6828  *      Currently attention is masked.
6829  *      Having an MCP lock on the load/unload process does not guarantee that
6830  *      there is no Timer disable during Func6/7 enable. This is because the
6831  *      Timers scan is currently being cleared by the MCP on FLR.
6832  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6833  *      there is error before clearing it. But the flow above is simpler and
6834  *      more general.
6835  *      All ILT entries are written by zero+valid and not just PF6/7
6836  *      ILT entries since in the future the ILT entries allocation for
6837  *      PF-s might be dynamic.
6838  */
6839                 struct ilt_client_info ilt_cli;
6840                 struct bnx2x_ilt ilt;
6841                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6842                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6843
6844                 /* initialize dummy TM client */
6845                 ilt_cli.start = 0;
6846                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6847                 ilt_cli.client_num = ILT_CLIENT_TM;
6848
6849                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6850                  * Step 2: set the timers first/last ilt entry to point
6851                  * to the entire range to prevent ILT range error for 3rd/4th
6852                  * vnic (this code assumes existence of the vnic)
6853                  *
6854                  * both steps performed by call to bnx2x_ilt_client_init_op()
6855                  * with dummy TM client
6856                  *
6857                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6858                  * and his brother are split registers
6859                  */
6860                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6861                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6862                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6863
6864                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6865                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6866                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6867         }
6868
6869         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6870         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6871
6872         if (!CHIP_IS_E1x(bp)) {
6873                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6874                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6875                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6876
6877                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6878
6879                 /* let the HW do it's magic ... */
6880                 do {
6881                         msleep(200);
6882                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6883                 } while (factor-- && (val != 1));
6884
6885                 if (val != 1) {
6886                         BNX2X_ERR("ATC_INIT failed\n");
6887                         return -EBUSY;
6888                 }
6889         }
6890
6891         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6892
6893         bnx2x_iov_init_dmae(bp);
6894
6895         /* clean the DMAE memory */
6896         bp->dmae_ready = 1;
6897         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6898
6899         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6900
6901         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6902
6903         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6904
6905         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6906
6907         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6908         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6909         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6910         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6911
6912         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6913
6914         /* QM queues pointers table */
6915         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6916
6917         /* soft reset pulse */
6918         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6919         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6920
6921         if (CNIC_SUPPORT(bp))
6922                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6923
6924         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6925
6926         if (!CHIP_REV_IS_SLOW(bp))
6927                 /* enable hw interrupt from doorbell Q */
6928                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6929
6930         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6931
6932         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6933         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6934
6935         if (!CHIP_IS_E1(bp))
6936                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6937
6938         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6939                 if (IS_MF_AFEX(bp)) {
6940                         /* configure that VNTag and VLAN headers must be
6941                          * received in afex mode
6942                          */
6943                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6944                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6945                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6946                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6947                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6948                 } else {
6949                         /* Bit-map indicating which L2 hdrs may appear
6950                          * after the basic Ethernet header
6951                          */
6952                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6953                                bp->path_has_ovlan ? 7 : 6);
6954                 }
6955         }
6956
6957         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6958         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6959         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6960         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6961
6962         if (!CHIP_IS_E1x(bp)) {
6963                 /* reset VFC memories */
6964                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6965                            VFC_MEMORIES_RST_REG_CAM_RST |
6966                            VFC_MEMORIES_RST_REG_RAM_RST);
6967                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6968                            VFC_MEMORIES_RST_REG_CAM_RST |
6969                            VFC_MEMORIES_RST_REG_RAM_RST);
6970
6971                 msleep(20);
6972         }
6973
6974         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6975         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6976         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6977         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6978
6979         /* sync semi rtc */
6980         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6981                0x80000000);
6982         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6983                0x80000000);
6984
6985         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6986         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6987         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6988
6989         if (!CHIP_IS_E1x(bp)) {
6990                 if (IS_MF_AFEX(bp)) {
6991                         /* configure that VNTag and VLAN headers must be
6992                          * sent in afex mode
6993                          */
6994                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6995                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6996                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6997                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6998                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6999                 } else {
7000                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7001                                bp->path_has_ovlan ? 7 : 6);
7002                 }
7003         }
7004
7005         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7006
7007         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7008
7009         if (CNIC_SUPPORT(bp)) {
7010                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7011                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7012                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7013                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7014                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7015                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7016                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7017                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7018                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7019                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7020         }
7021         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7022
7023         if (sizeof(union cdu_context) != 1024)
7024                 /* we currently assume that a context is 1024 bytes */
7025                 dev_alert(&bp->pdev->dev,
7026                           "please adjust the size of cdu_context(%ld)\n",
7027                           (long)sizeof(union cdu_context));
7028
7029         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7030         val = (4 << 24) + (0 << 12) + 1024;
7031         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7032
7033         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7034         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7035         /* enable context validation interrupt from CFC */
7036         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7037
7038         /* set the thresholds to prevent CFC/CDU race */
7039         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7040
7041         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7042
7043         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7044                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7045
7046         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7047         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7048
7049         /* Reset PCIE errors for debug */
7050         REG_WR(bp, 0x2814, 0xffffffff);
7051         REG_WR(bp, 0x3820, 0xffffffff);
7052
7053         if (!CHIP_IS_E1x(bp)) {
7054                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7055                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7056                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7057                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7058                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7059                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7060                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7061                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7062                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7063                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7064                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7065         }
7066
7067         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7068         if (!CHIP_IS_E1(bp)) {
7069                 /* in E3 this done in per-port section */
7070                 if (!CHIP_IS_E3(bp))
7071                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7072         }
7073         if (CHIP_IS_E1H(bp))
7074                 /* not applicable for E2 (and above ...) */
7075                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7076
7077         if (CHIP_REV_IS_SLOW(bp))
7078                 msleep(200);
7079
7080         /* finish CFC init */
7081         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7082         if (val != 1) {
7083                 BNX2X_ERR("CFC LL_INIT failed\n");
7084                 return -EBUSY;
7085         }
7086         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7087         if (val != 1) {
7088                 BNX2X_ERR("CFC AC_INIT failed\n");
7089                 return -EBUSY;
7090         }
7091         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7092         if (val != 1) {
7093                 BNX2X_ERR("CFC CAM_INIT failed\n");
7094                 return -EBUSY;
7095         }
7096         REG_WR(bp, CFC_REG_DEBUG0, 0);
7097
7098         if (CHIP_IS_E1(bp)) {
7099                 /* read NIG statistic
7100                    to see if this is our first up since powerup */
7101                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7102                 val = *bnx2x_sp(bp, wb_data[0]);
7103
7104                 /* do internal memory self test */
7105                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7106                         BNX2X_ERR("internal mem self test failed\n");
7107                         return -EBUSY;
7108                 }
7109         }
7110
7111         bnx2x_setup_fan_failure_detection(bp);
7112
7113         /* clear PXP2 attentions */
7114         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7115
7116         bnx2x_enable_blocks_attention(bp);
7117         bnx2x_enable_blocks_parity(bp);
7118
7119         if (!BP_NOMCP(bp)) {
7120                 if (CHIP_IS_E1x(bp))
7121                         bnx2x__common_init_phy(bp);
7122         } else
7123                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7124
7125         return 0;
7126 }
7127
7128 /**
7129  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7130  *
7131  * @bp:         driver handle
7132  */
7133 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7134 {
7135         int rc = bnx2x_init_hw_common(bp);
7136
7137         if (rc)
7138                 return rc;
7139
7140         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7141         if (!BP_NOMCP(bp))
7142                 bnx2x__common_init_phy(bp);
7143
7144         return 0;
7145 }
7146
7147 static int bnx2x_init_hw_port(struct bnx2x *bp)
7148 {
7149         int port = BP_PORT(bp);
7150         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7151         u32 low, high;
7152         u32 val, reg;
7153
7154         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7155
7156         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7157
7158         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7159         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7160         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7161
7162         /* Timers bug workaround: disables the pf_master bit in pglue at
7163          * common phase, we need to enable it here before any dmae access are
7164          * attempted. Therefore we manually added the enable-master to the
7165          * port phase (it also happens in the function phase)
7166          */
7167         if (!CHIP_IS_E1x(bp))
7168                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7169
7170         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7171         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7172         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7173         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7174
7175         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7176         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7177         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7178         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7179
7180         /* QM cid (connection) count */
7181         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7182
7183         if (CNIC_SUPPORT(bp)) {
7184                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7185                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7186                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7187         }
7188
7189         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7190
7191         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7192
7193         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7194
7195                 if (IS_MF(bp))
7196                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7197                 else if (bp->dev->mtu > 4096) {
7198                         if (bp->flags & ONE_PORT_FLAG)
7199                                 low = 160;
7200                         else {
7201                                 val = bp->dev->mtu;
7202                                 /* (24*1024 + val*4)/256 */
7203                                 low = 96 + (val/64) +
7204                                                 ((val % 64) ? 1 : 0);
7205                         }
7206                 } else
7207                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7208                 high = low + 56;        /* 14*1024/256 */
7209                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7210                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7211         }
7212
7213         if (CHIP_MODE_IS_4_PORT(bp))
7214                 REG_WR(bp, (BP_PORT(bp) ?
7215                             BRB1_REG_MAC_GUARANTIED_1 :
7216                             BRB1_REG_MAC_GUARANTIED_0), 40);
7217
7218         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7219         if (CHIP_IS_E3B0(bp)) {
7220                 if (IS_MF_AFEX(bp)) {
7221                         /* configure headers for AFEX mode */
7222                         REG_WR(bp, BP_PORT(bp) ?
7223                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7224                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7225                         REG_WR(bp, BP_PORT(bp) ?
7226                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7227                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7228                         REG_WR(bp, BP_PORT(bp) ?
7229                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7230                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7231                 } else {
7232                         /* Ovlan exists only if we are in multi-function +
7233                          * switch-dependent mode, in switch-independent there
7234                          * is no ovlan headers
7235                          */
7236                         REG_WR(bp, BP_PORT(bp) ?
7237                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7238                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7239                                (bp->path_has_ovlan ? 7 : 6));
7240                 }
7241         }
7242
7243         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7244         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7245         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7246         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7247
7248         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7249         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7250         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7251         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7252
7253         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7254         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7255
7256         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7257
7258         if (CHIP_IS_E1x(bp)) {
7259                 /* configure PBF to work without PAUSE mtu 9000 */
7260                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7261
7262                 /* update threshold */
7263                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7264                 /* update init credit */
7265                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7266
7267                 /* probe changes */
7268                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7269                 udelay(50);
7270                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7271         }
7272
7273         if (CNIC_SUPPORT(bp))
7274                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7275
7276         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7277         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7278
7279         if (CHIP_IS_E1(bp)) {
7280                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7281                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7282         }
7283         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7284
7285         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7286
7287         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7288         /* init aeu_mask_attn_func_0/1:
7289          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7290          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7291          *             bits 4-7 are used for "per vn group attention" */
7292         val = IS_MF(bp) ? 0xF7 : 0x7;
7293         /* Enable DCBX attention for all but E1 */
7294         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7295         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7296
7297         /* SCPAD_PARITY should NOT trigger close the gates */
7298         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7299         REG_WR(bp, reg,
7300                REG_RD(bp, reg) &
7301                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7302
7303         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7304         REG_WR(bp, reg,
7305                REG_RD(bp, reg) &
7306                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7307
7308         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7309
7310         if (!CHIP_IS_E1x(bp)) {
7311                 /* Bit-map indicating which L2 hdrs may appear after the
7312                  * basic Ethernet header
7313                  */
7314                 if (IS_MF_AFEX(bp))
7315                         REG_WR(bp, BP_PORT(bp) ?
7316                                NIG_REG_P1_HDRS_AFTER_BASIC :
7317                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7318                 else
7319                         REG_WR(bp, BP_PORT(bp) ?
7320                                NIG_REG_P1_HDRS_AFTER_BASIC :
7321                                NIG_REG_P0_HDRS_AFTER_BASIC,
7322                                IS_MF_SD(bp) ? 7 : 6);
7323
7324                 if (CHIP_IS_E3(bp))
7325                         REG_WR(bp, BP_PORT(bp) ?
7326                                    NIG_REG_LLH1_MF_MODE :
7327                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7328         }
7329         if (!CHIP_IS_E3(bp))
7330                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7331
7332         if (!CHIP_IS_E1(bp)) {
7333                 /* 0x2 disable mf_ov, 0x1 enable */
7334                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7335                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7336
7337                 if (!CHIP_IS_E1x(bp)) {
7338                         val = 0;
7339                         switch (bp->mf_mode) {
7340                         case MULTI_FUNCTION_SD:
7341                                 val = 1;
7342                                 break;
7343                         case MULTI_FUNCTION_SI:
7344                         case MULTI_FUNCTION_AFEX:
7345                                 val = 2;
7346                                 break;
7347                         }
7348
7349                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7350                                                   NIG_REG_LLH0_CLS_TYPE), val);
7351                 }
7352                 {
7353                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7354                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7355                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7356                 }
7357         }
7358
7359         /* If SPIO5 is set to generate interrupts, enable it for this port */
7360         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7361         if (val & MISC_SPIO_SPIO5) {
7362                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7363                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7364                 val = REG_RD(bp, reg_addr);
7365                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7366                 REG_WR(bp, reg_addr, val);
7367         }
7368
7369         return 0;
7370 }
7371
7372 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7373 {
7374         int reg;
7375         u32 wb_write[2];
7376
7377         if (CHIP_IS_E1(bp))
7378                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7379         else
7380                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7381
7382         wb_write[0] = ONCHIP_ADDR1(addr);
7383         wb_write[1] = ONCHIP_ADDR2(addr);
7384         REG_WR_DMAE(bp, reg, wb_write, 2);
7385 }
7386
7387 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7388 {
7389         u32 data, ctl, cnt = 100;
7390         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7391         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7392         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7393         u32 sb_bit =  1 << (idu_sb_id%32);
7394         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7395         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7396
7397         /* Not supported in BC mode */
7398         if (CHIP_INT_MODE_IS_BC(bp))
7399                 return;
7400
7401         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7402                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7403                 IGU_REGULAR_CLEANUP_SET                         |
7404                 IGU_REGULAR_BCLEANUP;
7405
7406         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7407               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7408               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7409
7410         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7411                          data, igu_addr_data);
7412         REG_WR(bp, igu_addr_data, data);
7413         mmiowb();
7414         barrier();
7415         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7416                           ctl, igu_addr_ctl);
7417         REG_WR(bp, igu_addr_ctl, ctl);
7418         mmiowb();
7419         barrier();
7420
7421         /* wait for clean up to finish */
7422         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7423                 msleep(20);
7424
7425         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7426                 DP(NETIF_MSG_HW,
7427                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7428                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7429         }
7430 }
7431
7432 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7433 {
7434         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7435 }
7436
7437 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7438 {
7439         u32 i, base = FUNC_ILT_BASE(func);
7440         for (i = base; i < base + ILT_PER_FUNC; i++)
7441                 bnx2x_ilt_wr(bp, i, 0);
7442 }
7443
7444 static void bnx2x_init_searcher(struct bnx2x *bp)
7445 {
7446         int port = BP_PORT(bp);
7447         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7448         /* T1 hash bits value determines the T1 number of entries */
7449         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7450 }
7451
7452 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7453 {
7454         int rc;
7455         struct bnx2x_func_state_params func_params = {NULL};
7456         struct bnx2x_func_switch_update_params *switch_update_params =
7457                 &func_params.params.switch_update;
7458
7459         /* Prepare parameters for function state transitions */
7460         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7461         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7462
7463         func_params.f_obj = &bp->func_obj;
7464         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7465
7466         /* Function parameters */
7467         switch_update_params->suspend = suspend;
7468
7469         rc = bnx2x_func_state_change(bp, &func_params);
7470
7471         return rc;
7472 }
7473
7474 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7475 {
7476         int rc, i, port = BP_PORT(bp);
7477         int vlan_en = 0, mac_en[NUM_MACS];
7478
7479         /* Close input from network */
7480         if (bp->mf_mode == SINGLE_FUNCTION) {
7481                 bnx2x_set_rx_filter(&bp->link_params, 0);
7482         } else {
7483                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7484                                    NIG_REG_LLH0_FUNC_EN);
7485                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7486                           NIG_REG_LLH0_FUNC_EN, 0);
7487                 for (i = 0; i < NUM_MACS; i++) {
7488                         mac_en[i] = REG_RD(bp, port ?
7489                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7490                                               4 * i) :
7491                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7492                                               4 * i));
7493                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7494                                               4 * i) :
7495                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7496                 }
7497         }
7498
7499         /* Close BMC to host */
7500         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7501                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7502
7503         /* Suspend Tx switching to the PF. Completion of this ramrod
7504          * further guarantees that all the packets of that PF / child
7505          * VFs in BRB were processed by the Parser, so it is safe to
7506          * change the NIC_MODE register.
7507          */
7508         rc = bnx2x_func_switch_update(bp, 1);
7509         if (rc) {
7510                 BNX2X_ERR("Can't suspend tx-switching!\n");
7511                 return rc;
7512         }
7513
7514         /* Change NIC_MODE register */
7515         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7516
7517         /* Open input from network */
7518         if (bp->mf_mode == SINGLE_FUNCTION) {
7519                 bnx2x_set_rx_filter(&bp->link_params, 1);
7520         } else {
7521                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7522                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7523                 for (i = 0; i < NUM_MACS; i++) {
7524                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7525                                               4 * i) :
7526                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7527                                   mac_en[i]);
7528                 }
7529         }
7530
7531         /* Enable BMC to host */
7532         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7533                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7534
7535         /* Resume Tx switching to the PF */
7536         rc = bnx2x_func_switch_update(bp, 0);
7537         if (rc) {
7538                 BNX2X_ERR("Can't resume tx-switching!\n");
7539                 return rc;
7540         }
7541
7542         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7543         return 0;
7544 }
7545
7546 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7547 {
7548         int rc;
7549
7550         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7551
7552         if (CONFIGURE_NIC_MODE(bp)) {
7553                 /* Configure searcher as part of function hw init */
7554                 bnx2x_init_searcher(bp);
7555
7556                 /* Reset NIC mode */
7557                 rc = bnx2x_reset_nic_mode(bp);
7558                 if (rc)
7559                         BNX2X_ERR("Can't change NIC mode!\n");
7560                 return rc;
7561         }
7562
7563         return 0;
7564 }
7565
7566 static int bnx2x_init_hw_func(struct bnx2x *bp)
7567 {
7568         int port = BP_PORT(bp);
7569         int func = BP_FUNC(bp);
7570         int init_phase = PHASE_PF0 + func;
7571         struct bnx2x_ilt *ilt = BP_ILT(bp);
7572         u16 cdu_ilt_start;
7573         u32 addr, val;
7574         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7575         int i, main_mem_width, rc;
7576
7577         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7578
7579         /* FLR cleanup - hmmm */
7580         if (!CHIP_IS_E1x(bp)) {
7581                 rc = bnx2x_pf_flr_clnup(bp);
7582                 if (rc) {
7583                         bnx2x_fw_dump(bp);
7584                         return rc;
7585                 }
7586         }
7587
7588         /* set MSI reconfigure capability */
7589         if (bp->common.int_block == INT_BLOCK_HC) {
7590                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7591                 val = REG_RD(bp, addr);
7592                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7593                 REG_WR(bp, addr, val);
7594         }
7595
7596         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7597         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7598
7599         ilt = BP_ILT(bp);
7600         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7601
7602         if (IS_SRIOV(bp))
7603                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7604         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7605
7606         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7607          * those of the VFs, so start line should be reset
7608          */
7609         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7610         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7611                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7612                 ilt->lines[cdu_ilt_start + i].page_mapping =
7613                         bp->context[i].cxt_mapping;
7614                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7615         }
7616
7617         bnx2x_ilt_init_op(bp, INITOP_SET);
7618
7619         if (!CONFIGURE_NIC_MODE(bp)) {
7620                 bnx2x_init_searcher(bp);
7621                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7622                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7623         } else {
7624                 /* Set NIC mode */
7625                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7626                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7627         }
7628
7629         if (!CHIP_IS_E1x(bp)) {
7630                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7631
7632                 /* Turn on a single ISR mode in IGU if driver is going to use
7633                  * INT#x or MSI
7634                  */
7635                 if (!(bp->flags & USING_MSIX_FLAG))
7636                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7637                 /*
7638                  * Timers workaround bug: function init part.
7639                  * Need to wait 20msec after initializing ILT,
7640                  * needed to make sure there are no requests in
7641                  * one of the PXP internal queues with "old" ILT addresses
7642                  */
7643                 msleep(20);
7644                 /*
7645                  * Master enable - Due to WB DMAE writes performed before this
7646                  * register is re-initialized as part of the regular function
7647                  * init
7648                  */
7649                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7650                 /* Enable the function in IGU */
7651                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7652         }
7653
7654         bp->dmae_ready = 1;
7655
7656         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7657
7658         if (!CHIP_IS_E1x(bp))
7659                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7660
7661         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7662         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7663         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7664         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7665         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7666         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7667         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7668         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7669         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7670         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7671         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7672         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7673         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7674
7675         if (!CHIP_IS_E1x(bp))
7676                 REG_WR(bp, QM_REG_PF_EN, 1);
7677
7678         if (!CHIP_IS_E1x(bp)) {
7679                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7680                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7681                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7682                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7683         }
7684         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7685
7686         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7687         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7688         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7689
7690         bnx2x_iov_init_dq(bp);
7691
7692         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7693         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7694         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7695         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7696         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7697         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7698         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7699         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7700         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7701         if (!CHIP_IS_E1x(bp))
7702                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7703
7704         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7705
7706         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7707
7708         if (!CHIP_IS_E1x(bp))
7709                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7710
7711         if (IS_MF(bp)) {
7712                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7713                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7714         }
7715
7716         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7717
7718         /* HC init per function */
7719         if (bp->common.int_block == INT_BLOCK_HC) {
7720                 if (CHIP_IS_E1H(bp)) {
7721                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7722
7723                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7724                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7725                 }
7726                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7727
7728         } else {
7729                 int num_segs, sb_idx, prod_offset;
7730
7731                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7732
7733                 if (!CHIP_IS_E1x(bp)) {
7734                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7735                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7736                 }
7737
7738                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7739
7740                 if (!CHIP_IS_E1x(bp)) {
7741                         int dsb_idx = 0;
7742                         /**
7743                          * Producer memory:
7744                          * E2 mode: address 0-135 match to the mapping memory;
7745                          * 136 - PF0 default prod; 137 - PF1 default prod;
7746                          * 138 - PF2 default prod; 139 - PF3 default prod;
7747                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7748                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7749                          * 144-147 reserved.
7750                          *
7751                          * E1.5 mode - In backward compatible mode;
7752                          * for non default SB; each even line in the memory
7753                          * holds the U producer and each odd line hold
7754                          * the C producer. The first 128 producers are for
7755                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7756                          * producers are for the DSB for each PF.
7757                          * Each PF has five segments: (the order inside each
7758                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7759                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7760                          * 144-147 attn prods;
7761                          */
7762                         /* non-default-status-blocks */
7763                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7764                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7765                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7766                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7767                                         num_segs;
7768
7769                                 for (i = 0; i < num_segs; i++) {
7770                                         addr = IGU_REG_PROD_CONS_MEMORY +
7771                                                         (prod_offset + i) * 4;
7772                                         REG_WR(bp, addr, 0);
7773                                 }
7774                                 /* send consumer update with value 0 */
7775                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7776                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7777                                 bnx2x_igu_clear_sb(bp,
7778                                                    bp->igu_base_sb + sb_idx);
7779                         }
7780
7781                         /* default-status-blocks */
7782                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7783                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7784
7785                         if (CHIP_MODE_IS_4_PORT(bp))
7786                                 dsb_idx = BP_FUNC(bp);
7787                         else
7788                                 dsb_idx = BP_VN(bp);
7789
7790                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7791                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7792                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7793
7794                         /*
7795                          * igu prods come in chunks of E1HVN_MAX (4) -
7796                          * does not matters what is the current chip mode
7797                          */
7798                         for (i = 0; i < (num_segs * E1HVN_MAX);
7799                              i += E1HVN_MAX) {
7800                                 addr = IGU_REG_PROD_CONS_MEMORY +
7801                                                         (prod_offset + i)*4;
7802                                 REG_WR(bp, addr, 0);
7803                         }
7804                         /* send consumer update with 0 */
7805                         if (CHIP_INT_MODE_IS_BC(bp)) {
7806                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7807                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7808                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7809                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7810                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7811                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7812                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7813                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7814                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7815                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7816                         } else {
7817                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7818                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7819                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7820                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7821                         }
7822                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7823
7824                         /* !!! These should become driver const once
7825                            rf-tool supports split-68 const */
7826                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7827                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7828                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7829                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7830                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7831                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7832                 }
7833         }
7834
7835         /* Reset PCIE errors for debug */
7836         REG_WR(bp, 0x2114, 0xffffffff);
7837         REG_WR(bp, 0x2120, 0xffffffff);
7838
7839         if (CHIP_IS_E1x(bp)) {
7840                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7841                 main_mem_base = HC_REG_MAIN_MEMORY +
7842                                 BP_PORT(bp) * (main_mem_size * 4);
7843                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7844                 main_mem_width = 8;
7845
7846                 val = REG_RD(bp, main_mem_prty_clr);
7847                 if (val)
7848                         DP(NETIF_MSG_HW,
7849                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7850                            val);
7851
7852                 /* Clear "false" parity errors in MSI-X table */
7853                 for (i = main_mem_base;
7854                      i < main_mem_base + main_mem_size * 4;
7855                      i += main_mem_width) {
7856                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7857                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7858                                          i, main_mem_width / 4);
7859                 }
7860                 /* Clear HC parity attention */
7861                 REG_RD(bp, main_mem_prty_clr);
7862         }
7863
7864 #ifdef BNX2X_STOP_ON_ERROR
7865         /* Enable STORMs SP logging */
7866         REG_WR8(bp, BAR_USTRORM_INTMEM +
7867                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7868         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7869                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7870         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7871                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7872         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7873                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7874 #endif
7875
7876         bnx2x_phy_probe(&bp->link_params);
7877
7878         return 0;
7879 }
7880
7881 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7882 {
7883         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7884
7885         if (!CHIP_IS_E1x(bp))
7886                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7887                                sizeof(struct host_hc_status_block_e2));
7888         else
7889                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7890                                sizeof(struct host_hc_status_block_e1x));
7891
7892         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7893 }
7894
7895 void bnx2x_free_mem(struct bnx2x *bp)
7896 {
7897         int i;
7898
7899         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7900                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7901
7902         if (IS_VF(bp))
7903                 return;
7904
7905         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7906                        sizeof(struct host_sp_status_block));
7907
7908         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7909                        sizeof(struct bnx2x_slowpath));
7910
7911         for (i = 0; i < L2_ILT_LINES(bp); i++)
7912                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7913                                bp->context[i].size);
7914         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7915
7916         BNX2X_FREE(bp->ilt->lines);
7917
7918         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7919
7920         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7921                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7922
7923         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7924
7925         bnx2x_iov_free_mem(bp);
7926 }
7927
7928 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7929 {
7930         if (!CHIP_IS_E1x(bp))
7931                 /* size = the status block + ramrod buffers */
7932                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7933                                 sizeof(struct host_hc_status_block_e2));
7934         else
7935                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7936                                 &bp->cnic_sb_mapping,
7937                                 sizeof(struct
7938                                        host_hc_status_block_e1x));
7939
7940         if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7941                 /* allocate searcher T2 table, as it wasn't allocated before */
7942                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7943
7944         /* write address to which L5 should insert its values */
7945         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7946                 &bp->slowpath->drv_info_to_mcp;
7947
7948         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7949                 goto alloc_mem_err;
7950
7951         return 0;
7952
7953 alloc_mem_err:
7954         bnx2x_free_mem_cnic(bp);
7955         BNX2X_ERR("Can't allocate memory\n");
7956         return -ENOMEM;
7957 }
7958
7959 int bnx2x_alloc_mem(struct bnx2x *bp)
7960 {
7961         int i, allocated, context_size;
7962
7963         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7964                 /* allocate searcher T2 table */
7965                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7966
7967         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7968                         sizeof(struct host_sp_status_block));
7969
7970         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7971                         sizeof(struct bnx2x_slowpath));
7972
7973         /* Allocate memory for CDU context:
7974          * This memory is allocated separately and not in the generic ILT
7975          * functions because CDU differs in few aspects:
7976          * 1. There are multiple entities allocating memory for context -
7977          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7978          * its own ILT lines.
7979          * 2. Since CDU page-size is not a single 4KB page (which is the case
7980          * for the other ILT clients), to be efficient we want to support
7981          * allocation of sub-page-size in the last entry.
7982          * 3. Context pointers are used by the driver to pass to FW / update
7983          * the context (for the other ILT clients the pointers are used just to
7984          * free the memory during unload).
7985          */
7986         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7987
7988         for (i = 0, allocated = 0; allocated < context_size; i++) {
7989                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7990                                           (context_size - allocated));
7991                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7992                                 &bp->context[i].cxt_mapping,
7993                                 bp->context[i].size);
7994                 allocated += bp->context[i].size;
7995         }
7996         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7997
7998         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7999                 goto alloc_mem_err;
8000
8001         if (bnx2x_iov_alloc_mem(bp))
8002                 goto alloc_mem_err;
8003
8004         /* Slow path ring */
8005         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
8006
8007         /* EQ */
8008         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
8009                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
8010
8011         return 0;
8012
8013 alloc_mem_err:
8014         bnx2x_free_mem(bp);
8015         BNX2X_ERR("Can't allocate memory\n");
8016         return -ENOMEM;
8017 }
8018
8019 /*
8020  * Init service functions
8021  */
8022
8023 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8024                       struct bnx2x_vlan_mac_obj *obj, bool set,
8025                       int mac_type, unsigned long *ramrod_flags)
8026 {
8027         int rc;
8028         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8029
8030         memset(&ramrod_param, 0, sizeof(ramrod_param));
8031
8032         /* Fill general parameters */
8033         ramrod_param.vlan_mac_obj = obj;
8034         ramrod_param.ramrod_flags = *ramrod_flags;
8035
8036         /* Fill a user request section if needed */
8037         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8038                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8039
8040                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8041
8042                 /* Set the command: ADD or DEL */
8043                 if (set)
8044                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8045                 else
8046                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8047         }
8048
8049         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8050
8051         if (rc == -EEXIST) {
8052                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8053                 /* do not treat adding same MAC as error */
8054                 rc = 0;
8055         } else if (rc < 0)
8056                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8057
8058         return rc;
8059 }
8060
8061 int bnx2x_del_all_macs(struct bnx2x *bp,
8062                        struct bnx2x_vlan_mac_obj *mac_obj,
8063                        int mac_type, bool wait_for_comp)
8064 {
8065         int rc;
8066         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8067
8068         /* Wait for completion of requested */
8069         if (wait_for_comp)
8070                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8071
8072         /* Set the mac type of addresses we want to clear */
8073         __set_bit(mac_type, &vlan_mac_flags);
8074
8075         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8076         if (rc < 0)
8077                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8078
8079         return rc;
8080 }
8081
8082 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8083 {
8084         if (is_zero_ether_addr(bp->dev->dev_addr) &&
8085             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8086                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8087                    "Ignoring Zero MAC for STORAGE SD mode\n");
8088                 return 0;
8089         }
8090
8091         if (IS_PF(bp)) {
8092                 unsigned long ramrod_flags = 0;
8093
8094                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8095                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8096                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8097                                          &bp->sp_objs->mac_obj, set,
8098                                          BNX2X_ETH_MAC, &ramrod_flags);
8099         } else { /* vf */
8100                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8101                                              bp->fp->index, true);
8102         }
8103 }
8104
8105 int bnx2x_setup_leading(struct bnx2x *bp)
8106 {
8107         if (IS_PF(bp))
8108                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8109         else /* VF */
8110                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8111 }
8112
8113 /**
8114  * bnx2x_set_int_mode - configure interrupt mode
8115  *
8116  * @bp:         driver handle
8117  *
8118  * In case of MSI-X it will also try to enable MSI-X.
8119  */
8120 int bnx2x_set_int_mode(struct bnx2x *bp)
8121 {
8122         int rc = 0;
8123
8124         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8125                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8126                 return -EINVAL;
8127         }
8128
8129         switch (int_mode) {
8130         case BNX2X_INT_MODE_MSIX:
8131                 /* attempt to enable msix */
8132                 rc = bnx2x_enable_msix(bp);
8133
8134                 /* msix attained */
8135                 if (!rc)
8136                         return 0;
8137
8138                 /* vfs use only msix */
8139                 if (rc && IS_VF(bp))
8140                         return rc;
8141
8142                 /* failed to enable multiple MSI-X */
8143                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8144                                bp->num_queues,
8145                                1 + bp->num_cnic_queues);
8146
8147                 /* falling through... */
8148         case BNX2X_INT_MODE_MSI:
8149                 bnx2x_enable_msi(bp);
8150
8151                 /* falling through... */
8152         case BNX2X_INT_MODE_INTX:
8153                 bp->num_ethernet_queues = 1;
8154                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8155                 BNX2X_DEV_INFO("set number of queues to 1\n");
8156                 break;
8157         default:
8158                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8159                 return -EINVAL;
8160         }
8161         return 0;
8162 }
8163
8164 /* must be called prior to any HW initializations */
8165 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8166 {
8167         if (IS_SRIOV(bp))
8168                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8169         return L2_ILT_LINES(bp);
8170 }
8171
8172 void bnx2x_ilt_set_info(struct bnx2x *bp)
8173 {
8174         struct ilt_client_info *ilt_client;
8175         struct bnx2x_ilt *ilt = BP_ILT(bp);
8176         u16 line = 0;
8177
8178         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8179         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8180
8181         /* CDU */
8182         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8183         ilt_client->client_num = ILT_CLIENT_CDU;
8184         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8185         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8186         ilt_client->start = line;
8187         line += bnx2x_cid_ilt_lines(bp);
8188
8189         if (CNIC_SUPPORT(bp))
8190                 line += CNIC_ILT_LINES;
8191         ilt_client->end = line - 1;
8192
8193         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8194            ilt_client->start,
8195            ilt_client->end,
8196            ilt_client->page_size,
8197            ilt_client->flags,
8198            ilog2(ilt_client->page_size >> 12));
8199
8200         /* QM */
8201         if (QM_INIT(bp->qm_cid_count)) {
8202                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8203                 ilt_client->client_num = ILT_CLIENT_QM;
8204                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8205                 ilt_client->flags = 0;
8206                 ilt_client->start = line;
8207
8208                 /* 4 bytes for each cid */
8209                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8210                                                          QM_ILT_PAGE_SZ);
8211
8212                 ilt_client->end = line - 1;
8213
8214                 DP(NETIF_MSG_IFUP,
8215                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8216                    ilt_client->start,
8217                    ilt_client->end,
8218                    ilt_client->page_size,
8219                    ilt_client->flags,
8220                    ilog2(ilt_client->page_size >> 12));
8221         }
8222
8223         if (CNIC_SUPPORT(bp)) {
8224                 /* SRC */
8225                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8226                 ilt_client->client_num = ILT_CLIENT_SRC;
8227                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8228                 ilt_client->flags = 0;
8229                 ilt_client->start = line;
8230                 line += SRC_ILT_LINES;
8231                 ilt_client->end = line - 1;
8232
8233                 DP(NETIF_MSG_IFUP,
8234                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8235                    ilt_client->start,
8236                    ilt_client->end,
8237                    ilt_client->page_size,
8238                    ilt_client->flags,
8239                    ilog2(ilt_client->page_size >> 12));
8240
8241                 /* TM */
8242                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8243                 ilt_client->client_num = ILT_CLIENT_TM;
8244                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8245                 ilt_client->flags = 0;
8246                 ilt_client->start = line;
8247                 line += TM_ILT_LINES;
8248                 ilt_client->end = line - 1;
8249
8250                 DP(NETIF_MSG_IFUP,
8251                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8252                    ilt_client->start,
8253                    ilt_client->end,
8254                    ilt_client->page_size,
8255                    ilt_client->flags,
8256                    ilog2(ilt_client->page_size >> 12));
8257         }
8258
8259         BUG_ON(line > ILT_MAX_LINES);
8260 }
8261
8262 /**
8263  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8264  *
8265  * @bp:                 driver handle
8266  * @fp:                 pointer to fastpath
8267  * @init_params:        pointer to parameters structure
8268  *
8269  * parameters configured:
8270  *      - HC configuration
8271  *      - Queue's CDU context
8272  */
8273 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8274         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8275 {
8276         u8 cos;
8277         int cxt_index, cxt_offset;
8278
8279         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8280         if (!IS_FCOE_FP(fp)) {
8281                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8282                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8283
8284                 /* If HC is supported, enable host coalescing in the transition
8285                  * to INIT state.
8286                  */
8287                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8288                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8289
8290                 /* HC rate */
8291                 init_params->rx.hc_rate = bp->rx_ticks ?
8292                         (1000000 / bp->rx_ticks) : 0;
8293                 init_params->tx.hc_rate = bp->tx_ticks ?
8294                         (1000000 / bp->tx_ticks) : 0;
8295
8296                 /* FW SB ID */
8297                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8298                         fp->fw_sb_id;
8299
8300                 /*
8301                  * CQ index among the SB indices: FCoE clients uses the default
8302                  * SB, therefore it's different.
8303                  */
8304                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8305                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8306         }
8307
8308         /* set maximum number of COSs supported by this queue */
8309         init_params->max_cos = fp->max_cos;
8310
8311         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8312             fp->index, init_params->max_cos);
8313
8314         /* set the context pointers queue object */
8315         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8316                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8317                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8318                                 ILT_PAGE_CIDS);
8319                 init_params->cxts[cos] =
8320                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8321         }
8322 }
8323
8324 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8325                         struct bnx2x_queue_state_params *q_params,
8326                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8327                         int tx_index, bool leading)
8328 {
8329         memset(tx_only_params, 0, sizeof(*tx_only_params));
8330
8331         /* Set the command */
8332         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8333
8334         /* Set tx-only QUEUE flags: don't zero statistics */
8335         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8336
8337         /* choose the index of the cid to send the slow path on */
8338         tx_only_params->cid_index = tx_index;
8339
8340         /* Set general TX_ONLY_SETUP parameters */
8341         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8342
8343         /* Set Tx TX_ONLY_SETUP parameters */
8344         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8345
8346         DP(NETIF_MSG_IFUP,
8347            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8348            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8349            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8350            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8351
8352         /* send the ramrod */
8353         return bnx2x_queue_state_change(bp, q_params);
8354 }
8355
8356 /**
8357  * bnx2x_setup_queue - setup queue
8358  *
8359  * @bp:         driver handle
8360  * @fp:         pointer to fastpath
8361  * @leading:    is leading
8362  *
8363  * This function performs 2 steps in a Queue state machine
8364  *      actually: 1) RESET->INIT 2) INIT->SETUP
8365  */
8366
8367 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8368                        bool leading)
8369 {
8370         struct bnx2x_queue_state_params q_params = {NULL};
8371         struct bnx2x_queue_setup_params *setup_params =
8372                                                 &q_params.params.setup;
8373         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8374                                                 &q_params.params.tx_only;
8375         int rc;
8376         u8 tx_index;
8377
8378         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8379
8380         /* reset IGU state skip FCoE L2 queue */
8381         if (!IS_FCOE_FP(fp))
8382                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8383                              IGU_INT_ENABLE, 0);
8384
8385         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8386         /* We want to wait for completion in this context */
8387         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8388
8389         /* Prepare the INIT parameters */
8390         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8391
8392         /* Set the command */
8393         q_params.cmd = BNX2X_Q_CMD_INIT;
8394
8395         /* Change the state to INIT */
8396         rc = bnx2x_queue_state_change(bp, &q_params);
8397         if (rc) {
8398                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8399                 return rc;
8400         }
8401
8402         DP(NETIF_MSG_IFUP, "init complete\n");
8403
8404         /* Now move the Queue to the SETUP state... */
8405         memset(setup_params, 0, sizeof(*setup_params));
8406
8407         /* Set QUEUE flags */
8408         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8409
8410         /* Set general SETUP parameters */
8411         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8412                                 FIRST_TX_COS_INDEX);
8413
8414         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8415                             &setup_params->rxq_params);
8416
8417         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8418                            FIRST_TX_COS_INDEX);
8419
8420         /* Set the command */
8421         q_params.cmd = BNX2X_Q_CMD_SETUP;
8422
8423         if (IS_FCOE_FP(fp))
8424                 bp->fcoe_init = true;
8425
8426         /* Change the state to SETUP */
8427         rc = bnx2x_queue_state_change(bp, &q_params);
8428         if (rc) {
8429                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8430                 return rc;
8431         }
8432
8433         /* loop through the relevant tx-only indices */
8434         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8435               tx_index < fp->max_cos;
8436               tx_index++) {
8437
8438                 /* prepare and send tx-only ramrod*/
8439                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8440                                           tx_only_params, tx_index, leading);
8441                 if (rc) {
8442                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8443                                   fp->index, tx_index);
8444                         return rc;
8445                 }
8446         }
8447
8448         return rc;
8449 }
8450
8451 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8452 {
8453         struct bnx2x_fastpath *fp = &bp->fp[index];
8454         struct bnx2x_fp_txdata *txdata;
8455         struct bnx2x_queue_state_params q_params = {NULL};
8456         int rc, tx_index;
8457
8458         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8459
8460         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8461         /* We want to wait for completion in this context */
8462         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8463
8464         /* close tx-only connections */
8465         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8466              tx_index < fp->max_cos;
8467              tx_index++){
8468
8469                 /* ascertain this is a normal queue*/
8470                 txdata = fp->txdata_ptr[tx_index];
8471
8472                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8473                                                         txdata->txq_index);
8474
8475                 /* send halt terminate on tx-only connection */
8476                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8477                 memset(&q_params.params.terminate, 0,
8478                        sizeof(q_params.params.terminate));
8479                 q_params.params.terminate.cid_index = tx_index;
8480
8481                 rc = bnx2x_queue_state_change(bp, &q_params);
8482                 if (rc)
8483                         return rc;
8484
8485                 /* send halt terminate on tx-only connection */
8486                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8487                 memset(&q_params.params.cfc_del, 0,
8488                        sizeof(q_params.params.cfc_del));
8489                 q_params.params.cfc_del.cid_index = tx_index;
8490                 rc = bnx2x_queue_state_change(bp, &q_params);
8491                 if (rc)
8492                         return rc;
8493         }
8494         /* Stop the primary connection: */
8495         /* ...halt the connection */
8496         q_params.cmd = BNX2X_Q_CMD_HALT;
8497         rc = bnx2x_queue_state_change(bp, &q_params);
8498         if (rc)
8499                 return rc;
8500
8501         /* ...terminate the connection */
8502         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8503         memset(&q_params.params.terminate, 0,
8504                sizeof(q_params.params.terminate));
8505         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8506         rc = bnx2x_queue_state_change(bp, &q_params);
8507         if (rc)
8508                 return rc;
8509         /* ...delete cfc entry */
8510         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8511         memset(&q_params.params.cfc_del, 0,
8512                sizeof(q_params.params.cfc_del));
8513         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8514         return bnx2x_queue_state_change(bp, &q_params);
8515 }
8516
8517 static void bnx2x_reset_func(struct bnx2x *bp)
8518 {
8519         int port = BP_PORT(bp);
8520         int func = BP_FUNC(bp);
8521         int i;
8522
8523         /* Disable the function in the FW */
8524         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8525         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8526         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8527         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8528
8529         /* FP SBs */
8530         for_each_eth_queue(bp, i) {
8531                 struct bnx2x_fastpath *fp = &bp->fp[i];
8532                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8533                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8534                            SB_DISABLED);
8535         }
8536
8537         if (CNIC_LOADED(bp))
8538                 /* CNIC SB */
8539                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8540                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8541                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8542
8543         /* SP SB */
8544         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8545                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8546                 SB_DISABLED);
8547
8548         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8549                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8550                        0);
8551
8552         /* Configure IGU */
8553         if (bp->common.int_block == INT_BLOCK_HC) {
8554                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8555                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8556         } else {
8557                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8558                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8559         }
8560
8561         if (CNIC_LOADED(bp)) {
8562                 /* Disable Timer scan */
8563                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8564                 /*
8565                  * Wait for at least 10ms and up to 2 second for the timers
8566                  * scan to complete
8567                  */
8568                 for (i = 0; i < 200; i++) {
8569                         usleep_range(10000, 20000);
8570                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8571                                 break;
8572                 }
8573         }
8574         /* Clear ILT */
8575         bnx2x_clear_func_ilt(bp, func);
8576
8577         /* Timers workaround bug for E2: if this is vnic-3,
8578          * we need to set the entire ilt range for this timers.
8579          */
8580         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8581                 struct ilt_client_info ilt_cli;
8582                 /* use dummy TM client */
8583                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8584                 ilt_cli.start = 0;
8585                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8586                 ilt_cli.client_num = ILT_CLIENT_TM;
8587
8588                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8589         }
8590
8591         /* this assumes that reset_port() called before reset_func()*/
8592         if (!CHIP_IS_E1x(bp))
8593                 bnx2x_pf_disable(bp);
8594
8595         bp->dmae_ready = 0;
8596 }
8597
8598 static void bnx2x_reset_port(struct bnx2x *bp)
8599 {
8600         int port = BP_PORT(bp);
8601         u32 val;
8602
8603         /* Reset physical Link */
8604         bnx2x__link_reset(bp);
8605
8606         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8607
8608         /* Do not rcv packets to BRB */
8609         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8610         /* Do not direct rcv packets that are not for MCP to the BRB */
8611         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8612                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8613
8614         /* Configure AEU */
8615         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8616
8617         msleep(100);
8618         /* Check for BRB port occupancy */
8619         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8620         if (val)
8621                 DP(NETIF_MSG_IFDOWN,
8622                    "BRB1 is not empty  %d blocks are occupied\n", val);
8623
8624         /* TODO: Close Doorbell port? */
8625 }
8626
8627 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8628 {
8629         struct bnx2x_func_state_params func_params = {NULL};
8630
8631         /* Prepare parameters for function state transitions */
8632         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8633
8634         func_params.f_obj = &bp->func_obj;
8635         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8636
8637         func_params.params.hw_init.load_phase = load_code;
8638
8639         return bnx2x_func_state_change(bp, &func_params);
8640 }
8641
8642 static int bnx2x_func_stop(struct bnx2x *bp)
8643 {
8644         struct bnx2x_func_state_params func_params = {NULL};
8645         int rc;
8646
8647         /* Prepare parameters for function state transitions */
8648         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8649         func_params.f_obj = &bp->func_obj;
8650         func_params.cmd = BNX2X_F_CMD_STOP;
8651
8652         /*
8653          * Try to stop the function the 'good way'. If fails (in case
8654          * of a parity error during bnx2x_chip_cleanup()) and we are
8655          * not in a debug mode, perform a state transaction in order to
8656          * enable further HW_RESET transaction.
8657          */
8658         rc = bnx2x_func_state_change(bp, &func_params);
8659         if (rc) {
8660 #ifdef BNX2X_STOP_ON_ERROR
8661                 return rc;
8662 #else
8663                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8664                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8665                 return bnx2x_func_state_change(bp, &func_params);
8666 #endif
8667         }
8668
8669         return 0;
8670 }
8671
8672 /**
8673  * bnx2x_send_unload_req - request unload mode from the MCP.
8674  *
8675  * @bp:                 driver handle
8676  * @unload_mode:        requested function's unload mode
8677  *
8678  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8679  */
8680 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8681 {
8682         u32 reset_code = 0;
8683         int port = BP_PORT(bp);
8684
8685         /* Select the UNLOAD request mode */
8686         if (unload_mode == UNLOAD_NORMAL)
8687                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8688
8689         else if (bp->flags & NO_WOL_FLAG)
8690                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8691
8692         else if (bp->wol) {
8693                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8694                 u8 *mac_addr = bp->dev->dev_addr;
8695                 struct pci_dev *pdev = bp->pdev;
8696                 u32 val;
8697                 u16 pmc;
8698
8699                 /* The mac address is written to entries 1-4 to
8700                  * preserve entry 0 which is used by the PMF
8701                  */
8702                 u8 entry = (BP_VN(bp) + 1)*8;
8703
8704                 val = (mac_addr[0] << 8) | mac_addr[1];
8705                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8706
8707                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8708                       (mac_addr[4] << 8) | mac_addr[5];
8709                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8710
8711                 /* Enable the PME and clear the status */
8712                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
8713                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8714                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
8715
8716                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8717
8718         } else
8719                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8720
8721         /* Send the request to the MCP */
8722         if (!BP_NOMCP(bp))
8723                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8724         else {
8725                 int path = BP_PATH(bp);
8726
8727                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8728                    path, load_count[path][0], load_count[path][1],
8729                    load_count[path][2]);
8730                 load_count[path][0]--;
8731                 load_count[path][1 + port]--;
8732                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8733                    path, load_count[path][0], load_count[path][1],
8734                    load_count[path][2]);
8735                 if (load_count[path][0] == 0)
8736                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8737                 else if (load_count[path][1 + port] == 0)
8738                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8739                 else
8740                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8741         }
8742
8743         return reset_code;
8744 }
8745
8746 /**
8747  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8748  *
8749  * @bp:         driver handle
8750  * @keep_link:          true iff link should be kept up
8751  */
8752 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8753 {
8754         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8755
8756         /* Report UNLOAD_DONE to MCP */
8757         if (!BP_NOMCP(bp))
8758                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8759 }
8760
8761 static int bnx2x_func_wait_started(struct bnx2x *bp)
8762 {
8763         int tout = 50;
8764         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8765
8766         if (!bp->port.pmf)
8767                 return 0;
8768
8769         /*
8770          * (assumption: No Attention from MCP at this stage)
8771          * PMF probably in the middle of TX disable/enable transaction
8772          * 1. Sync IRS for default SB
8773          * 2. Sync SP queue - this guarantees us that attention handling started
8774          * 3. Wait, that TX disable/enable transaction completes
8775          *
8776          * 1+2 guarantee that if DCBx attention was scheduled it already changed
8777          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8778          * received completion for the transaction the state is TX_STOPPED.
8779          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8780          * transaction.
8781          */
8782
8783         /* make sure default SB ISR is done */
8784         if (msix)
8785                 synchronize_irq(bp->msix_table[0].vector);
8786         else
8787                 synchronize_irq(bp->pdev->irq);
8788
8789         flush_workqueue(bnx2x_wq);
8790
8791         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8792                                 BNX2X_F_STATE_STARTED && tout--)
8793                 msleep(20);
8794
8795         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8796                                                 BNX2X_F_STATE_STARTED) {
8797 #ifdef BNX2X_STOP_ON_ERROR
8798                 BNX2X_ERR("Wrong function state\n");
8799                 return -EBUSY;
8800 #else
8801                 /*
8802                  * Failed to complete the transaction in a "good way"
8803                  * Force both transactions with CLR bit
8804                  */
8805                 struct bnx2x_func_state_params func_params = {NULL};
8806
8807                 DP(NETIF_MSG_IFDOWN,
8808                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8809
8810                 func_params.f_obj = &bp->func_obj;
8811                 __set_bit(RAMROD_DRV_CLR_ONLY,
8812                                         &func_params.ramrod_flags);
8813
8814                 /* STARTED-->TX_ST0PPED */
8815                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8816                 bnx2x_func_state_change(bp, &func_params);
8817
8818                 /* TX_ST0PPED-->STARTED */
8819                 func_params.cmd = BNX2X_F_CMD_TX_START;
8820                 return bnx2x_func_state_change(bp, &func_params);
8821 #endif
8822         }
8823
8824         return 0;
8825 }
8826
8827 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8828 {
8829         int port = BP_PORT(bp);
8830         int i, rc = 0;
8831         u8 cos;
8832         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8833         u32 reset_code;
8834
8835         /* Wait until tx fastpath tasks complete */
8836         for_each_tx_queue(bp, i) {
8837                 struct bnx2x_fastpath *fp = &bp->fp[i];
8838
8839                 for_each_cos_in_tx_queue(fp, cos)
8840                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8841 #ifdef BNX2X_STOP_ON_ERROR
8842                 if (rc)
8843                         return;
8844 #endif
8845         }
8846
8847         /* Give HW time to discard old tx messages */
8848         usleep_range(1000, 2000);
8849
8850         /* Clean all ETH MACs */
8851         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8852                                 false);
8853         if (rc < 0)
8854                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8855
8856         /* Clean up UC list  */
8857         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8858                                 true);
8859         if (rc < 0)
8860                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8861                           rc);
8862
8863         /* Disable LLH */
8864         if (!CHIP_IS_E1(bp))
8865                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8866
8867         /* Set "drop all" (stop Rx).
8868          * We need to take a netif_addr_lock() here in order to prevent
8869          * a race between the completion code and this code.
8870          */
8871         netif_addr_lock_bh(bp->dev);
8872         /* Schedule the rx_mode command */
8873         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8874                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8875         else
8876                 bnx2x_set_storm_rx_mode(bp);
8877
8878         /* Cleanup multicast configuration */
8879         rparam.mcast_obj = &bp->mcast_obj;
8880         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8881         if (rc < 0)
8882                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8883
8884         netif_addr_unlock_bh(bp->dev);
8885
8886         bnx2x_iov_chip_cleanup(bp);
8887
8888         /*
8889          * Send the UNLOAD_REQUEST to the MCP. This will return if
8890          * this function should perform FUNC, PORT or COMMON HW
8891          * reset.
8892          */
8893         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8894
8895         /*
8896          * (assumption: No Attention from MCP at this stage)
8897          * PMF probably in the middle of TX disable/enable transaction
8898          */
8899         rc = bnx2x_func_wait_started(bp);
8900         if (rc) {
8901                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8902 #ifdef BNX2X_STOP_ON_ERROR
8903                 return;
8904 #endif
8905         }
8906
8907         /* Close multi and leading connections
8908          * Completions for ramrods are collected in a synchronous way
8909          */
8910         for_each_eth_queue(bp, i)
8911                 if (bnx2x_stop_queue(bp, i))
8912 #ifdef BNX2X_STOP_ON_ERROR
8913                         return;
8914 #else
8915                         goto unload_error;
8916 #endif
8917
8918         if (CNIC_LOADED(bp)) {
8919                 for_each_cnic_queue(bp, i)
8920                         if (bnx2x_stop_queue(bp, i))
8921 #ifdef BNX2X_STOP_ON_ERROR
8922                                 return;
8923 #else
8924                                 goto unload_error;
8925 #endif
8926         }
8927
8928         /* If SP settings didn't get completed so far - something
8929          * very wrong has happen.
8930          */
8931         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8932                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8933
8934 #ifndef BNX2X_STOP_ON_ERROR
8935 unload_error:
8936 #endif
8937         rc = bnx2x_func_stop(bp);
8938         if (rc) {
8939                 BNX2X_ERR("Function stop failed!\n");
8940 #ifdef BNX2X_STOP_ON_ERROR
8941                 return;
8942 #endif
8943         }
8944
8945         /* Disable HW interrupts, NAPI */
8946         bnx2x_netif_stop(bp, 1);
8947         /* Delete all NAPI objects */
8948         bnx2x_del_all_napi(bp);
8949         if (CNIC_LOADED(bp))
8950                 bnx2x_del_all_napi_cnic(bp);
8951
8952         /* Release IRQs */
8953         bnx2x_free_irq(bp);
8954
8955         /* Reset the chip */
8956         rc = bnx2x_reset_hw(bp, reset_code);
8957         if (rc)
8958                 BNX2X_ERR("HW_RESET failed\n");
8959
8960         /* Report UNLOAD_DONE to MCP */
8961         bnx2x_send_unload_done(bp, keep_link);
8962 }
8963
8964 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8965 {
8966         u32 val;
8967
8968         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8969
8970         if (CHIP_IS_E1(bp)) {
8971                 int port = BP_PORT(bp);
8972                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8973                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8974
8975                 val = REG_RD(bp, addr);
8976                 val &= ~(0x300);
8977                 REG_WR(bp, addr, val);
8978         } else {
8979                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8980                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8981                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8982                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8983         }
8984 }
8985
8986 /* Close gates #2, #3 and #4: */
8987 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8988 {
8989         u32 val;
8990
8991         /* Gates #2 and #4a are closed/opened for "not E1" only */
8992         if (!CHIP_IS_E1(bp)) {
8993                 /* #4 */
8994                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8995                 /* #2 */
8996                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8997         }
8998
8999         /* #3 */
9000         if (CHIP_IS_E1x(bp)) {
9001                 /* Prevent interrupts from HC on both ports */
9002                 val = REG_RD(bp, HC_REG_CONFIG_1);
9003                 REG_WR(bp, HC_REG_CONFIG_1,
9004                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9005                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9006
9007                 val = REG_RD(bp, HC_REG_CONFIG_0);
9008                 REG_WR(bp, HC_REG_CONFIG_0,
9009                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9010                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9011         } else {
9012                 /* Prevent incoming interrupts in IGU */
9013                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9014
9015                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9016                        (!close) ?
9017                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9018                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9019         }
9020
9021         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9022                 close ? "closing" : "opening");
9023         mmiowb();
9024 }
9025
9026 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9027
9028 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9029 {
9030         /* Do some magic... */
9031         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9032         *magic_val = val & SHARED_MF_CLP_MAGIC;
9033         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9034 }
9035
9036 /**
9037  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9038  *
9039  * @bp:         driver handle
9040  * @magic_val:  old value of the `magic' bit.
9041  */
9042 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9043 {
9044         /* Restore the `magic' bit value... */
9045         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9046         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9047                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9048 }
9049
9050 /**
9051  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9052  *
9053  * @bp:         driver handle
9054  * @magic_val:  old value of 'magic' bit.
9055  *
9056  * Takes care of CLP configurations.
9057  */
9058 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9059 {
9060         u32 shmem;
9061         u32 validity_offset;
9062
9063         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9064
9065         /* Set `magic' bit in order to save MF config */
9066         if (!CHIP_IS_E1(bp))
9067                 bnx2x_clp_reset_prep(bp, magic_val);
9068
9069         /* Get shmem offset */
9070         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9071         validity_offset =
9072                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9073
9074         /* Clear validity map flags */
9075         if (shmem > 0)
9076                 REG_WR(bp, shmem + validity_offset, 0);
9077 }
9078
9079 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9080 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9081
9082 /**
9083  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9084  *
9085  * @bp: driver handle
9086  */
9087 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9088 {
9089         /* special handling for emulation and FPGA,
9090            wait 10 times longer */
9091         if (CHIP_REV_IS_SLOW(bp))
9092                 msleep(MCP_ONE_TIMEOUT*10);
9093         else
9094                 msleep(MCP_ONE_TIMEOUT);
9095 }
9096
9097 /*
9098  * initializes bp->common.shmem_base and waits for validity signature to appear
9099  */
9100 static int bnx2x_init_shmem(struct bnx2x *bp)
9101 {
9102         int cnt = 0;
9103         u32 val = 0;
9104
9105         do {
9106                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9107                 if (bp->common.shmem_base) {
9108                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9109                         if (val & SHR_MEM_VALIDITY_MB)
9110                                 return 0;
9111                 }
9112
9113                 bnx2x_mcp_wait_one(bp);
9114
9115         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9116
9117         BNX2X_ERR("BAD MCP validity signature\n");
9118
9119         return -ENODEV;
9120 }
9121
9122 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9123 {
9124         int rc = bnx2x_init_shmem(bp);
9125
9126         /* Restore the `magic' bit value */
9127         if (!CHIP_IS_E1(bp))
9128                 bnx2x_clp_reset_done(bp, magic_val);
9129
9130         return rc;
9131 }
9132
9133 static void bnx2x_pxp_prep(struct bnx2x *bp)
9134 {
9135         if (!CHIP_IS_E1(bp)) {
9136                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9137                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9138                 mmiowb();
9139         }
9140 }
9141
9142 /*
9143  * Reset the whole chip except for:
9144  *      - PCIE core
9145  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9146  *              one reset bit)
9147  *      - IGU
9148  *      - MISC (including AEU)
9149  *      - GRC
9150  *      - RBCN, RBCP
9151  */
9152 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9153 {
9154         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9155         u32 global_bits2, stay_reset2;
9156
9157         /*
9158          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9159          * (per chip) blocks.
9160          */
9161         global_bits2 =
9162                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9163                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9164
9165         /* Don't reset the following blocks.
9166          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9167          *            reset, as in 4 port device they might still be owned
9168          *            by the MCP (there is only one leader per path).
9169          */
9170         not_reset_mask1 =
9171                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9172                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9173                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9174
9175         not_reset_mask2 =
9176                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9177                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9178                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9179                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9180                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9181                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9182                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9183                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9184                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9185                 MISC_REGISTERS_RESET_REG_2_PGLC |
9186                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9187                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9188                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9189                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9190                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9191                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9192
9193         /*
9194          * Keep the following blocks in reset:
9195          *  - all xxMACs are handled by the bnx2x_link code.
9196          */
9197         stay_reset2 =
9198                 MISC_REGISTERS_RESET_REG_2_XMAC |
9199                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9200
9201         /* Full reset masks according to the chip */
9202         reset_mask1 = 0xffffffff;
9203
9204         if (CHIP_IS_E1(bp))
9205                 reset_mask2 = 0xffff;
9206         else if (CHIP_IS_E1H(bp))
9207                 reset_mask2 = 0x1ffff;
9208         else if (CHIP_IS_E2(bp))
9209                 reset_mask2 = 0xfffff;
9210         else /* CHIP_IS_E3 */
9211                 reset_mask2 = 0x3ffffff;
9212
9213         /* Don't reset global blocks unless we need to */
9214         if (!global)
9215                 reset_mask2 &= ~global_bits2;
9216
9217         /*
9218          * In case of attention in the QM, we need to reset PXP
9219          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9220          * because otherwise QM reset would release 'close the gates' shortly
9221          * before resetting the PXP, then the PSWRQ would send a write
9222          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9223          * read the payload data from PSWWR, but PSWWR would not
9224          * respond. The write queue in PGLUE would stuck, dmae commands
9225          * would not return. Therefore it's important to reset the second
9226          * reset register (containing the
9227          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9228          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9229          * bit).
9230          */
9231         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9232                reset_mask2 & (~not_reset_mask2));
9233
9234         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9235                reset_mask1 & (~not_reset_mask1));
9236
9237         barrier();
9238         mmiowb();
9239
9240         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9241                reset_mask2 & (~stay_reset2));
9242
9243         barrier();
9244         mmiowb();
9245
9246         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9247         mmiowb();
9248 }
9249
9250 /**
9251  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9252  * It should get cleared in no more than 1s.
9253  *
9254  * @bp: driver handle
9255  *
9256  * It should get cleared in no more than 1s. Returns 0 if
9257  * pending writes bit gets cleared.
9258  */
9259 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9260 {
9261         u32 cnt = 1000;
9262         u32 pend_bits = 0;
9263
9264         do {
9265                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9266
9267                 if (pend_bits == 0)
9268                         break;
9269
9270                 usleep_range(1000, 2000);
9271         } while (cnt-- > 0);
9272
9273         if (cnt <= 0) {
9274                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9275                           pend_bits);
9276                 return -EBUSY;
9277         }
9278
9279         return 0;
9280 }
9281
9282 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9283 {
9284         int cnt = 1000;
9285         u32 val = 0;
9286         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9287         u32 tags_63_32 = 0;
9288
9289         /* Empty the Tetris buffer, wait for 1s */
9290         do {
9291                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9292                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9293                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9294                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9295                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9296                 if (CHIP_IS_E3(bp))
9297                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9298
9299                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9300                     ((port_is_idle_0 & 0x1) == 0x1) &&
9301                     ((port_is_idle_1 & 0x1) == 0x1) &&
9302                     (pgl_exp_rom2 == 0xffffffff) &&
9303                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9304                         break;
9305                 usleep_range(1000, 2000);
9306         } while (cnt-- > 0);
9307
9308         if (cnt <= 0) {
9309                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9310                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9311                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9312                           pgl_exp_rom2);
9313                 return -EAGAIN;
9314         }
9315
9316         barrier();
9317
9318         /* Close gates #2, #3 and #4 */
9319         bnx2x_set_234_gates(bp, true);
9320
9321         /* Poll for IGU VQs for 57712 and newer chips */
9322         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9323                 return -EAGAIN;
9324
9325         /* TBD: Indicate that "process kill" is in progress to MCP */
9326
9327         /* Clear "unprepared" bit */
9328         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9329         barrier();
9330
9331         /* Make sure all is written to the chip before the reset */
9332         mmiowb();
9333
9334         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9335          * PSWHST, GRC and PSWRD Tetris buffer.
9336          */
9337         usleep_range(1000, 2000);
9338
9339         /* Prepare to chip reset: */
9340         /* MCP */
9341         if (global)
9342                 bnx2x_reset_mcp_prep(bp, &val);
9343
9344         /* PXP */
9345         bnx2x_pxp_prep(bp);
9346         barrier();
9347
9348         /* reset the chip */
9349         bnx2x_process_kill_chip_reset(bp, global);
9350         barrier();
9351
9352         /* Recover after reset: */
9353         /* MCP */
9354         if (global && bnx2x_reset_mcp_comp(bp, val))
9355                 return -EAGAIN;
9356
9357         /* TBD: Add resetting the NO_MCP mode DB here */
9358
9359         /* Open the gates #2, #3 and #4 */
9360         bnx2x_set_234_gates(bp, false);
9361
9362         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9363          * reset state, re-enable attentions. */
9364
9365         return 0;
9366 }
9367
9368 static int bnx2x_leader_reset(struct bnx2x *bp)
9369 {
9370         int rc = 0;
9371         bool global = bnx2x_reset_is_global(bp);
9372         u32 load_code;
9373
9374         /* if not going to reset MCP - load "fake" driver to reset HW while
9375          * driver is owner of the HW
9376          */
9377         if (!global && !BP_NOMCP(bp)) {
9378                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9379                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9380                 if (!load_code) {
9381                         BNX2X_ERR("MCP response failure, aborting\n");
9382                         rc = -EAGAIN;
9383                         goto exit_leader_reset;
9384                 }
9385                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9386                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9387                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9388                         rc = -EAGAIN;
9389                         goto exit_leader_reset2;
9390                 }
9391                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9392                 if (!load_code) {
9393                         BNX2X_ERR("MCP response failure, aborting\n");
9394                         rc = -EAGAIN;
9395                         goto exit_leader_reset2;
9396                 }
9397         }
9398
9399         /* Try to recover after the failure */
9400         if (bnx2x_process_kill(bp, global)) {
9401                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9402                           BP_PATH(bp));
9403                 rc = -EAGAIN;
9404                 goto exit_leader_reset2;
9405         }
9406
9407         /*
9408          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9409          * state.
9410          */
9411         bnx2x_set_reset_done(bp);
9412         if (global)
9413                 bnx2x_clear_reset_global(bp);
9414
9415 exit_leader_reset2:
9416         /* unload "fake driver" if it was loaded */
9417         if (!global && !BP_NOMCP(bp)) {
9418                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9419                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9420         }
9421 exit_leader_reset:
9422         bp->is_leader = 0;
9423         bnx2x_release_leader_lock(bp);
9424         smp_mb();
9425         return rc;
9426 }
9427
9428 static void bnx2x_recovery_failed(struct bnx2x *bp)
9429 {
9430         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9431
9432         /* Disconnect this device */
9433         netif_device_detach(bp->dev);
9434
9435         /*
9436          * Block ifup for all function on this engine until "process kill"
9437          * or power cycle.
9438          */
9439         bnx2x_set_reset_in_progress(bp);
9440
9441         /* Shut down the power */
9442         bnx2x_set_power_state(bp, PCI_D3hot);
9443
9444         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9445
9446         smp_mb();
9447 }
9448
9449 /*
9450  * Assumption: runs under rtnl lock. This together with the fact
9451  * that it's called only from bnx2x_sp_rtnl() ensure that it
9452  * will never be called when netif_running(bp->dev) is false.
9453  */
9454 static void bnx2x_parity_recover(struct bnx2x *bp)
9455 {
9456         bool global = false;
9457         u32 error_recovered, error_unrecovered;
9458         bool is_parity;
9459
9460         DP(NETIF_MSG_HW, "Handling parity\n");
9461         while (1) {
9462                 switch (bp->recovery_state) {
9463                 case BNX2X_RECOVERY_INIT:
9464                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9465                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9466                         WARN_ON(!is_parity);
9467
9468                         /* Try to get a LEADER_LOCK HW lock */
9469                         if (bnx2x_trylock_leader_lock(bp)) {
9470                                 bnx2x_set_reset_in_progress(bp);
9471                                 /*
9472                                  * Check if there is a global attention and if
9473                                  * there was a global attention, set the global
9474                                  * reset bit.
9475                                  */
9476
9477                                 if (global)
9478                                         bnx2x_set_reset_global(bp);
9479
9480                                 bp->is_leader = 1;
9481                         }
9482
9483                         /* Stop the driver */
9484                         /* If interface has been removed - break */
9485                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9486                                 return;
9487
9488                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9489
9490                         /* Ensure "is_leader", MCP command sequence and
9491                          * "recovery_state" update values are seen on other
9492                          * CPUs.
9493                          */
9494                         smp_mb();
9495                         break;
9496
9497                 case BNX2X_RECOVERY_WAIT:
9498                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9499                         if (bp->is_leader) {
9500                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9501                                 bool other_load_status =
9502                                         bnx2x_get_load_status(bp, other_engine);
9503                                 bool load_status =
9504                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9505                                 global = bnx2x_reset_is_global(bp);
9506
9507                                 /*
9508                                  * In case of a parity in a global block, let
9509                                  * the first leader that performs a
9510                                  * leader_reset() reset the global blocks in
9511                                  * order to clear global attentions. Otherwise
9512                                  * the gates will remain closed for that
9513                                  * engine.
9514                                  */
9515                                 if (load_status ||
9516                                     (global && other_load_status)) {
9517                                         /* Wait until all other functions get
9518                                          * down.
9519                                          */
9520                                         schedule_delayed_work(&bp->sp_rtnl_task,
9521                                                                 HZ/10);
9522                                         return;
9523                                 } else {
9524                                         /* If all other functions got down -
9525                                          * try to bring the chip back to
9526                                          * normal. In any case it's an exit
9527                                          * point for a leader.
9528                                          */
9529                                         if (bnx2x_leader_reset(bp)) {
9530                                                 bnx2x_recovery_failed(bp);
9531                                                 return;
9532                                         }
9533
9534                                         /* If we are here, means that the
9535                                          * leader has succeeded and doesn't
9536                                          * want to be a leader any more. Try
9537                                          * to continue as a none-leader.
9538                                          */
9539                                         break;
9540                                 }
9541                         } else { /* non-leader */
9542                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9543                                         /* Try to get a LEADER_LOCK HW lock as
9544                                          * long as a former leader may have
9545                                          * been unloaded by the user or
9546                                          * released a leadership by another
9547                                          * reason.
9548                                          */
9549                                         if (bnx2x_trylock_leader_lock(bp)) {
9550                                                 /* I'm a leader now! Restart a
9551                                                  * switch case.
9552                                                  */
9553                                                 bp->is_leader = 1;
9554                                                 break;
9555                                         }
9556
9557                                         schedule_delayed_work(&bp->sp_rtnl_task,
9558                                                                 HZ/10);
9559                                         return;
9560
9561                                 } else {
9562                                         /*
9563                                          * If there was a global attention, wait
9564                                          * for it to be cleared.
9565                                          */
9566                                         if (bnx2x_reset_is_global(bp)) {
9567                                                 schedule_delayed_work(
9568                                                         &bp->sp_rtnl_task,
9569                                                         HZ/10);
9570                                                 return;
9571                                         }
9572
9573                                         error_recovered =
9574                                           bp->eth_stats.recoverable_error;
9575                                         error_unrecovered =
9576                                           bp->eth_stats.unrecoverable_error;
9577                                         bp->recovery_state =
9578                                                 BNX2X_RECOVERY_NIC_LOADING;
9579                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9580                                                 error_unrecovered++;
9581                                                 netdev_err(bp->dev,
9582                                                            "Recovery failed. Power cycle needed\n");
9583                                                 /* Disconnect this device */
9584                                                 netif_device_detach(bp->dev);
9585                                                 /* Shut down the power */
9586                                                 bnx2x_set_power_state(
9587                                                         bp, PCI_D3hot);
9588                                                 smp_mb();
9589                                         } else {
9590                                                 bp->recovery_state =
9591                                                         BNX2X_RECOVERY_DONE;
9592                                                 error_recovered++;
9593                                                 smp_mb();
9594                                         }
9595                                         bp->eth_stats.recoverable_error =
9596                                                 error_recovered;
9597                                         bp->eth_stats.unrecoverable_error =
9598                                                 error_unrecovered;
9599
9600                                         return;
9601                                 }
9602                         }
9603                 default:
9604                         return;
9605                 }
9606         }
9607 }
9608
9609 static int bnx2x_close(struct net_device *dev);
9610
9611 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9612  * scheduled on a general queue in order to prevent a dead lock.
9613  */
9614 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9615 {
9616         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9617
9618         rtnl_lock();
9619
9620         if (!netif_running(bp->dev)) {
9621                 rtnl_unlock();
9622                 return;
9623         }
9624
9625         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9626 #ifdef BNX2X_STOP_ON_ERROR
9627                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9628                           "you will need to reboot when done\n");
9629                 goto sp_rtnl_not_reset;
9630 #endif
9631                 /*
9632                  * Clear all pending SP commands as we are going to reset the
9633                  * function anyway.
9634                  */
9635                 bp->sp_rtnl_state = 0;
9636                 smp_mb();
9637
9638                 bnx2x_parity_recover(bp);
9639
9640                 rtnl_unlock();
9641                 return;
9642         }
9643
9644         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9645 #ifdef BNX2X_STOP_ON_ERROR
9646                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9647                           "you will need to reboot when done\n");
9648                 goto sp_rtnl_not_reset;
9649 #endif
9650
9651                 /*
9652                  * Clear all pending SP commands as we are going to reset the
9653                  * function anyway.
9654                  */
9655                 bp->sp_rtnl_state = 0;
9656                 smp_mb();
9657
9658                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9659                 bnx2x_nic_load(bp, LOAD_NORMAL);
9660
9661                 rtnl_unlock();
9662                 return;
9663         }
9664 #ifdef BNX2X_STOP_ON_ERROR
9665 sp_rtnl_not_reset:
9666 #endif
9667         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9668                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9669         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9670                 bnx2x_after_function_update(bp);
9671         /*
9672          * in case of fan failure we need to reset id if the "stop on error"
9673          * debug flag is set, since we trying to prevent permanent overheating
9674          * damage
9675          */
9676         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9677                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9678                 netif_device_detach(bp->dev);
9679                 bnx2x_close(bp->dev);
9680                 rtnl_unlock();
9681                 return;
9682         }
9683
9684         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9685                 DP(BNX2X_MSG_SP,
9686                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9687                 bnx2x_vfpf_set_mcast(bp->dev);
9688         }
9689         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9690                                &bp->sp_rtnl_state)){
9691                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9692                         bnx2x_tx_disable(bp);
9693                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9694                 }
9695         }
9696
9697         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9698                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9699                 bnx2x_set_rx_mode_inner(bp);
9700         }
9701
9702         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9703                                &bp->sp_rtnl_state))
9704                 bnx2x_pf_set_vfs_vlan(bp);
9705
9706         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state))
9707                 bnx2x_dcbx_stop_hw_tx(bp);
9708
9709         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state))
9710                 bnx2x_dcbx_resume_hw_tx(bp);
9711
9712         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9713          * can be called from other contexts as well)
9714          */
9715         rtnl_unlock();
9716
9717         /* enable SR-IOV if applicable */
9718         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9719                                                &bp->sp_rtnl_state)) {
9720                 bnx2x_disable_sriov(bp);
9721                 bnx2x_enable_sriov(bp);
9722         }
9723 }
9724
9725 static void bnx2x_period_task(struct work_struct *work)
9726 {
9727         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9728
9729         if (!netif_running(bp->dev))
9730                 goto period_task_exit;
9731
9732         if (CHIP_REV_IS_SLOW(bp)) {
9733                 BNX2X_ERR("period task called on emulation, ignoring\n");
9734                 goto period_task_exit;
9735         }
9736
9737         bnx2x_acquire_phy_lock(bp);
9738         /*
9739          * The barrier is needed to ensure the ordering between the writing to
9740          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9741          * the reading here.
9742          */
9743         smp_mb();
9744         if (bp->port.pmf) {
9745                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9746
9747                 /* Re-queue task in 1 sec */
9748                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9749         }
9750
9751         bnx2x_release_phy_lock(bp);
9752 period_task_exit:
9753         return;
9754 }
9755
9756 /*
9757  * Init service functions
9758  */
9759
9760 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9761 {
9762         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9763         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9764         return base + (BP_ABS_FUNC(bp)) * stride;
9765 }
9766
9767 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9768                                         struct bnx2x_mac_vals *vals)
9769 {
9770         u32 val, base_addr, offset, mask, reset_reg;
9771         bool mac_stopped = false;
9772         u8 port = BP_PORT(bp);
9773
9774         /* reset addresses as they also mark which values were changed */
9775         vals->bmac_addr = 0;
9776         vals->umac_addr = 0;
9777         vals->xmac_addr = 0;
9778         vals->emac_addr = 0;
9779
9780         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9781
9782         if (!CHIP_IS_E3(bp)) {
9783                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9784                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9785                 if ((mask & reset_reg) && val) {
9786                         u32 wb_data[2];
9787                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9788                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9789                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9790                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9791                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9792
9793                         /*
9794                          * use rd/wr since we cannot use dmae. This is safe
9795                          * since MCP won't access the bus due to the request
9796                          * to unload, and no function on the path can be
9797                          * loaded at this time.
9798                          */
9799                         wb_data[0] = REG_RD(bp, base_addr + offset);
9800                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9801                         vals->bmac_addr = base_addr + offset;
9802                         vals->bmac_val[0] = wb_data[0];
9803                         vals->bmac_val[1] = wb_data[1];
9804                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9805                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9806                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9807                 }
9808                 BNX2X_DEV_INFO("Disable emac Rx\n");
9809                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9810                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9811                 REG_WR(bp, vals->emac_addr, 0);
9812                 mac_stopped = true;
9813         } else {
9814                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9815                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9816                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9817                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9818                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9819                                val & ~(1 << 1));
9820                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9821                                val | (1 << 1));
9822                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9823                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9824                         REG_WR(bp, vals->xmac_addr, 0);
9825                         mac_stopped = true;
9826                 }
9827                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9828                 if (mask & reset_reg) {
9829                         BNX2X_DEV_INFO("Disable umac Rx\n");
9830                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9831                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9832                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9833                         REG_WR(bp, vals->umac_addr, 0);
9834                         mac_stopped = true;
9835                 }
9836         }
9837
9838         if (mac_stopped)
9839                 msleep(20);
9840 }
9841
9842 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9843 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9844 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9845 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9846
9847 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9848 {
9849         u16 rcq, bd;
9850         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9851
9852         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9853         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9854
9855         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9856         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9857
9858         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9859                        port, bd, rcq);
9860 }
9861
9862 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9863 {
9864         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9865                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9866         if (!rc) {
9867                 BNX2X_ERR("MCP response failure, aborting\n");
9868                 return -EBUSY;
9869         }
9870
9871         return 0;
9872 }
9873
9874 static struct bnx2x_prev_path_list *
9875                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9876 {
9877         struct bnx2x_prev_path_list *tmp_list;
9878
9879         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9880                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9881                     bp->pdev->bus->number == tmp_list->bus &&
9882                     BP_PATH(bp) == tmp_list->path)
9883                         return tmp_list;
9884
9885         return NULL;
9886 }
9887
9888 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9889 {
9890         struct bnx2x_prev_path_list *tmp_list;
9891         int rc;
9892
9893         rc = down_interruptible(&bnx2x_prev_sem);
9894         if (rc) {
9895                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9896                 return rc;
9897         }
9898
9899         tmp_list = bnx2x_prev_path_get_entry(bp);
9900         if (tmp_list) {
9901                 tmp_list->aer = 1;
9902                 rc = 0;
9903         } else {
9904                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9905                           BP_PATH(bp));
9906         }
9907
9908         up(&bnx2x_prev_sem);
9909
9910         return rc;
9911 }
9912
9913 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9914 {
9915         struct bnx2x_prev_path_list *tmp_list;
9916         int rc = false;
9917
9918         if (down_trylock(&bnx2x_prev_sem))
9919                 return false;
9920
9921         tmp_list = bnx2x_prev_path_get_entry(bp);
9922         if (tmp_list) {
9923                 if (tmp_list->aer) {
9924                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9925                            BP_PATH(bp));
9926                 } else {
9927                         rc = true;
9928                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9929                                        BP_PATH(bp));
9930                 }
9931         }
9932
9933         up(&bnx2x_prev_sem);
9934
9935         return rc;
9936 }
9937
9938 bool bnx2x_port_after_undi(struct bnx2x *bp)
9939 {
9940         struct bnx2x_prev_path_list *entry;
9941         bool val;
9942
9943         down(&bnx2x_prev_sem);
9944
9945         entry = bnx2x_prev_path_get_entry(bp);
9946         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
9947
9948         up(&bnx2x_prev_sem);
9949
9950         return val;
9951 }
9952
9953 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9954 {
9955         struct bnx2x_prev_path_list *tmp_list;
9956         int rc;
9957
9958         rc = down_interruptible(&bnx2x_prev_sem);
9959         if (rc) {
9960                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9961                 return rc;
9962         }
9963
9964         /* Check whether the entry for this path already exists */
9965         tmp_list = bnx2x_prev_path_get_entry(bp);
9966         if (tmp_list) {
9967                 if (!tmp_list->aer) {
9968                         BNX2X_ERR("Re-Marking the path.\n");
9969                 } else {
9970                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9971                            BP_PATH(bp));
9972                         tmp_list->aer = 0;
9973                 }
9974                 up(&bnx2x_prev_sem);
9975                 return 0;
9976         }
9977         up(&bnx2x_prev_sem);
9978
9979         /* Create an entry for this path and add it */
9980         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9981         if (!tmp_list) {
9982                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9983                 return -ENOMEM;
9984         }
9985
9986         tmp_list->bus = bp->pdev->bus->number;
9987         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9988         tmp_list->path = BP_PATH(bp);
9989         tmp_list->aer = 0;
9990         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9991
9992         rc = down_interruptible(&bnx2x_prev_sem);
9993         if (rc) {
9994                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9995                 kfree(tmp_list);
9996         } else {
9997                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
9998                    BP_PATH(bp));
9999                 list_add(&tmp_list->list, &bnx2x_prev_list);
10000                 up(&bnx2x_prev_sem);
10001         }
10002
10003         return rc;
10004 }
10005
10006 static int bnx2x_do_flr(struct bnx2x *bp)
10007 {
10008         struct pci_dev *dev = bp->pdev;
10009
10010         if (CHIP_IS_E1x(bp)) {
10011                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10012                 return -EINVAL;
10013         }
10014
10015         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10016         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10017                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10018                           bp->common.bc_ver);
10019                 return -EINVAL;
10020         }
10021
10022         if (!pci_wait_for_pending_transaction(dev))
10023                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10024
10025         BNX2X_DEV_INFO("Initiating FLR\n");
10026         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10027
10028         return 0;
10029 }
10030
10031 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10032 {
10033         int rc;
10034
10035         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10036
10037         /* Test if previous unload process was already finished for this path */
10038         if (bnx2x_prev_is_path_marked(bp))
10039                 return bnx2x_prev_mcp_done(bp);
10040
10041         BNX2X_DEV_INFO("Path is unmarked\n");
10042
10043         /* If function has FLR capabilities, and existing FW version matches
10044          * the one required, then FLR will be sufficient to clean any residue
10045          * left by previous driver
10046          */
10047         rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
10048
10049         if (!rc) {
10050                 /* fw version is good */
10051                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10052                 rc = bnx2x_do_flr(bp);
10053         }
10054
10055         if (!rc) {
10056                 /* FLR was performed */
10057                 BNX2X_DEV_INFO("FLR successful\n");
10058                 return 0;
10059         }
10060
10061         BNX2X_DEV_INFO("Could not FLR\n");
10062
10063         /* Close the MCP request, return failure*/
10064         rc = bnx2x_prev_mcp_done(bp);
10065         if (!rc)
10066                 rc = BNX2X_PREV_WAIT_NEEDED;
10067
10068         return rc;
10069 }
10070
10071 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10072 {
10073         u32 reset_reg, tmp_reg = 0, rc;
10074         bool prev_undi = false;
10075         struct bnx2x_mac_vals mac_vals;
10076
10077         /* It is possible a previous function received 'common' answer,
10078          * but hasn't loaded yet, therefore creating a scenario of
10079          * multiple functions receiving 'common' on the same path.
10080          */
10081         BNX2X_DEV_INFO("Common unload Flow\n");
10082
10083         memset(&mac_vals, 0, sizeof(mac_vals));
10084
10085         if (bnx2x_prev_is_path_marked(bp))
10086                 return bnx2x_prev_mcp_done(bp);
10087
10088         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10089
10090         /* Reset should be performed after BRB is emptied */
10091         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10092                 u32 timer_count = 1000;
10093
10094                 /* Close the MAC Rx to prevent BRB from filling up */
10095                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10096
10097                 /* close LLH filters towards the BRB */
10098                 bnx2x_set_rx_filter(&bp->link_params, 0);
10099
10100                 /* Check if the UNDI driver was previously loaded
10101                  * UNDI driver initializes CID offset for normal bell to 0x7
10102                  */
10103                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10104                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10105                         if (tmp_reg == 0x7) {
10106                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10107                                 prev_undi = true;
10108                                 /* clear the UNDI indication */
10109                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10110                                 /* clear possible idle check errors */
10111                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10112                         }
10113                 }
10114                 if (!CHIP_IS_E1x(bp))
10115                         /* block FW from writing to host */
10116                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10117
10118                 /* wait until BRB is empty */
10119                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10120                 while (timer_count) {
10121                         u32 prev_brb = tmp_reg;
10122
10123                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10124                         if (!tmp_reg)
10125                                 break;
10126
10127                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10128
10129                         /* reset timer as long as BRB actually gets emptied */
10130                         if (prev_brb > tmp_reg)
10131                                 timer_count = 1000;
10132                         else
10133                                 timer_count--;
10134
10135                         /* If UNDI resides in memory, manually increment it */
10136                         if (prev_undi)
10137                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10138
10139                         udelay(10);
10140                 }
10141
10142                 if (!timer_count)
10143                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10144         }
10145
10146         /* No packets are in the pipeline, path is ready for reset */
10147         bnx2x_reset_common(bp);
10148
10149         if (mac_vals.xmac_addr)
10150                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10151         if (mac_vals.umac_addr)
10152                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10153         if (mac_vals.emac_addr)
10154                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10155         if (mac_vals.bmac_addr) {
10156                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10157                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10158         }
10159
10160         rc = bnx2x_prev_mark_path(bp, prev_undi);
10161         if (rc) {
10162                 bnx2x_prev_mcp_done(bp);
10163                 return rc;
10164         }
10165
10166         return bnx2x_prev_mcp_done(bp);
10167 }
10168
10169 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10170  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10171  * the addresses of the transaction, resulting in was-error bit set in the pci
10172  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10173  * to clear the interrupt which detected this from the pglueb and the was done
10174  * bit
10175  */
10176 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10177 {
10178         if (!CHIP_IS_E1x(bp)) {
10179                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10180                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10181                         DP(BNX2X_MSG_SP,
10182                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10183                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10184                                1 << BP_FUNC(bp));
10185                 }
10186         }
10187 }
10188
10189 static int bnx2x_prev_unload(struct bnx2x *bp)
10190 {
10191         int time_counter = 10;
10192         u32 rc, fw, hw_lock_reg, hw_lock_val;
10193         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10194
10195         /* clear hw from errors which may have resulted from an interrupted
10196          * dmae transaction.
10197          */
10198         bnx2x_prev_interrupted_dmae(bp);
10199
10200         /* Release previously held locks */
10201         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10202                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10203                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10204
10205         hw_lock_val = REG_RD(bp, hw_lock_reg);
10206         if (hw_lock_val) {
10207                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10208                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10209                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10210                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10211                 }
10212
10213                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10214                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10215         } else
10216                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10217
10218         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10219                 BNX2X_DEV_INFO("Release previously held alr\n");
10220                 bnx2x_release_alr(bp);
10221         }
10222
10223         do {
10224                 int aer = 0;
10225                 /* Lock MCP using an unload request */
10226                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10227                 if (!fw) {
10228                         BNX2X_ERR("MCP response failure, aborting\n");
10229                         rc = -EBUSY;
10230                         break;
10231                 }
10232
10233                 rc = down_interruptible(&bnx2x_prev_sem);
10234                 if (rc) {
10235                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10236                                   rc);
10237                 } else {
10238                         /* If Path is marked by EEH, ignore unload status */
10239                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10240                                  bnx2x_prev_path_get_entry(bp)->aer);
10241                         up(&bnx2x_prev_sem);
10242                 }
10243
10244                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10245                         rc = bnx2x_prev_unload_common(bp);
10246                         break;
10247                 }
10248
10249                 /* non-common reply from MCP might require looping */
10250                 rc = bnx2x_prev_unload_uncommon(bp);
10251                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10252                         break;
10253
10254                 msleep(20);
10255         } while (--time_counter);
10256
10257         if (!time_counter || rc) {
10258                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10259                 rc = -EBUSY;
10260         }
10261
10262         /* Mark function if its port was used to boot from SAN */
10263         if (bnx2x_port_after_undi(bp))
10264                 bp->link_params.feature_config_flags |=
10265                         FEATURE_CONFIG_BOOT_FROM_SAN;
10266
10267         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10268
10269         return rc;
10270 }
10271
10272 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10273 {
10274         u32 val, val2, val3, val4, id, boot_mode;
10275         u16 pmc;
10276
10277         /* Get the chip revision id and number. */
10278         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10279         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10280         id = ((val & 0xffff) << 16);
10281         val = REG_RD(bp, MISC_REG_CHIP_REV);
10282         id |= ((val & 0xf) << 12);
10283
10284         /* Metal is read from PCI regs, but we can't access >=0x400 from
10285          * the configuration space (so we need to reg_rd)
10286          */
10287         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10288         id |= (((val >> 24) & 0xf) << 4);
10289         val = REG_RD(bp, MISC_REG_BOND_ID);
10290         id |= (val & 0xf);
10291         bp->common.chip_id = id;
10292
10293         /* force 57811 according to MISC register */
10294         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10295                 if (CHIP_IS_57810(bp))
10296                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10297                                 (bp->common.chip_id & 0x0000FFFF);
10298                 else if (CHIP_IS_57810_MF(bp))
10299                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10300                                 (bp->common.chip_id & 0x0000FFFF);
10301                 bp->common.chip_id |= 0x1;
10302         }
10303
10304         /* Set doorbell size */
10305         bp->db_size = (1 << BNX2X_DB_SHIFT);
10306
10307         if (!CHIP_IS_E1x(bp)) {
10308                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10309                 if ((val & 1) == 0)
10310                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10311                 else
10312                         val = (val >> 1) & 1;
10313                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10314                                                        "2_PORT_MODE");
10315                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10316                                                  CHIP_2_PORT_MODE;
10317
10318                 if (CHIP_MODE_IS_4_PORT(bp))
10319                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10320                 else
10321                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10322         } else {
10323                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10324                 bp->pfid = bp->pf_num;                  /* 0..7 */
10325         }
10326
10327         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10328
10329         bp->link_params.chip_id = bp->common.chip_id;
10330         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10331
10332         val = (REG_RD(bp, 0x2874) & 0x55);
10333         if ((bp->common.chip_id & 0x1) ||
10334             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10335                 bp->flags |= ONE_PORT_FLAG;
10336                 BNX2X_DEV_INFO("single port device\n");
10337         }
10338
10339         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10340         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10341                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10342         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10343                        bp->common.flash_size, bp->common.flash_size);
10344
10345         bnx2x_init_shmem(bp);
10346
10347         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10348                                         MISC_REG_GENERIC_CR_1 :
10349                                         MISC_REG_GENERIC_CR_0));
10350
10351         bp->link_params.shmem_base = bp->common.shmem_base;
10352         bp->link_params.shmem2_base = bp->common.shmem2_base;
10353         if (SHMEM2_RD(bp, size) >
10354             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10355                 bp->link_params.lfa_base =
10356                 REG_RD(bp, bp->common.shmem2_base +
10357                        (u32)offsetof(struct shmem2_region,
10358                                      lfa_host_addr[BP_PORT(bp)]));
10359         else
10360                 bp->link_params.lfa_base = 0;
10361         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10362                        bp->common.shmem_base, bp->common.shmem2_base);
10363
10364         if (!bp->common.shmem_base) {
10365                 BNX2X_DEV_INFO("MCP not active\n");
10366                 bp->flags |= NO_MCP_FLAG;
10367                 return;
10368         }
10369
10370         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10371         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10372
10373         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10374                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10375                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10376
10377         bp->link_params.feature_config_flags = 0;
10378         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10379         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10380                 bp->link_params.feature_config_flags |=
10381                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10382         else
10383                 bp->link_params.feature_config_flags &=
10384                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10385
10386         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10387         bp->common.bc_ver = val;
10388         BNX2X_DEV_INFO("bc_ver %X\n", val);
10389         if (val < BNX2X_BC_VER) {
10390                 /* for now only warn
10391                  * later we might need to enforce this */
10392                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10393                           BNX2X_BC_VER, val);
10394         }
10395         bp->link_params.feature_config_flags |=
10396                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10397                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10398
10399         bp->link_params.feature_config_flags |=
10400                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10401                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10402         bp->link_params.feature_config_flags |=
10403                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10404                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10405         bp->link_params.feature_config_flags |=
10406                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10407                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10408
10409         bp->link_params.feature_config_flags |=
10410                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10411                 FEATURE_CONFIG_MT_SUPPORT : 0;
10412
10413         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10414                         BC_SUPPORTS_PFC_STATS : 0;
10415
10416         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10417                         BC_SUPPORTS_FCOE_FEATURES : 0;
10418
10419         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10420                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10421
10422         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10423                         BC_SUPPORTS_RMMOD_CMD : 0;
10424
10425         boot_mode = SHMEM_RD(bp,
10426                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10427                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10428         switch (boot_mode) {
10429         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10430                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10431                 break;
10432         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10433                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10434                 break;
10435         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10436                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10437                 break;
10438         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10439                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10440                 break;
10441         }
10442
10443         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10444         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10445
10446         BNX2X_DEV_INFO("%sWoL capable\n",
10447                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10448
10449         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10450         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10451         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10452         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10453
10454         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10455                  val, val2, val3, val4);
10456 }
10457
10458 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10459 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10460
10461 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10462 {
10463         int pfid = BP_FUNC(bp);
10464         int igu_sb_id;
10465         u32 val;
10466         u8 fid, igu_sb_cnt = 0;
10467
10468         bp->igu_base_sb = 0xff;
10469         if (CHIP_INT_MODE_IS_BC(bp)) {
10470                 int vn = BP_VN(bp);
10471                 igu_sb_cnt = bp->igu_sb_cnt;
10472                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10473                         FP_SB_MAX_E1x;
10474
10475                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10476                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10477
10478                 return 0;
10479         }
10480
10481         /* IGU in normal mode - read CAM */
10482         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10483              igu_sb_id++) {
10484                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10485                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10486                         continue;
10487                 fid = IGU_FID(val);
10488                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10489                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10490                                 continue;
10491                         if (IGU_VEC(val) == 0)
10492                                 /* default status block */
10493                                 bp->igu_dsb_id = igu_sb_id;
10494                         else {
10495                                 if (bp->igu_base_sb == 0xff)
10496                                         bp->igu_base_sb = igu_sb_id;
10497                                 igu_sb_cnt++;
10498                         }
10499                 }
10500         }
10501
10502 #ifdef CONFIG_PCI_MSI
10503         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10504          * optional that number of CAM entries will not be equal to the value
10505          * advertised in PCI.
10506          * Driver should use the minimal value of both as the actual status
10507          * block count
10508          */
10509         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10510 #endif
10511
10512         if (igu_sb_cnt == 0) {
10513                 BNX2X_ERR("CAM configuration error\n");
10514                 return -EINVAL;
10515         }
10516
10517         return 0;
10518 }
10519
10520 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10521 {
10522         int cfg_size = 0, idx, port = BP_PORT(bp);
10523
10524         /* Aggregation of supported attributes of all external phys */
10525         bp->port.supported[0] = 0;
10526         bp->port.supported[1] = 0;
10527         switch (bp->link_params.num_phys) {
10528         case 1:
10529                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10530                 cfg_size = 1;
10531                 break;
10532         case 2:
10533                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10534                 cfg_size = 1;
10535                 break;
10536         case 3:
10537                 if (bp->link_params.multi_phy_config &
10538                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10539                         bp->port.supported[1] =
10540                                 bp->link_params.phy[EXT_PHY1].supported;
10541                         bp->port.supported[0] =
10542                                 bp->link_params.phy[EXT_PHY2].supported;
10543                 } else {
10544                         bp->port.supported[0] =
10545                                 bp->link_params.phy[EXT_PHY1].supported;
10546                         bp->port.supported[1] =
10547                                 bp->link_params.phy[EXT_PHY2].supported;
10548                 }
10549                 cfg_size = 2;
10550                 break;
10551         }
10552
10553         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10554                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10555                            SHMEM_RD(bp,
10556                            dev_info.port_hw_config[port].external_phy_config),
10557                            SHMEM_RD(bp,
10558                            dev_info.port_hw_config[port].external_phy_config2));
10559                         return;
10560         }
10561
10562         if (CHIP_IS_E3(bp))
10563                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10564         else {
10565                 switch (switch_cfg) {
10566                 case SWITCH_CFG_1G:
10567                         bp->port.phy_addr = REG_RD(
10568                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10569                         break;
10570                 case SWITCH_CFG_10G:
10571                         bp->port.phy_addr = REG_RD(
10572                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10573                         break;
10574                 default:
10575                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10576                                   bp->port.link_config[0]);
10577                         return;
10578                 }
10579         }
10580         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10581         /* mask what we support according to speed_cap_mask per configuration */
10582         for (idx = 0; idx < cfg_size; idx++) {
10583                 if (!(bp->link_params.speed_cap_mask[idx] &
10584                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10585                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10586
10587                 if (!(bp->link_params.speed_cap_mask[idx] &
10588                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10589                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10590
10591                 if (!(bp->link_params.speed_cap_mask[idx] &
10592                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10593                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10594
10595                 if (!(bp->link_params.speed_cap_mask[idx] &
10596                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10597                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10598
10599                 if (!(bp->link_params.speed_cap_mask[idx] &
10600                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10601                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10602                                                      SUPPORTED_1000baseT_Full);
10603
10604                 if (!(bp->link_params.speed_cap_mask[idx] &
10605                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10606                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10607
10608                 if (!(bp->link_params.speed_cap_mask[idx] &
10609                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10610                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10611
10612                 if (!(bp->link_params.speed_cap_mask[idx] &
10613                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10614                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10615         }
10616
10617         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10618                        bp->port.supported[1]);
10619 }
10620
10621 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10622 {
10623         u32 link_config, idx, cfg_size = 0;
10624         bp->port.advertising[0] = 0;
10625         bp->port.advertising[1] = 0;
10626         switch (bp->link_params.num_phys) {
10627         case 1:
10628         case 2:
10629                 cfg_size = 1;
10630                 break;
10631         case 3:
10632                 cfg_size = 2;
10633                 break;
10634         }
10635         for (idx = 0; idx < cfg_size; idx++) {
10636                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10637                 link_config = bp->port.link_config[idx];
10638                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10639                 case PORT_FEATURE_LINK_SPEED_AUTO:
10640                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10641                                 bp->link_params.req_line_speed[idx] =
10642                                         SPEED_AUTO_NEG;
10643                                 bp->port.advertising[idx] |=
10644                                         bp->port.supported[idx];
10645                                 if (bp->link_params.phy[EXT_PHY1].type ==
10646                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10647                                         bp->port.advertising[idx] |=
10648                                         (SUPPORTED_100baseT_Half |
10649                                          SUPPORTED_100baseT_Full);
10650                         } else {
10651                                 /* force 10G, no AN */
10652                                 bp->link_params.req_line_speed[idx] =
10653                                         SPEED_10000;
10654                                 bp->port.advertising[idx] |=
10655                                         (ADVERTISED_10000baseT_Full |
10656                                          ADVERTISED_FIBRE);
10657                                 continue;
10658                         }
10659                         break;
10660
10661                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10662                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10663                                 bp->link_params.req_line_speed[idx] =
10664                                         SPEED_10;
10665                                 bp->port.advertising[idx] |=
10666                                         (ADVERTISED_10baseT_Full |
10667                                          ADVERTISED_TP);
10668                         } else {
10669                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10670                                             link_config,
10671                                     bp->link_params.speed_cap_mask[idx]);
10672                                 return;
10673                         }
10674                         break;
10675
10676                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10677                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10678                                 bp->link_params.req_line_speed[idx] =
10679                                         SPEED_10;
10680                                 bp->link_params.req_duplex[idx] =
10681                                         DUPLEX_HALF;
10682                                 bp->port.advertising[idx] |=
10683                                         (ADVERTISED_10baseT_Half |
10684                                          ADVERTISED_TP);
10685                         } else {
10686                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10687                                             link_config,
10688                                           bp->link_params.speed_cap_mask[idx]);
10689                                 return;
10690                         }
10691                         break;
10692
10693                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10694                         if (bp->port.supported[idx] &
10695                             SUPPORTED_100baseT_Full) {
10696                                 bp->link_params.req_line_speed[idx] =
10697                                         SPEED_100;
10698                                 bp->port.advertising[idx] |=
10699                                         (ADVERTISED_100baseT_Full |
10700                                          ADVERTISED_TP);
10701                         } else {
10702                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10703                                             link_config,
10704                                           bp->link_params.speed_cap_mask[idx]);
10705                                 return;
10706                         }
10707                         break;
10708
10709                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10710                         if (bp->port.supported[idx] &
10711                             SUPPORTED_100baseT_Half) {
10712                                 bp->link_params.req_line_speed[idx] =
10713                                                                 SPEED_100;
10714                                 bp->link_params.req_duplex[idx] =
10715                                                                 DUPLEX_HALF;
10716                                 bp->port.advertising[idx] |=
10717                                         (ADVERTISED_100baseT_Half |
10718                                          ADVERTISED_TP);
10719                         } else {
10720                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10721                                     link_config,
10722                                     bp->link_params.speed_cap_mask[idx]);
10723                                 return;
10724                         }
10725                         break;
10726
10727                 case PORT_FEATURE_LINK_SPEED_1G:
10728                         if (bp->port.supported[idx] &
10729                             SUPPORTED_1000baseT_Full) {
10730                                 bp->link_params.req_line_speed[idx] =
10731                                         SPEED_1000;
10732                                 bp->port.advertising[idx] |=
10733                                         (ADVERTISED_1000baseT_Full |
10734                                          ADVERTISED_TP);
10735                         } else {
10736                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10737                                     link_config,
10738                                     bp->link_params.speed_cap_mask[idx]);
10739                                 return;
10740                         }
10741                         break;
10742
10743                 case PORT_FEATURE_LINK_SPEED_2_5G:
10744                         if (bp->port.supported[idx] &
10745                             SUPPORTED_2500baseX_Full) {
10746                                 bp->link_params.req_line_speed[idx] =
10747                                         SPEED_2500;
10748                                 bp->port.advertising[idx] |=
10749                                         (ADVERTISED_2500baseX_Full |
10750                                                 ADVERTISED_TP);
10751                         } else {
10752                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10753                                     link_config,
10754                                     bp->link_params.speed_cap_mask[idx]);
10755                                 return;
10756                         }
10757                         break;
10758
10759                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10760                         if (bp->port.supported[idx] &
10761                             SUPPORTED_10000baseT_Full) {
10762                                 bp->link_params.req_line_speed[idx] =
10763                                         SPEED_10000;
10764                                 bp->port.advertising[idx] |=
10765                                         (ADVERTISED_10000baseT_Full |
10766                                                 ADVERTISED_FIBRE);
10767                         } else {
10768                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10769                                     link_config,
10770                                     bp->link_params.speed_cap_mask[idx]);
10771                                 return;
10772                         }
10773                         break;
10774                 case PORT_FEATURE_LINK_SPEED_20G:
10775                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10776
10777                         break;
10778                 default:
10779                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10780                                   link_config);
10781                                 bp->link_params.req_line_speed[idx] =
10782                                                         SPEED_AUTO_NEG;
10783                                 bp->port.advertising[idx] =
10784                                                 bp->port.supported[idx];
10785                         break;
10786                 }
10787
10788                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10789                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10790                 if (bp->link_params.req_flow_ctrl[idx] ==
10791                     BNX2X_FLOW_CTRL_AUTO) {
10792                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10793                                 bp->link_params.req_flow_ctrl[idx] =
10794                                                         BNX2X_FLOW_CTRL_NONE;
10795                         else
10796                                 bnx2x_set_requested_fc(bp);
10797                 }
10798
10799                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10800                                bp->link_params.req_line_speed[idx],
10801                                bp->link_params.req_duplex[idx],
10802                                bp->link_params.req_flow_ctrl[idx],
10803                                bp->port.advertising[idx]);
10804         }
10805 }
10806
10807 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10808 {
10809         __be16 mac_hi_be = cpu_to_be16(mac_hi);
10810         __be32 mac_lo_be = cpu_to_be32(mac_lo);
10811         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10812         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10813 }
10814
10815 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10816 {
10817         int port = BP_PORT(bp);
10818         u32 config;
10819         u32 ext_phy_type, ext_phy_config, eee_mode;
10820
10821         bp->link_params.bp = bp;
10822         bp->link_params.port = port;
10823
10824         bp->link_params.lane_config =
10825                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10826
10827         bp->link_params.speed_cap_mask[0] =
10828                 SHMEM_RD(bp,
10829                          dev_info.port_hw_config[port].speed_capability_mask) &
10830                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10831         bp->link_params.speed_cap_mask[1] =
10832                 SHMEM_RD(bp,
10833                          dev_info.port_hw_config[port].speed_capability_mask2) &
10834                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10835         bp->port.link_config[0] =
10836                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10837
10838         bp->port.link_config[1] =
10839                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10840
10841         bp->link_params.multi_phy_config =
10842                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10843         /* If the device is capable of WoL, set the default state according
10844          * to the HW
10845          */
10846         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10847         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10848                    (config & PORT_FEATURE_WOL_ENABLED));
10849
10850         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10851             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10852                 bp->flags |= NO_ISCSI_FLAG;
10853         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10854             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10855                 bp->flags |= NO_FCOE_FLAG;
10856
10857         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10858                        bp->link_params.lane_config,
10859                        bp->link_params.speed_cap_mask[0],
10860                        bp->port.link_config[0]);
10861
10862         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10863                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10864         bnx2x_phy_probe(&bp->link_params);
10865         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10866
10867         bnx2x_link_settings_requested(bp);
10868
10869         /*
10870          * If connected directly, work with the internal PHY, otherwise, work
10871          * with the external PHY
10872          */
10873         ext_phy_config =
10874                 SHMEM_RD(bp,
10875                          dev_info.port_hw_config[port].external_phy_config);
10876         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10877         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10878                 bp->mdio.prtad = bp->port.phy_addr;
10879
10880         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10881                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10882                 bp->mdio.prtad =
10883                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10884
10885         /* Configure link feature according to nvram value */
10886         eee_mode = (((SHMEM_RD(bp, dev_info.
10887                       port_feature_config[port].eee_power_mode)) &
10888                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10889                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10890         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10891                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10892                                            EEE_MODE_ENABLE_LPI |
10893                                            EEE_MODE_OUTPUT_TIME;
10894         } else {
10895                 bp->link_params.eee_mode = 0;
10896         }
10897 }
10898
10899 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10900 {
10901         u32 no_flags = NO_ISCSI_FLAG;
10902         int port = BP_PORT(bp);
10903         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10904                                 drv_lic_key[port].max_iscsi_conn);
10905
10906         if (!CNIC_SUPPORT(bp)) {
10907                 bp->flags |= no_flags;
10908                 return;
10909         }
10910
10911         /* Get the number of maximum allowed iSCSI connections */
10912         bp->cnic_eth_dev.max_iscsi_conn =
10913                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10914                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10915
10916         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10917                        bp->cnic_eth_dev.max_iscsi_conn);
10918
10919         /*
10920          * If maximum allowed number of connections is zero -
10921          * disable the feature.
10922          */
10923         if (!bp->cnic_eth_dev.max_iscsi_conn)
10924                 bp->flags |= no_flags;
10925 }
10926
10927 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10928 {
10929         /* Port info */
10930         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10931                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10932         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10933                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10934
10935         /* Node info */
10936         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10937                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10938         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10939                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10940 }
10941
10942 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
10943 {
10944         u8 count = 0;
10945
10946         if (IS_MF(bp)) {
10947                 u8 fid;
10948
10949                 /* iterate over absolute function ids for this path: */
10950                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
10951                         if (IS_MF_SD(bp)) {
10952                                 u32 cfg = MF_CFG_RD(bp,
10953                                                     func_mf_config[fid].config);
10954
10955                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
10956                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
10957                                             FUNC_MF_CFG_PROTOCOL_FCOE))
10958                                         count++;
10959                         } else {
10960                                 u32 cfg = MF_CFG_RD(bp,
10961                                                     func_ext_config[fid].
10962                                                                       func_cfg);
10963
10964                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
10965                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
10966                                         count++;
10967                         }
10968                 }
10969         } else { /* SF */
10970                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
10971
10972                 for (port = 0; port < port_cnt; port++) {
10973                         u32 lic = SHMEM_RD(bp,
10974                                            drv_lic_key[port].max_fcoe_conn) ^
10975                                   FW_ENCODE_32BIT_PATTERN;
10976                         if (lic)
10977                                 count++;
10978                 }
10979         }
10980
10981         return count;
10982 }
10983
10984 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10985 {
10986         int port = BP_PORT(bp);
10987         int func = BP_ABS_FUNC(bp);
10988         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10989                                 drv_lic_key[port].max_fcoe_conn);
10990         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
10991
10992         if (!CNIC_SUPPORT(bp)) {
10993                 bp->flags |= NO_FCOE_FLAG;
10994                 return;
10995         }
10996
10997         /* Get the number of maximum allowed FCoE connections */
10998         bp->cnic_eth_dev.max_fcoe_conn =
10999                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11000                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11001
11002         /* Calculate the number of maximum allowed FCoE tasks */
11003         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11004
11005         /* check if FCoE resources must be shared between different functions */
11006         if (num_fcoe_func)
11007                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11008
11009         /* Read the WWN: */
11010         if (!IS_MF(bp)) {
11011                 /* Port info */
11012                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11013                         SHMEM_RD(bp,
11014                                  dev_info.port_hw_config[port].
11015                                  fcoe_wwn_port_name_upper);
11016                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11017                         SHMEM_RD(bp,
11018                                  dev_info.port_hw_config[port].
11019                                  fcoe_wwn_port_name_lower);
11020
11021                 /* Node info */
11022                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11023                         SHMEM_RD(bp,
11024                                  dev_info.port_hw_config[port].
11025                                  fcoe_wwn_node_name_upper);
11026                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11027                         SHMEM_RD(bp,
11028                                  dev_info.port_hw_config[port].
11029                                  fcoe_wwn_node_name_lower);
11030         } else if (!IS_MF_SD(bp)) {
11031                 /*
11032                  * Read the WWN info only if the FCoE feature is enabled for
11033                  * this function.
11034                  */
11035                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11036                         bnx2x_get_ext_wwn_info(bp, func);
11037
11038         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
11039                 bnx2x_get_ext_wwn_info(bp, func);
11040         }
11041
11042         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11043
11044         /*
11045          * If maximum allowed number of connections is zero -
11046          * disable the feature.
11047          */
11048         if (!bp->cnic_eth_dev.max_fcoe_conn)
11049                 bp->flags |= NO_FCOE_FLAG;
11050 }
11051
11052 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11053 {
11054         /*
11055          * iSCSI may be dynamically disabled but reading
11056          * info here we will decrease memory usage by driver
11057          * if the feature is disabled for good
11058          */
11059         bnx2x_get_iscsi_info(bp);
11060         bnx2x_get_fcoe_info(bp);
11061 }
11062
11063 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11064 {
11065         u32 val, val2;
11066         int func = BP_ABS_FUNC(bp);
11067         int port = BP_PORT(bp);
11068         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11069         u8 *fip_mac = bp->fip_mac;
11070
11071         if (IS_MF(bp)) {
11072                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11073                  * FCoE MAC then the appropriate feature should be disabled.
11074                  * In non SD mode features configuration comes from struct
11075                  * func_ext_config.
11076                  */
11077                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11078                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11079                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11080                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11081                                                  iscsi_mac_addr_upper);
11082                                 val = MF_CFG_RD(bp, func_ext_config[func].
11083                                                 iscsi_mac_addr_lower);
11084                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11085                                 BNX2X_DEV_INFO
11086                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11087                         } else {
11088                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11089                         }
11090
11091                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11092                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11093                                                  fcoe_mac_addr_upper);
11094                                 val = MF_CFG_RD(bp, func_ext_config[func].
11095                                                 fcoe_mac_addr_lower);
11096                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11097                                 BNX2X_DEV_INFO
11098                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11099                         } else {
11100                                 bp->flags |= NO_FCOE_FLAG;
11101                         }
11102
11103                         bp->mf_ext_config = cfg;
11104
11105                 } else { /* SD MODE */
11106                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11107                                 /* use primary mac as iscsi mac */
11108                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11109
11110                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11111                                 BNX2X_DEV_INFO
11112                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11113                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11114                                 /* use primary mac as fip mac */
11115                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11116                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11117                                 BNX2X_DEV_INFO
11118                                         ("Read FIP MAC: %pM\n", fip_mac);
11119                         }
11120                 }
11121
11122                 /* If this is a storage-only interface, use SAN mac as
11123                  * primary MAC. Notice that for SD this is already the case,
11124                  * as the SAN mac was copied from the primary MAC.
11125                  */
11126                 if (IS_MF_FCOE_AFEX(bp))
11127                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11128         } else {
11129                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11130                                 iscsi_mac_upper);
11131                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11132                                iscsi_mac_lower);
11133                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11134
11135                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11136                                 fcoe_fip_mac_upper);
11137                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11138                                fcoe_fip_mac_lower);
11139                 bnx2x_set_mac_buf(fip_mac, val, val2);
11140         }
11141
11142         /* Disable iSCSI OOO if MAC configuration is invalid. */
11143         if (!is_valid_ether_addr(iscsi_mac)) {
11144                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11145                 memset(iscsi_mac, 0, ETH_ALEN);
11146         }
11147
11148         /* Disable FCoE if MAC configuration is invalid. */
11149         if (!is_valid_ether_addr(fip_mac)) {
11150                 bp->flags |= NO_FCOE_FLAG;
11151                 memset(bp->fip_mac, 0, ETH_ALEN);
11152         }
11153 }
11154
11155 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11156 {
11157         u32 val, val2;
11158         int func = BP_ABS_FUNC(bp);
11159         int port = BP_PORT(bp);
11160
11161         /* Zero primary MAC configuration */
11162         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11163
11164         if (BP_NOMCP(bp)) {
11165                 BNX2X_ERROR("warning: random MAC workaround active\n");
11166                 eth_hw_addr_random(bp->dev);
11167         } else if (IS_MF(bp)) {
11168                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11169                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11170                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11171                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11172                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11173
11174                 if (CNIC_SUPPORT(bp))
11175                         bnx2x_get_cnic_mac_hwinfo(bp);
11176         } else {
11177                 /* in SF read MACs from port configuration */
11178                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11179                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11180                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11181
11182                 if (CNIC_SUPPORT(bp))
11183                         bnx2x_get_cnic_mac_hwinfo(bp);
11184         }
11185
11186         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11187
11188         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11189                 dev_err(&bp->pdev->dev,
11190                         "bad Ethernet MAC address configuration: %pM\n"
11191                         "change it manually before bringing up the appropriate network interface\n",
11192                         bp->dev->dev_addr);
11193 }
11194
11195 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11196 {
11197         int tmp;
11198         u32 cfg;
11199
11200         if (IS_VF(bp))
11201                 return 0;
11202
11203         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11204                 /* Take function: tmp = func */
11205                 tmp = BP_ABS_FUNC(bp);
11206                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11207                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11208         } else {
11209                 /* Take port: tmp = port */
11210                 tmp = BP_PORT(bp);
11211                 cfg = SHMEM_RD(bp,
11212                                dev_info.port_hw_config[tmp].generic_features);
11213                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11214         }
11215         return cfg;
11216 }
11217
11218 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11219 {
11220         int /*abs*/func = BP_ABS_FUNC(bp);
11221         int vn;
11222         u32 val = 0;
11223         int rc = 0;
11224
11225         bnx2x_get_common_hwinfo(bp);
11226
11227         /*
11228          * initialize IGU parameters
11229          */
11230         if (CHIP_IS_E1x(bp)) {
11231                 bp->common.int_block = INT_BLOCK_HC;
11232
11233                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11234                 bp->igu_base_sb = 0;
11235         } else {
11236                 bp->common.int_block = INT_BLOCK_IGU;
11237
11238                 /* do not allow device reset during IGU info processing */
11239                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11240
11241                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11242
11243                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11244                         int tout = 5000;
11245
11246                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11247
11248                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11249                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11250                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11251
11252                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11253                                 tout--;
11254                                 usleep_range(1000, 2000);
11255                         }
11256
11257                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11258                                 dev_err(&bp->pdev->dev,
11259                                         "FORCING Normal Mode failed!!!\n");
11260                                 bnx2x_release_hw_lock(bp,
11261                                                       HW_LOCK_RESOURCE_RESET);
11262                                 return -EPERM;
11263                         }
11264                 }
11265
11266                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11267                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11268                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11269                 } else
11270                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11271
11272                 rc = bnx2x_get_igu_cam_info(bp);
11273                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11274                 if (rc)
11275                         return rc;
11276         }
11277
11278         /*
11279          * set base FW non-default (fast path) status block id, this value is
11280          * used to initialize the fw_sb_id saved on the fp/queue structure to
11281          * determine the id used by the FW.
11282          */
11283         if (CHIP_IS_E1x(bp))
11284                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11285         else /*
11286               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11287               * the same queue are indicated on the same IGU SB). So we prefer
11288               * FW and IGU SBs to be the same value.
11289               */
11290                 bp->base_fw_ndsb = bp->igu_base_sb;
11291
11292         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11293                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11294                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11295
11296         /*
11297          * Initialize MF configuration
11298          */
11299
11300         bp->mf_ov = 0;
11301         bp->mf_mode = 0;
11302         vn = BP_VN(bp);
11303
11304         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11305                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11306                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11307                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11308
11309                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11310                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11311                 else
11312                         bp->common.mf_cfg_base = bp->common.shmem_base +
11313                                 offsetof(struct shmem_region, func_mb) +
11314                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11315                 /*
11316                  * get mf configuration:
11317                  * 1. Existence of MF configuration
11318                  * 2. MAC address must be legal (check only upper bytes)
11319                  *    for  Switch-Independent mode;
11320                  *    OVLAN must be legal for Switch-Dependent mode
11321                  * 3. SF_MODE configures specific MF mode
11322                  */
11323                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11324                         /* get mf configuration */
11325                         val = SHMEM_RD(bp,
11326                                        dev_info.shared_feature_config.config);
11327                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11328
11329                         switch (val) {
11330                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11331                                 val = MF_CFG_RD(bp, func_mf_config[func].
11332                                                 mac_upper);
11333                                 /* check for legal mac (upper bytes)*/
11334                                 if (val != 0xffff) {
11335                                         bp->mf_mode = MULTI_FUNCTION_SI;
11336                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11337                                                    func_mf_config[func].config);
11338                                 } else
11339                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11340                                 break;
11341                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11342                                 if ((!CHIP_IS_E1x(bp)) &&
11343                                     (MF_CFG_RD(bp, func_mf_config[func].
11344                                                mac_upper) != 0xffff) &&
11345                                     (SHMEM2_HAS(bp,
11346                                                 afex_driver_support))) {
11347                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11348                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11349                                                 func_mf_config[func].config);
11350                                 } else {
11351                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11352                                 }
11353                                 break;
11354                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11355                                 /* get OV configuration */
11356                                 val = MF_CFG_RD(bp,
11357                                         func_mf_config[FUNC_0].e1hov_tag);
11358                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11359
11360                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11361                                         bp->mf_mode = MULTI_FUNCTION_SD;
11362                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11363                                                 func_mf_config[func].config);
11364                                 } else
11365                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11366                                 break;
11367                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11368                                 bp->mf_config[vn] = 0;
11369                                 break;
11370                         default:
11371                                 /* Unknown configuration: reset mf_config */
11372                                 bp->mf_config[vn] = 0;
11373                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11374                         }
11375                 }
11376
11377                 BNX2X_DEV_INFO("%s function mode\n",
11378                                IS_MF(bp) ? "multi" : "single");
11379
11380                 switch (bp->mf_mode) {
11381                 case MULTI_FUNCTION_SD:
11382                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11383                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11384                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11385                                 bp->mf_ov = val;
11386                                 bp->path_has_ovlan = true;
11387
11388                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11389                                                func, bp->mf_ov, bp->mf_ov);
11390                         } else {
11391                                 dev_err(&bp->pdev->dev,
11392                                         "No valid MF OV for func %d, aborting\n",
11393                                         func);
11394                                 return -EPERM;
11395                         }
11396                         break;
11397                 case MULTI_FUNCTION_AFEX:
11398                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11399                         break;
11400                 case MULTI_FUNCTION_SI:
11401                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11402                                        func);
11403                         break;
11404                 default:
11405                         if (vn) {
11406                                 dev_err(&bp->pdev->dev,
11407                                         "VN %d is in a single function mode, aborting\n",
11408                                         vn);
11409                                 return -EPERM;
11410                         }
11411                         break;
11412                 }
11413
11414                 /* check if other port on the path needs ovlan:
11415                  * Since MF configuration is shared between ports
11416                  * Possible mixed modes are only
11417                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11418                  */
11419                 if (CHIP_MODE_IS_4_PORT(bp) &&
11420                     !bp->path_has_ovlan &&
11421                     !IS_MF(bp) &&
11422                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11423                         u8 other_port = !BP_PORT(bp);
11424                         u8 other_func = BP_PATH(bp) + 2*other_port;
11425                         val = MF_CFG_RD(bp,
11426                                         func_mf_config[other_func].e1hov_tag);
11427                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11428                                 bp->path_has_ovlan = true;
11429                 }
11430         }
11431
11432         /* adjust igu_sb_cnt to MF for E1x */
11433         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11434                 bp->igu_sb_cnt /= E1HVN_MAX;
11435
11436         /* port info */
11437         bnx2x_get_port_hwinfo(bp);
11438
11439         /* Get MAC addresses */
11440         bnx2x_get_mac_hwinfo(bp);
11441
11442         bnx2x_get_cnic_info(bp);
11443
11444         return rc;
11445 }
11446
11447 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11448 {
11449         int cnt, i, block_end, rodi;
11450         char vpd_start[BNX2X_VPD_LEN+1];
11451         char str_id_reg[VENDOR_ID_LEN+1];
11452         char str_id_cap[VENDOR_ID_LEN+1];
11453         char *vpd_data;
11454         char *vpd_extended_data = NULL;
11455         u8 len;
11456
11457         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11458         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11459
11460         if (cnt < BNX2X_VPD_LEN)
11461                 goto out_not_found;
11462
11463         /* VPD RO tag should be first tag after identifier string, hence
11464          * we should be able to find it in first BNX2X_VPD_LEN chars
11465          */
11466         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11467                              PCI_VPD_LRDT_RO_DATA);
11468         if (i < 0)
11469                 goto out_not_found;
11470
11471         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11472                     pci_vpd_lrdt_size(&vpd_start[i]);
11473
11474         i += PCI_VPD_LRDT_TAG_SIZE;
11475
11476         if (block_end > BNX2X_VPD_LEN) {
11477                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11478                 if (vpd_extended_data  == NULL)
11479                         goto out_not_found;
11480
11481                 /* read rest of vpd image into vpd_extended_data */
11482                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11483                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11484                                    block_end - BNX2X_VPD_LEN,
11485                                    vpd_extended_data + BNX2X_VPD_LEN);
11486                 if (cnt < (block_end - BNX2X_VPD_LEN))
11487                         goto out_not_found;
11488                 vpd_data = vpd_extended_data;
11489         } else
11490                 vpd_data = vpd_start;
11491
11492         /* now vpd_data holds full vpd content in both cases */
11493
11494         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11495                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11496         if (rodi < 0)
11497                 goto out_not_found;
11498
11499         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11500
11501         if (len != VENDOR_ID_LEN)
11502                 goto out_not_found;
11503
11504         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11505
11506         /* vendor specific info */
11507         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11508         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11509         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11510             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11511
11512                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11513                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11514                 if (rodi >= 0) {
11515                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11516
11517                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11518
11519                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11520                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11521                                 bp->fw_ver[len] = ' ';
11522                         }
11523                 }
11524                 kfree(vpd_extended_data);
11525                 return;
11526         }
11527 out_not_found:
11528         kfree(vpd_extended_data);
11529         return;
11530 }
11531
11532 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11533 {
11534         u32 flags = 0;
11535
11536         if (CHIP_REV_IS_FPGA(bp))
11537                 SET_FLAGS(flags, MODE_FPGA);
11538         else if (CHIP_REV_IS_EMUL(bp))
11539                 SET_FLAGS(flags, MODE_EMUL);
11540         else
11541                 SET_FLAGS(flags, MODE_ASIC);
11542
11543         if (CHIP_MODE_IS_4_PORT(bp))
11544                 SET_FLAGS(flags, MODE_PORT4);
11545         else
11546                 SET_FLAGS(flags, MODE_PORT2);
11547
11548         if (CHIP_IS_E2(bp))
11549                 SET_FLAGS(flags, MODE_E2);
11550         else if (CHIP_IS_E3(bp)) {
11551                 SET_FLAGS(flags, MODE_E3);
11552                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11553                         SET_FLAGS(flags, MODE_E3_A0);
11554                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11555                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11556         }
11557
11558         if (IS_MF(bp)) {
11559                 SET_FLAGS(flags, MODE_MF);
11560                 switch (bp->mf_mode) {
11561                 case MULTI_FUNCTION_SD:
11562                         SET_FLAGS(flags, MODE_MF_SD);
11563                         break;
11564                 case MULTI_FUNCTION_SI:
11565                         SET_FLAGS(flags, MODE_MF_SI);
11566                         break;
11567                 case MULTI_FUNCTION_AFEX:
11568                         SET_FLAGS(flags, MODE_MF_AFEX);
11569                         break;
11570                 }
11571         } else
11572                 SET_FLAGS(flags, MODE_SF);
11573
11574 #if defined(__LITTLE_ENDIAN)
11575         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11576 #else /*(__BIG_ENDIAN)*/
11577         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11578 #endif
11579         INIT_MODE_FLAGS(bp) = flags;
11580 }
11581
11582 static int bnx2x_init_bp(struct bnx2x *bp)
11583 {
11584         int func;
11585         int rc;
11586
11587         mutex_init(&bp->port.phy_mutex);
11588         mutex_init(&bp->fw_mb_mutex);
11589         spin_lock_init(&bp->stats_lock);
11590         sema_init(&bp->stats_sema, 1);
11591
11592         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11593         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11594         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11595         if (IS_PF(bp)) {
11596                 rc = bnx2x_get_hwinfo(bp);
11597                 if (rc)
11598                         return rc;
11599         } else {
11600                 eth_zero_addr(bp->dev->dev_addr);
11601         }
11602
11603         bnx2x_set_modes_bitmap(bp);
11604
11605         rc = bnx2x_alloc_mem_bp(bp);
11606         if (rc)
11607                 return rc;
11608
11609         bnx2x_read_fwinfo(bp);
11610
11611         func = BP_FUNC(bp);
11612
11613         /* need to reset chip if undi was active */
11614         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11615                 /* init fw_seq */
11616                 bp->fw_seq =
11617                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11618                                                         DRV_MSG_SEQ_NUMBER_MASK;
11619                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11620
11621                 bnx2x_prev_unload(bp);
11622         }
11623
11624         if (CHIP_REV_IS_FPGA(bp))
11625                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11626
11627         if (BP_NOMCP(bp) && (func == 0))
11628                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11629
11630         bp->disable_tpa = disable_tpa;
11631         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11632
11633         /* Set TPA flags */
11634         if (bp->disable_tpa) {
11635                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11636                 bp->dev->features &= ~NETIF_F_LRO;
11637         } else {
11638                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11639                 bp->dev->features |= NETIF_F_LRO;
11640         }
11641
11642         if (CHIP_IS_E1(bp))
11643                 bp->dropless_fc = 0;
11644         else
11645                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11646
11647         bp->mrrs = mrrs;
11648
11649         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11650         if (IS_VF(bp))
11651                 bp->rx_ring_size = MAX_RX_AVAIL;
11652
11653         /* make sure that the numbers are in the right granularity */
11654         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11655         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11656
11657         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11658
11659         init_timer(&bp->timer);
11660         bp->timer.expires = jiffies + bp->current_interval;
11661         bp->timer.data = (unsigned long) bp;
11662         bp->timer.function = bnx2x_timer;
11663
11664         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11665             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11666             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11667             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11668                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11669                 bnx2x_dcbx_init_params(bp);
11670         } else {
11671                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11672         }
11673
11674         if (CHIP_IS_E1x(bp))
11675                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11676         else
11677                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11678
11679         /* multiple tx priority */
11680         if (IS_VF(bp))
11681                 bp->max_cos = 1;
11682         else if (CHIP_IS_E1x(bp))
11683                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11684         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11685                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11686         else if (CHIP_IS_E3B0(bp))
11687                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11688         else
11689                 BNX2X_ERR("unknown chip %x revision %x\n",
11690                           CHIP_NUM(bp), CHIP_REV(bp));
11691         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11692
11693         /* We need at least one default status block for slow-path events,
11694          * second status block for the L2 queue, and a third status block for
11695          * CNIC if supported.
11696          */
11697         if (IS_VF(bp))
11698                 bp->min_msix_vec_cnt = 1;
11699         else if (CNIC_SUPPORT(bp))
11700                 bp->min_msix_vec_cnt = 3;
11701         else /* PF w/o cnic */
11702                 bp->min_msix_vec_cnt = 2;
11703         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11704
11705         bp->dump_preset_idx = 1;
11706
11707         return rc;
11708 }
11709
11710 /****************************************************************************
11711 * General service functions
11712 ****************************************************************************/
11713
11714 /*
11715  * net_device service functions
11716  */
11717
11718 /* called with rtnl_lock */
11719 static int bnx2x_open(struct net_device *dev)
11720 {
11721         struct bnx2x *bp = netdev_priv(dev);
11722         int rc;
11723
11724         bp->stats_init = true;
11725
11726         netif_carrier_off(dev);
11727
11728         bnx2x_set_power_state(bp, PCI_D0);
11729
11730         /* If parity had happen during the unload, then attentions
11731          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11732          * want the first function loaded on the current engine to
11733          * complete the recovery.
11734          * Parity recovery is only relevant for PF driver.
11735          */
11736         if (IS_PF(bp)) {
11737                 int other_engine = BP_PATH(bp) ? 0 : 1;
11738                 bool other_load_status, load_status;
11739                 bool global = false;
11740
11741                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11742                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11743                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11744                     bnx2x_chk_parity_attn(bp, &global, true)) {
11745                         do {
11746                                 /* If there are attentions and they are in a
11747                                  * global blocks, set the GLOBAL_RESET bit
11748                                  * regardless whether it will be this function
11749                                  * that will complete the recovery or not.
11750                                  */
11751                                 if (global)
11752                                         bnx2x_set_reset_global(bp);
11753
11754                                 /* Only the first function on the current
11755                                  * engine should try to recover in open. In case
11756                                  * of attentions in global blocks only the first
11757                                  * in the chip should try to recover.
11758                                  */
11759                                 if ((!load_status &&
11760                                      (!global || !other_load_status)) &&
11761                                       bnx2x_trylock_leader_lock(bp) &&
11762                                       !bnx2x_leader_reset(bp)) {
11763                                         netdev_info(bp->dev,
11764                                                     "Recovered in open\n");
11765                                         break;
11766                                 }
11767
11768                                 /* recovery has failed... */
11769                                 bnx2x_set_power_state(bp, PCI_D3hot);
11770                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11771
11772                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11773                                           "If you still see this message after a few retries then power cycle is required.\n");
11774
11775                                 return -EAGAIN;
11776                         } while (0);
11777                 }
11778         }
11779
11780         bp->recovery_state = BNX2X_RECOVERY_DONE;
11781         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11782         if (rc)
11783                 return rc;
11784         return bnx2x_open_epilog(bp);
11785 }
11786
11787 /* called with rtnl_lock */
11788 static int bnx2x_close(struct net_device *dev)
11789 {
11790         struct bnx2x *bp = netdev_priv(dev);
11791
11792         /* Unload the driver, release IRQs */
11793         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11794
11795         return 0;
11796 }
11797
11798 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11799                                       struct bnx2x_mcast_ramrod_params *p)
11800 {
11801         int mc_count = netdev_mc_count(bp->dev);
11802         struct bnx2x_mcast_list_elem *mc_mac =
11803                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11804         struct netdev_hw_addr *ha;
11805
11806         if (!mc_mac)
11807                 return -ENOMEM;
11808
11809         INIT_LIST_HEAD(&p->mcast_list);
11810
11811         netdev_for_each_mc_addr(ha, bp->dev) {
11812                 mc_mac->mac = bnx2x_mc_addr(ha);
11813                 list_add_tail(&mc_mac->link, &p->mcast_list);
11814                 mc_mac++;
11815         }
11816
11817         p->mcast_list_len = mc_count;
11818
11819         return 0;
11820 }
11821
11822 static void bnx2x_free_mcast_macs_list(
11823         struct bnx2x_mcast_ramrod_params *p)
11824 {
11825         struct bnx2x_mcast_list_elem *mc_mac =
11826                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11827                                  link);
11828
11829         WARN_ON(!mc_mac);
11830         kfree(mc_mac);
11831 }
11832
11833 /**
11834  * bnx2x_set_uc_list - configure a new unicast MACs list.
11835  *
11836  * @bp: driver handle
11837  *
11838  * We will use zero (0) as a MAC type for these MACs.
11839  */
11840 static int bnx2x_set_uc_list(struct bnx2x *bp)
11841 {
11842         int rc;
11843         struct net_device *dev = bp->dev;
11844         struct netdev_hw_addr *ha;
11845         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11846         unsigned long ramrod_flags = 0;
11847
11848         /* First schedule a cleanup up of old configuration */
11849         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11850         if (rc < 0) {
11851                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11852                 return rc;
11853         }
11854
11855         netdev_for_each_uc_addr(ha, dev) {
11856                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11857                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11858                 if (rc == -EEXIST) {
11859                         DP(BNX2X_MSG_SP,
11860                            "Failed to schedule ADD operations: %d\n", rc);
11861                         /* do not treat adding same MAC as error */
11862                         rc = 0;
11863
11864                 } else if (rc < 0) {
11865
11866                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11867                                   rc);
11868                         return rc;
11869                 }
11870         }
11871
11872         /* Execute the pending commands */
11873         __set_bit(RAMROD_CONT, &ramrod_flags);
11874         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11875                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11876 }
11877
11878 static int bnx2x_set_mc_list(struct bnx2x *bp)
11879 {
11880         struct net_device *dev = bp->dev;
11881         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11882         int rc = 0;
11883
11884         rparam.mcast_obj = &bp->mcast_obj;
11885
11886         /* first, clear all configured multicast MACs */
11887         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11888         if (rc < 0) {
11889                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11890                 return rc;
11891         }
11892
11893         /* then, configure a new MACs list */
11894         if (netdev_mc_count(dev)) {
11895                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11896                 if (rc) {
11897                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11898                                   rc);
11899                         return rc;
11900                 }
11901
11902                 /* Now add the new MACs */
11903                 rc = bnx2x_config_mcast(bp, &rparam,
11904                                         BNX2X_MCAST_CMD_ADD);
11905                 if (rc < 0)
11906                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11907                                   rc);
11908
11909                 bnx2x_free_mcast_macs_list(&rparam);
11910         }
11911
11912         return rc;
11913 }
11914
11915 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11916 void bnx2x_set_rx_mode(struct net_device *dev)
11917 {
11918         struct bnx2x *bp = netdev_priv(dev);
11919
11920         if (bp->state != BNX2X_STATE_OPEN) {
11921                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11922                 return;
11923         } else {
11924                 /* Schedule an SP task to handle rest of change */
11925                 DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n");
11926                 smp_mb__before_clear_bit();
11927                 set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state);
11928                 smp_mb__after_clear_bit();
11929                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11930         }
11931 }
11932
11933 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
11934 {
11935         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11936
11937         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11938
11939         netif_addr_lock_bh(bp->dev);
11940
11941         if (bp->dev->flags & IFF_PROMISC) {
11942                 rx_mode = BNX2X_RX_MODE_PROMISC;
11943         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
11944                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
11945                     CHIP_IS_E1(bp))) {
11946                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11947         } else {
11948                 if (IS_PF(bp)) {
11949                         /* some multicasts */
11950                         if (bnx2x_set_mc_list(bp) < 0)
11951                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11952
11953                         /* release bh lock, as bnx2x_set_uc_list might sleep */
11954                         netif_addr_unlock_bh(bp->dev);
11955                         if (bnx2x_set_uc_list(bp) < 0)
11956                                 rx_mode = BNX2X_RX_MODE_PROMISC;
11957                         netif_addr_lock_bh(bp->dev);
11958                 } else {
11959                         /* configuring mcast to a vf involves sleeping (when we
11960                          * wait for the pf's response).
11961                          */
11962                         smp_mb__before_clear_bit();
11963                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11964                                 &bp->sp_rtnl_state);
11965                         smp_mb__after_clear_bit();
11966                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11967                 }
11968         }
11969
11970         bp->rx_mode = rx_mode;
11971         /* handle ISCSI SD mode */
11972         if (IS_MF_ISCSI_SD(bp))
11973                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11974
11975         /* Schedule the rx_mode command */
11976         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11977                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11978                 netif_addr_unlock_bh(bp->dev);
11979                 return;
11980         }
11981
11982         if (IS_PF(bp)) {
11983                 bnx2x_set_storm_rx_mode(bp);
11984                 netif_addr_unlock_bh(bp->dev);
11985         } else {
11986                 /* VF will need to request the PF to make this change, and so
11987                  * the VF needs to release the bottom-half lock prior to the
11988                  * request (as it will likely require sleep on the VF side)
11989                  */
11990                 netif_addr_unlock_bh(bp->dev);
11991                 bnx2x_vfpf_storm_rx_mode(bp);
11992         }
11993 }
11994
11995 /* called with rtnl_lock */
11996 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11997                            int devad, u16 addr)
11998 {
11999         struct bnx2x *bp = netdev_priv(netdev);
12000         u16 value;
12001         int rc;
12002
12003         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12004            prtad, devad, addr);
12005
12006         /* The HW expects different devad if CL22 is used */
12007         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12008
12009         bnx2x_acquire_phy_lock(bp);
12010         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12011         bnx2x_release_phy_lock(bp);
12012         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12013
12014         if (!rc)
12015                 rc = value;
12016         return rc;
12017 }
12018
12019 /* called with rtnl_lock */
12020 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12021                             u16 addr, u16 value)
12022 {
12023         struct bnx2x *bp = netdev_priv(netdev);
12024         int rc;
12025
12026         DP(NETIF_MSG_LINK,
12027            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12028            prtad, devad, addr, value);
12029
12030         /* The HW expects different devad if CL22 is used */
12031         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12032
12033         bnx2x_acquire_phy_lock(bp);
12034         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12035         bnx2x_release_phy_lock(bp);
12036         return rc;
12037 }
12038
12039 /* called with rtnl_lock */
12040 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12041 {
12042         struct bnx2x *bp = netdev_priv(dev);
12043         struct mii_ioctl_data *mdio = if_mii(ifr);
12044
12045         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12046            mdio->phy_id, mdio->reg_num, mdio->val_in);
12047
12048         if (!netif_running(dev))
12049                 return -EAGAIN;
12050
12051         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12052 }
12053
12054 #ifdef CONFIG_NET_POLL_CONTROLLER
12055 static void poll_bnx2x(struct net_device *dev)
12056 {
12057         struct bnx2x *bp = netdev_priv(dev);
12058         int i;
12059
12060         for_each_eth_queue(bp, i) {
12061                 struct bnx2x_fastpath *fp = &bp->fp[i];
12062                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12063         }
12064 }
12065 #endif
12066
12067 static int bnx2x_validate_addr(struct net_device *dev)
12068 {
12069         struct bnx2x *bp = netdev_priv(dev);
12070
12071         /* query the bulletin board for mac address configured by the PF */
12072         if (IS_VF(bp))
12073                 bnx2x_sample_bulletin(bp);
12074
12075         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12076                 BNX2X_ERR("Non-valid Ethernet address\n");
12077                 return -EADDRNOTAVAIL;
12078         }
12079         return 0;
12080 }
12081
12082 static const struct net_device_ops bnx2x_netdev_ops = {
12083         .ndo_open               = bnx2x_open,
12084         .ndo_stop               = bnx2x_close,
12085         .ndo_start_xmit         = bnx2x_start_xmit,
12086         .ndo_select_queue       = bnx2x_select_queue,
12087         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12088         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12089         .ndo_validate_addr      = bnx2x_validate_addr,
12090         .ndo_do_ioctl           = bnx2x_ioctl,
12091         .ndo_change_mtu         = bnx2x_change_mtu,
12092         .ndo_fix_features       = bnx2x_fix_features,
12093         .ndo_set_features       = bnx2x_set_features,
12094         .ndo_tx_timeout         = bnx2x_tx_timeout,
12095 #ifdef CONFIG_NET_POLL_CONTROLLER
12096         .ndo_poll_controller    = poll_bnx2x,
12097 #endif
12098         .ndo_setup_tc           = bnx2x_setup_tc,
12099 #ifdef CONFIG_BNX2X_SRIOV
12100         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12101         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12102         .ndo_get_vf_config      = bnx2x_get_vf_config,
12103 #endif
12104 #ifdef NETDEV_FCOE_WWNN
12105         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12106 #endif
12107
12108 #ifdef CONFIG_NET_RX_BUSY_POLL
12109         .ndo_busy_poll          = bnx2x_low_latency_recv,
12110 #endif
12111 };
12112
12113 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12114 {
12115         struct device *dev = &bp->pdev->dev;
12116
12117         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
12118                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
12119                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
12120                         return -EIO;
12121                 }
12122         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
12123                 dev_err(dev, "System does not support DMA, aborting\n");
12124                 return -EIO;
12125         }
12126
12127         return 0;
12128 }
12129
12130 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12131                           struct net_device *dev, unsigned long board_type)
12132 {
12133         int rc;
12134         u32 pci_cfg_dword;
12135         bool chip_is_e1x = (board_type == BCM57710 ||
12136                             board_type == BCM57711 ||
12137                             board_type == BCM57711E);
12138
12139         SET_NETDEV_DEV(dev, &pdev->dev);
12140
12141         bp->dev = dev;
12142         bp->pdev = pdev;
12143
12144         rc = pci_enable_device(pdev);
12145         if (rc) {
12146                 dev_err(&bp->pdev->dev,
12147                         "Cannot enable PCI device, aborting\n");
12148                 goto err_out;
12149         }
12150
12151         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12152                 dev_err(&bp->pdev->dev,
12153                         "Cannot find PCI device base address, aborting\n");
12154                 rc = -ENODEV;
12155                 goto err_out_disable;
12156         }
12157
12158         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12159                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12160                 rc = -ENODEV;
12161                 goto err_out_disable;
12162         }
12163
12164         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12165         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12166             PCICFG_REVESION_ID_ERROR_VAL) {
12167                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12168                 rc = -ENODEV;
12169                 goto err_out_disable;
12170         }
12171
12172         if (atomic_read(&pdev->enable_cnt) == 1) {
12173                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12174                 if (rc) {
12175                         dev_err(&bp->pdev->dev,
12176                                 "Cannot obtain PCI resources, aborting\n");
12177                         goto err_out_disable;
12178                 }
12179
12180                 pci_set_master(pdev);
12181                 pci_save_state(pdev);
12182         }
12183
12184         if (IS_PF(bp)) {
12185                 if (!pdev->pm_cap) {
12186                         dev_err(&bp->pdev->dev,
12187                                 "Cannot find power management capability, aborting\n");
12188                         rc = -EIO;
12189                         goto err_out_release;
12190                 }
12191         }
12192
12193         if (!pci_is_pcie(pdev)) {
12194                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12195                 rc = -EIO;
12196                 goto err_out_release;
12197         }
12198
12199         rc = bnx2x_set_coherency_mask(bp);
12200         if (rc)
12201                 goto err_out_release;
12202
12203         dev->mem_start = pci_resource_start(pdev, 0);
12204         dev->base_addr = dev->mem_start;
12205         dev->mem_end = pci_resource_end(pdev, 0);
12206
12207         dev->irq = pdev->irq;
12208
12209         bp->regview = pci_ioremap_bar(pdev, 0);
12210         if (!bp->regview) {
12211                 dev_err(&bp->pdev->dev,
12212                         "Cannot map register space, aborting\n");
12213                 rc = -ENOMEM;
12214                 goto err_out_release;
12215         }
12216
12217         /* In E1/E1H use pci device function given by kernel.
12218          * In E2/E3 read physical function from ME register since these chips
12219          * support Physical Device Assignment where kernel BDF maybe arbitrary
12220          * (depending on hypervisor).
12221          */
12222         if (chip_is_e1x) {
12223                 bp->pf_num = PCI_FUNC(pdev->devfn);
12224         } else {
12225                 /* chip is E2/3*/
12226                 pci_read_config_dword(bp->pdev,
12227                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12228                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12229                                   ME_REG_ABS_PF_NUM_SHIFT);
12230         }
12231         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12232
12233         /* clean indirect addresses */
12234         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12235                                PCICFG_VENDOR_ID_OFFSET);
12236         /*
12237          * Clean the following indirect addresses for all functions since it
12238          * is not used by the driver.
12239          */
12240         if (IS_PF(bp)) {
12241                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12242                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12243                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12244                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12245
12246                 if (chip_is_e1x) {
12247                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12248                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12249                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12250                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12251                 }
12252
12253                 /* Enable internal target-read (in case we are probed after PF
12254                  * FLR). Must be done prior to any BAR read access. Only for
12255                  * 57712 and up
12256                  */
12257                 if (!chip_is_e1x)
12258                         REG_WR(bp,
12259                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12260         }
12261
12262         dev->watchdog_timeo = TX_TIMEOUT;
12263
12264         dev->netdev_ops = &bnx2x_netdev_ops;
12265         bnx2x_set_ethtool_ops(bp, dev);
12266
12267         dev->priv_flags |= IFF_UNICAST_FLT;
12268
12269         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12270                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12271                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12272                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12273         if (!CHIP_IS_E1x(bp)) {
12274                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12275                 dev->hw_enc_features =
12276                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12277                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12278                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12279         }
12280
12281         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12282                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12283
12284         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12285         dev->features |= NETIF_F_HIGHDMA;
12286
12287         /* Add Loopback capability to the device */
12288         dev->hw_features |= NETIF_F_LOOPBACK;
12289
12290 #ifdef BCM_DCBNL
12291         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12292 #endif
12293
12294         /* get_port_hwinfo() will set prtad and mmds properly */
12295         bp->mdio.prtad = MDIO_PRTAD_NONE;
12296         bp->mdio.mmds = 0;
12297         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12298         bp->mdio.dev = dev;
12299         bp->mdio.mdio_read = bnx2x_mdio_read;
12300         bp->mdio.mdio_write = bnx2x_mdio_write;
12301
12302         return 0;
12303
12304 err_out_release:
12305         if (atomic_read(&pdev->enable_cnt) == 1)
12306                 pci_release_regions(pdev);
12307
12308 err_out_disable:
12309         pci_disable_device(pdev);
12310         pci_set_drvdata(pdev, NULL);
12311
12312 err_out:
12313         return rc;
12314 }
12315
12316 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width,
12317                                        enum bnx2x_pci_bus_speed *speed)
12318 {
12319         u32 link_speed, val = 0;
12320
12321         pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12322         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12323
12324         link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12325
12326         switch (link_speed) {
12327         case 3:
12328                 *speed = BNX2X_PCI_LINK_SPEED_8000;
12329                 break;
12330         case 2:
12331                 *speed = BNX2X_PCI_LINK_SPEED_5000;
12332                 break;
12333         default:
12334                 *speed = BNX2X_PCI_LINK_SPEED_2500;
12335         }
12336 }
12337
12338 /*(DEBLOBBED)*/
12339
12340 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12341 {
12342         const __be32 *source = (const __be32 *)_source;
12343         u32 *target = (u32 *)_target;
12344         u32 i;
12345
12346         for (i = 0; i < n/4; i++)
12347                 target[i] = be32_to_cpu(source[i]);
12348 }
12349
12350 /*
12351    Ops array is stored in the following format:
12352    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12353  */
12354 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12355 {
12356         const __be32 *source = (const __be32 *)_source;
12357         struct raw_op *target = (struct raw_op *)_target;
12358         u32 i, j, tmp;
12359
12360         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12361                 tmp = be32_to_cpu(source[j]);
12362                 target[i].op = (tmp >> 24) & 0xff;
12363                 target[i].offset = tmp & 0xffffff;
12364                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12365         }
12366 }
12367
12368 /* IRO array is stored in the following format:
12369  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12370  */
12371 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12372 {
12373         const __be32 *source = (const __be32 *)_source;
12374         struct iro *target = (struct iro *)_target;
12375         u32 i, j, tmp;
12376
12377         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12378                 target[i].base = be32_to_cpu(source[j]);
12379                 j++;
12380                 tmp = be32_to_cpu(source[j]);
12381                 target[i].m1 = (tmp >> 16) & 0xffff;
12382                 target[i].m2 = tmp & 0xffff;
12383                 j++;
12384                 tmp = be32_to_cpu(source[j]);
12385                 target[i].m3 = (tmp >> 16) & 0xffff;
12386                 target[i].size = tmp & 0xffff;
12387                 j++;
12388         }
12389 }
12390
12391 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12392 {
12393         const __be16 *source = (const __be16 *)_source;
12394         u16 *target = (u16 *)_target;
12395         u32 i;
12396
12397         for (i = 0; i < n/2; i++)
12398                 target[i] = be16_to_cpu(source[i]);
12399 }
12400
12401 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12402 do {                                                                    \
12403         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12404         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12405         if (!bp->arr)                                                   \
12406                 goto lbl;                                               \
12407         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12408              (u8 *)bp->arr, len);                                       \
12409 } while (0)
12410
12411 static int bnx2x_init_firmware(struct bnx2x *bp)
12412 {
12413         const char *fw_file_name;
12414         struct bnx2x_fw_file_hdr *fw_hdr;
12415         int rc;
12416
12417         if (bp->firmware)
12418                 return 0;
12419
12420         if (CHIP_IS_E1(bp))
12421                 fw_file_name = FW_FILE_NAME_E1;
12422         else if (CHIP_IS_E1H(bp))
12423                 fw_file_name = FW_FILE_NAME_E1H;
12424         else if (!CHIP_IS_E1x(bp))
12425                 fw_file_name = FW_FILE_NAME_E2;
12426         else {
12427                 BNX2X_ERR("Unsupported chip revision\n");
12428                 return -EINVAL;
12429         }
12430         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12431
12432         rc = reject_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12433         if (rc) {
12434                 BNX2X_ERR("Can't load firmware file %s\n",
12435                           fw_file_name);
12436                 goto reject_firmware_exit;
12437         }
12438
12439         /*(DEBLOBBED)*/
12440         if (rc) {
12441                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12442                 goto reject_firmware_exit;
12443         }
12444
12445         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12446
12447         /* Initialize the pointers to the init arrays */
12448         /* Blob */
12449         BNX2X_ALLOC_AND_SET(init_data, reject_firmware_exit, be32_to_cpu_n);
12450
12451         /* Opcodes */
12452         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12453
12454         /* Offsets */
12455         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12456                             be16_to_cpu_n);
12457
12458         /* STORMs firmware */
12459         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12460                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12461         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12462                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12463         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12464                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12465         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12466                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12467         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12468                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12469         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12470                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12471         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12472                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12473         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12474                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12475         /* IRO */
12476         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12477
12478         return 0;
12479
12480 iro_alloc_err:
12481         kfree(bp->init_ops_offsets);
12482 init_offsets_alloc_err:
12483         kfree(bp->init_ops);
12484 init_ops_alloc_err:
12485         kfree(bp->init_data);
12486 reject_firmware_exit:
12487         release_firmware(bp->firmware);
12488         bp->firmware = NULL;
12489
12490         return rc;
12491 }
12492
12493 static void bnx2x_release_firmware(struct bnx2x *bp)
12494 {
12495         kfree(bp->init_ops_offsets);
12496         kfree(bp->init_ops);
12497         kfree(bp->init_data);
12498         release_firmware(bp->firmware);
12499         bp->firmware = NULL;
12500 }
12501
12502 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12503         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12504         .init_hw_cmn      = bnx2x_init_hw_common,
12505         .init_hw_port     = bnx2x_init_hw_port,
12506         .init_hw_func     = bnx2x_init_hw_func,
12507
12508         .reset_hw_cmn     = bnx2x_reset_common,
12509         .reset_hw_port    = bnx2x_reset_port,
12510         .reset_hw_func    = bnx2x_reset_func,
12511
12512         .gunzip_init      = bnx2x_gunzip_init,
12513         .gunzip_end       = bnx2x_gunzip_end,
12514
12515         .init_fw          = bnx2x_init_firmware,
12516         .release_fw       = bnx2x_release_firmware,
12517 };
12518
12519 void bnx2x__init_func_obj(struct bnx2x *bp)
12520 {
12521         /* Prepare DMAE related driver resources */
12522         bnx2x_setup_dmae(bp);
12523
12524         bnx2x_init_func_obj(bp, &bp->func_obj,
12525                             bnx2x_sp(bp, func_rdata),
12526                             bnx2x_sp_mapping(bp, func_rdata),
12527                             bnx2x_sp(bp, func_afex_rdata),
12528                             bnx2x_sp_mapping(bp, func_afex_rdata),
12529                             &bnx2x_func_sp_drv);
12530 }
12531
12532 /* must be called after sriov-enable */
12533 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12534 {
12535         int cid_count = BNX2X_L2_MAX_CID(bp);
12536
12537         if (IS_SRIOV(bp))
12538                 cid_count += BNX2X_VF_CIDS;
12539
12540         if (CNIC_SUPPORT(bp))
12541                 cid_count += CNIC_CID_MAX;
12542
12543         return roundup(cid_count, QM_CID_ROUND);
12544 }
12545
12546 /**
12547  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12548  *
12549  * @dev:        pci device
12550  *
12551  */
12552 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
12553 {
12554         int index;
12555         u16 control = 0;
12556
12557         /*
12558          * If MSI-X is not supported - return number of SBs needed to support
12559          * one fast path queue: one FP queue + SB for CNIC
12560          */
12561         if (!pdev->msix_cap) {
12562                 dev_info(&pdev->dev, "no msix capability found\n");
12563                 return 1 + cnic_cnt;
12564         }
12565         dev_info(&pdev->dev, "msix capability found\n");
12566
12567         /*
12568          * The value in the PCI configuration space is the index of the last
12569          * entry, namely one less than the actual size of the table, which is
12570          * exactly what we want to return from this function: number of all SBs
12571          * without the default SB.
12572          * For VFs there is no default SB, then we return (index+1).
12573          */
12574         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
12575
12576         index = control & PCI_MSIX_FLAGS_QSIZE;
12577
12578         return index;
12579 }
12580
12581 static int set_max_cos_est(int chip_id)
12582 {
12583         switch (chip_id) {
12584         case BCM57710:
12585         case BCM57711:
12586         case BCM57711E:
12587                 return BNX2X_MULTI_TX_COS_E1X;
12588         case BCM57712:
12589         case BCM57712_MF:
12590                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12591         case BCM57800:
12592         case BCM57800_MF:
12593         case BCM57810:
12594         case BCM57810_MF:
12595         case BCM57840_4_10:
12596         case BCM57840_2_20:
12597         case BCM57840_O:
12598         case BCM57840_MFO:
12599         case BCM57840_MF:
12600         case BCM57811:
12601         case BCM57811_MF:
12602                 return BNX2X_MULTI_TX_COS_E3B0;
12603         case BCM57712_VF:
12604         case BCM57800_VF:
12605         case BCM57810_VF:
12606         case BCM57840_VF:
12607         case BCM57811_VF:
12608                 return 1;
12609         default:
12610                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12611                 return -ENODEV;
12612         }
12613 }
12614
12615 static int set_is_vf(int chip_id)
12616 {
12617         switch (chip_id) {
12618         case BCM57712_VF:
12619         case BCM57800_VF:
12620         case BCM57810_VF:
12621         case BCM57840_VF:
12622         case BCM57811_VF:
12623                 return true;
12624         default:
12625                 return false;
12626         }
12627 }
12628
12629 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12630
12631 static int bnx2x_init_one(struct pci_dev *pdev,
12632                                     const struct pci_device_id *ent)
12633 {
12634         struct net_device *dev = NULL;
12635         struct bnx2x *bp;
12636         int pcie_width;
12637         enum bnx2x_pci_bus_speed pcie_speed;
12638         int rc, max_non_def_sbs;
12639         int rx_count, tx_count, rss_count, doorbell_size;
12640         int max_cos_est;
12641         bool is_vf;
12642         int cnic_cnt;
12643
12644         /* An estimated maximum supported CoS number according to the chip
12645          * version.
12646          * We will try to roughly estimate the maximum number of CoSes this chip
12647          * may support in order to minimize the memory allocated for Tx
12648          * netdev_queue's. This number will be accurately calculated during the
12649          * initialization of bp->max_cos based on the chip versions AND chip
12650          * revision in the bnx2x_init_bp().
12651          */
12652         max_cos_est = set_max_cos_est(ent->driver_data);
12653         if (max_cos_est < 0)
12654                 return max_cos_est;
12655         is_vf = set_is_vf(ent->driver_data);
12656         cnic_cnt = is_vf ? 0 : 1;
12657
12658         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12659
12660         /* add another SB for VF as it has no default SB */
12661         max_non_def_sbs += is_vf ? 1 : 0;
12662
12663         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12664         rss_count = max_non_def_sbs - cnic_cnt;
12665
12666         if (rss_count < 1)
12667                 return -EINVAL;
12668
12669         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12670         rx_count = rss_count + cnic_cnt;
12671
12672         /* Maximum number of netdev Tx queues:
12673          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12674          */
12675         tx_count = rss_count * max_cos_est + cnic_cnt;
12676
12677         /* dev zeroed in init_etherdev */
12678         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12679         if (!dev)
12680                 return -ENOMEM;
12681
12682         bp = netdev_priv(dev);
12683
12684         bp->flags = 0;
12685         if (is_vf)
12686                 bp->flags |= IS_VF_FLAG;
12687
12688         bp->igu_sb_cnt = max_non_def_sbs;
12689         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12690         bp->msg_enable = debug;
12691         bp->cnic_support = cnic_cnt;
12692         bp->cnic_probe = bnx2x_cnic_probe;
12693
12694         pci_set_drvdata(pdev, dev);
12695
12696         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12697         if (rc < 0) {
12698                 free_netdev(dev);
12699                 return rc;
12700         }
12701
12702         BNX2X_DEV_INFO("This is a %s function\n",
12703                        IS_PF(bp) ? "physical" : "virtual");
12704         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12705         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12706         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12707                        tx_count, rx_count);
12708
12709         rc = bnx2x_init_bp(bp);
12710         if (rc)
12711                 goto init_one_exit;
12712
12713         /* Map doorbells here as we need the real value of bp->max_cos which
12714          * is initialized in bnx2x_init_bp() to determine the number of
12715          * l2 connections.
12716          */
12717         if (IS_VF(bp)) {
12718                 bp->doorbells = bnx2x_vf_doorbells(bp);
12719                 rc = bnx2x_vf_pci_alloc(bp);
12720                 if (rc)
12721                         goto init_one_exit;
12722         } else {
12723                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12724                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12725                         dev_err(&bp->pdev->dev,
12726                                 "Cannot map doorbells, bar size too small, aborting\n");
12727                         rc = -ENOMEM;
12728                         goto init_one_exit;
12729                 }
12730                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12731                                                 doorbell_size);
12732         }
12733         if (!bp->doorbells) {
12734                 dev_err(&bp->pdev->dev,
12735                         "Cannot map doorbell space, aborting\n");
12736                 rc = -ENOMEM;
12737                 goto init_one_exit;
12738         }
12739
12740         if (IS_VF(bp)) {
12741                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12742                 if (rc)
12743                         goto init_one_exit;
12744         }
12745
12746         /* Enable SRIOV if capability found in configuration space */
12747         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12748         if (rc)
12749                 goto init_one_exit;
12750
12751         /* calc qm_cid_count */
12752         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12753         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12754
12755         /* disable FCOE L2 queue for E1x*/
12756         if (CHIP_IS_E1x(bp))
12757                 bp->flags |= NO_FCOE_FLAG;
12758
12759         /* Set bp->num_queues for MSI-X mode*/
12760         bnx2x_set_num_queues(bp);
12761
12762         /* Configure interrupt mode: try to enable MSI-X/MSI if
12763          * needed.
12764          */
12765         rc = bnx2x_set_int_mode(bp);
12766         if (rc) {
12767                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12768                 goto init_one_exit;
12769         }
12770         BNX2X_DEV_INFO("set interrupts successfully\n");
12771
12772         /* register the net device */
12773         rc = register_netdev(dev);
12774         if (rc) {
12775                 dev_err(&pdev->dev, "Cannot register net device\n");
12776                 goto init_one_exit;
12777         }
12778         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12779
12780         if (!NO_FCOE(bp)) {
12781                 /* Add storage MAC address */
12782                 rtnl_lock();
12783                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12784                 rtnl_unlock();
12785         }
12786
12787         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12788         BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12789                        pcie_width, pcie_speed);
12790
12791         BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12792                        board_info[ent->driver_data].name,
12793                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12794                        pcie_width,
12795                        pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" :
12796                        pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" :
12797                        pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" :
12798                        "Unknown",
12799                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
12800
12801         return 0;
12802
12803 init_one_exit:
12804         if (bp->regview)
12805                 iounmap(bp->regview);
12806
12807         if (IS_PF(bp) && bp->doorbells)
12808                 iounmap(bp->doorbells);
12809
12810         free_netdev(dev);
12811
12812         if (atomic_read(&pdev->enable_cnt) == 1)
12813                 pci_release_regions(pdev);
12814
12815         pci_disable_device(pdev);
12816         pci_set_drvdata(pdev, NULL);
12817
12818         return rc;
12819 }
12820
12821 static void __bnx2x_remove(struct pci_dev *pdev,
12822                            struct net_device *dev,
12823                            struct bnx2x *bp,
12824                            bool remove_netdev)
12825 {
12826         /* Delete storage MAC address */
12827         if (!NO_FCOE(bp)) {
12828                 rtnl_lock();
12829                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12830                 rtnl_unlock();
12831         }
12832
12833 #ifdef BCM_DCBNL
12834         /* Delete app tlvs from dcbnl */
12835         bnx2x_dcbnl_update_applist(bp, true);
12836 #endif
12837
12838         if (IS_PF(bp) &&
12839             !BP_NOMCP(bp) &&
12840             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
12841                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
12842
12843         /* Close the interface - either directly or implicitly */
12844         if (remove_netdev) {
12845                 unregister_netdev(dev);
12846         } else {
12847                 rtnl_lock();
12848                 dev_close(dev);
12849                 rtnl_unlock();
12850         }
12851
12852         bnx2x_iov_remove_one(bp);
12853
12854         /* Power on: we can't let PCI layer write to us while we are in D3 */
12855         if (IS_PF(bp))
12856                 bnx2x_set_power_state(bp, PCI_D0);
12857
12858         /* Disable MSI/MSI-X */
12859         bnx2x_disable_msi(bp);
12860
12861         /* Power off */
12862         if (IS_PF(bp))
12863                 bnx2x_set_power_state(bp, PCI_D3hot);
12864
12865         /* Make sure RESET task is not scheduled before continuing */
12866         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12867
12868         /* send message via vfpf channel to release the resources of this vf */
12869         if (IS_VF(bp))
12870                 bnx2x_vfpf_release(bp);
12871
12872         /* Assumes no further PCIe PM changes will occur */
12873         if (system_state == SYSTEM_POWER_OFF) {
12874                 pci_wake_from_d3(pdev, bp->wol);
12875                 pci_set_power_state(pdev, PCI_D3hot);
12876         }
12877
12878         if (bp->regview)
12879                 iounmap(bp->regview);
12880
12881         /* for vf doorbells are part of the regview and were unmapped along with
12882          * it. FW is only loaded by PF.
12883          */
12884         if (IS_PF(bp)) {
12885                 if (bp->doorbells)
12886                         iounmap(bp->doorbells);
12887
12888                 bnx2x_release_firmware(bp);
12889         }
12890         bnx2x_free_mem_bp(bp);
12891
12892         if (remove_netdev)
12893                 free_netdev(dev);
12894
12895         if (atomic_read(&pdev->enable_cnt) == 1)
12896                 pci_release_regions(pdev);
12897
12898         pci_disable_device(pdev);
12899         pci_set_drvdata(pdev, NULL);
12900 }
12901
12902 static void bnx2x_remove_one(struct pci_dev *pdev)
12903 {
12904         struct net_device *dev = pci_get_drvdata(pdev);
12905         struct bnx2x *bp;
12906
12907         if (!dev) {
12908                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12909                 return;
12910         }
12911         bp = netdev_priv(dev);
12912
12913         __bnx2x_remove(pdev, dev, bp, true);
12914 }
12915
12916 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12917 {
12918         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12919
12920         bp->rx_mode = BNX2X_RX_MODE_NONE;
12921
12922         if (CNIC_LOADED(bp))
12923                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12924
12925         /* Stop Tx */
12926         bnx2x_tx_disable(bp);
12927         /* Delete all NAPI objects */
12928         bnx2x_del_all_napi(bp);
12929         if (CNIC_LOADED(bp))
12930                 bnx2x_del_all_napi_cnic(bp);
12931         netdev_reset_tc(bp->dev);
12932
12933         del_timer_sync(&bp->timer);
12934         cancel_delayed_work(&bp->sp_task);
12935         cancel_delayed_work(&bp->period_task);
12936
12937         spin_lock_bh(&bp->stats_lock);
12938         bp->stats_state = STATS_STATE_DISABLED;
12939         spin_unlock_bh(&bp->stats_lock);
12940
12941         bnx2x_save_statistics(bp);
12942
12943         netif_carrier_off(bp->dev);
12944
12945         return 0;
12946 }
12947
12948 /**
12949  * bnx2x_io_error_detected - called when PCI error is detected
12950  * @pdev: Pointer to PCI device
12951  * @state: The current pci connection state
12952  *
12953  * This function is called after a PCI bus error affecting
12954  * this device has been detected.
12955  */
12956 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12957                                                 pci_channel_state_t state)
12958 {
12959         struct net_device *dev = pci_get_drvdata(pdev);
12960         struct bnx2x *bp = netdev_priv(dev);
12961
12962         rtnl_lock();
12963
12964         BNX2X_ERR("IO error detected\n");
12965
12966         netif_device_detach(dev);
12967
12968         if (state == pci_channel_io_perm_failure) {
12969                 rtnl_unlock();
12970                 return PCI_ERS_RESULT_DISCONNECT;
12971         }
12972
12973         if (netif_running(dev))
12974                 bnx2x_eeh_nic_unload(bp);
12975
12976         bnx2x_prev_path_mark_eeh(bp);
12977
12978         pci_disable_device(pdev);
12979
12980         rtnl_unlock();
12981
12982         /* Request a slot reset */
12983         return PCI_ERS_RESULT_NEED_RESET;
12984 }
12985
12986 /**
12987  * bnx2x_io_slot_reset - called after the PCI bus has been reset
12988  * @pdev: Pointer to PCI device
12989  *
12990  * Restart the card from scratch, as if from a cold-boot.
12991  */
12992 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12993 {
12994         struct net_device *dev = pci_get_drvdata(pdev);
12995         struct bnx2x *bp = netdev_priv(dev);
12996         int i;
12997
12998         rtnl_lock();
12999         BNX2X_ERR("IO slot reset initializing...\n");
13000         if (pci_enable_device(pdev)) {
13001                 dev_err(&pdev->dev,
13002                         "Cannot re-enable PCI device after reset\n");
13003                 rtnl_unlock();
13004                 return PCI_ERS_RESULT_DISCONNECT;
13005         }
13006
13007         pci_set_master(pdev);
13008         pci_restore_state(pdev);
13009         pci_save_state(pdev);
13010
13011         if (netif_running(dev))
13012                 bnx2x_set_power_state(bp, PCI_D0);
13013
13014         if (netif_running(dev)) {
13015                 BNX2X_ERR("IO slot reset --> driver unload\n");
13016
13017                 /* MCP should have been reset; Need to wait for validity */
13018                 bnx2x_init_shmem(bp);
13019
13020                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13021                         u32 v;
13022
13023                         v = SHMEM2_RD(bp,
13024                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13025                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13026                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13027                 }
13028                 bnx2x_drain_tx_queues(bp);
13029                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13030                 bnx2x_netif_stop(bp, 1);
13031                 bnx2x_free_irq(bp);
13032
13033                 /* Report UNLOAD_DONE to MCP */
13034                 bnx2x_send_unload_done(bp, true);
13035
13036                 bp->sp_state = 0;
13037                 bp->port.pmf = 0;
13038
13039                 bnx2x_prev_unload(bp);
13040
13041                 /* We should have reseted the engine, so It's fair to
13042                  * assume the FW will no longer write to the bnx2x driver.
13043                  */
13044                 bnx2x_squeeze_objects(bp);
13045                 bnx2x_free_skbs(bp);
13046                 for_each_rx_queue(bp, i)
13047                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13048                 bnx2x_free_fp_mem(bp);
13049                 bnx2x_free_mem(bp);
13050
13051                 bp->state = BNX2X_STATE_CLOSED;
13052         }
13053
13054         rtnl_unlock();
13055
13056         return PCI_ERS_RESULT_RECOVERED;
13057 }
13058
13059 /**
13060  * bnx2x_io_resume - called when traffic can start flowing again
13061  * @pdev: Pointer to PCI device
13062  *
13063  * This callback is called when the error recovery driver tells us that
13064  * its OK to resume normal operation.
13065  */
13066 static void bnx2x_io_resume(struct pci_dev *pdev)
13067 {
13068         struct net_device *dev = pci_get_drvdata(pdev);
13069         struct bnx2x *bp = netdev_priv(dev);
13070
13071         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13072                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13073                 return;
13074         }
13075
13076         rtnl_lock();
13077
13078         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13079                                                         DRV_MSG_SEQ_NUMBER_MASK;
13080
13081         if (netif_running(dev))
13082                 bnx2x_nic_load(bp, LOAD_NORMAL);
13083
13084         netif_device_attach(dev);
13085
13086         rtnl_unlock();
13087 }
13088
13089 static const struct pci_error_handlers bnx2x_err_handler = {
13090         .error_detected = bnx2x_io_error_detected,
13091         .slot_reset     = bnx2x_io_slot_reset,
13092         .resume         = bnx2x_io_resume,
13093 };
13094
13095 static void bnx2x_shutdown(struct pci_dev *pdev)
13096 {
13097         struct net_device *dev = pci_get_drvdata(pdev);
13098         struct bnx2x *bp;
13099
13100         if (!dev)
13101                 return;
13102
13103         bp = netdev_priv(dev);
13104         if (!bp)
13105                 return;
13106
13107         rtnl_lock();
13108         netif_device_detach(dev);
13109         rtnl_unlock();
13110
13111         /* Don't remove the netdevice, as there are scenarios which will cause
13112          * the kernel to hang, e.g., when trying to remove bnx2i while the
13113          * rootfs is mounted from SAN.
13114          */
13115         __bnx2x_remove(pdev, dev, bp, false);
13116 }
13117
13118 static struct pci_driver bnx2x_pci_driver = {
13119         .name        = DRV_MODULE_NAME,
13120         .id_table    = bnx2x_pci_tbl,
13121         .probe       = bnx2x_init_one,
13122         .remove      = bnx2x_remove_one,
13123         .suspend     = bnx2x_suspend,
13124         .resume      = bnx2x_resume,
13125         .err_handler = &bnx2x_err_handler,
13126 #ifdef CONFIG_BNX2X_SRIOV
13127         .sriov_configure = bnx2x_sriov_configure,
13128 #endif
13129         .shutdown    = bnx2x_shutdown,
13130 };
13131
13132 static int __init bnx2x_init(void)
13133 {
13134         int ret;
13135
13136         pr_info("%s", version);
13137
13138         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13139         if (bnx2x_wq == NULL) {
13140                 pr_err("Cannot create workqueue\n");
13141                 return -ENOMEM;
13142         }
13143
13144         ret = pci_register_driver(&bnx2x_pci_driver);
13145         if (ret) {
13146                 pr_err("Cannot register driver\n");
13147                 destroy_workqueue(bnx2x_wq);
13148         }
13149         return ret;
13150 }
13151
13152 static void __exit bnx2x_cleanup(void)
13153 {
13154         struct list_head *pos, *q;
13155
13156         pci_unregister_driver(&bnx2x_pci_driver);
13157
13158         destroy_workqueue(bnx2x_wq);
13159
13160         /* Free globally allocated resources */
13161         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13162                 struct bnx2x_prev_path_list *tmp =
13163                         list_entry(pos, struct bnx2x_prev_path_list, list);
13164                 list_del(pos);
13165                 kfree(tmp);
13166         }
13167 }
13168
13169 void bnx2x_notify_link_changed(struct bnx2x *bp)
13170 {
13171         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13172 }
13173
13174 module_init(bnx2x_init);
13175 module_exit(bnx2x_cleanup);
13176
13177 /**
13178  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13179  *
13180  * @bp:         driver handle
13181  * @set:        set or clear the CAM entry
13182  *
13183  * This function will wait until the ramrod completion returns.
13184  * Return 0 if success, -ENODEV if ramrod doesn't return.
13185  */
13186 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13187 {
13188         unsigned long ramrod_flags = 0;
13189
13190         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13191         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13192                                  &bp->iscsi_l2_mac_obj, true,
13193                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13194 }
13195
13196 /* count denotes the number of new completions we have seen */
13197 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13198 {
13199         struct eth_spe *spe;
13200         int cxt_index, cxt_offset;
13201
13202 #ifdef BNX2X_STOP_ON_ERROR
13203         if (unlikely(bp->panic))
13204                 return;
13205 #endif
13206
13207         spin_lock_bh(&bp->spq_lock);
13208         BUG_ON(bp->cnic_spq_pending < count);
13209         bp->cnic_spq_pending -= count;
13210
13211         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13212                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13213                                 & SPE_HDR_CONN_TYPE) >>
13214                                 SPE_HDR_CONN_TYPE_SHIFT;
13215                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13216                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13217
13218                 /* Set validation for iSCSI L2 client before sending SETUP
13219                  *  ramrod
13220                  */
13221                 if (type == ETH_CONNECTION_TYPE) {
13222                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13223                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13224                                         ILT_PAGE_CIDS;
13225                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13226                                         (cxt_index * ILT_PAGE_CIDS);
13227                                 bnx2x_set_ctx_validation(bp,
13228                                         &bp->context[cxt_index].
13229                                                          vcxt[cxt_offset].eth,
13230                                         BNX2X_ISCSI_ETH_CID(bp));
13231                         }
13232                 }
13233
13234                 /*
13235                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13236                  * and in the air. We also check that number of outstanding
13237                  * COMMON ramrods is not more than the EQ and SPQ can
13238                  * accommodate.
13239                  */
13240                 if (type == ETH_CONNECTION_TYPE) {
13241                         if (!atomic_read(&bp->cq_spq_left))
13242                                 break;
13243                         else
13244                                 atomic_dec(&bp->cq_spq_left);
13245                 } else if (type == NONE_CONNECTION_TYPE) {
13246                         if (!atomic_read(&bp->eq_spq_left))
13247                                 break;
13248                         else
13249                                 atomic_dec(&bp->eq_spq_left);
13250                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13251                            (type == FCOE_CONNECTION_TYPE)) {
13252                         if (bp->cnic_spq_pending >=
13253                             bp->cnic_eth_dev.max_kwqe_pending)
13254                                 break;
13255                         else
13256                                 bp->cnic_spq_pending++;
13257                 } else {
13258                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13259                         bnx2x_panic();
13260                         break;
13261                 }
13262
13263                 spe = bnx2x_sp_get_next(bp);
13264                 *spe = *bp->cnic_kwq_cons;
13265
13266                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13267                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13268
13269                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13270                         bp->cnic_kwq_cons = bp->cnic_kwq;
13271                 else
13272                         bp->cnic_kwq_cons++;
13273         }
13274         bnx2x_sp_prod_update(bp);
13275         spin_unlock_bh(&bp->spq_lock);
13276 }
13277
13278 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13279                                struct kwqe_16 *kwqes[], u32 count)
13280 {
13281         struct bnx2x *bp = netdev_priv(dev);
13282         int i;
13283
13284 #ifdef BNX2X_STOP_ON_ERROR
13285         if (unlikely(bp->panic)) {
13286                 BNX2X_ERR("Can't post to SP queue while panic\n");
13287                 return -EIO;
13288         }
13289 #endif
13290
13291         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13292             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13293                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13294                 return -EAGAIN;
13295         }
13296
13297         spin_lock_bh(&bp->spq_lock);
13298
13299         for (i = 0; i < count; i++) {
13300                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13301
13302                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13303                         break;
13304
13305                 *bp->cnic_kwq_prod = *spe;
13306
13307                 bp->cnic_kwq_pending++;
13308
13309                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13310                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13311                    spe->data.update_data_addr.hi,
13312                    spe->data.update_data_addr.lo,
13313                    bp->cnic_kwq_pending);
13314
13315                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13316                         bp->cnic_kwq_prod = bp->cnic_kwq;
13317                 else
13318                         bp->cnic_kwq_prod++;
13319         }
13320
13321         spin_unlock_bh(&bp->spq_lock);
13322
13323         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13324                 bnx2x_cnic_sp_post(bp, 0);
13325
13326         return i;
13327 }
13328
13329 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13330 {
13331         struct cnic_ops *c_ops;
13332         int rc = 0;
13333
13334         mutex_lock(&bp->cnic_mutex);
13335         c_ops = rcu_dereference_protected(bp->cnic_ops,
13336                                           lockdep_is_held(&bp->cnic_mutex));
13337         if (c_ops)
13338                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13339         mutex_unlock(&bp->cnic_mutex);
13340
13341         return rc;
13342 }
13343
13344 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13345 {
13346         struct cnic_ops *c_ops;
13347         int rc = 0;
13348
13349         rcu_read_lock();
13350         c_ops = rcu_dereference(bp->cnic_ops);
13351         if (c_ops)
13352                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13353         rcu_read_unlock();
13354
13355         return rc;
13356 }
13357
13358 /*
13359  * for commands that have no data
13360  */
13361 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13362 {
13363         struct cnic_ctl_info ctl = {0};
13364
13365         ctl.cmd = cmd;
13366
13367         return bnx2x_cnic_ctl_send(bp, &ctl);
13368 }
13369
13370 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13371 {
13372         struct cnic_ctl_info ctl = {0};
13373
13374         /* first we tell CNIC and only then we count this as a completion */
13375         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13376         ctl.data.comp.cid = cid;
13377         ctl.data.comp.error = err;
13378
13379         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13380         bnx2x_cnic_sp_post(bp, 0);
13381 }
13382
13383 /* Called with netif_addr_lock_bh() taken.
13384  * Sets an rx_mode config for an iSCSI ETH client.
13385  * Doesn't block.
13386  * Completion should be checked outside.
13387  */
13388 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13389 {
13390         unsigned long accept_flags = 0, ramrod_flags = 0;
13391         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13392         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13393
13394         if (start) {
13395                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13396                  * because it's the only way for UIO Queue to accept
13397                  * multicasts (in non-promiscuous mode only one Queue per
13398                  * function will receive multicast packets (leading in our
13399                  * case).
13400                  */
13401                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13402                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13403                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13404                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13405
13406                 /* Clear STOP_PENDING bit if START is requested */
13407                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13408
13409                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13410         } else
13411                 /* Clear START_PENDING bit if STOP is requested */
13412                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13413
13414         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13415                 set_bit(sched_state, &bp->sp_state);
13416         else {
13417                 __set_bit(RAMROD_RX, &ramrod_flags);
13418                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13419                                     ramrod_flags);
13420         }
13421 }
13422
13423 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13424 {
13425         struct bnx2x *bp = netdev_priv(dev);
13426         int rc = 0;
13427
13428         switch (ctl->cmd) {
13429         case DRV_CTL_CTXTBL_WR_CMD: {
13430                 u32 index = ctl->data.io.offset;
13431                 dma_addr_t addr = ctl->data.io.dma_addr;
13432
13433                 bnx2x_ilt_wr(bp, index, addr);
13434                 break;
13435         }
13436
13437         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13438                 int count = ctl->data.credit.credit_count;
13439
13440                 bnx2x_cnic_sp_post(bp, count);
13441                 break;
13442         }
13443
13444         /* rtnl_lock is held.  */
13445         case DRV_CTL_START_L2_CMD: {
13446                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13447                 unsigned long sp_bits = 0;
13448
13449                 /* Configure the iSCSI classification object */
13450                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13451                                    cp->iscsi_l2_client_id,
13452                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13453                                    bnx2x_sp(bp, mac_rdata),
13454                                    bnx2x_sp_mapping(bp, mac_rdata),
13455                                    BNX2X_FILTER_MAC_PENDING,
13456                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13457                                    &bp->macs_pool);
13458
13459                 /* Set iSCSI MAC address */
13460                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13461                 if (rc)
13462                         break;
13463
13464                 mmiowb();
13465                 barrier();
13466
13467                 /* Start accepting on iSCSI L2 ring */
13468
13469                 netif_addr_lock_bh(dev);
13470                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13471                 netif_addr_unlock_bh(dev);
13472
13473                 /* bits to wait on */
13474                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13475                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13476
13477                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13478                         BNX2X_ERR("rx_mode completion timed out!\n");
13479
13480                 break;
13481         }
13482
13483         /* rtnl_lock is held.  */
13484         case DRV_CTL_STOP_L2_CMD: {
13485                 unsigned long sp_bits = 0;
13486
13487                 /* Stop accepting on iSCSI L2 ring */
13488                 netif_addr_lock_bh(dev);
13489                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13490                 netif_addr_unlock_bh(dev);
13491
13492                 /* bits to wait on */
13493                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13494                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13495
13496                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13497                         BNX2X_ERR("rx_mode completion timed out!\n");
13498
13499                 mmiowb();
13500                 barrier();
13501
13502                 /* Unset iSCSI L2 MAC */
13503                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13504                                         BNX2X_ISCSI_ETH_MAC, true);
13505                 break;
13506         }
13507         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13508                 int count = ctl->data.credit.credit_count;
13509
13510                 smp_mb__before_atomic_inc();
13511                 atomic_add(count, &bp->cq_spq_left);
13512                 smp_mb__after_atomic_inc();
13513                 break;
13514         }
13515         case DRV_CTL_ULP_REGISTER_CMD: {
13516                 int ulp_type = ctl->data.register_data.ulp_type;
13517
13518                 if (CHIP_IS_E3(bp)) {
13519                         int idx = BP_FW_MB_IDX(bp);
13520                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13521                         int path = BP_PATH(bp);
13522                         int port = BP_PORT(bp);
13523                         int i;
13524                         u32 scratch_offset;
13525                         u32 *host_addr;
13526
13527                         /* first write capability to shmem2 */
13528                         if (ulp_type == CNIC_ULP_ISCSI)
13529                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13530                         else if (ulp_type == CNIC_ULP_FCOE)
13531                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13532                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13533
13534                         if ((ulp_type != CNIC_ULP_FCOE) ||
13535                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13536                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13537                                 break;
13538
13539                         /* if reached here - should write fcoe capabilities */
13540                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13541                         if (!scratch_offset)
13542                                 break;
13543                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13544                                                    fcoe_features[path][port]);
13545                         host_addr = (u32 *) &(ctl->data.register_data.
13546                                               fcoe_features);
13547                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13548                              i += 4)
13549                                 REG_WR(bp, scratch_offset + i,
13550                                        *(host_addr + i/4));
13551                 }
13552                 break;
13553         }
13554
13555         case DRV_CTL_ULP_UNREGISTER_CMD: {
13556                 int ulp_type = ctl->data.ulp_type;
13557
13558                 if (CHIP_IS_E3(bp)) {
13559                         int idx = BP_FW_MB_IDX(bp);
13560                         u32 cap;
13561
13562                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13563                         if (ulp_type == CNIC_ULP_ISCSI)
13564                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13565                         else if (ulp_type == CNIC_ULP_FCOE)
13566                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13567                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13568                 }
13569                 break;
13570         }
13571
13572         default:
13573                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13574                 rc = -EINVAL;
13575         }
13576
13577         return rc;
13578 }
13579
13580 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13581 {
13582         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13583
13584         if (bp->flags & USING_MSIX_FLAG) {
13585                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13586                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13587                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13588         } else {
13589                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13590                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13591         }
13592         if (!CHIP_IS_E1x(bp))
13593                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13594         else
13595                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13596
13597         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13598         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13599         cp->irq_arr[1].status_blk = bp->def_status_blk;
13600         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13601         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13602
13603         cp->num_irq = 2;
13604 }
13605
13606 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13607 {
13608         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13609
13610         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13611                              bnx2x_cid_ilt_lines(bp);
13612         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13613         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13614         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13615
13616         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
13617            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
13618            cp->iscsi_l2_cid);
13619
13620         if (NO_ISCSI_OOO(bp))
13621                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13622 }
13623
13624 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13625                                void *data)
13626 {
13627         struct bnx2x *bp = netdev_priv(dev);
13628         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13629         int rc;
13630
13631         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13632
13633         if (ops == NULL) {
13634                 BNX2X_ERR("NULL ops received\n");
13635                 return -EINVAL;
13636         }
13637
13638         if (!CNIC_SUPPORT(bp)) {
13639                 BNX2X_ERR("Can't register CNIC when not supported\n");
13640                 return -EOPNOTSUPP;
13641         }
13642
13643         if (!CNIC_LOADED(bp)) {
13644                 rc = bnx2x_load_cnic(bp);
13645                 if (rc) {
13646                         BNX2X_ERR("CNIC-related load failed\n");
13647                         return rc;
13648                 }
13649         }
13650
13651         bp->cnic_enabled = true;
13652
13653         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13654         if (!bp->cnic_kwq)
13655                 return -ENOMEM;
13656
13657         bp->cnic_kwq_cons = bp->cnic_kwq;
13658         bp->cnic_kwq_prod = bp->cnic_kwq;
13659         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13660
13661         bp->cnic_spq_pending = 0;
13662         bp->cnic_kwq_pending = 0;
13663
13664         bp->cnic_data = data;
13665
13666         cp->num_irq = 0;
13667         cp->drv_state |= CNIC_DRV_STATE_REGD;
13668         cp->iro_arr = bp->iro_arr;
13669
13670         bnx2x_setup_cnic_irq_info(bp);
13671
13672         rcu_assign_pointer(bp->cnic_ops, ops);
13673
13674         return 0;
13675 }
13676
13677 static int bnx2x_unregister_cnic(struct net_device *dev)
13678 {
13679         struct bnx2x *bp = netdev_priv(dev);
13680         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13681
13682         mutex_lock(&bp->cnic_mutex);
13683         cp->drv_state = 0;
13684         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13685         mutex_unlock(&bp->cnic_mutex);
13686         synchronize_rcu();
13687         bp->cnic_enabled = false;
13688         kfree(bp->cnic_kwq);
13689         bp->cnic_kwq = NULL;
13690
13691         return 0;
13692 }
13693
13694 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13695 {
13696         struct bnx2x *bp = netdev_priv(dev);
13697         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13698
13699         /* If both iSCSI and FCoE are disabled - return NULL in
13700          * order to indicate CNIC that it should not try to work
13701          * with this device.
13702          */
13703         if (NO_ISCSI(bp) && NO_FCOE(bp))
13704                 return NULL;
13705
13706         cp->drv_owner = THIS_MODULE;
13707         cp->chip_id = CHIP_ID(bp);
13708         cp->pdev = bp->pdev;
13709         cp->io_base = bp->regview;
13710         cp->io_base2 = bp->doorbells;
13711         cp->max_kwqe_pending = 8;
13712         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13713         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13714                              bnx2x_cid_ilt_lines(bp);
13715         cp->ctx_tbl_len = CNIC_ILT_LINES;
13716         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13717         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13718         cp->drv_ctl = bnx2x_drv_ctl;
13719         cp->drv_register_cnic = bnx2x_register_cnic;
13720         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13721         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13722         cp->iscsi_l2_client_id =
13723                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13724         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13725
13726         if (NO_ISCSI_OOO(bp))
13727                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13728
13729         if (NO_ISCSI(bp))
13730                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13731
13732         if (NO_FCOE(bp))
13733                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13734
13735         BNX2X_DEV_INFO(
13736                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13737            cp->ctx_blk_size,
13738            cp->ctx_tbl_offset,
13739            cp->ctx_tbl_len,
13740            cp->starting_cid);
13741         return cp;
13742 }
13743
13744 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13745 {
13746         struct bnx2x *bp = fp->bp;
13747         u32 offset = BAR_USTRORM_INTMEM;
13748
13749         if (IS_VF(bp))
13750                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13751         else if (!CHIP_IS_E1x(bp))
13752                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13753         else
13754                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13755
13756         return offset;
13757 }
13758
13759 /* called only on E1H or E2.
13760  * When pretending to be PF, the pretend value is the function number 0...7
13761  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13762  * combination
13763  */
13764 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13765 {
13766         u32 pretend_reg;
13767
13768         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13769                 return -1;
13770
13771         /* get my own pretend register */
13772         pretend_reg = bnx2x_get_pretend_reg(bp);
13773         REG_WR(bp, pretend_reg, pretend_func_val);
13774         REG_RD(bp, pretend_reg);
13775         return 0;
13776 }