drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/crash_dump.h>
  45 #include <net/ip.h>
  46 #include <net/ipv6.h>
  47 #include <net/tcp.h>
  48 #include <net/vxlan.h>
  49 #include <net/checksum.h>
  50 #include <net/ip6_checksum.h>
  51 #include <linux/workqueue.h>
  52 #include <linux/crc32.h>
  53 #include <linux/crc32c.h>
  54 #include <linux/prefetch.h>
  55 #include <linux/zlib.h>
  56 #include <linux/io.h>
  57 #include <linux/semaphore.h>
  58 #include <linux/stringify.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include "bnx2x.h"
  62 #include "bnx2x_init.h"
  63 #include "bnx2x_init_ops.h"
  64 #include "bnx2x_cmn.h"
  65 #include "bnx2x_vfpf.h"
  66 #include "bnx2x_dcb.h"
  67 #include "bnx2x_sp.h"
  68 #include <linux/firmware.h>
  69 #include "bnx2x_fw_file_hdr.h"
  70 /* FW files */
  71 /*(DEBLOBBED)*/
  72 #define FW_FILE_NAME_E1         "/*(DEBLOBBED)*/"
  73 #define FW_FILE_NAME_E1H        "/*(DEBLOBBED)*/"
  74 #define FW_FILE_NAME_E2         "/*(DEBLOBBED)*/"
  75 #define bnx2x_init_block(bp, start, end) \
  76   return (printk(KERN_ERR "%s: Missing Free firmware\n", bp->dev->name),\
  77           -EINVAL)
  78
  79 /* Time in jiffies before concluding the transmitter is hung */
  80 #define TX_TIMEOUT              (5*HZ)
  81
  82 static char version[] =
  83         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  84         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  85
  86 MODULE_AUTHOR("Eliezer Tamir");
  87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  88                    "BCM57710/57711/57711E/"
  89                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  90                    "57840/57840_MF Driver");
  91 MODULE_LICENSE("GPL");
  92 MODULE_VERSION(DRV_MODULE_VERSION);
  93 /*(DEBLOBBED)*/
  94
  95 int bnx2x_num_queues;
  96 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
  97 MODULE_PARM_DESC(num_queues,
  98                  " Set number of queues (default is as a number of CPUs)");
  99
 100 static int disable_tpa;
 101 module_param(disable_tpa, int, S_IRUGO);
 102 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 103
 104 static int int_mode;
 105 module_param(int_mode, int, S_IRUGO);
 106 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 107                                 "(1 INT#x; 2 MSI)");
 108
 109 static int dropless_fc;
 110 module_param(dropless_fc, int, S_IRUGO);
 111 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 112
 113 static int mrrs = -1;
 114 module_param(mrrs, int, S_IRUGO);
 115 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 116
 117 static int debug;
 118 module_param(debug, int, S_IRUGO);
 119 MODULE_PARM_DESC(debug, " Default debug msglevel");
 120
 121 static struct workqueue_struct *bnx2x_wq;
 122 struct workqueue_struct *bnx2x_iov_wq;
 123
 124 struct bnx2x_mac_vals {
 125         u32 xmac_addr;
 126         u32 xmac_val;
 127         u32 emac_addr;
 128         u32 emac_val;
 129         u32 umac_addr[2];
 130         u32 umac_val[2];
 131         u32 bmac_addr;
 132         u32 bmac_val[2];
 133 };
 134
 135 enum bnx2x_board_type {
 136         BCM57710 = 0,
 137         BCM57711,
 138         BCM57711E,
 139         BCM57712,
 140         BCM57712_MF,
 141         BCM57712_VF,
 142         BCM57800,
 143         BCM57800_MF,
 144         BCM57800_VF,
 145         BCM57810,
 146         BCM57810_MF,
 147         BCM57810_VF,
 148         BCM57840_4_10,
 149         BCM57840_2_20,
 150         BCM57840_MF,
 151         BCM57840_VF,
 152         BCM57811,
 153         BCM57811_MF,
 154         BCM57840_O,
 155         BCM57840_MFO,
 156         BCM57811_VF
 157 };
 158
 159 /* indexed by board_type, above */
 160 static struct {
 161         char *name;
 162 } board_info[] = {
 163         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 164         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 165         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 166         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 167         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 168         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 169         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 170         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 171         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 173         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 174         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 175         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 176         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 177         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 178         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 179         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 180         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 181         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 182         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 183         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 184 };
 185
 186 #ifndef PCI_DEVICE_ID_NX2_57710
 187 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 188 #endif
 189 #ifndef PCI_DEVICE_ID_NX2_57711
 190 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57711E
 193 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57712
 196 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 199 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 202 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57800
 205 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 208 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 211 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57810
 214 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 217 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57840_O
 220 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 223 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 226 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 229 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 232 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 235 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 238 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57811
 241 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 244 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 245 #endif
 246 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 247 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 248 #endif
 249
 250 static const struct pci_device_id bnx2x_pci_tbl[] = {
 251         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 272         { 0 }
 273 };
 274
 275 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 276
 277 /* Global resources for unloading a previously loaded device */
 278 #define BNX2X_PREV_WAIT_NEEDED 1
 279 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 280 static LIST_HEAD(bnx2x_prev_list);
 281
 282 /* Forward declaration */
 283 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 284 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 285 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 286
 287 /****************************************************************************
 288 * General service functions
 289 ****************************************************************************/
 290
 291 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 292
 293 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 294                                        u32 addr, dma_addr_t mapping)
 295 {
 296         REG_WR(bp,  addr, U64_LO(mapping));
 297         REG_WR(bp,  addr + 4, U64_HI(mapping));
 298 }
 299
 300 static void storm_memset_spq_addr(struct bnx2x *bp,
 301                                   dma_addr_t mapping, u16 abs_fid)
 302 {
 303         u32 addr = XSEM_REG_FAST_MEMORY +
 304                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 305
 306         __storm_memset_dma_mapping(bp, addr, mapping);
 307 }
 308
 309 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 310                                   u16 pf_id)
 311 {
 312         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 313                 pf_id);
 314         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 315                 pf_id);
 316         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 317                 pf_id);
 318         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 319                 pf_id);
 320 }
 321
 322 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 323                                  u8 enable)
 324 {
 325         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 326                 enable);
 327         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 328                 enable);
 329         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 330                 enable);
 331         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 332                 enable);
 333 }
 334
 335 static void storm_memset_eq_data(struct bnx2x *bp,
 336                                  struct event_ring_data *eq_data,
 337                                 u16 pfid)
 338 {
 339         size_t size = sizeof(struct event_ring_data);
 340
 341         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 342
 343         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 344 }
 345
 346 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 347                                  u16 pfid)
 348 {
 349         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 350         REG_WR16(bp, addr, eq_prod);
 351 }
 352
 353 /* used only at init
 354  * locking is done by mcp
 355  */
 356 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 357 {
 358         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 359         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 360         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 361                                PCICFG_VENDOR_ID_OFFSET);
 362 }
 363
 364 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 365 {
 366         u32 val;
 367
 368         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 369         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 370         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 371                                PCICFG_VENDOR_ID_OFFSET);
 372
 373         return val;
 374 }
 375
 376 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 377 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 378 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 379 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 380 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 381
 382 static void bnx2x_dp_dmae(struct bnx2x *bp,
 383                           struct dmae_command *dmae, int msglvl)
 384 {
 385         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 386         int i;
 387
 388         switch (dmae->opcode & DMAE_COMMAND_DST) {
 389         case DMAE_CMD_DST_PCI:
 390                 if (src_type == DMAE_CMD_SRC_PCI)
 391                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 392                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 393                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 394                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 395                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 396                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 397                            dmae->comp_val);
 398                 else
 399                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 400                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 401                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 402                            dmae->opcode, dmae->src_addr_lo >> 2,
 403                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 404                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 405                            dmae->comp_val);
 406                 break;
 407         case DMAE_CMD_DST_GRC:
 408                 if (src_type == DMAE_CMD_SRC_PCI)
 409                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 410                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 411                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 412                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 413                            dmae->len, dmae->dst_addr_lo >> 2,
 414                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 415                            dmae->comp_val);
 416                 else
 417                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 418                            "src [%08x], len [%d*4], dst [%08x]\n"
 419                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 420                            dmae->opcode, dmae->src_addr_lo >> 2,
 421                            dmae->len, dmae->dst_addr_lo >> 2,
 422                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 423                            dmae->comp_val);
 424                 break;
 425         default:
 426                 if (src_type == DMAE_CMD_SRC_PCI)
 427                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 428                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 429                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 430                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 431                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 432                            dmae->comp_val);
 433                 else
 434                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 435                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 436                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 437                            dmae->opcode, dmae->src_addr_lo >> 2,
 438                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 439                            dmae->comp_val);
 440                 break;
 441         }
 442
 443         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 444                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 445                    i, *(((u32 *)dmae) + i));
 446 }
 447
 448 /* copy command into DMAE command memory and set DMAE command go */
 449 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 450 {
 451         u32 cmd_offset;
 452         int i;
 453
 454         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 455         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 456                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 457         }
 458         REG_WR(bp, dmae_reg_go_c[idx], 1);
 459 }
 460
 461 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 462 {
 463         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 464                            DMAE_CMD_C_ENABLE);
 465 }
 466
 467 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 468 {
 469         return opcode & ~DMAE_CMD_SRC_RESET;
 470 }
 471
 472 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 473                              bool with_comp, u8 comp_type)
 474 {
 475         u32 opcode = 0;
 476
 477         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 478                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 479
 480         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 481
 482         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 483         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 484                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 485         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 486
 487 #ifdef __BIG_ENDIAN
 488         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 489 #else
 490         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 491 #endif
 492         if (with_comp)
 493                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 494         return opcode;
 495 }
 496
 497 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 498                                       struct dmae_command *dmae,
 499                                       u8 src_type, u8 dst_type)
 500 {
 501         memset(dmae, 0, sizeof(struct dmae_command));
 502
 503         /* set the opcode */
 504         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 505                                          true, DMAE_COMP_PCI);
 506
 507         /* fill in the completion parameters */
 508         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 509         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 510         dmae->comp_val = DMAE_COMP_VAL;
 511 }
 512
 513 /* issue a dmae command over the init-channel and wait for completion */
 514 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 515                                u32 *comp)
 516 {
 517         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 518         int rc = 0;
 519
 520         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 521
 522         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 523          * as long as this code is called both from syscall context and
 524          * from ndo_set_rx_mode() flow that may be called from BH.
 525          */
 526
 527         spin_lock_bh(&bp->dmae_lock);
 528
 529         /* reset completion */
 530         *comp = 0;
 531
 532         /* post the command on the channel used for initializations */
 533         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 534
 535         /* wait for completion */
 536         udelay(5);
 537         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 538
 539                 if (!cnt ||
 540                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 541                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 542                         BNX2X_ERR("DMAE timeout!\n");
 543                         rc = DMAE_TIMEOUT;
 544                         goto unlock;
 545                 }
 546                 cnt--;
 547                 udelay(50);
 548         }
 549         if (*comp & DMAE_PCI_ERR_FLAG) {
 550                 BNX2X_ERR("DMAE PCI error!\n");
 551                 rc = DMAE_PCI_ERROR;
 552         }
 553
 554 unlock:
 555
 556         spin_unlock_bh(&bp->dmae_lock);
 557
 558         return rc;
 559 }
 560
 561 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 562                       u32 len32)
 563 {
 564         int rc;
 565         struct dmae_command dmae;
 566
 567         if (!bp->dmae_ready) {
 568                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 569
 570                 if (CHIP_IS_E1(bp))
 571                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 572                 else
 573                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 574                 return;
 575         }
 576
 577         /* set opcode and fixed command fields */
 578         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 579
 580         /* fill in addresses and len */
 581         dmae.src_addr_lo = U64_LO(dma_addr);
 582         dmae.src_addr_hi = U64_HI(dma_addr);
 583         dmae.dst_addr_lo = dst_addr >> 2;
 584         dmae.dst_addr_hi = 0;
 585         dmae.len = len32;
 586
 587         /* issue the command and wait for completion */
 588         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 589         if (rc) {
 590                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 591 #ifdef BNX2X_STOP_ON_ERROR
 592                 bnx2x_panic();
 593 #endif
 594         }
 595 }
 596
 597 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 598 {
 599         int rc;
 600         struct dmae_command dmae;
 601
 602         if (!bp->dmae_ready) {
 603                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 604                 int i;
 605
 606                 if (CHIP_IS_E1(bp))
 607                         for (i = 0; i < len32; i++)
 608                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 609                 else
 610                         for (i = 0; i < len32; i++)
 611                                 data[i] = REG_RD(bp, src_addr + i*4);
 612
 613                 return;
 614         }
 615
 616         /* set opcode and fixed command fields */
 617         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 618
 619         /* fill in addresses and len */
 620         dmae.src_addr_lo = src_addr >> 2;
 621         dmae.src_addr_hi = 0;
 622         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 623         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 624         dmae.len = len32;
 625
 626         /* issue the command and wait for completion */
 627         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 628         if (rc) {
 629                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 630 #ifdef BNX2X_STOP_ON_ERROR
 631                 bnx2x_panic();
 632 #endif
 633         }
 634 }
 635
 636 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 637                                       u32 addr, u32 len)
 638 {
 639         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 640         int offset = 0;
 641
 642         while (len > dmae_wr_max) {
 643                 bnx2x_write_dmae(bp, phys_addr + offset,
 644                                  addr + offset, dmae_wr_max);
 645                 offset += dmae_wr_max * 4;
 646                 len -= dmae_wr_max;
 647         }
 648
 649         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 650 }
 651
 652 enum storms {
 653            XSTORM,
 654            TSTORM,
 655            CSTORM,
 656            USTORM,
 657            MAX_STORMS
 658 };
 659
 660 #define STORMS_NUM 4
 661 #define REGS_IN_ENTRY 4
 662
 663 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 664                                               enum storms storm,
 665                                               int entry)
 666 {
 667         switch (storm) {
 668         case XSTORM:
 669                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 670         case TSTORM:
 671                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 672         case CSTORM:
 673                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 674         case USTORM:
 675                 return USTORM_ASSERT_LIST_OFFSET(entry);
 676         case MAX_STORMS:
 677         default:
 678                 BNX2X_ERR("unknown storm\n");
 679         }
 680         return -EINVAL;
 681 }
 682
 683 static int bnx2x_mc_assert(struct bnx2x *bp)
 684 {
 685         char last_idx;
 686         int i, j, rc = 0;
 687         enum storms storm;
 688         u32 regs[REGS_IN_ENTRY];
 689         u32 bar_storm_intmem[STORMS_NUM] = {
 690                 BAR_XSTRORM_INTMEM,
 691                 BAR_TSTRORM_INTMEM,
 692                 BAR_CSTRORM_INTMEM,
 693                 BAR_USTRORM_INTMEM
 694         };
 695         u32 storm_assert_list_index[STORMS_NUM] = {
 696                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 697                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 698                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 699                 USTORM_ASSERT_LIST_INDEX_OFFSET
 700         };
 701         char *storms_string[STORMS_NUM] = {
 702                 "XSTORM",
 703                 "TSTORM",
 704                 "CSTORM",
 705                 "USTORM"
 706         };
 707
 708         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 709                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 710                                    storm_assert_list_index[storm]);
 711                 if (last_idx)
 712                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 713                                   storms_string[storm], last_idx);
 714
 715                 /* print the asserts */
 716                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 717                         /* read a single assert entry */
 718                         for (j = 0; j < REGS_IN_ENTRY; j++)
 719                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 720                                           bnx2x_get_assert_list_entry(bp,
 721                                                                       storm,
 722                                                                       i) +
 723                                           sizeof(u32) * j);
 724
 725                         /* log entry if it contains a valid assert */
 726                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 727                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 728                                           storms_string[storm], i, regs[3],
 729                                           regs[2], regs[1], regs[0]);
 730                                 rc++;
 731                         } else {
 732                                 break;
 733                         }
 734                 }
 735         }
 736
 737         BNX2X_ERR("Chip Revision: %s, /*(DEBLOBBED)*/\n",
 738                   CHIP_IS_E1(bp) ? "everest1" :
 739                   CHIP_IS_E1H(bp) ? "everest1h" :
 740                   CHIP_IS_E2(bp) ? "everest2" : "everest3"/*(DEBLOBBED)*/);
 741
 742         return rc;
 743 }
 744
 745 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 746 #define SCRATCH_BUFFER_SIZE(bp) \
 747         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 748
 749 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 750 {
 751         u32 addr, val;
 752         u32 mark, offset;
 753         __be32 data[9];
 754         int word;
 755         u32 trace_shmem_base;
 756         if (BP_NOMCP(bp)) {
 757                 BNX2X_ERR("NO MCP - can not dump\n");
 758                 return;
 759         }
 760         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 761                 (bp->common.bc_ver & 0xff0000) >> 16,
 762                 (bp->common.bc_ver & 0xff00) >> 8,
 763                 (bp->common.bc_ver & 0xff));
 764
 765         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 766         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 767                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 768
 769         if (BP_PATH(bp) == 0)
 770                 trace_shmem_base = bp->common.shmem_base;
 771         else
 772                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 773
 774         /* sanity */
 775         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 776             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 777                                 SCRATCH_BUFFER_SIZE(bp)) {
 778                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 779                           trace_shmem_base);
 780                 return;
 781         }
 782
 783         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 784
 785         /* validate TRCB signature */
 786         mark = REG_RD(bp, addr);
 787         if (mark != MFW_TRACE_SIGNATURE) {
 788                 BNX2X_ERR("Trace buffer signature is missing.");
 789                 return ;
 790         }
 791
 792         /* read cyclic buffer pointer */
 793         addr += 4;
 794         mark = REG_RD(bp, addr);
 795         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 796         if (mark >= trace_shmem_base || mark < addr + 4) {
 797                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 798                 return;
 799         }
 800         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 801
 802         printk("%s", lvl);
 803
 804         /* dump buffer after the mark */
 805         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 806                 for (word = 0; word < 8; word++)
 807                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 808                 data[8] = 0x0;
 809                 pr_cont("%s", (char *)data);
 810         }
 811
 812         /* dump buffer before the mark */
 813         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 814                 for (word = 0; word < 8; word++)
 815                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 816                 data[8] = 0x0;
 817                 pr_cont("%s", (char *)data);
 818         }
 819         printk("%s" "end of fw dump\n", lvl);
 820 }
 821
 822 static void bnx2x_fw_dump(struct bnx2x *bp)
 823 {
 824         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 825 }
 826
 827 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 828 {
 829         int port = BP_PORT(bp);
 830         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 831         u32 val = REG_RD(bp, addr);
 832
 833         /* in E1 we must use only PCI configuration space to disable
 834          * MSI/MSIX capability
 835          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 836          */
 837         if (CHIP_IS_E1(bp)) {
 838                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 839                  * Use mask register to prevent from HC sending interrupts
 840                  * after we exit the function
 841                  */
 842                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 843
 844                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 845                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 846                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 847         } else
 848                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 849                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 850                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 851                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 852
 853         DP(NETIF_MSG_IFDOWN,
 854            "write %x to HC %d (addr 0x%x)\n",
 855            val, port, addr);
 856
 857         /* flush all outstanding writes */
 858         mmiowb();
 859
 860         REG_WR(bp, addr, val);
 861         if (REG_RD(bp, addr) != val)
 862                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 863 }
 864
 865 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 866 {
 867         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 868
 869         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 870                  IGU_PF_CONF_INT_LINE_EN |
 871                  IGU_PF_CONF_ATTN_BIT_EN);
 872
 873         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 874
 875         /* flush all outstanding writes */
 876         mmiowb();
 877
 878         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 879         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 880                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 881 }
 882
 883 static void bnx2x_int_disable(struct bnx2x *bp)
 884 {
 885         if (bp->common.int_block == INT_BLOCK_HC)
 886                 bnx2x_hc_int_disable(bp);
 887         else
 888                 bnx2x_igu_int_disable(bp);
 889 }
 890
 891 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 892 {
 893         int i;
 894         u16 j;
 895         struct hc_sp_status_block_data sp_sb_data;
 896         int func = BP_FUNC(bp);
 897 #ifdef BNX2X_STOP_ON_ERROR
 898         u16 start = 0, end = 0;
 899         u8 cos;
 900 #endif
 901         if (IS_PF(bp) && disable_int)
 902                 bnx2x_int_disable(bp);
 903
 904         bp->stats_state = STATS_STATE_DISABLED;
 905         bp->eth_stats.unrecoverable_error++;
 906         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 907
 908         BNX2X_ERR("begin crash dump -----------------\n");
 909
 910         /* Indices */
 911         /* Common */
 912         if (IS_PF(bp)) {
 913                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 914                 int data_size, cstorm_offset;
 915
 916                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 917                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 918                           bp->spq_prod_idx, bp->stats_counter);
 919                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 920                           def_sb->atten_status_block.attn_bits,
 921                           def_sb->atten_status_block.attn_bits_ack,
 922                           def_sb->atten_status_block.status_block_id,
 923                           def_sb->atten_status_block.attn_bits_index);
 924                 BNX2X_ERR("     def (");
 925                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 926                         pr_cont("0x%x%s",
 927                                 def_sb->sp_sb.index_values[i],
 928                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 929
 930                 data_size = sizeof(struct hc_sp_status_block_data) /
 931                             sizeof(u32);
 932                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 933                 for (i = 0; i < data_size; i++)
 934                         *((u32 *)&sp_sb_data + i) =
 935                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 936                                            i * sizeof(u32));
 937
 938                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 939                         sp_sb_data.igu_sb_id,
 940                         sp_sb_data.igu_seg_id,
 941                         sp_sb_data.p_func.pf_id,
 942                         sp_sb_data.p_func.vnic_id,
 943                         sp_sb_data.p_func.vf_id,
 944                         sp_sb_data.p_func.vf_valid,
 945                         sp_sb_data.state);
 946         }
 947
 948         for_each_eth_queue(bp, i) {
 949                 struct bnx2x_fastpath *fp = &bp->fp[i];
 950                 int loop;
 951                 struct hc_status_block_data_e2 sb_data_e2;
 952                 struct hc_status_block_data_e1x sb_data_e1x;
 953                 struct hc_status_block_sm  *hc_sm_p =
 954                         CHIP_IS_E1x(bp) ?
 955                         sb_data_e1x.common.state_machine :
 956                         sb_data_e2.common.state_machine;
 957                 struct hc_index_data *hc_index_p =
 958                         CHIP_IS_E1x(bp) ?
 959                         sb_data_e1x.index_data :
 960                         sb_data_e2.index_data;
 961                 u8 data_size, cos;
 962                 u32 *sb_data_p;
 963                 struct bnx2x_fp_txdata txdata;
 964
 965                 if (!bp->fp)
 966                         break;
 967
 968                 if (!fp->rx_cons_sb)
 969                         continue;
 970
 971                 /* Rx */
 972                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 973                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 974                           fp->rx_comp_prod,
 975                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 976                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 977                           fp->rx_sge_prod, fp->last_max_sge,
 978                           le16_to_cpu(fp->fp_hc_idx));
 979
 980                 /* Tx */
 981                 for_each_cos_in_tx_queue(fp, cos)
 982                 {
 983                         if (!fp->txdata_ptr[cos])
 984                                 break;
 985
 986                         txdata = *fp->txdata_ptr[cos];
 987
 988                         if (!txdata.tx_cons_sb)
 989                                 continue;
 990
 991                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 992                                   i, txdata.tx_pkt_prod,
 993                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 994                                   txdata.tx_bd_cons,
 995                                   le16_to_cpu(*txdata.tx_cons_sb));
 996                 }
 997
 998                 loop = CHIP_IS_E1x(bp) ?
 999                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1000
1001                 /* host sb data */
1002
1003                 if (IS_FCOE_FP(fp))
1004                         continue;
1005
1006                 BNX2X_ERR("     run indexes (");
1007                 for (j = 0; j < HC_SB_MAX_SM; j++)
1008                         pr_cont("0x%x%s",
1009                                fp->sb_running_index[j],
1010                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1011
1012                 BNX2X_ERR("     indexes (");
1013                 for (j = 0; j < loop; j++)
1014                         pr_cont("0x%x%s",
1015                                fp->sb_index_values[j],
1016                                (j == loop - 1) ? ")" : " ");
1017
1018                 /* VF cannot access FW refelection for status block */
1019                 if (IS_VF(bp))
1020                         continue;
1021
1022                 /* fw sb data */
1023                 data_size = CHIP_IS_E1x(bp) ?
1024                         sizeof(struct hc_status_block_data_e1x) :
1025                         sizeof(struct hc_status_block_data_e2);
1026                 data_size /= sizeof(u32);
1027                 sb_data_p = CHIP_IS_E1x(bp) ?
1028                         (u32 *)&sb_data_e1x :
1029                         (u32 *)&sb_data_e2;
1030                 /* copy sb data in here */
1031                 for (j = 0; j < data_size; j++)
1032                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1033                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1034                                 j * sizeof(u32));
1035
1036                 if (!CHIP_IS_E1x(bp)) {
1037                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1038                                 sb_data_e2.common.p_func.pf_id,
1039                                 sb_data_e2.common.p_func.vf_id,
1040                                 sb_data_e2.common.p_func.vf_valid,
1041                                 sb_data_e2.common.p_func.vnic_id,
1042                                 sb_data_e2.common.same_igu_sb_1b,
1043                                 sb_data_e2.common.state);
1044                 } else {
1045                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1046                                 sb_data_e1x.common.p_func.pf_id,
1047                                 sb_data_e1x.common.p_func.vf_id,
1048                                 sb_data_e1x.common.p_func.vf_valid,
1049                                 sb_data_e1x.common.p_func.vnic_id,
1050                                 sb_data_e1x.common.same_igu_sb_1b,
1051                                 sb_data_e1x.common.state);
1052                 }
1053
1054                 /* SB_SMs data */
1055                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1056                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1057                                 j, hc_sm_p[j].__flags,
1058                                 hc_sm_p[j].igu_sb_id,
1059                                 hc_sm_p[j].igu_seg_id,
1060                                 hc_sm_p[j].time_to_expire,
1061                                 hc_sm_p[j].timer_value);
1062                 }
1063
1064                 /* Indices data */
1065                 for (j = 0; j < loop; j++) {
1066                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1067                                hc_index_p[j].flags,
1068                                hc_index_p[j].timeout);
1069                 }
1070         }
1071
1072 #ifdef BNX2X_STOP_ON_ERROR
1073         if (IS_PF(bp)) {
1074                 /* event queue */
1075                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1076                 for (i = 0; i < NUM_EQ_DESC; i++) {
1077                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1078
1079                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1080                                   i, bp->eq_ring[i].message.opcode,
1081                                   bp->eq_ring[i].message.error);
1082                         BNX2X_ERR("data: %x %x %x\n",
1083                                   data[0], data[1], data[2]);
1084                 }
1085         }
1086
1087         /* Rings */
1088         /* Rx */
1089         for_each_valid_rx_queue(bp, i) {
1090                 struct bnx2x_fastpath *fp = &bp->fp[i];
1091
1092                 if (!bp->fp)
1093                         break;
1094
1095                 if (!fp->rx_cons_sb)
1096                         continue;
1097
1098                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1099                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1100                 for (j = start; j != end; j = RX_BD(j + 1)) {
1101                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1102                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1103
1104                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1105                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1106                 }
1107
1108                 start = RX_SGE(fp->rx_sge_prod);
1109                 end = RX_SGE(fp->last_max_sge);
1110                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1111                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1112                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1113
1114                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1115                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1116                 }
1117
1118                 start = RCQ_BD(fp->rx_comp_cons - 10);
1119                 end = RCQ_BD(fp->rx_comp_cons + 503);
1120                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1121                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1122
1123                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1124                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1125                 }
1126         }
1127
1128         /* Tx */
1129         for_each_valid_tx_queue(bp, i) {
1130                 struct bnx2x_fastpath *fp = &bp->fp[i];
1131
1132                 if (!bp->fp)
1133                         break;
1134
1135                 for_each_cos_in_tx_queue(fp, cos) {
1136                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1137
1138                         if (!fp->txdata_ptr[cos])
1139                                 break;
1140
1141                         if (!txdata->tx_cons_sb)
1142                                 continue;
1143
1144                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1145                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1146                         for (j = start; j != end; j = TX_BD(j + 1)) {
1147                                 struct sw_tx_bd *sw_bd =
1148                                         &txdata->tx_buf_ring[j];
1149
1150                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1151                                           i, cos, j, sw_bd->skb,
1152                                           sw_bd->first_bd);
1153                         }
1154
1155                         start = TX_BD(txdata->tx_bd_cons - 10);
1156                         end = TX_BD(txdata->tx_bd_cons + 254);
1157                         for (j = start; j != end; j = TX_BD(j + 1)) {
1158                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1159
1160                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1161                                           i, cos, j, tx_bd[0], tx_bd[1],
1162                                           tx_bd[2], tx_bd[3]);
1163                         }
1164                 }
1165         }
1166 #endif
1167         if (IS_PF(bp)) {
1168                 bnx2x_fw_dump(bp);
1169                 bnx2x_mc_assert(bp);
1170         }
1171         BNX2X_ERR("end crash dump -----------------\n");
1172 }
1173
1174 /*
1175  * FLR Support for E2
1176  *
1177  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1178  * initialization.
1179  */
1180 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1181 #define FLR_WAIT_INTERVAL       50      /* usec */
1182 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1183
1184 struct pbf_pN_buf_regs {
1185         int pN;
1186         u32 init_crd;
1187         u32 crd;
1188         u32 crd_freed;
1189 };
1190
1191 struct pbf_pN_cmd_regs {
1192         int pN;
1193         u32 lines_occup;
1194         u32 lines_freed;
1195 };
1196
1197 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1198                                      struct pbf_pN_buf_regs *regs,
1199                                      u32 poll_count)
1200 {
1201         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1202         u32 cur_cnt = poll_count;
1203
1204         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1205         crd = crd_start = REG_RD(bp, regs->crd);
1206         init_crd = REG_RD(bp, regs->init_crd);
1207
1208         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1209         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1210         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1211
1212         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1213                (init_crd - crd_start))) {
1214                 if (cur_cnt--) {
1215                         udelay(FLR_WAIT_INTERVAL);
1216                         crd = REG_RD(bp, regs->crd);
1217                         crd_freed = REG_RD(bp, regs->crd_freed);
1218                 } else {
1219                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1220                            regs->pN);
1221                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1222                            regs->pN, crd);
1223                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1224                            regs->pN, crd_freed);
1225                         break;
1226                 }
1227         }
1228         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1229            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1230 }
1231
1232 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1233                                      struct pbf_pN_cmd_regs *regs,
1234                                      u32 poll_count)
1235 {
1236         u32 occup, to_free, freed, freed_start;
1237         u32 cur_cnt = poll_count;
1238
1239         occup = to_free = REG_RD(bp, regs->lines_occup);
1240         freed = freed_start = REG_RD(bp, regs->lines_freed);
1241
1242         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1243         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1244
1245         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1246                 if (cur_cnt--) {
1247                         udelay(FLR_WAIT_INTERVAL);
1248                         occup = REG_RD(bp, regs->lines_occup);
1249                         freed = REG_RD(bp, regs->lines_freed);
1250                 } else {
1251                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1252                            regs->pN);
1253                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1254                            regs->pN, occup);
1255                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1256                            regs->pN, freed);
1257                         break;
1258                 }
1259         }
1260         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1261            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1262 }
1263
1264 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1265                                     u32 expected, u32 poll_count)
1266 {
1267         u32 cur_cnt = poll_count;
1268         u32 val;
1269
1270         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1271                 udelay(FLR_WAIT_INTERVAL);
1272
1273         return val;
1274 }
1275
1276 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1277                                     char *msg, u32 poll_cnt)
1278 {
1279         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1280         if (val != 0) {
1281                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1282                 return 1;
1283         }
1284         return 0;
1285 }
1286
1287 /* Common routines with VF FLR cleanup */
1288 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1289 {
1290         /* adjust polling timeout */
1291         if (CHIP_REV_IS_EMUL(bp))
1292                 return FLR_POLL_CNT * 2000;
1293
1294         if (CHIP_REV_IS_FPGA(bp))
1295                 return FLR_POLL_CNT * 120;
1296
1297         return FLR_POLL_CNT;
1298 }
1299
1300 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1301 {
1302         struct pbf_pN_cmd_regs cmd_regs[] = {
1303                 {0, (CHIP_IS_E3B0(bp)) ?
1304                         PBF_REG_TQ_OCCUPANCY_Q0 :
1305                         PBF_REG_P0_TQ_OCCUPANCY,
1306                     (CHIP_IS_E3B0(bp)) ?
1307                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1308                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1309                 {1, (CHIP_IS_E3B0(bp)) ?
1310                         PBF_REG_TQ_OCCUPANCY_Q1 :
1311                         PBF_REG_P1_TQ_OCCUPANCY,
1312                     (CHIP_IS_E3B0(bp)) ?
1313                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1314                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1315                 {4, (CHIP_IS_E3B0(bp)) ?
1316                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1317                         PBF_REG_P4_TQ_OCCUPANCY,
1318                     (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1320                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1321         };
1322
1323         struct pbf_pN_buf_regs buf_regs[] = {
1324                 {0, (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_INIT_CRD_Q0 :
1326                         PBF_REG_P0_INIT_CRD ,
1327                     (CHIP_IS_E3B0(bp)) ?
1328                         PBF_REG_CREDIT_Q0 :
1329                         PBF_REG_P0_CREDIT,
1330                     (CHIP_IS_E3B0(bp)) ?
1331                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1332                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1333                 {1, (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_INIT_CRD_Q1 :
1335                         PBF_REG_P1_INIT_CRD,
1336                     (CHIP_IS_E3B0(bp)) ?
1337                         PBF_REG_CREDIT_Q1 :
1338                         PBF_REG_P1_CREDIT,
1339                     (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1341                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1342                 {4, (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_INIT_CRD_LB_Q :
1344                         PBF_REG_P4_INIT_CRD,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_CREDIT_LB_Q :
1347                         PBF_REG_P4_CREDIT,
1348                     (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1350                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1351         };
1352
1353         int i;
1354
1355         /* Verify the command queues are flushed P0, P1, P4 */
1356         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1357                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1358
1359         /* Verify the transmission buffers are flushed P0, P1, P4 */
1360         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1361                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1362 }
1363
1364 #define OP_GEN_PARAM(param) \
1365         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1366
1367 #define OP_GEN_TYPE(type) \
1368         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1369
1370 #define OP_GEN_AGG_VECT(index) \
1371         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1372
1373 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1374 {
1375         u32 op_gen_command = 0;
1376         u32 comp_addr = BAR_CSTRORM_INTMEM +
1377                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1378         int ret = 0;
1379
1380         if (REG_RD(bp, comp_addr)) {
1381                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1382                 return 1;
1383         }
1384
1385         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1386         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1387         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1388         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1389
1390         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1391         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1392
1393         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1394                 BNX2X_ERR("FW final cleanup did not succeed\n");
1395                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1396                    (REG_RD(bp, comp_addr)));
1397                 bnx2x_panic();
1398                 return 1;
1399         }
1400         /* Zero completion for next FLR */
1401         REG_WR(bp, comp_addr, 0);
1402
1403         return ret;
1404 }
1405
1406 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1407 {
1408         u16 status;
1409
1410         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1411         return status & PCI_EXP_DEVSTA_TRPND;
1412 }
1413
1414 /* PF FLR specific routines
1415 */
1416 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1417 {
1418         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1419         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1420                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1421                         "CFC PF usage counter timed out",
1422                         poll_cnt))
1423                 return 1;
1424
1425         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1426         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1427                         DORQ_REG_PF_USAGE_CNT,
1428                         "DQ PF usage counter timed out",
1429                         poll_cnt))
1430                 return 1;
1431
1432         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1433         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1434                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1435                         "QM PF usage counter timed out",
1436                         poll_cnt))
1437                 return 1;
1438
1439         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1440         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1441                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1442                         "Timers VNIC usage counter timed out",
1443                         poll_cnt))
1444                 return 1;
1445         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1446                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1447                         "Timers NUM_SCANS usage counter timed out",
1448                         poll_cnt))
1449                 return 1;
1450
1451         /* Wait DMAE PF usage counter to zero */
1452         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1453                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1454                         "DMAE command register timed out",
1455                         poll_cnt))
1456                 return 1;
1457
1458         return 0;
1459 }
1460
1461 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1462 {
1463         u32 val;
1464
1465         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1466         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1467
1468         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1469         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1470
1471         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1472         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1473
1474         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1475         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1476
1477         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1478         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1479
1480         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1481         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1482
1483         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1484         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1485
1486         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1487         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1488            val);
1489 }
1490
1491 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1492 {
1493         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1494
1495         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1496
1497         /* Re-enable PF target read access */
1498         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1499
1500         /* Poll HW usage counters */
1501         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1502         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1503                 return -EBUSY;
1504
1505         /* Zero the igu 'trailing edge' and 'leading edge' */
1506
1507         /* Send the FW cleanup command */
1508         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1509                 return -EBUSY;
1510
1511         /* ATC cleanup */
1512
1513         /* Verify TX hw is flushed */
1514         bnx2x_tx_hw_flushed(bp, poll_cnt);
1515
1516         /* Wait 100ms (not adjusted according to platform) */
1517         msleep(100);
1518
1519         /* Verify no pending pci transactions */
1520         if (bnx2x_is_pcie_pending(bp->pdev))
1521                 BNX2X_ERR("PCIE Transactions still pending\n");
1522
1523         /* Debug */
1524         bnx2x_hw_enable_status(bp);
1525
1526         /*
1527          * Master enable - Due to WB DMAE writes performed before this
1528          * register is re-initialized as part of the regular function init
1529          */
1530         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1531
1532         return 0;
1533 }
1534
1535 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1536 {
1537         int port = BP_PORT(bp);
1538         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1539         u32 val = REG_RD(bp, addr);
1540         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1541         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1542         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1543
1544         if (msix) {
1545                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1546                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1547                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1548                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1549                 if (single_msix)
1550                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1551         } else if (msi) {
1552                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1553                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1554                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1555                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1556         } else {
1557                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1558                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1559                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1560                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1561
1562                 if (!CHIP_IS_E1(bp)) {
1563                         DP(NETIF_MSG_IFUP,
1564                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1565
1566                         REG_WR(bp, addr, val);
1567
1568                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1569                 }
1570         }
1571
1572         if (CHIP_IS_E1(bp))
1573                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1574
1575         DP(NETIF_MSG_IFUP,
1576            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1577            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1578
1579         REG_WR(bp, addr, val);
1580         /*
1581          * Ensure that HC_CONFIG is written before leading/trailing edge config
1582          */
1583         mmiowb();
1584         barrier();
1585
1586         if (!CHIP_IS_E1(bp)) {
1587                 /* init leading/trailing edge */
1588                 if (IS_MF(bp)) {
1589                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1590                         if (bp->port.pmf)
1591                                 /* enable nig and gpio3 attention */
1592                                 val |= 0x1100;
1593                 } else
1594                         val = 0xffff;
1595
1596                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1597                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1598         }
1599
1600         /* Make sure that interrupts are indeed enabled from here on */
1601         mmiowb();
1602 }
1603
1604 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1605 {
1606         u32 val;
1607         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1608         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1609         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1610
1611         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1612
1613         if (msix) {
1614                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1615                          IGU_PF_CONF_SINGLE_ISR_EN);
1616                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1617                         IGU_PF_CONF_ATTN_BIT_EN);
1618
1619                 if (single_msix)
1620                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1621         } else if (msi) {
1622                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1623                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1624                         IGU_PF_CONF_ATTN_BIT_EN |
1625                         IGU_PF_CONF_SINGLE_ISR_EN);
1626         } else {
1627                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1628                 val |= (IGU_PF_CONF_INT_LINE_EN |
1629                         IGU_PF_CONF_ATTN_BIT_EN |
1630                         IGU_PF_CONF_SINGLE_ISR_EN);
1631         }
1632
1633         /* Clean previous status - need to configure igu prior to ack*/
1634         if ((!msix) || single_msix) {
1635                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1636                 bnx2x_ack_int(bp);
1637         }
1638
1639         val |= IGU_PF_CONF_FUNC_EN;
1640
1641         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1642            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1643
1644         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1645
1646         if (val & IGU_PF_CONF_INT_LINE_EN)
1647                 pci_intx(bp->pdev, true);
1648
1649         barrier();
1650
1651         /* init leading/trailing edge */
1652         if (IS_MF(bp)) {
1653                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1654                 if (bp->port.pmf)
1655                         /* enable nig and gpio3 attention */
1656                         val |= 0x1100;
1657         } else
1658                 val = 0xffff;
1659
1660         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1661         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1662
1663         /* Make sure that interrupts are indeed enabled from here on */
1664         mmiowb();
1665 }
1666
1667 void bnx2x_int_enable(struct bnx2x *bp)
1668 {
1669         if (bp->common.int_block == INT_BLOCK_HC)
1670                 bnx2x_hc_int_enable(bp);
1671         else
1672                 bnx2x_igu_int_enable(bp);
1673 }
1674
1675 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1676 {
1677         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1678         int i, offset;
1679
1680         if (disable_hw)
1681                 /* prevent the HW from sending interrupts */
1682                 bnx2x_int_disable(bp);
1683
1684         /* make sure all ISRs are done */
1685         if (msix) {
1686                 synchronize_irq(bp->msix_table[0].vector);
1687                 offset = 1;
1688                 if (CNIC_SUPPORT(bp))
1689                         offset++;
1690                 for_each_eth_queue(bp, i)
1691                         synchronize_irq(bp->msix_table[offset++].vector);
1692         } else
1693                 synchronize_irq(bp->pdev->irq);
1694
1695         /* make sure sp_task is not running */
1696         cancel_delayed_work(&bp->sp_task);
1697         cancel_delayed_work(&bp->period_task);
1698         flush_workqueue(bnx2x_wq);
1699 }
1700
1701 /* fast path */
1702
1703 /*
1704  * General service functions
1705  */
1706
1707 /* Return true if succeeded to acquire the lock */
1708 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1709 {
1710         u32 lock_status;
1711         u32 resource_bit = (1 << resource);
1712         int func = BP_FUNC(bp);
1713         u32 hw_lock_control_reg;
1714
1715         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1716            "Trying to take a lock on resource %d\n", resource);
1717
1718         /* Validating that the resource is within range */
1719         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1720                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1721                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1722                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1723                 return false;
1724         }
1725
1726         if (func <= 5)
1727                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1728         else
1729                 hw_lock_control_reg =
1730                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1731
1732         /* Try to acquire the lock */
1733         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1734         lock_status = REG_RD(bp, hw_lock_control_reg);
1735         if (lock_status & resource_bit)
1736                 return true;
1737
1738         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1739            "Failed to get a lock on resource %d\n", resource);
1740         return false;
1741 }
1742
1743 /**
1744  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1745  *
1746  * @bp: driver handle
1747  *
1748  * Returns the recovery leader resource id according to the engine this function
1749  * belongs to. Currently only only 2 engines is supported.
1750  */
1751 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1752 {
1753         if (BP_PATH(bp))
1754                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1755         else
1756                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1757 }
1758
1759 /**
1760  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1761  *
1762  * @bp: driver handle
1763  *
1764  * Tries to acquire a leader lock for current engine.
1765  */
1766 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1767 {
1768         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1769 }
1770
1771 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1772
1773 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1774 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1775 {
1776         /* Set the interrupt occurred bit for the sp-task to recognize it
1777          * must ack the interrupt and transition according to the IGU
1778          * state machine.
1779          */
1780         atomic_set(&bp->interrupt_occurred, 1);
1781
1782         /* The sp_task must execute only after this bit
1783          * is set, otherwise we will get out of sync and miss all
1784          * further interrupts. Hence, the barrier.
1785          */
1786         smp_wmb();
1787
1788         /* schedule sp_task to workqueue */
1789         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1790 }
1791
1792 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1793 {
1794         struct bnx2x *bp = fp->bp;
1795         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1796         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1797         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1798         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1799
1800         DP(BNX2X_MSG_SP,
1801            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1802            fp->index, cid, command, bp->state,
1803            rr_cqe->ramrod_cqe.ramrod_type);
1804
1805         /* If cid is within VF range, replace the slowpath object with the
1806          * one corresponding to this VF
1807          */
1808         if (cid >= BNX2X_FIRST_VF_CID  &&
1809             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1810                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1811
1812         switch (command) {
1813         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1814                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1815                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1816                 break;
1817
1818         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1819                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1820                 drv_cmd = BNX2X_Q_CMD_SETUP;
1821                 break;
1822
1823         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1824                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1825                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1826                 break;
1827
1828         case (RAMROD_CMD_ID_ETH_HALT):
1829                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1830                 drv_cmd = BNX2X_Q_CMD_HALT;
1831                 break;
1832
1833         case (RAMROD_CMD_ID_ETH_TERMINATE):
1834                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1835                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1836                 break;
1837
1838         case (RAMROD_CMD_ID_ETH_EMPTY):
1839                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1840                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1841                 break;
1842
1843         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1844                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1845                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1846                 break;
1847
1848         default:
1849                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1850                           command, fp->index);
1851                 return;
1852         }
1853
1854         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1855             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1856                 /* q_obj->complete_cmd() failure means that this was
1857                  * an unexpected completion.
1858                  *
1859                  * In this case we don't want to increase the bp->spq_left
1860                  * because apparently we haven't sent this command the first
1861                  * place.
1862                  */
1863 #ifdef BNX2X_STOP_ON_ERROR
1864                 bnx2x_panic();
1865 #else
1866                 return;
1867 #endif
1868
1869         smp_mb__before_atomic();
1870         atomic_inc(&bp->cq_spq_left);
1871         /* push the change in bp->spq_left and towards the memory */
1872         smp_mb__after_atomic();
1873
1874         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1875
1876         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1877             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1878                 /* if Q update ramrod is completed for last Q in AFEX vif set
1879                  * flow, then ACK MCP at the end
1880                  *
1881                  * mark pending ACK to MCP bit.
1882                  * prevent case that both bits are cleared.
1883                  * At the end of load/unload driver checks that
1884                  * sp_state is cleared, and this order prevents
1885                  * races
1886                  */
1887                 smp_mb__before_atomic();
1888                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1889                 wmb();
1890                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1891                 smp_mb__after_atomic();
1892
1893                 /* schedule the sp task as mcp ack is required */
1894                 bnx2x_schedule_sp_task(bp);
1895         }
1896
1897         return;
1898 }
1899
1900 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1901 {
1902         struct bnx2x *bp = netdev_priv(dev_instance);
1903         u16 status = bnx2x_ack_int(bp);
1904         u16 mask;
1905         int i;
1906         u8 cos;
1907
1908         /* Return here if interrupt is shared and it's not for us */
1909         if (unlikely(status == 0)) {
1910                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1911                 return IRQ_NONE;
1912         }
1913         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1914
1915 #ifdef BNX2X_STOP_ON_ERROR
1916         if (unlikely(bp->panic))
1917                 return IRQ_HANDLED;
1918 #endif
1919
1920         for_each_eth_queue(bp, i) {
1921                 struct bnx2x_fastpath *fp = &bp->fp[i];
1922
1923                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1924                 if (status & mask) {
1925                         /* Handle Rx or Tx according to SB id */
1926                         for_each_cos_in_tx_queue(fp, cos)
1927                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1928                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1929                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1930                         status &= ~mask;
1931                 }
1932         }
1933
1934         if (CNIC_SUPPORT(bp)) {
1935                 mask = 0x2;
1936                 if (status & (mask | 0x1)) {
1937                         struct cnic_ops *c_ops = NULL;
1938
1939                         rcu_read_lock();
1940                         c_ops = rcu_dereference(bp->cnic_ops);
1941                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1942                                       CNIC_DRV_STATE_HANDLES_IRQ))
1943                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1944                         rcu_read_unlock();
1945
1946                         status &= ~mask;
1947                 }
1948         }
1949
1950         if (unlikely(status & 0x1)) {
1951
1952                 /* schedule sp task to perform default status block work, ack
1953                  * attentions and enable interrupts.
1954                  */
1955                 bnx2x_schedule_sp_task(bp);
1956
1957                 status &= ~0x1;
1958                 if (!status)
1959                         return IRQ_HANDLED;
1960         }
1961
1962         if (unlikely(status))
1963                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1964                    status);
1965
1966         return IRQ_HANDLED;
1967 }
1968
1969 /* Link */
1970
1971 /*
1972  * General service functions
1973  */
1974
1975 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1976 {
1977         u32 lock_status;
1978         u32 resource_bit = (1 << resource);
1979         int func = BP_FUNC(bp);
1980         u32 hw_lock_control_reg;
1981         int cnt;
1982
1983         /* Validating that the resource is within range */
1984         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1985                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1986                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1987                 return -EINVAL;
1988         }
1989
1990         if (func <= 5) {
1991                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1992         } else {
1993                 hw_lock_control_reg =
1994                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1995         }
1996
1997         /* Validating that the resource is not already taken */
1998         lock_status = REG_RD(bp, hw_lock_control_reg);
1999         if (lock_status & resource_bit) {
2000                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2001                    lock_status, resource_bit);
2002                 return -EEXIST;
2003         }
2004
2005         /* Try for 5 second every 5ms */
2006         for (cnt = 0; cnt < 1000; cnt++) {
2007                 /* Try to acquire the lock */
2008                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2009                 lock_status = REG_RD(bp, hw_lock_control_reg);
2010                 if (lock_status & resource_bit)
2011                         return 0;
2012
2013                 usleep_range(5000, 10000);
2014         }
2015         BNX2X_ERR("Timeout\n");
2016         return -EAGAIN;
2017 }
2018
2019 int bnx2x_release_leader_lock(struct bnx2x *bp)
2020 {
2021         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2022 }
2023
2024 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2025 {
2026         u32 lock_status;
2027         u32 resource_bit = (1 << resource);
2028         int func = BP_FUNC(bp);
2029         u32 hw_lock_control_reg;
2030
2031         /* Validating that the resource is within range */
2032         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2033                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2034                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2035                 return -EINVAL;
2036         }
2037
2038         if (func <= 5) {
2039                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2040         } else {
2041                 hw_lock_control_reg =
2042                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2043         }
2044
2045         /* Validating that the resource is currently taken */
2046         lock_status = REG_RD(bp, hw_lock_control_reg);
2047         if (!(lock_status & resource_bit)) {
2048                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2049                           lock_status, resource_bit);
2050                 return -EFAULT;
2051         }
2052
2053         REG_WR(bp, hw_lock_control_reg, resource_bit);
2054         return 0;
2055 }
2056
2057 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2058 {
2059         /* The GPIO should be swapped if swap register is set and active */
2060         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2061                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2062         int gpio_shift = gpio_num +
2063                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2064         u32 gpio_mask = (1 << gpio_shift);
2065         u32 gpio_reg;
2066         int value;
2067
2068         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2069                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2070                 return -EINVAL;
2071         }
2072
2073         /* read GPIO value */
2074         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2075
2076         /* get the requested pin value */
2077         if ((gpio_reg & gpio_mask) == gpio_mask)
2078                 value = 1;
2079         else
2080                 value = 0;
2081
2082         return value;
2083 }
2084
2085 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2086 {
2087         /* The GPIO should be swapped if swap register is set and active */
2088         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2089                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2090         int gpio_shift = gpio_num +
2091                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2092         u32 gpio_mask = (1 << gpio_shift);
2093         u32 gpio_reg;
2094
2095         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2096                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2097                 return -EINVAL;
2098         }
2099
2100         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2101         /* read GPIO and mask except the float bits */
2102         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2103
2104         switch (mode) {
2105         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2106                 DP(NETIF_MSG_LINK,
2107                    "Set GPIO %d (shift %d) -> output low\n",
2108                    gpio_num, gpio_shift);
2109                 /* clear FLOAT and set CLR */
2110                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2111                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2112                 break;
2113
2114         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2115                 DP(NETIF_MSG_LINK,
2116                    "Set GPIO %d (shift %d) -> output high\n",
2117                    gpio_num, gpio_shift);
2118                 /* clear FLOAT and set SET */
2119                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2120                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2121                 break;
2122
2123         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2124                 DP(NETIF_MSG_LINK,
2125                    "Set GPIO %d (shift %d) -> input\n",
2126                    gpio_num, gpio_shift);
2127                 /* set FLOAT */
2128                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2129                 break;
2130
2131         default:
2132                 break;
2133         }
2134
2135         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2136         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2137
2138         return 0;
2139 }
2140
2141 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2142 {
2143         u32 gpio_reg = 0;
2144         int rc = 0;
2145
2146         /* Any port swapping should be handled by caller. */
2147
2148         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2149         /* read GPIO and mask except the float bits */
2150         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2151         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2152         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2153         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2154
2155         switch (mode) {
2156         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2157                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2158                 /* set CLR */
2159                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2160                 break;
2161
2162         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2163                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2164                 /* set SET */
2165                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2166                 break;
2167
2168         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2169                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2170                 /* set FLOAT */
2171                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2172                 break;
2173
2174         default:
2175                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2176                 rc = -EINVAL;
2177                 break;
2178         }
2179
2180         if (rc == 0)
2181                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2182
2183         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2184
2185         return rc;
2186 }
2187
2188 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2189 {
2190         /* The GPIO should be swapped if swap register is set and active */
2191         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2192                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2193         int gpio_shift = gpio_num +
2194                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2195         u32 gpio_mask = (1 << gpio_shift);
2196         u32 gpio_reg;
2197
2198         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2199                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2200                 return -EINVAL;
2201         }
2202
2203         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2204         /* read GPIO int */
2205         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2206
2207         switch (mode) {
2208         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2209                 DP(NETIF_MSG_LINK,
2210                    "Clear GPIO INT %d (shift %d) -> output low\n",
2211                    gpio_num, gpio_shift);
2212                 /* clear SET and set CLR */
2213                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2214                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2215                 break;
2216
2217         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2218                 DP(NETIF_MSG_LINK,
2219                    "Set GPIO INT %d (shift %d) -> output high\n",
2220                    gpio_num, gpio_shift);
2221                 /* clear CLR and set SET */
2222                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2223                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2224                 break;
2225
2226         default:
2227                 break;
2228         }
2229
2230         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2231         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2232
2233         return 0;
2234 }
2235
2236 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2237 {
2238         u32 spio_reg;
2239
2240         /* Only 2 SPIOs are configurable */
2241         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2242                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2243                 return -EINVAL;
2244         }
2245
2246         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2247         /* read SPIO and mask except the float bits */
2248         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2249
2250         switch (mode) {
2251         case MISC_SPIO_OUTPUT_LOW:
2252                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2253                 /* clear FLOAT and set CLR */
2254                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2255                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2256                 break;
2257
2258         case MISC_SPIO_OUTPUT_HIGH:
2259                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2260                 /* clear FLOAT and set SET */
2261                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2262                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2263                 break;
2264
2265         case MISC_SPIO_INPUT_HI_Z:
2266                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2267                 /* set FLOAT */
2268                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2269                 break;
2270
2271         default:
2272                 break;
2273         }
2274
2275         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2276         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2277
2278         return 0;
2279 }
2280
2281 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2282 {
2283         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2284         switch (bp->link_vars.ieee_fc &
2285                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2286         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2287                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2288                                                    ADVERTISED_Pause);
2289                 break;
2290
2291         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2292                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2293                                                   ADVERTISED_Pause);
2294                 break;
2295
2296         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2297                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2298                 break;
2299
2300         default:
2301                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2302                                                    ADVERTISED_Pause);
2303                 break;
2304         }
2305 }
2306
2307 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2308 {
2309         /* Initialize link parameters structure variables
2310          * It is recommended to turn off RX FC for jumbo frames
2311          *  for better performance
2312          */
2313         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2314                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2315         else
2316                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2317 }
2318
2319 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2320 {
2321         u32 pause_enabled = 0;
2322
2323         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2324                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2325                         pause_enabled = 1;
2326
2327                 REG_WR(bp, BAR_USTRORM_INTMEM +
2328                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2329                        pause_enabled);
2330         }
2331
2332         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2333            pause_enabled ? "enabled" : "disabled");
2334 }
2335
2336 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2337 {
2338         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2339         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2340
2341         if (!BP_NOMCP(bp)) {
2342                 bnx2x_set_requested_fc(bp);
2343                 bnx2x_acquire_phy_lock(bp);
2344
2345                 if (load_mode == LOAD_DIAG) {
2346                         struct link_params *lp = &bp->link_params;
2347                         lp->loopback_mode = LOOPBACK_XGXS;
2348                         /* do PHY loopback at 10G speed, if possible */
2349                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2350                                 if (lp->speed_cap_mask[cfx_idx] &
2351                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2352                                         lp->req_line_speed[cfx_idx] =
2353                                         SPEED_10000;
2354                                 else
2355                                         lp->req_line_speed[cfx_idx] =
2356                                         SPEED_1000;
2357                         }
2358                 }
2359
2360                 if (load_mode == LOAD_LOOPBACK_EXT) {
2361                         struct link_params *lp = &bp->link_params;
2362                         lp->loopback_mode = LOOPBACK_EXT;
2363                 }
2364
2365                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2366
2367                 bnx2x_release_phy_lock(bp);
2368
2369                 bnx2x_init_dropless_fc(bp);
2370
2371                 bnx2x_calc_fc_adv(bp);
2372
2373                 if (bp->link_vars.link_up) {
2374                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2375                         bnx2x_link_report(bp);
2376                 }
2377                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2378                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2379                 return rc;
2380         }
2381         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2382         return -EINVAL;
2383 }
2384
2385 void bnx2x_link_set(struct bnx2x *bp)
2386 {
2387         if (!BP_NOMCP(bp)) {
2388                 bnx2x_acquire_phy_lock(bp);
2389                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2390                 bnx2x_release_phy_lock(bp);
2391
2392                 bnx2x_init_dropless_fc(bp);
2393
2394                 bnx2x_calc_fc_adv(bp);
2395         } else
2396                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2397 }
2398
2399 static void bnx2x__link_reset(struct bnx2x *bp)
2400 {
2401         if (!BP_NOMCP(bp)) {
2402                 bnx2x_acquire_phy_lock(bp);
2403                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2404                 bnx2x_release_phy_lock(bp);
2405         } else
2406                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2407 }
2408
2409 void bnx2x_force_link_reset(struct bnx2x *bp)
2410 {
2411         bnx2x_acquire_phy_lock(bp);
2412         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2413         bnx2x_release_phy_lock(bp);
2414 }
2415
2416 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2417 {
2418         u8 rc = 0;
2419
2420         if (!BP_NOMCP(bp)) {
2421                 bnx2x_acquire_phy_lock(bp);
2422                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2423                                      is_serdes);
2424                 bnx2x_release_phy_lock(bp);
2425         } else
2426                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2427
2428         return rc;
2429 }
2430
2431 /* Calculates the sum of vn_min_rates.
2432    It's needed for further normalizing of the min_rates.
2433    Returns:
2434      sum of vn_min_rates.
2435        or
2436      0 - if all the min_rates are 0.
2437      In the later case fairness algorithm should be deactivated.
2438      If not all min_rates are zero then those that are zeroes will be set to 1.
2439  */
2440 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2441                                       struct cmng_init_input *input)
2442 {
2443         int all_zero = 1;
2444         int vn;
2445
2446         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2447                 u32 vn_cfg = bp->mf_config[vn];
2448                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2449                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2450
2451                 /* Skip hidden vns */
2452                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2453                         vn_min_rate = 0;
2454                 /* If min rate is zero - set it to 1 */
2455                 else if (!vn_min_rate)
2456                         vn_min_rate = DEF_MIN_RATE;
2457                 else
2458                         all_zero = 0;
2459
2460                 input->vnic_min_rate[vn] = vn_min_rate;
2461         }
2462
2463         /* if ETS or all min rates are zeros - disable fairness */
2464         if (BNX2X_IS_ETS_ENABLED(bp)) {
2465                 input->flags.cmng_enables &=
2466                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2467                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2468         } else if (all_zero) {
2469                 input->flags.cmng_enables &=
2470                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2471                 DP(NETIF_MSG_IFUP,
2472                    "All MIN values are zeroes fairness will be disabled\n");
2473         } else
2474                 input->flags.cmng_enables |=
2475                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476 }
2477
2478 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2479                                     struct cmng_init_input *input)
2480 {
2481         u16 vn_max_rate;
2482         u32 vn_cfg = bp->mf_config[vn];
2483
2484         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2485                 vn_max_rate = 0;
2486         else {
2487                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2488
2489                 if (IS_MF_SI(bp)) {
2490                         /* maxCfg in percents of linkspeed */
2491                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2492                 } else /* SD modes */
2493                         /* maxCfg is absolute in 100Mb units */
2494                         vn_max_rate = maxCfg * 100;
2495         }
2496
2497         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2498
2499         input->vnic_max_rate[vn] = vn_max_rate;
2500 }
2501
2502 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2503 {
2504         if (CHIP_REV_IS_SLOW(bp))
2505                 return CMNG_FNS_NONE;
2506         if (IS_MF(bp))
2507                 return CMNG_FNS_MINMAX;
2508
2509         return CMNG_FNS_NONE;
2510 }
2511
2512 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2513 {
2514         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2515
2516         if (BP_NOMCP(bp))
2517                 return; /* what should be the default value in this case */
2518
2519         /* For 2 port configuration the absolute function number formula
2520          * is:
2521          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2522          *
2523          *      and there are 4 functions per port
2524          *
2525          * For 4 port configuration it is
2526          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2527          *
2528          *      and there are 2 functions per port
2529          */
2530         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2531                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2532
2533                 if (func >= E1H_FUNC_MAX)
2534                         break;
2535
2536                 bp->mf_config[vn] =
2537                         MF_CFG_RD(bp, func_mf_config[func].config);
2538         }
2539         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2540                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2541                 bp->flags |= MF_FUNC_DIS;
2542         } else {
2543                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2544                 bp->flags &= ~MF_FUNC_DIS;
2545         }
2546 }
2547
2548 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2549 {
2550         struct cmng_init_input input;
2551         memset(&input, 0, sizeof(struct cmng_init_input));
2552
2553         input.port_rate = bp->link_vars.line_speed;
2554
2555         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2556                 int vn;
2557
2558                 /* read mf conf from shmem */
2559                 if (read_cfg)
2560                         bnx2x_read_mf_cfg(bp);
2561
2562                 /* vn_weight_sum and enable fairness if not 0 */
2563                 bnx2x_calc_vn_min(bp, &input);
2564
2565                 /* calculate and set min-max rate for each vn */
2566                 if (bp->port.pmf)
2567                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2568                                 bnx2x_calc_vn_max(bp, vn, &input);
2569
2570                 /* always enable rate shaping and fairness */
2571                 input.flags.cmng_enables |=
2572                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2573
2574                 bnx2x_init_cmng(&input, &bp->cmng);
2575                 return;
2576         }
2577
2578         /* rate shaping and fairness are disabled */
2579         DP(NETIF_MSG_IFUP,
2580            "rate shaping and fairness are disabled\n");
2581 }
2582
2583 static void storm_memset_cmng(struct bnx2x *bp,
2584                               struct cmng_init *cmng,
2585                               u8 port)
2586 {
2587         int vn;
2588         size_t size = sizeof(struct cmng_struct_per_port);
2589
2590         u32 addr = BAR_XSTRORM_INTMEM +
2591                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2592
2593         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2594
2595         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2596                 int func = func_by_vn(bp, vn);
2597
2598                 addr = BAR_XSTRORM_INTMEM +
2599                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2600                 size = sizeof(struct rate_shaping_vars_per_vn);
2601                 __storm_memset_struct(bp, addr, size,
2602                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2603
2604                 addr = BAR_XSTRORM_INTMEM +
2605                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2606                 size = sizeof(struct fairness_vars_per_vn);
2607                 __storm_memset_struct(bp, addr, size,
2608                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2609         }
2610 }
2611
2612 /* init cmng mode in HW according to local configuration */
2613 void bnx2x_set_local_cmng(struct bnx2x *bp)
2614 {
2615         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2616
2617         if (cmng_fns != CMNG_FNS_NONE) {
2618                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2619                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2620         } else {
2621                 /* rate shaping and fairness are disabled */
2622                 DP(NETIF_MSG_IFUP,
2623                    "single function mode without fairness\n");
2624         }
2625 }
2626
2627 /* This function is called upon link interrupt */
2628 static void bnx2x_link_attn(struct bnx2x *bp)
2629 {
2630         /* Make sure that we are synced with the current statistics */
2631         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2632
2633         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2634
2635         bnx2x_init_dropless_fc(bp);
2636
2637         if (bp->link_vars.link_up) {
2638
2639                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2640                         struct host_port_stats *pstats;
2641
2642                         pstats = bnx2x_sp(bp, port_stats);
2643                         /* reset old mac stats */
2644                         memset(&(pstats->mac_stx[0]), 0,
2645                                sizeof(struct mac_stx));
2646                 }
2647                 if (bp->state == BNX2X_STATE_OPEN)
2648                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2649         }
2650
2651         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2652                 bnx2x_set_local_cmng(bp);
2653
2654         __bnx2x_link_report(bp);
2655
2656         if (IS_MF(bp))
2657                 bnx2x_link_sync_notify(bp);
2658 }
2659
2660 void bnx2x__link_status_update(struct bnx2x *bp)
2661 {
2662         if (bp->state != BNX2X_STATE_OPEN)
2663                 return;
2664
2665         /* read updated dcb configuration */
2666         if (IS_PF(bp)) {
2667                 bnx2x_dcbx_pmf_update(bp);
2668                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2669                 if (bp->link_vars.link_up)
2670                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2671                 else
2672                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2673                         /* indicate link status */
2674                 bnx2x_link_report(bp);
2675
2676         } else { /* VF */
2677                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2678                                           SUPPORTED_10baseT_Full |
2679                                           SUPPORTED_100baseT_Half |
2680                                           SUPPORTED_100baseT_Full |
2681                                           SUPPORTED_1000baseT_Full |
2682                                           SUPPORTED_2500baseX_Full |
2683                                           SUPPORTED_10000baseT_Full |
2684                                           SUPPORTED_TP |
2685                                           SUPPORTED_FIBRE |
2686                                           SUPPORTED_Autoneg |
2687                                           SUPPORTED_Pause |
2688                                           SUPPORTED_Asym_Pause);
2689                 bp->port.advertising[0] = bp->port.supported[0];
2690
2691                 bp->link_params.bp = bp;
2692                 bp->link_params.port = BP_PORT(bp);
2693                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2694                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2695                 bp->link_params.req_line_speed[0] = SPEED_10000;
2696                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2697                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2698                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2699                 bp->link_vars.line_speed = SPEED_10000;
2700                 bp->link_vars.link_status =
2701                         (LINK_STATUS_LINK_UP |
2702                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2703                 bp->link_vars.link_up = 1;
2704                 bp->link_vars.duplex = DUPLEX_FULL;
2705                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2706                 __bnx2x_link_report(bp);
2707
2708                 bnx2x_sample_bulletin(bp);
2709
2710                 /* if bulletin board did not have an update for link status
2711                  * __bnx2x_link_report will report current status
2712                  * but it will NOT duplicate report in case of already reported
2713                  * during sampling bulletin board.
2714                  */
2715                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2716         }
2717 }
2718
2719 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2720                                   u16 vlan_val, u8 allowed_prio)
2721 {
2722         struct bnx2x_func_state_params func_params = {NULL};
2723         struct bnx2x_func_afex_update_params *f_update_params =
2724                 &func_params.params.afex_update;
2725
2726         func_params.f_obj = &bp->func_obj;
2727         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2728
2729         /* no need to wait for RAMROD completion, so don't
2730          * set RAMROD_COMP_WAIT flag
2731          */
2732
2733         f_update_params->vif_id = vifid;
2734         f_update_params->afex_default_vlan = vlan_val;
2735         f_update_params->allowed_priorities = allowed_prio;
2736
2737         /* if ramrod can not be sent, response to MCP immediately */
2738         if (bnx2x_func_state_change(bp, &func_params) < 0)
2739                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2740
2741         return 0;
2742 }
2743
2744 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2745                                           u16 vif_index, u8 func_bit_map)
2746 {
2747         struct bnx2x_func_state_params func_params = {NULL};
2748         struct bnx2x_func_afex_viflists_params *update_params =
2749                 &func_params.params.afex_viflists;
2750         int rc;
2751         u32 drv_msg_code;
2752
2753         /* validate only LIST_SET and LIST_GET are received from switch */
2754         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2755                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2756                           cmd_type);
2757
2758         func_params.f_obj = &bp->func_obj;
2759         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2760
2761         /* set parameters according to cmd_type */
2762         update_params->afex_vif_list_command = cmd_type;
2763         update_params->vif_list_index = vif_index;
2764         update_params->func_bit_map =
2765                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2766         update_params->func_to_clear = 0;
2767         drv_msg_code =
2768                 (cmd_type == VIF_LIST_RULE_GET) ?
2769                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2770                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2771
2772         /* if ramrod can not be sent, respond to MCP immediately for
2773          * SET and GET requests (other are not triggered from MCP)
2774          */
2775         rc = bnx2x_func_state_change(bp, &func_params);
2776         if (rc < 0)
2777                 bnx2x_fw_command(bp, drv_msg_code, 0);
2778
2779         return 0;
2780 }
2781
2782 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2783 {
2784         struct afex_stats afex_stats;
2785         u32 func = BP_ABS_FUNC(bp);
2786         u32 mf_config;
2787         u16 vlan_val;
2788         u32 vlan_prio;
2789         u16 vif_id;
2790         u8 allowed_prio;
2791         u8 vlan_mode;
2792         u32 addr_to_write, vifid, addrs, stats_type, i;
2793
2794         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2795                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2796                 DP(BNX2X_MSG_MCP,
2797                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2798                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2799         }
2800
2801         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2802                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2803                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2804                 DP(BNX2X_MSG_MCP,
2805                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2806                    vifid, addrs);
2807                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2808                                                addrs);
2809         }
2810
2811         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2812                 addr_to_write = SHMEM2_RD(bp,
2813                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2814                 stats_type = SHMEM2_RD(bp,
2815                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2816
2817                 DP(BNX2X_MSG_MCP,
2818                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2819                    addr_to_write);
2820
2821                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2822
2823                 /* write response to scratchpad, for MCP */
2824                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2825                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2826                                *(((u32 *)(&afex_stats))+i));
2827
2828                 /* send ack message to MCP */
2829                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2830         }
2831
2832         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2833                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2834                 bp->mf_config[BP_VN(bp)] = mf_config;
2835                 DP(BNX2X_MSG_MCP,
2836                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2837                    mf_config);
2838
2839                 /* if VIF_SET is "enabled" */
2840                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2841                         /* set rate limit directly to internal RAM */
2842                         struct cmng_init_input cmng_input;
2843                         struct rate_shaping_vars_per_vn m_rs_vn;
2844                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2845                         u32 addr = BAR_XSTRORM_INTMEM +
2846                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2847
2848                         bp->mf_config[BP_VN(bp)] = mf_config;
2849
2850                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2851                         m_rs_vn.vn_counter.rate =
2852                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2853                         m_rs_vn.vn_counter.quota =
2854                                 (m_rs_vn.vn_counter.rate *
2855                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2856
2857                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2858
2859                         /* read relevant values from mf_cfg struct in shmem */
2860                         vif_id =
2861                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2862                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2863                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2864                         vlan_val =
2865                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2866                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2867                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2868                         vlan_prio = (mf_config &
2869                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2870                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2871                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2872                         vlan_mode =
2873                                 (MF_CFG_RD(bp,
2874                                            func_mf_config[func].afex_config) &
2875                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2876                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2877                         allowed_prio =
2878                                 (MF_CFG_RD(bp,
2879                                            func_mf_config[func].afex_config) &
2880                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2881                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2882
2883                         /* send ramrod to FW, return in case of failure */
2884                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2885                                                    allowed_prio))
2886                                 return;
2887
2888                         bp->afex_def_vlan_tag = vlan_val;
2889                         bp->afex_vlan_mode = vlan_mode;
2890                 } else {
2891                         /* notify link down because BP->flags is disabled */
2892                         bnx2x_link_report(bp);
2893
2894                         /* send INVALID VIF ramrod to FW */
2895                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2896
2897                         /* Reset the default afex VLAN */
2898                         bp->afex_def_vlan_tag = -1;
2899                 }
2900         }
2901 }
2902
2903 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2904 {
2905         struct bnx2x_func_switch_update_params *switch_update_params;
2906         struct bnx2x_func_state_params func_params;
2907
2908         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2909         switch_update_params = &func_params.params.switch_update;
2910         func_params.f_obj = &bp->func_obj;
2911         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2912
2913         if (IS_MF_UFP(bp)) {
2914                 int func = BP_ABS_FUNC(bp);
2915                 u32 val;
2916
2917                 /* Re-learn the S-tag from shmem */
2918                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2919                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2920                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2921                         bp->mf_ov = val;
2922                 } else {
2923                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2924                         goto fail;
2925                 }
2926
2927                 /* Configure new S-tag in LLH */
2928                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2929                        bp->mf_ov);
2930
2931                 /* Send Ramrod to update FW of change */
2932                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2933                           &switch_update_params->changes);
2934                 switch_update_params->vlan = bp->mf_ov;
2935
2936                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2937                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2938                                   bp->mf_ov);
2939                         goto fail;
2940                 }
2941
2942                 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2943
2944                 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2945
2946                 return;
2947         }
2948
2949         /* not supported by SW yet */
2950 fail:
2951         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2952 }
2953
2954 static void bnx2x_pmf_update(struct bnx2x *bp)
2955 {
2956         int port = BP_PORT(bp);
2957         u32 val;
2958
2959         bp->port.pmf = 1;
2960         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2961
2962         /*
2963          * We need the mb() to ensure the ordering between the writing to
2964          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2965          */
2966         smp_mb();
2967
2968         /* queue a periodic task */
2969         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2970
2971         bnx2x_dcbx_pmf_update(bp);
2972
2973         /* enable nig attention */
2974         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2975         if (bp->common.int_block == INT_BLOCK_HC) {
2976                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2977                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2978         } else if (!CHIP_IS_E1x(bp)) {
2979                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2980                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2981         }
2982
2983         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2984 }
2985
2986 /* end of Link */
2987
2988 /* slow path */
2989
2990 /*
2991  * General service functions
2992  */
2993
2994 /* send the MCP a request, block until there is a reply */
2995 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2996 {
2997         int mb_idx = BP_FW_MB_IDX(bp);
2998         u32 seq;
2999         u32 rc = 0;
3000         u32 cnt = 1;
3001         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3002
3003         mutex_lock(&bp->fw_mb_mutex);
3004         seq = ++bp->fw_seq;
3005         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3006         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3007
3008         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3009                         (command | seq), param);
3010
3011         do {
3012                 /* let the FW do it's magic ... */
3013                 msleep(delay);
3014
3015                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3016
3017                 /* Give the FW up to 5 second (500*10ms) */
3018         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3019
3020         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3021            cnt*delay, rc, seq);
3022
3023         /* is this a reply to our command? */
3024         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3025                 rc &= FW_MSG_CODE_MASK;
3026         else {
3027                 /* FW BUG! */
3028                 BNX2X_ERR("FW failed to respond!\n");
3029                 bnx2x_fw_dump(bp);
3030                 rc = 0;
3031         }
3032         mutex_unlock(&bp->fw_mb_mutex);
3033
3034         return rc;
3035 }
3036
3037 static void storm_memset_func_cfg(struct bnx2x *bp,
3038                                  struct tstorm_eth_function_common_config *tcfg,
3039                                  u16 abs_fid)
3040 {
3041         size_t size = sizeof(struct tstorm_eth_function_common_config);
3042
3043         u32 addr = BAR_TSTRORM_INTMEM +
3044                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3045
3046         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3047 }
3048
3049 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3050 {
3051         if (CHIP_IS_E1x(bp)) {
3052                 struct tstorm_eth_function_common_config tcfg = {0};
3053
3054                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3055         }
3056
3057         /* Enable the function in the FW */
3058         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3059         storm_memset_func_en(bp, p->func_id, 1);
3060
3061         /* spq */
3062         if (p->func_flgs & FUNC_FLG_SPQ) {
3063                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3064                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3065                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3066         }
3067 }
3068
3069 /**
3070  * bnx2x_get_common_flags - Return common flags
3071  *
3072  * @bp          device handle
3073  * @fp          queue handle
3074  * @zero_stats  TRUE if statistics zeroing is needed
3075  *
3076  * Return the flags that are common for the Tx-only and not normal connections.
3077  */
3078 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3079                                             struct bnx2x_fastpath *fp,
3080                                             bool zero_stats)
3081 {
3082         unsigned long flags = 0;
3083
3084         /* PF driver will always initialize the Queue to an ACTIVE state */
3085         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3086
3087         /* tx only connections collect statistics (on the same index as the
3088          * parent connection). The statistics are zeroed when the parent
3089          * connection is initialized.
3090          */
3091
3092         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3093         if (zero_stats)
3094                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3095
3096         if (bp->flags & TX_SWITCHING)
3097                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3098
3099         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3100         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3101
3102 #ifdef BNX2X_STOP_ON_ERROR
3103         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3104 #endif
3105
3106         return flags;
3107 }
3108
3109 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3110                                        struct bnx2x_fastpath *fp,
3111                                        bool leading)
3112 {
3113         unsigned long flags = 0;
3114
3115         /* calculate other queue flags */
3116         if (IS_MF_SD(bp))
3117                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3118
3119         if (IS_FCOE_FP(fp)) {
3120                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3121                 /* For FCoE - force usage of default priority (for afex) */
3122                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3123         }
3124
3125         if (fp->mode != TPA_MODE_DISABLED) {
3126                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3127                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3128                 if (fp->mode == TPA_MODE_GRO)
3129                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3130         }
3131
3132         if (leading) {
3133                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3134                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3135         }
3136
3137         /* Always set HW VLAN stripping */
3138         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3139
3140         /* configure silent vlan removal */
3141         if (IS_MF_AFEX(bp))
3142                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3143
3144         return flags | bnx2x_get_common_flags(bp, fp, true);
3145 }
3146
3147 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3148         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3149         u8 cos)
3150 {
3151         gen_init->stat_id = bnx2x_stats_id(fp);
3152         gen_init->spcl_id = fp->cl_id;
3153
3154         /* Always use mini-jumbo MTU for FCoE L2 ring */
3155         if (IS_FCOE_FP(fp))
3156                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3157         else
3158                 gen_init->mtu = bp->dev->mtu;
3159
3160         gen_init->cos = cos;
3161
3162         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3163 }
3164
3165 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3166         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3167         struct bnx2x_rxq_setup_params *rxq_init)
3168 {
3169         u8 max_sge = 0;
3170         u16 sge_sz = 0;
3171         u16 tpa_agg_size = 0;
3172
3173         if (fp->mode != TPA_MODE_DISABLED) {
3174                 pause->sge_th_lo = SGE_TH_LO(bp);
3175                 pause->sge_th_hi = SGE_TH_HI(bp);
3176
3177                 /* validate SGE ring has enough to cross high threshold */
3178                 WARN_ON(bp->dropless_fc &&
3179                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3180                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3181
3182                 tpa_agg_size = TPA_AGG_SIZE;
3183                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3184                         SGE_PAGE_SHIFT;
3185                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3186                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3187                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3188         }
3189
3190         /* pause - not for e1 */
3191         if (!CHIP_IS_E1(bp)) {
3192                 pause->bd_th_lo = BD_TH_LO(bp);
3193                 pause->bd_th_hi = BD_TH_HI(bp);
3194
3195                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3196                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3197                 /*
3198                  * validate that rings have enough entries to cross
3199                  * high thresholds
3200                  */
3201                 WARN_ON(bp->dropless_fc &&
3202                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3203                                 bp->rx_ring_size);
3204                 WARN_ON(bp->dropless_fc &&
3205                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3206                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3207
3208                 pause->pri_map = 1;
3209         }
3210
3211         /* rxq setup */
3212         rxq_init->dscr_map = fp->rx_desc_mapping;
3213         rxq_init->sge_map = fp->rx_sge_mapping;
3214         rxq_init->rcq_map = fp->rx_comp_mapping;
3215         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3216
3217         /* This should be a maximum number of data bytes that may be
3218          * placed on the BD (not including paddings).
3219          */
3220         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3221                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3222
3223         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3224         rxq_init->tpa_agg_sz = tpa_agg_size;
3225         rxq_init->sge_buf_sz = sge_sz;
3226         rxq_init->max_sges_pkt = max_sge;
3227         rxq_init->rss_engine_id = BP_FUNC(bp);
3228         rxq_init->mcast_engine_id = BP_FUNC(bp);
3229
3230         /* Maximum number or simultaneous TPA aggregation for this Queue.
3231          *
3232          * For PF Clients it should be the maximum available number.
3233          * VF driver(s) may want to define it to a smaller value.
3234          */
3235         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3236
3237         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3238         rxq_init->fw_sb_id = fp->fw_sb_id;
3239
3240         if (IS_FCOE_FP(fp))
3241                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3242         else
3243                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3244         /* configure silent vlan removal
3245          * if multi function mode is afex, then mask default vlan
3246          */
3247         if (IS_MF_AFEX(bp)) {
3248                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3249                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3250         }
3251 }
3252
3253 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3254         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3255         u8 cos)
3256 {
3257         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3258         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3259         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3260         txq_init->fw_sb_id = fp->fw_sb_id;
3261
3262         /*
3263          * set the tss leading client id for TX classification ==
3264          * leading RSS client id
3265          */
3266         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3267
3268         if (IS_FCOE_FP(fp)) {
3269                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3270                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3271         }
3272 }
3273
3274 static void bnx2x_pf_init(struct bnx2x *bp)
3275 {
3276         struct bnx2x_func_init_params func_init = {0};
3277         struct event_ring_data eq_data = { {0} };
3278         u16 flags;
3279
3280         if (!CHIP_IS_E1x(bp)) {
3281                 /* reset IGU PF statistics: MSIX + ATTN */
3282                 /* PF */
3283                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3284                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3285                            (CHIP_MODE_IS_4_PORT(bp) ?
3286                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3287                 /* ATTN */
3288                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3289                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3290                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3291                            (CHIP_MODE_IS_4_PORT(bp) ?
3292                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3293         }
3294
3295         /* function setup flags */
3296         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3297
3298         /* This flag is relevant for E1x only.
3299          * E2 doesn't have a TPA configuration in a function level.
3300          */
3301         flags |= (bp->dev->features & NETIF_F_LRO) ? FUNC_FLG_TPA : 0;
3302
3303         func_init.func_flgs = flags;
3304         func_init.pf_id = BP_FUNC(bp);
3305         func_init.func_id = BP_FUNC(bp);
3306         func_init.spq_map = bp->spq_mapping;
3307         func_init.spq_prod = bp->spq_prod_idx;
3308
3309         bnx2x_func_init(bp, &func_init);
3310
3311         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3312
3313         /*
3314          * Congestion management values depend on the link rate
3315          * There is no active link so initial link rate is set to 10 Gbps.
3316          * When the link comes up The congestion management values are
3317          * re-calculated according to the actual link rate.
3318          */
3319         bp->link_vars.line_speed = SPEED_10000;
3320         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3321
3322         /* Only the PMF sets the HW */
3323         if (bp->port.pmf)
3324                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3325
3326         /* init Event Queue - PCI bus guarantees correct endianity*/
3327         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3328         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3329         eq_data.producer = bp->eq_prod;
3330         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3331         eq_data.sb_id = DEF_SB_ID;
3332         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3333 }
3334
3335 static void bnx2x_e1h_disable(struct bnx2x *bp)
3336 {
3337         int port = BP_PORT(bp);
3338
3339         bnx2x_tx_disable(bp);
3340
3341         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3342 }
3343
3344 static void bnx2x_e1h_enable(struct bnx2x *bp)
3345 {
3346         int port = BP_PORT(bp);
3347
3348         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3349                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3350
3351         /* Tx queue should be only re-enabled */
3352         netif_tx_wake_all_queues(bp->dev);
3353
3354         /*
3355          * Should not call netif_carrier_on since it will be called if the link
3356          * is up when checking for link state
3357          */
3358 }
3359
3360 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3361
3362 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3363 {
3364         struct eth_stats_info *ether_stat =
3365                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3366         struct bnx2x_vlan_mac_obj *mac_obj =
3367                 &bp->sp_objs->mac_obj;
3368         int i;
3369
3370         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3371                 ETH_STAT_INFO_VERSION_LEN);
3372
3373         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3374          * mac_local field in ether_stat struct. The base address is offset by 2
3375          * bytes to account for the field being 8 bytes but a mac address is
3376          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3377          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3378          * allocated by the ether_stat struct, so the macs will land in their
3379          * proper positions.
3380          */
3381         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3382                 memset(ether_stat->mac_local + i, 0,
3383                        sizeof(ether_stat->mac_local[0]));
3384         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3385                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3386                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3387                                 ETH_ALEN);
3388         ether_stat->mtu_size = bp->dev->mtu;
3389         if (bp->dev->features & NETIF_F_RXCSUM)
3390                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3391         if (bp->dev->features & NETIF_F_TSO)
3392                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3393         ether_stat->feature_flags |= bp->common.boot_mode;
3394
3395         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3396
3397         ether_stat->txq_size = bp->tx_ring_size;
3398         ether_stat->rxq_size = bp->rx_ring_size;
3399
3400 #ifdef CONFIG_BNX2X_SRIOV
3401         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3402 #endif
3403 }
3404
3405 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3406 {
3407         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3408         struct fcoe_stats_info *fcoe_stat =
3409                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3410
3411         if (!CNIC_LOADED(bp))
3412                 return;
3413
3414         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3415
3416         fcoe_stat->qos_priority =
3417                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3418
3419         /* insert FCoE stats from ramrod response */
3420         if (!NO_FCOE(bp)) {
3421                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3422                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3423                         tstorm_queue_statistics;
3424
3425                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3426                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3427                         xstorm_queue_statistics;
3428
3429                 struct fcoe_statistics_params *fw_fcoe_stat =
3430                         &bp->fw_stats_data->fcoe;
3431
3432                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3433                           fcoe_stat->rx_bytes_lo,
3434                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3435
3436                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3437                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3438                           fcoe_stat->rx_bytes_lo,
3439                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3440
3441                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3442                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3443                           fcoe_stat->rx_bytes_lo,
3444                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3445
3446                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3447                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3448                           fcoe_stat->rx_bytes_lo,
3449                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3450
3451                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3452                           fcoe_stat->rx_frames_lo,
3453                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3454
3455                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3456                           fcoe_stat->rx_frames_lo,
3457                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3458
3459                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460                           fcoe_stat->rx_frames_lo,
3461                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3462
3463                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3464                           fcoe_stat->rx_frames_lo,
3465                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3466
3467                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3468                           fcoe_stat->tx_bytes_lo,
3469                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3470
3471                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3472                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3473                           fcoe_stat->tx_bytes_lo,
3474                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3475
3476                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3477                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3478                           fcoe_stat->tx_bytes_lo,
3479                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3480
3481                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3482                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3483                           fcoe_stat->tx_bytes_lo,
3484                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3485
3486                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3487                           fcoe_stat->tx_frames_lo,
3488                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3489
3490                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3491                           fcoe_stat->tx_frames_lo,
3492                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3493
3494                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495                           fcoe_stat->tx_frames_lo,
3496                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3497
3498                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3499                           fcoe_stat->tx_frames_lo,
3500                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3501         }
3502
3503         /* ask L5 driver to add data to the struct */
3504         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3505 }
3506
3507 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3508 {
3509         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3510         struct iscsi_stats_info *iscsi_stat =
3511                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3512
3513         if (!CNIC_LOADED(bp))
3514                 return;
3515
3516         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3517                ETH_ALEN);
3518
3519         iscsi_stat->qos_priority =
3520                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3521
3522         /* ask L5 driver to add data to the struct */
3523         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3524 }
3525
3526 /* called due to MCP event (on pmf):
3527  *      reread new bandwidth configuration
3528  *      configure FW
3529  *      notify others function about the change
3530  */
3531 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3532 {
3533         if (bp->link_vars.link_up) {
3534                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3535                 bnx2x_link_sync_notify(bp);
3536         }
3537         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3538 }
3539
3540 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3541 {
3542         bnx2x_config_mf_bw(bp);
3543         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3544 }
3545
3546 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3547 {
3548         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3549         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3550 }
3551
3552 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3553 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3554
3555 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3556 {
3557         enum drv_info_opcode op_code;
3558         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3559         bool release = false;
3560         int wait;
3561
3562         /* if drv_info version supported by MFW doesn't match - send NACK */
3563         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3564                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3565                 return;
3566         }
3567
3568         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3569                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3570
3571         /* Must prevent other flows from accessing drv_info_to_mcp */
3572         mutex_lock(&bp->drv_info_mutex);
3573
3574         memset(&bp->slowpath->drv_info_to_mcp, 0,
3575                sizeof(union drv_info_to_mcp));
3576
3577         switch (op_code) {
3578         case ETH_STATS_OPCODE:
3579                 bnx2x_drv_info_ether_stat(bp);
3580                 break;
3581         case FCOE_STATS_OPCODE:
3582                 bnx2x_drv_info_fcoe_stat(bp);
3583                 break;
3584         case ISCSI_STATS_OPCODE:
3585                 bnx2x_drv_info_iscsi_stat(bp);
3586                 break;
3587         default:
3588                 /* if op code isn't supported - send NACK */
3589                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3590                 goto out;
3591         }
3592
3593         /* if we got drv_info attn from MFW then these fields are defined in
3594          * shmem2 for sure
3595          */
3596         SHMEM2_WR(bp, drv_info_host_addr_lo,
3597                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3598         SHMEM2_WR(bp, drv_info_host_addr_hi,
3599                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3600
3601         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3602
3603         /* Since possible management wants both this and get_driver_version
3604          * need to wait until management notifies us it finished utilizing
3605          * the buffer.
3606          */
3607         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3608                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3609         } else if (!bp->drv_info_mng_owner) {
3610                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3611
3612                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3613                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3614
3615                         /* Management is done; need to clear indication */
3616                         if (indication & bit) {
3617                                 SHMEM2_WR(bp, mfw_drv_indication,
3618                                           indication & ~bit);
3619                                 release = true;
3620                                 break;
3621                         }
3622
3623                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3624                 }
3625         }
3626         if (!release) {
3627                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3628                 bp->drv_info_mng_owner = true;
3629         }
3630
3631 out:
3632         mutex_unlock(&bp->drv_info_mutex);
3633 }
3634
3635 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3636 {
3637         u8 vals[4];
3638         int i = 0;
3639
3640         if (bnx2x_format) {
3641                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3642                            &vals[0], &vals[1], &vals[2], &vals[3]);
3643                 if (i > 0)
3644                         vals[0] -= '0';
3645         } else {
3646                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3647                            &vals[0], &vals[1], &vals[2], &vals[3]);
3648         }
3649
3650         while (i < 4)
3651                 vals[i++] = 0;
3652
3653         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3654 }
3655
3656 void bnx2x_update_mng_version(struct bnx2x *bp)
3657 {
3658         u32 iscsiver = DRV_VER_NOT_LOADED;
3659         u32 fcoever = DRV_VER_NOT_LOADED;
3660         u32 ethver = DRV_VER_NOT_LOADED;
3661         int idx = BP_FW_MB_IDX(bp);
3662         u8 *version;
3663
3664         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3665                 return;
3666
3667         mutex_lock(&bp->drv_info_mutex);
3668         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3669         if (bp->drv_info_mng_owner)
3670                 goto out;
3671
3672         if (bp->state != BNX2X_STATE_OPEN)
3673                 goto out;
3674
3675         /* Parse ethernet driver version */
3676         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3677         if (!CNIC_LOADED(bp))
3678                 goto out;
3679
3680         /* Try getting storage driver version via cnic */
3681         memset(&bp->slowpath->drv_info_to_mcp, 0,
3682                sizeof(union drv_info_to_mcp));
3683         bnx2x_drv_info_iscsi_stat(bp);
3684         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3685         iscsiver = bnx2x_update_mng_version_utility(version, false);
3686
3687         memset(&bp->slowpath->drv_info_to_mcp, 0,
3688                sizeof(union drv_info_to_mcp));
3689         bnx2x_drv_info_fcoe_stat(bp);
3690         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3691         fcoever = bnx2x_update_mng_version_utility(version, false);
3692
3693 out:
3694         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3695         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3696         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3697
3698         mutex_unlock(&bp->drv_info_mutex);
3699
3700         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3701            ethver, iscsiver, fcoever);
3702 }
3703
3704 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3705 {
3706         u32 cmd_ok, cmd_fail;
3707
3708         /* sanity */
3709         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3710             event & DRV_STATUS_OEM_EVENT_MASK) {
3711                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3712                 return;
3713         }
3714
3715         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3716                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3717                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3718         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3719                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3720                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3721         }
3722
3723         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3724
3725         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3726                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3727                 /* This is the only place besides the function initialization
3728                  * where the bp->flags can change so it is done without any
3729                  * locks
3730                  */
3731                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3732                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3733                         bp->flags |= MF_FUNC_DIS;
3734
3735                         bnx2x_e1h_disable(bp);
3736                 } else {
3737                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3738                         bp->flags &= ~MF_FUNC_DIS;
3739
3740                         bnx2x_e1h_enable(bp);
3741                 }
3742                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3743                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3744         }
3745
3746         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3747                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3748                 bnx2x_config_mf_bw(bp);
3749                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3750                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3751         }
3752
3753         /* Report results to MCP */
3754         if (event)
3755                 bnx2x_fw_command(bp, cmd_fail, 0);
3756         else
3757                 bnx2x_fw_command(bp, cmd_ok, 0);
3758 }
3759
3760 /* must be called under the spq lock */
3761 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3762 {
3763         struct eth_spe *next_spe = bp->spq_prod_bd;
3764
3765         if (bp->spq_prod_bd == bp->spq_last_bd) {
3766                 bp->spq_prod_bd = bp->spq;
3767                 bp->spq_prod_idx = 0;
3768                 DP(BNX2X_MSG_SP, "end of spq\n");
3769         } else {
3770                 bp->spq_prod_bd++;
3771                 bp->spq_prod_idx++;
3772         }
3773         return next_spe;
3774 }
3775
3776 /* must be called under the spq lock */
3777 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3778 {
3779         int func = BP_FUNC(bp);
3780
3781         /*
3782          * Make sure that BD data is updated before writing the producer:
3783          * BD data is written to the memory, the producer is read from the
3784          * memory, thus we need a full memory barrier to ensure the ordering.
3785          */
3786         mb();
3787
3788         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3789                  bp->spq_prod_idx);
3790         mmiowb();
3791 }
3792
3793 /**
3794  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3795  *
3796  * @cmd:        command to check
3797  * @cmd_type:   command type
3798  */
3799 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3800 {
3801         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3802             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3803             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3804             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3805             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3806             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3807             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3808                 return true;
3809         else
3810                 return false;
3811 }
3812
3813 /**
3814  * bnx2x_sp_post - place a single command on an SP ring
3815  *
3816  * @bp:         driver handle
3817  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3818  * @cid:        SW CID the command is related to
3819  * @data_hi:    command private data address (high 32 bits)
3820  * @data_lo:    command private data address (low 32 bits)
3821  * @cmd_type:   command type (e.g. NONE, ETH)
3822  *
3823  * SP data is handled as if it's always an address pair, thus data fields are
3824  * not swapped to little endian in upper functions. Instead this function swaps
3825  * data as if it's two u32 fields.
3826  */
3827 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3828                   u32 data_hi, u32 data_lo, int cmd_type)
3829 {
3830         struct eth_spe *spe;
3831         u16 type;
3832         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3833
3834 #ifdef BNX2X_STOP_ON_ERROR
3835         if (unlikely(bp->panic)) {
3836                 BNX2X_ERR("Can't post SP when there is panic\n");
3837                 return -EIO;
3838         }
3839 #endif
3840
3841         spin_lock_bh(&bp->spq_lock);
3842
3843         if (common) {
3844                 if (!atomic_read(&bp->eq_spq_left)) {
3845                         BNX2X_ERR("BUG! EQ ring full!\n");
3846                         spin_unlock_bh(&bp->spq_lock);
3847                         bnx2x_panic();
3848                         return -EBUSY;
3849                 }
3850         } else if (!atomic_read(&bp->cq_spq_left)) {
3851                         BNX2X_ERR("BUG! SPQ ring full!\n");
3852                         spin_unlock_bh(&bp->spq_lock);
3853                         bnx2x_panic();
3854                         return -EBUSY;
3855         }
3856
3857         spe = bnx2x_sp_get_next(bp);
3858
3859         /* CID needs port number to be encoded int it */
3860         spe->hdr.conn_and_cmd_data =
3861                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3862                                     HW_CID(bp, cid));
3863
3864         /* In some cases, type may already contain the func-id
3865          * mainly in SRIOV related use cases, so we add it here only
3866          * if it's not already set.
3867          */
3868         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3869                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3870                         SPE_HDR_CONN_TYPE;
3871                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3872                          SPE_HDR_FUNCTION_ID);
3873         } else {
3874                 type = cmd_type;
3875         }
3876
3877         spe->hdr.type = cpu_to_le16(type);
3878
3879         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3880         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3881
3882         /*
3883          * It's ok if the actual decrement is issued towards the memory
3884          * somewhere between the spin_lock and spin_unlock. Thus no
3885          * more explicit memory barrier is needed.
3886          */
3887         if (common)
3888                 atomic_dec(&bp->eq_spq_left);
3889         else
3890                 atomic_dec(&bp->cq_spq_left);
3891
3892         DP(BNX2X_MSG_SP,
3893            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3894            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3895            (u32)(U64_LO(bp->spq_mapping) +
3896            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3897            HW_CID(bp, cid), data_hi, data_lo, type,
3898            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3899
3900         bnx2x_sp_prod_update(bp);
3901         spin_unlock_bh(&bp->spq_lock);
3902         return 0;
3903 }
3904
3905 /* acquire split MCP access lock register */
3906 static int bnx2x_acquire_alr(struct bnx2x *bp)
3907 {
3908         u32 j, val;
3909         int rc = 0;
3910
3911         might_sleep();
3912         for (j = 0; j < 1000; j++) {
3913                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3914                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3915                 if (val & MCPR_ACCESS_LOCK_LOCK)
3916                         break;
3917
3918                 usleep_range(5000, 10000);
3919         }
3920         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3921                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3922                 rc = -EBUSY;
3923         }
3924
3925         return rc;
3926 }
3927
3928 /* release split MCP access lock register */
3929 static void bnx2x_release_alr(struct bnx2x *bp)
3930 {
3931         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3932 }
3933
3934 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3935 #define BNX2X_DEF_SB_IDX        0x0002
3936
3937 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3938 {
3939         struct host_sp_status_block *def_sb = bp->def_status_blk;
3940         u16 rc = 0;
3941
3942         barrier(); /* status block is written to by the chip */
3943         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3944                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3945                 rc |= BNX2X_DEF_SB_ATT_IDX;
3946         }
3947
3948         if (bp->def_idx != def_sb->sp_sb.running_index) {
3949                 bp->def_idx = def_sb->sp_sb.running_index;
3950                 rc |= BNX2X_DEF_SB_IDX;
3951         }
3952
3953         /* Do not reorder: indices reading should complete before handling */
3954         barrier();
3955         return rc;
3956 }
3957
3958 /*
3959  * slow path service functions
3960  */
3961
3962 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3963 {
3964         int port = BP_PORT(bp);
3965         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3966                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3967         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3968                                        NIG_REG_MASK_INTERRUPT_PORT0;
3969         u32 aeu_mask;
3970         u32 nig_mask = 0;
3971         u32 reg_addr;
3972
3973         if (bp->attn_state & asserted)
3974                 BNX2X_ERR("IGU ERROR\n");
3975
3976         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3977         aeu_mask = REG_RD(bp, aeu_addr);
3978
3979         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3980            aeu_mask, asserted);
3981         aeu_mask &= ~(asserted & 0x3ff);
3982         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3983
3984         REG_WR(bp, aeu_addr, aeu_mask);
3985         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3986
3987         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3988         bp->attn_state |= asserted;
3989         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3990
3991         if (asserted & ATTN_HARD_WIRED_MASK) {
3992                 if (asserted & ATTN_NIG_FOR_FUNC) {
3993
3994                         bnx2x_acquire_phy_lock(bp);
3995
3996                         /* save nig interrupt mask */
3997                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3998
3999                         /* If nig_mask is not set, no need to call the update
4000                          * function.
4001                          */
4002                         if (nig_mask) {
4003                                 REG_WR(bp, nig_int_mask_addr, 0);
4004
4005                                 bnx2x_link_attn(bp);
4006                         }
4007
4008                         /* handle unicore attn? */
4009                 }
4010                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4011                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4012
4013                 if (asserted & GPIO_2_FUNC)
4014                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4015
4016                 if (asserted & GPIO_3_FUNC)
4017                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4018
4019                 if (asserted & GPIO_4_FUNC)
4020                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4021
4022                 if (port == 0) {
4023                         if (asserted & ATTN_GENERAL_ATTN_1) {
4024                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4025                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4026                         }
4027                         if (asserted & ATTN_GENERAL_ATTN_2) {
4028                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4029                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4030                         }
4031                         if (asserted & ATTN_GENERAL_ATTN_3) {
4032                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4033                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4034                         }
4035                 } else {
4036                         if (asserted & ATTN_GENERAL_ATTN_4) {
4037                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4038                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4039                         }
4040                         if (asserted & ATTN_GENERAL_ATTN_5) {
4041                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4042                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4043                         }
4044                         if (asserted & ATTN_GENERAL_ATTN_6) {
4045                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4046                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4047                         }
4048                 }
4049
4050         } /* if hardwired */
4051
4052         if (bp->common.int_block == INT_BLOCK_HC)
4053                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4054                             COMMAND_REG_ATTN_BITS_SET);
4055         else
4056                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4057
4058         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4059            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4060         REG_WR(bp, reg_addr, asserted);
4061
4062         /* now set back the mask */
4063         if (asserted & ATTN_NIG_FOR_FUNC) {
4064                 /* Verify that IGU ack through BAR was written before restoring
4065                  * NIG mask. This loop should exit after 2-3 iterations max.
4066                  */
4067                 if (bp->common.int_block != INT_BLOCK_HC) {
4068                         u32 cnt = 0, igu_acked;
4069                         do {
4070                                 igu_acked = REG_RD(bp,
4071                                                    IGU_REG_ATTENTION_ACK_BITS);
4072                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4073                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4074                         if (!igu_acked)
4075                                 DP(NETIF_MSG_HW,
4076                                    "Failed to verify IGU ack on time\n");
4077                         barrier();
4078                 }
4079                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4080                 bnx2x_release_phy_lock(bp);
4081         }
4082 }
4083
4084 static void bnx2x_fan_failure(struct bnx2x *bp)
4085 {
4086         int port = BP_PORT(bp);
4087         u32 ext_phy_config;
4088         /* mark the failure */
4089         ext_phy_config =
4090                 SHMEM_RD(bp,
4091                          dev_info.port_hw_config[port].external_phy_config);
4092
4093         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4094         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4095         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4096                  ext_phy_config);
4097
4098         /* log the failure */
4099         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4100                             "Please contact OEM Support for assistance\n");
4101
4102         /* Schedule device reset (unload)
4103          * This is due to some boards consuming sufficient power when driver is
4104          * up to overheat if fan fails.
4105          */
4106         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4107 }
4108
4109 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4110 {
4111         int port = BP_PORT(bp);
4112         int reg_offset;
4113         u32 val;
4114
4115         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4116                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4117
4118         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4119
4120                 val = REG_RD(bp, reg_offset);
4121                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4122                 REG_WR(bp, reg_offset, val);
4123
4124                 BNX2X_ERR("SPIO5 hw attention\n");
4125
4126                 /* Fan failure attention */
4127                 bnx2x_hw_reset_phy(&bp->link_params);
4128                 bnx2x_fan_failure(bp);
4129         }
4130
4131         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4132                 bnx2x_acquire_phy_lock(bp);
4133                 bnx2x_handle_module_detect_int(&bp->link_params);
4134                 bnx2x_release_phy_lock(bp);
4135         }
4136
4137         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4138
4139                 val = REG_RD(bp, reg_offset);
4140                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4141                 REG_WR(bp, reg_offset, val);
4142
4143                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4144                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4145                 bnx2x_panic();
4146         }
4147 }
4148
4149 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4150 {
4151         u32 val;
4152
4153         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4154
4155                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4156                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4157                 /* DORQ discard attention */
4158                 if (val & 0x2)
4159                         BNX2X_ERR("FATAL error from DORQ\n");
4160         }
4161
4162         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4163
4164                 int port = BP_PORT(bp);
4165                 int reg_offset;
4166
4167                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4168                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4169
4170                 val = REG_RD(bp, reg_offset);
4171                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4172                 REG_WR(bp, reg_offset, val);
4173
4174                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4175                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4176                 bnx2x_panic();
4177         }
4178 }
4179
4180 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4181 {
4182         u32 val;
4183
4184         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4185
4186                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4187                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4188                 /* CFC error attention */
4189                 if (val & 0x2)
4190                         BNX2X_ERR("FATAL error from CFC\n");
4191         }
4192
4193         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4194                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4195                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4196                 /* RQ_USDMDP_FIFO_OVERFLOW */
4197                 if (val & 0x18000)
4198                         BNX2X_ERR("FATAL error from PXP\n");
4199
4200                 if (!CHIP_IS_E1x(bp)) {
4201                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4202                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4203                 }
4204         }
4205
4206         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4207
4208                 int port = BP_PORT(bp);
4209                 int reg_offset;
4210
4211                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4212                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4213
4214                 val = REG_RD(bp, reg_offset);
4215                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4216                 REG_WR(bp, reg_offset, val);
4217
4218                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4219                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4220                 bnx2x_panic();
4221         }
4222 }
4223
4224 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4225 {
4226         u32 val;
4227
4228         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4229
4230                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4231                         int func = BP_FUNC(bp);
4232
4233                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4234                         bnx2x_read_mf_cfg(bp);
4235                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4236                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4237                         val = SHMEM_RD(bp,
4238                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4239
4240                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4241                                    DRV_STATUS_OEM_EVENT_MASK))
4242                                 bnx2x_oem_event(bp,
4243                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4244                                                 DRV_STATUS_OEM_EVENT_MASK)));
4245
4246                         if (val & DRV_STATUS_SET_MF_BW)
4247                                 bnx2x_set_mf_bw(bp);
4248
4249                         if (val & DRV_STATUS_DRV_INFO_REQ)
4250                                 bnx2x_handle_drv_info_req(bp);
4251
4252                         if (val & DRV_STATUS_VF_DISABLED)
4253                                 bnx2x_schedule_iov_task(bp,
4254                                                         BNX2X_IOV_HANDLE_FLR);
4255
4256                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4257                                 bnx2x_pmf_update(bp);
4258
4259                         if (bp->port.pmf &&
4260                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4261                                 bp->dcbx_enabled > 0)
4262                                 /* start dcbx state machine */
4263                                 bnx2x_dcbx_set_params(bp,
4264                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4265                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4266                                 bnx2x_handle_afex_cmd(bp,
4267                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4268                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4269                                 bnx2x_handle_eee_event(bp);
4270
4271                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4272                                 bnx2x_handle_update_svid_cmd(bp);
4273
4274                         if (bp->link_vars.periodic_flags &
4275                             PERIODIC_FLAGS_LINK_EVENT) {
4276                                 /*  sync with link */
4277                                 bnx2x_acquire_phy_lock(bp);
4278                                 bp->link_vars.periodic_flags &=
4279                                         ~PERIODIC_FLAGS_LINK_EVENT;
4280                                 bnx2x_release_phy_lock(bp);
4281                                 if (IS_MF(bp))
4282                                         bnx2x_link_sync_notify(bp);
4283                                 bnx2x_link_report(bp);
4284                         }
4285                         /* Always call it here: bnx2x_link_report() will
4286                          * prevent the link indication duplication.
4287                          */
4288                         bnx2x__link_status_update(bp);
4289                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4290
4291                         BNX2X_ERR("MC assert!\n");
4292                         bnx2x_mc_assert(bp);
4293                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4294                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4295                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4296                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4297                         bnx2x_panic();
4298
4299                 } else if (attn & BNX2X_MCP_ASSERT) {
4300
4301                         BNX2X_ERR("MCP assert!\n");
4302                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4303                         bnx2x_fw_dump(bp);
4304
4305                 } else
4306                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4307         }
4308
4309         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4310                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4311                 if (attn & BNX2X_GRC_TIMEOUT) {
4312                         val = CHIP_IS_E1(bp) ? 0 :
4313                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4314                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4315                 }
4316                 if (attn & BNX2X_GRC_RSV) {
4317                         val = CHIP_IS_E1(bp) ? 0 :
4318                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4319                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4320                 }
4321                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4322         }
4323 }
4324
4325 /*
4326  * Bits map:
4327  * 0-7   - Engine0 load counter.
4328  * 8-15  - Engine1 load counter.
4329  * 16    - Engine0 RESET_IN_PROGRESS bit.
4330  * 17    - Engine1 RESET_IN_PROGRESS bit.
4331  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4332  *         on the engine
4333  * 19    - Engine1 ONE_IS_LOADED.
4334  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4335  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4336  *         just the one belonging to its engine).
4337  *
4338  */
4339 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4340
4341 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4342 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4343 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4344 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4345 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4346 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4347 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4348
4349 /*
4350  * Set the GLOBAL_RESET bit.
4351  *
4352  * Should be run under rtnl lock
4353  */
4354 void bnx2x_set_reset_global(struct bnx2x *bp)
4355 {
4356         u32 val;
4357         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4358         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4359         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4360         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4361 }
4362
4363 /*
4364  * Clear the GLOBAL_RESET bit.
4365  *
4366  * Should be run under rtnl lock
4367  */
4368 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4369 {
4370         u32 val;
4371         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4372         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4373         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4374         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4375 }
4376
4377 /*
4378  * Checks the GLOBAL_RESET bit.
4379  *
4380  * should be run under rtnl lock
4381  */
4382 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4383 {
4384         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4385
4386         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4387         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4388 }
4389
4390 /*
4391  * Clear RESET_IN_PROGRESS bit for the current engine.
4392  *
4393  * Should be run under rtnl lock
4394  */
4395 static void bnx2x_set_reset_done(struct bnx2x *bp)
4396 {
4397         u32 val;
4398         u32 bit = BP_PATH(bp) ?
4399                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4400         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4401         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4402
4403         /* Clear the bit */
4404         val &= ~bit;
4405         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4406
4407         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4408 }
4409
4410 /*
4411  * Set RESET_IN_PROGRESS for the current engine.
4412  *
4413  * should be run under rtnl lock
4414  */
4415 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4416 {
4417         u32 val;
4418         u32 bit = BP_PATH(bp) ?
4419                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4420         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4421         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4422
4423         /* Set the bit */
4424         val |= bit;
4425         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4426         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4427 }
4428
4429 /*
4430  * Checks the RESET_IN_PROGRESS bit for the given engine.
4431  * should be run under rtnl lock
4432  */
4433 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4434 {
4435         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4436         u32 bit = engine ?
4437                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4438
4439         /* return false if bit is set */
4440         return (val & bit) ? false : true;
4441 }
4442
4443 /*
4444  * set pf load for the current pf.
4445  *
4446  * should be run under rtnl lock
4447  */
4448 void bnx2x_set_pf_load(struct bnx2x *bp)
4449 {
4450         u32 val1, val;
4451         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4452                              BNX2X_PATH0_LOAD_CNT_MASK;
4453         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4454                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4455
4456         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4457         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4458
4459         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4460
4461         /* get the current counter value */
4462         val1 = (val & mask) >> shift;
4463
4464         /* set bit of that PF */
4465         val1 |= (1 << bp->pf_num);
4466
4467         /* clear the old value */
4468         val &= ~mask;
4469
4470         /* set the new one */
4471         val |= ((val1 << shift) & mask);
4472
4473         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4474         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4475 }
4476
4477 /**
4478  * bnx2x_clear_pf_load - clear pf load mark
4479  *
4480  * @bp:         driver handle
4481  *
4482  * Should be run under rtnl lock.
4483  * Decrements the load counter for the current engine. Returns
4484  * whether other functions are still loaded
4485  */
4486 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4487 {
4488         u32 val1, val;
4489         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4490                              BNX2X_PATH0_LOAD_CNT_MASK;
4491         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4492                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4493
4494         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4495         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4496         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4497
4498         /* get the current counter value */
4499         val1 = (val & mask) >> shift;
4500
4501         /* clear bit of that PF */
4502         val1 &= ~(1 << bp->pf_num);
4503
4504         /* clear the old value */
4505         val &= ~mask;
4506
4507         /* set the new one */
4508         val |= ((val1 << shift) & mask);
4509
4510         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4511         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4512         return val1 != 0;
4513 }
4514
4515 /*
4516  * Read the load status for the current engine.
4517  *
4518  * should be run under rtnl lock
4519  */
4520 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4521 {
4522         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4523                              BNX2X_PATH0_LOAD_CNT_MASK);
4524         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4525                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4526         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4527
4528         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4529
4530         val = (val & mask) >> shift;
4531
4532         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4533            engine, val);
4534
4535         return val != 0;
4536 }
4537
4538 static void _print_parity(struct bnx2x *bp, u32 reg)
4539 {
4540         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4541 }
4542
4543 static void _print_next_block(int idx, const char *blk)
4544 {
4545         pr_cont("%s%s", idx ? ", " : "", blk);
4546 }
4547
4548 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4549                                             int *par_num, bool print)
4550 {
4551         u32 cur_bit;
4552         bool res;
4553         int i;
4554
4555         res = false;
4556
4557         for (i = 0; sig; i++) {
4558                 cur_bit = (0x1UL << i);
4559                 if (sig & cur_bit) {
4560                         res |= true; /* Each bit is real error! */
4561
4562                         if (print) {
4563                                 switch (cur_bit) {
4564                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4565                                         _print_next_block((*par_num)++, "BRB");
4566                                         _print_parity(bp,
4567                                                       BRB1_REG_BRB1_PRTY_STS);
4568                                         break;
4569                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4570                                         _print_next_block((*par_num)++,
4571                                                           "PARSER");
4572                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4573                                         break;
4574                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4575                                         _print_next_block((*par_num)++, "TSDM");
4576                                         _print_parity(bp,
4577                                                       TSDM_REG_TSDM_PRTY_STS);
4578                                         break;
4579                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4580                                         _print_next_block((*par_num)++,
4581                                                           "SEARCHER");
4582                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4583                                         break;
4584                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4585                                         _print_next_block((*par_num)++, "TCM");
4586                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4587                                         break;
4588                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4589                                         _print_next_block((*par_num)++,
4590                                                           "TSEMI");
4591                                         _print_parity(bp,
4592                                                       TSEM_REG_TSEM_PRTY_STS_0);
4593                                         _print_parity(bp,
4594                                                       TSEM_REG_TSEM_PRTY_STS_1);
4595                                         break;
4596                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4597                                         _print_next_block((*par_num)++, "XPB");
4598                                         _print_parity(bp, GRCBASE_XPB +
4599                                                           PB_REG_PB_PRTY_STS);
4600                                         break;
4601                                 }
4602                         }
4603
4604                         /* Clear the bit */
4605                         sig &= ~cur_bit;
4606                 }
4607         }
4608
4609         return res;
4610 }
4611
4612 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4613                                             int *par_num, bool *global,
4614                                             bool print)
4615 {
4616         u32 cur_bit;
4617         bool res;
4618         int i;
4619
4620         res = false;
4621
4622         for (i = 0; sig; i++) {
4623                 cur_bit = (0x1UL << i);
4624                 if (sig & cur_bit) {
4625                         res |= true; /* Each bit is real error! */
4626                         switch (cur_bit) {
4627                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4628                                 if (print) {
4629                                         _print_next_block((*par_num)++, "PBF");
4630                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4631                                 }
4632                                 break;
4633                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4634                                 if (print) {
4635                                         _print_next_block((*par_num)++, "QM");
4636                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4637                                 }
4638                                 break;
4639                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4640                                 if (print) {
4641                                         _print_next_block((*par_num)++, "TM");
4642                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4643                                 }
4644                                 break;
4645                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4646                                 if (print) {
4647                                         _print_next_block((*par_num)++, "XSDM");
4648                                         _print_parity(bp,
4649                                                       XSDM_REG_XSDM_PRTY_STS);
4650                                 }
4651                                 break;
4652                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4653                                 if (print) {
4654                                         _print_next_block((*par_num)++, "XCM");
4655                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4656                                 }
4657                                 break;
4658                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4659                                 if (print) {
4660                                         _print_next_block((*par_num)++,
4661                                                           "XSEMI");
4662                                         _print_parity(bp,
4663                                                       XSEM_REG_XSEM_PRTY_STS_0);
4664                                         _print_parity(bp,
4665                                                       XSEM_REG_XSEM_PRTY_STS_1);
4666                                 }
4667                                 break;
4668                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4669                                 if (print) {
4670                                         _print_next_block((*par_num)++,
4671                                                           "DOORBELLQ");
4672                                         _print_parity(bp,
4673                                                       DORQ_REG_DORQ_PRTY_STS);
4674                                 }
4675                                 break;
4676                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4677                                 if (print) {
4678                                         _print_next_block((*par_num)++, "NIG");
4679                                         if (CHIP_IS_E1x(bp)) {
4680                                                 _print_parity(bp,
4681                                                         NIG_REG_NIG_PRTY_STS);
4682                                         } else {
4683                                                 _print_parity(bp,
4684                                                         NIG_REG_NIG_PRTY_STS_0);
4685                                                 _print_parity(bp,
4686                                                         NIG_REG_NIG_PRTY_STS_1);
4687                                         }
4688                                 }
4689                                 break;
4690                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4691                                 if (print)
4692                                         _print_next_block((*par_num)++,
4693                                                           "VAUX PCI CORE");
4694                                 *global = true;
4695                                 break;
4696                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4697                                 if (print) {
4698                                         _print_next_block((*par_num)++,
4699                                                           "DEBUG");
4700                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4701                                 }
4702                                 break;
4703                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4704                                 if (print) {
4705                                         _print_next_block((*par_num)++, "USDM");
4706                                         _print_parity(bp,
4707                                                       USDM_REG_USDM_PRTY_STS);
4708                                 }
4709                                 break;
4710                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4711                                 if (print) {
4712                                         _print_next_block((*par_num)++, "UCM");
4713                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4714                                 }
4715                                 break;
4716                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4717                                 if (print) {
4718                                         _print_next_block((*par_num)++,
4719                                                           "USEMI");
4720                                         _print_parity(bp,
4721                                                       USEM_REG_USEM_PRTY_STS_0);
4722                                         _print_parity(bp,
4723                                                       USEM_REG_USEM_PRTY_STS_1);
4724                                 }
4725                                 break;
4726                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4727                                 if (print) {
4728                                         _print_next_block((*par_num)++, "UPB");
4729                                         _print_parity(bp, GRCBASE_UPB +
4730                                                           PB_REG_PB_PRTY_STS);
4731                                 }
4732                                 break;
4733                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4734                                 if (print) {
4735                                         _print_next_block((*par_num)++, "CSDM");
4736                                         _print_parity(bp,
4737                                                       CSDM_REG_CSDM_PRTY_STS);
4738                                 }
4739                                 break;
4740                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4741                                 if (print) {
4742                                         _print_next_block((*par_num)++, "CCM");
4743                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4744                                 }
4745                                 break;
4746                         }
4747
4748                         /* Clear the bit */
4749                         sig &= ~cur_bit;
4750                 }
4751         }
4752
4753         return res;
4754 }
4755
4756 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4757                                             int *par_num, bool print)
4758 {
4759         u32 cur_bit;
4760         bool res;
4761         int i;
4762
4763         res = false;
4764
4765         for (i = 0; sig; i++) {
4766                 cur_bit = (0x1UL << i);
4767                 if (sig & cur_bit) {
4768                         res = true; /* Each bit is real error! */
4769                         if (print) {
4770                                 switch (cur_bit) {
4771                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4772                                         _print_next_block((*par_num)++,
4773                                                           "CSEMI");
4774                                         _print_parity(bp,
4775                                                       CSEM_REG_CSEM_PRTY_STS_0);
4776                                         _print_parity(bp,
4777                                                       CSEM_REG_CSEM_PRTY_STS_1);
4778                                         break;
4779                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4780                                         _print_next_block((*par_num)++, "PXP");
4781                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4782                                         _print_parity(bp,
4783                                                       PXP2_REG_PXP2_PRTY_STS_0);
4784                                         _print_parity(bp,
4785                                                       PXP2_REG_PXP2_PRTY_STS_1);
4786                                         break;
4787                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4788                                         _print_next_block((*par_num)++,
4789                                                           "PXPPCICLOCKCLIENT");
4790                                         break;
4791                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4792                                         _print_next_block((*par_num)++, "CFC");
4793                                         _print_parity(bp,
4794                                                       CFC_REG_CFC_PRTY_STS);
4795                                         break;
4796                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4797                                         _print_next_block((*par_num)++, "CDU");
4798                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4799                                         break;
4800                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4801                                         _print_next_block((*par_num)++, "DMAE");
4802                                         _print_parity(bp,
4803                                                       DMAE_REG_DMAE_PRTY_STS);
4804                                         break;
4805                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4806                                         _print_next_block((*par_num)++, "IGU");
4807                                         if (CHIP_IS_E1x(bp))
4808                                                 _print_parity(bp,
4809                                                         HC_REG_HC_PRTY_STS);
4810                                         else
4811                                                 _print_parity(bp,
4812                                                         IGU_REG_IGU_PRTY_STS);
4813                                         break;
4814                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4815                                         _print_next_block((*par_num)++, "MISC");
4816                                         _print_parity(bp,
4817                                                       MISC_REG_MISC_PRTY_STS);
4818                                         break;
4819                                 }
4820                         }
4821
4822                         /* Clear the bit */
4823                         sig &= ~cur_bit;
4824                 }
4825         }
4826
4827         return res;
4828 }
4829
4830 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4831                                             int *par_num, bool *global,
4832                                             bool print)
4833 {
4834         bool res = false;
4835         u32 cur_bit;
4836         int i;
4837
4838         for (i = 0; sig; i++) {
4839                 cur_bit = (0x1UL << i);
4840                 if (sig & cur_bit) {
4841                         switch (cur_bit) {
4842                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4843                                 if (print)
4844                                         _print_next_block((*par_num)++,
4845                                                           "MCP ROM");
4846                                 *global = true;
4847                                 res = true;
4848                                 break;
4849                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4850                                 if (print)
4851                                         _print_next_block((*par_num)++,
4852                                                           "MCP UMP RX");
4853                                 *global = true;
4854                                 res = true;
4855                                 break;
4856                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4857                                 if (print)
4858                                         _print_next_block((*par_num)++,
4859                                                           "MCP UMP TX");
4860                                 *global = true;
4861                                 res = true;
4862                                 break;
4863                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4864                                 if (print)
4865                                         _print_next_block((*par_num)++,
4866                                                           "MCP SCPAD");
4867                                 /* clear latched SCPAD PATIRY from MCP */
4868                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4869                                        1UL << 10);
4870                                 break;
4871                         }
4872
4873                         /* Clear the bit */
4874                         sig &= ~cur_bit;
4875                 }
4876         }
4877
4878         return res;
4879 }
4880
4881 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4882                                             int *par_num, bool print)
4883 {
4884         u32 cur_bit;
4885         bool res;
4886         int i;
4887
4888         res = false;
4889
4890         for (i = 0; sig; i++) {
4891                 cur_bit = (0x1UL << i);
4892                 if (sig & cur_bit) {
4893                         res = true; /* Each bit is real error! */
4894                         if (print) {
4895                                 switch (cur_bit) {
4896                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4897                                         _print_next_block((*par_num)++,
4898                                                           "PGLUE_B");
4899                                         _print_parity(bp,
4900                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4901                                         break;
4902                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4903                                         _print_next_block((*par_num)++, "ATC");
4904                                         _print_parity(bp,
4905                                                       ATC_REG_ATC_PRTY_STS);
4906                                         break;
4907                                 }
4908                         }
4909                         /* Clear the bit */
4910                         sig &= ~cur_bit;
4911                 }
4912         }
4913
4914         return res;
4915 }
4916
4917 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4918                               u32 *sig)
4919 {
4920         bool res = false;
4921
4922         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4923             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4924             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4925             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4926             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4927                 int par_num = 0;
4928                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4929                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4930                           sig[0] & HW_PRTY_ASSERT_SET_0,
4931                           sig[1] & HW_PRTY_ASSERT_SET_1,
4932                           sig[2] & HW_PRTY_ASSERT_SET_2,
4933                           sig[3] & HW_PRTY_ASSERT_SET_3,
4934                           sig[4] & HW_PRTY_ASSERT_SET_4);
4935                 if (print)
4936                         netdev_err(bp->dev,
4937                                    "Parity errors detected in blocks: ");
4938                 res |= bnx2x_check_blocks_with_parity0(bp,
4939                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4940                 res |= bnx2x_check_blocks_with_parity1(bp,
4941                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4942                 res |= bnx2x_check_blocks_with_parity2(bp,
4943                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4944                 res |= bnx2x_check_blocks_with_parity3(bp,
4945                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4946                 res |= bnx2x_check_blocks_with_parity4(bp,
4947                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4948
4949                 if (print)
4950                         pr_cont("\n");
4951         }
4952
4953         return res;
4954 }
4955
4956 /**
4957  * bnx2x_chk_parity_attn - checks for parity attentions.
4958  *
4959  * @bp:         driver handle
4960  * @global:     true if there was a global attention
4961  * @print:      show parity attention in syslog
4962  */
4963 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4964 {
4965         struct attn_route attn = { {0} };
4966         int port = BP_PORT(bp);
4967
4968         attn.sig[0] = REG_RD(bp,
4969                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4970                              port*4);
4971         attn.sig[1] = REG_RD(bp,
4972                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4973                              port*4);
4974         attn.sig[2] = REG_RD(bp,
4975                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4976                              port*4);
4977         attn.sig[3] = REG_RD(bp,
4978                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4979                              port*4);
4980         /* Since MCP attentions can't be disabled inside the block, we need to
4981          * read AEU registers to see whether they're currently disabled
4982          */
4983         attn.sig[3] &= ((REG_RD(bp,
4984                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4985                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4986                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4987                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4988
4989         if (!CHIP_IS_E1x(bp))
4990                 attn.sig[4] = REG_RD(bp,
4991                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4992                                      port*4);
4993
4994         return bnx2x_parity_attn(bp, global, print, attn.sig);
4995 }
4996
4997 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4998 {
4999         u32 val;
5000         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5001
5002                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5003                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5004                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5005                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5006                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5007                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5008                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5009                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5010                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5011                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5012                 if (val &
5013                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5014                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5015                 if (val &
5016                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5017                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5018                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5019                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5020                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5021                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5022                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5023                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5024         }
5025         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5026                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5027                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5028                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5029                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5030                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5031                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5032                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5033                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5034                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5035                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5036                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5037                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5038                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5039                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5040         }
5041
5042         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5043                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5044                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5045                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5046                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5047         }
5048 }
5049
5050 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5051 {
5052         struct attn_route attn, *group_mask;
5053         int port = BP_PORT(bp);
5054         int index;
5055         u32 reg_addr;
5056         u32 val;
5057         u32 aeu_mask;
5058         bool global = false;
5059
5060         /* need to take HW lock because MCP or other port might also
5061            try to handle this event */
5062         bnx2x_acquire_alr(bp);
5063
5064         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5065 #ifndef BNX2X_STOP_ON_ERROR
5066                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5067                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5068                 /* Disable HW interrupts */
5069                 bnx2x_int_disable(bp);
5070                 /* In case of parity errors don't handle attentions so that
5071                  * other function would "see" parity errors.
5072                  */
5073 #else
5074                 bnx2x_panic();
5075 #endif
5076                 bnx2x_release_alr(bp);
5077                 return;
5078         }
5079
5080         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5081         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5082         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5083         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5084         if (!CHIP_IS_E1x(bp))
5085                 attn.sig[4] =
5086                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5087         else
5088                 attn.sig[4] = 0;
5089
5090         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5091            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5092
5093         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5094                 if (deasserted & (1 << index)) {
5095                         group_mask = &bp->attn_group[index];
5096
5097                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5098                            index,
5099                            group_mask->sig[0], group_mask->sig[1],
5100                            group_mask->sig[2], group_mask->sig[3],
5101                            group_mask->sig[4]);
5102
5103                         bnx2x_attn_int_deasserted4(bp,
5104                                         attn.sig[4] & group_mask->sig[4]);
5105                         bnx2x_attn_int_deasserted3(bp,
5106                                         attn.sig[3] & group_mask->sig[3]);
5107                         bnx2x_attn_int_deasserted1(bp,
5108                                         attn.sig[1] & group_mask->sig[1]);
5109                         bnx2x_attn_int_deasserted2(bp,
5110                                         attn.sig[2] & group_mask->sig[2]);
5111                         bnx2x_attn_int_deasserted0(bp,
5112                                         attn.sig[0] & group_mask->sig[0]);
5113                 }
5114         }
5115
5116         bnx2x_release_alr(bp);
5117
5118         if (bp->common.int_block == INT_BLOCK_HC)
5119                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5120                             COMMAND_REG_ATTN_BITS_CLR);
5121         else
5122                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5123
5124         val = ~deasserted;
5125         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5126            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5127         REG_WR(bp, reg_addr, val);
5128
5129         if (~bp->attn_state & deasserted)
5130                 BNX2X_ERR("IGU ERROR\n");
5131
5132         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5133                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5134
5135         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5136         aeu_mask = REG_RD(bp, reg_addr);
5137
5138         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5139            aeu_mask, deasserted);
5140         aeu_mask |= (deasserted & 0x3ff);
5141         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5142
5143         REG_WR(bp, reg_addr, aeu_mask);
5144         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5145
5146         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5147         bp->attn_state &= ~deasserted;
5148         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5149 }
5150
5151 static void bnx2x_attn_int(struct bnx2x *bp)
5152 {
5153         /* read local copy of bits */
5154         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5155                                                                 attn_bits);
5156         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5157                                                                 attn_bits_ack);
5158         u32 attn_state = bp->attn_state;
5159
5160         /* look for changed bits */
5161         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5162         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5163
5164         DP(NETIF_MSG_HW,
5165            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5166            attn_bits, attn_ack, asserted, deasserted);
5167
5168         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5169                 BNX2X_ERR("BAD attention state\n");
5170
5171         /* handle bits that were raised */
5172         if (asserted)
5173                 bnx2x_attn_int_asserted(bp, asserted);
5174
5175         if (deasserted)
5176                 bnx2x_attn_int_deasserted(bp, deasserted);
5177 }
5178
5179 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5180                       u16 index, u8 op, u8 update)
5181 {
5182         u32 igu_addr = bp->igu_base_addr;
5183         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5184         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5185                              igu_addr);
5186 }
5187
5188 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5189 {
5190         /* No memory barriers */
5191         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5192         mmiowb(); /* keep prod updates ordered */
5193 }
5194
5195 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5196                                       union event_ring_elem *elem)
5197 {
5198         u8 err = elem->message.error;
5199
5200         if (!bp->cnic_eth_dev.starting_cid  ||
5201             (cid < bp->cnic_eth_dev.starting_cid &&
5202             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5203                 return 1;
5204
5205         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5206
5207         if (unlikely(err)) {
5208
5209                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5210                           cid);
5211                 bnx2x_panic_dump(bp, false);
5212         }
5213         bnx2x_cnic_cfc_comp(bp, cid, err);
5214         return 0;
5215 }
5216
5217 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5218 {
5219         struct bnx2x_mcast_ramrod_params rparam;
5220         int rc;
5221
5222         memset(&rparam, 0, sizeof(rparam));
5223
5224         rparam.mcast_obj = &bp->mcast_obj;
5225
5226         netif_addr_lock_bh(bp->dev);
5227
5228         /* Clear pending state for the last command */
5229         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5230
5231         /* If there are pending mcast commands - send them */
5232         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5233                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5234                 if (rc < 0)
5235                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5236                                   rc);
5237         }
5238
5239         netif_addr_unlock_bh(bp->dev);
5240 }
5241
5242 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5243                                             union event_ring_elem *elem)
5244 {
5245         unsigned long ramrod_flags = 0;
5246         int rc = 0;
5247         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5248         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5249
5250         /* Always push next commands out, don't wait here */
5251         __set_bit(RAMROD_CONT, &ramrod_flags);
5252
5253         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5254                             >> BNX2X_SWCID_SHIFT) {
5255         case BNX2X_FILTER_MAC_PENDING:
5256                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5257                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5258                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5259                 else
5260                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5261
5262                 break;
5263         case BNX2X_FILTER_MCAST_PENDING:
5264                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5265                 /* This is only relevant for 57710 where multicast MACs are
5266                  * configured as unicast MACs using the same ramrod.
5267                  */
5268                 bnx2x_handle_mcast_eqe(bp);
5269                 return;
5270         default:
5271                 BNX2X_ERR("Unsupported classification command: %d\n",
5272                           elem->message.data.eth_event.echo);
5273                 return;
5274         }
5275
5276         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5277
5278         if (rc < 0)
5279                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5280         else if (rc > 0)
5281                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5282 }
5283
5284 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5285
5286 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5287 {
5288         netif_addr_lock_bh(bp->dev);
5289
5290         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5291
5292         /* Send rx_mode command again if was requested */
5293         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5294                 bnx2x_set_storm_rx_mode(bp);
5295         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5296                                     &bp->sp_state))
5297                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5298         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5299                                     &bp->sp_state))
5300                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5301
5302         netif_addr_unlock_bh(bp->dev);
5303 }
5304
5305 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5306                                               union event_ring_elem *elem)
5307 {
5308         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5309                 DP(BNX2X_MSG_SP,
5310                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5311                    elem->message.data.vif_list_event.func_bit_map);
5312                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5313                         elem->message.data.vif_list_event.func_bit_map);
5314         } else if (elem->message.data.vif_list_event.echo ==
5315                    VIF_LIST_RULE_SET) {
5316                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5317                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5318         }
5319 }
5320
5321 /* called with rtnl_lock */
5322 static void bnx2x_after_function_update(struct bnx2x *bp)
5323 {
5324         int q, rc;
5325         struct bnx2x_fastpath *fp;
5326         struct bnx2x_queue_state_params queue_params = {NULL};
5327         struct bnx2x_queue_update_params *q_update_params =
5328                 &queue_params.params.update;
5329
5330         /* Send Q update command with afex vlan removal values for all Qs */
5331         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5332
5333         /* set silent vlan removal values according to vlan mode */
5334         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5335                   &q_update_params->update_flags);
5336         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5337                   &q_update_params->update_flags);
5338         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5339
5340         /* in access mode mark mask and value are 0 to strip all vlans */
5341         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5342                 q_update_params->silent_removal_value = 0;
5343                 q_update_params->silent_removal_mask = 0;
5344         } else {
5345                 q_update_params->silent_removal_value =
5346                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5347                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5348         }
5349
5350         for_each_eth_queue(bp, q) {
5351                 /* Set the appropriate Queue object */
5352                 fp = &bp->fp[q];
5353                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5354
5355                 /* send the ramrod */
5356                 rc = bnx2x_queue_state_change(bp, &queue_params);
5357                 if (rc < 0)
5358                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5359                                   q);
5360         }
5361
5362         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5363                 fp = &bp->fp[FCOE_IDX(bp)];
5364                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5365
5366                 /* clear pending completion bit */
5367                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5368
5369                 /* mark latest Q bit */
5370                 smp_mb__before_atomic();
5371                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5372                 smp_mb__after_atomic();
5373
5374                 /* send Q update ramrod for FCoE Q */
5375                 rc = bnx2x_queue_state_change(bp, &queue_params);
5376                 if (rc < 0)
5377                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5378                                   q);
5379         } else {
5380                 /* If no FCoE ring - ACK MCP now */
5381                 bnx2x_link_report(bp);
5382                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5383         }
5384 }
5385
5386 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5387         struct bnx2x *bp, u32 cid)
5388 {
5389         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5390
5391         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5392                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5393         else
5394                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5395 }
5396
5397 static void bnx2x_eq_int(struct bnx2x *bp)
5398 {
5399         u16 hw_cons, sw_cons, sw_prod;
5400         union event_ring_elem *elem;
5401         u8 echo;
5402         u32 cid;
5403         u8 opcode;
5404         int rc, spqe_cnt = 0;
5405         struct bnx2x_queue_sp_obj *q_obj;
5406         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5407         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5408
5409         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5410
5411         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5412          * when we get the next-page we need to adjust so the loop
5413          * condition below will be met. The next element is the size of a
5414          * regular element and hence incrementing by 1
5415          */
5416         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5417                 hw_cons++;
5418
5419         /* This function may never run in parallel with itself for a
5420          * specific bp, thus there is no need in "paired" read memory
5421          * barrier here.
5422          */
5423         sw_cons = bp->eq_cons;
5424         sw_prod = bp->eq_prod;
5425
5426         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5427                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5428
5429         for (; sw_cons != hw_cons;
5430               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5431
5432                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5433
5434                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5435                 if (!rc) {
5436                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5437                            rc);
5438                         goto next_spqe;
5439                 }
5440
5441                 /* elem CID originates from FW; actually LE */
5442                 cid = SW_CID((__force __le32)
5443                              elem->message.data.cfc_del_event.cid);
5444                 opcode = elem->message.opcode;
5445
5446                 /* handle eq element */
5447                 switch (opcode) {
5448                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5449                         bnx2x_vf_mbx_schedule(bp,
5450                                               &elem->message.data.vf_pf_event);
5451                         continue;
5452
5453                 case EVENT_RING_OPCODE_STAT_QUERY:
5454                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5455                                "got statistics comp event %d\n",
5456                                bp->stats_comp++);
5457                         /* nothing to do with stats comp */
5458                         goto next_spqe;
5459
5460                 case EVENT_RING_OPCODE_CFC_DEL:
5461                         /* handle according to cid range */
5462                         /*
5463                          * we may want to verify here that the bp state is
5464                          * HALTING
5465                          */
5466                         DP(BNX2X_MSG_SP,
5467                            "got delete ramrod for MULTI[%d]\n", cid);
5468
5469                         if (CNIC_LOADED(bp) &&
5470                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5471                                 goto next_spqe;
5472
5473                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5474
5475                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5476                                 break;
5477
5478                         goto next_spqe;
5479
5480                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5481                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5482                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5483                         if (f_obj->complete_cmd(bp, f_obj,
5484                                                 BNX2X_F_CMD_TX_STOP))
5485                                 break;
5486                         goto next_spqe;
5487
5488                 case EVENT_RING_OPCODE_START_TRAFFIC:
5489                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5490                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5491                         if (f_obj->complete_cmd(bp, f_obj,
5492                                                 BNX2X_F_CMD_TX_START))
5493                                 break;
5494                         goto next_spqe;
5495
5496                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5497                         echo = elem->message.data.function_update_event.echo;
5498                         if (echo == SWITCH_UPDATE) {
5499                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5500                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5501                                 if (f_obj->complete_cmd(
5502                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5503                                         break;
5504
5505                         } else {
5506                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5507
5508                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5509                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5510                                 f_obj->complete_cmd(bp, f_obj,
5511                                                     BNX2X_F_CMD_AFEX_UPDATE);
5512
5513                                 /* We will perform the Queues update from
5514                                  * sp_rtnl task as all Queue SP operations
5515                                  * should run under rtnl_lock.
5516                                  */
5517                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5518                         }
5519
5520                         goto next_spqe;
5521
5522                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5523                         f_obj->complete_cmd(bp, f_obj,
5524                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5525                         bnx2x_after_afex_vif_lists(bp, elem);
5526                         goto next_spqe;
5527                 case EVENT_RING_OPCODE_FUNCTION_START:
5528                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5529                            "got FUNC_START ramrod\n");
5530                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5531                                 break;
5532
5533                         goto next_spqe;
5534
5535                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5536                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5537                            "got FUNC_STOP ramrod\n");
5538                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5539                                 break;
5540
5541                         goto next_spqe;
5542
5543                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5544                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5545                            "got set_timesync ramrod completion\n");
5546                         if (f_obj->complete_cmd(bp, f_obj,
5547                                                 BNX2X_F_CMD_SET_TIMESYNC))
5548                                 break;
5549                         goto next_spqe;
5550                 }
5551
5552                 switch (opcode | bp->state) {
5553                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5554                       BNX2X_STATE_OPEN):
5555                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5556                       BNX2X_STATE_OPENING_WAIT4_PORT):
5557                         cid = elem->message.data.eth_event.echo &
5558                                 BNX2X_SWCID_MASK;
5559                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5560                            cid);
5561                         rss_raw->clear_pending(rss_raw);
5562                         break;
5563
5564                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5565                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5566                 case (EVENT_RING_OPCODE_SET_MAC |
5567                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5568                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5569                       BNX2X_STATE_OPEN):
5570                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5571                       BNX2X_STATE_DIAG):
5572                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5573                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5574                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5575                         bnx2x_handle_classification_eqe(bp, elem);
5576                         break;
5577
5578                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5579                       BNX2X_STATE_OPEN):
5580                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5581                       BNX2X_STATE_DIAG):
5582                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5583                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5584                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5585                         bnx2x_handle_mcast_eqe(bp);
5586                         break;
5587
5588                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5589                       BNX2X_STATE_OPEN):
5590                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5591                       BNX2X_STATE_DIAG):
5592                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5593                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5594                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5595                         bnx2x_handle_rx_mode_eqe(bp);
5596                         break;
5597                 default:
5598                         /* unknown event log error and continue */
5599                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5600                                   elem->message.opcode, bp->state);
5601                 }
5602 next_spqe:
5603                 spqe_cnt++;
5604         } /* for */
5605
5606         smp_mb__before_atomic();
5607         atomic_add(spqe_cnt, &bp->eq_spq_left);
5608
5609         bp->eq_cons = sw_cons;
5610         bp->eq_prod = sw_prod;
5611         /* Make sure that above mem writes were issued towards the memory */
5612         smp_wmb();
5613
5614         /* update producer */
5615         bnx2x_update_eq_prod(bp, bp->eq_prod);
5616 }
5617
5618 static void bnx2x_sp_task(struct work_struct *work)
5619 {
5620         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5621
5622         DP(BNX2X_MSG_SP, "sp task invoked\n");
5623
5624         /* make sure the atomic interrupt_occurred has been written */
5625         smp_rmb();
5626         if (atomic_read(&bp->interrupt_occurred)) {
5627
5628                 /* what work needs to be performed? */
5629                 u16 status = bnx2x_update_dsb_idx(bp);
5630
5631                 DP(BNX2X_MSG_SP, "status %x\n", status);
5632                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5633                 atomic_set(&bp->interrupt_occurred, 0);
5634
5635                 /* HW attentions */
5636                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5637                         bnx2x_attn_int(bp);
5638                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5639                 }
5640
5641                 /* SP events: STAT_QUERY and others */
5642                 if (status & BNX2X_DEF_SB_IDX) {
5643                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5644
5645                 if (FCOE_INIT(bp) &&
5646                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5647                                 /* Prevent local bottom-halves from running as
5648                                  * we are going to change the local NAPI list.
5649                                  */
5650                                 local_bh_disable();
5651                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5652                                 local_bh_enable();
5653                         }
5654
5655                         /* Handle EQ completions */
5656                         bnx2x_eq_int(bp);
5657                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5658                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5659
5660                         status &= ~BNX2X_DEF_SB_IDX;
5661                 }
5662
5663                 /* if status is non zero then perhaps something went wrong */
5664                 if (unlikely(status))
5665                         DP(BNX2X_MSG_SP,
5666                            "got an unknown interrupt! (status 0x%x)\n", status);
5667
5668                 /* ack status block only if something was actually handled */
5669                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5670                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5671         }
5672
5673         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5674         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5675                                &bp->sp_state)) {
5676                 bnx2x_link_report(bp);
5677                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5678         }
5679 }
5680
5681 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5682 {
5683         struct net_device *dev = dev_instance;
5684         struct bnx2x *bp = netdev_priv(dev);
5685
5686         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5687                      IGU_INT_DISABLE, 0);
5688
5689 #ifdef BNX2X_STOP_ON_ERROR
5690         if (unlikely(bp->panic))
5691                 return IRQ_HANDLED;
5692 #endif
5693
5694         if (CNIC_LOADED(bp)) {
5695                 struct cnic_ops *c_ops;
5696
5697                 rcu_read_lock();
5698                 c_ops = rcu_dereference(bp->cnic_ops);
5699                 if (c_ops)
5700                         c_ops->cnic_handler(bp->cnic_data, NULL);
5701                 rcu_read_unlock();
5702         }
5703
5704         /* schedule sp task to perform default status block work, ack
5705          * attentions and enable interrupts.
5706          */
5707         bnx2x_schedule_sp_task(bp);
5708
5709         return IRQ_HANDLED;
5710 }
5711
5712 /* end of slow path */
5713
5714 void bnx2x_drv_pulse(struct bnx2x *bp)
5715 {
5716         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5717                  bp->fw_drv_pulse_wr_seq);
5718 }
5719
5720 static void bnx2x_timer(unsigned long data)
5721 {
5722         struct bnx2x *bp = (struct bnx2x *) data;
5723
5724         if (!netif_running(bp->dev))
5725                 return;
5726
5727         if (IS_PF(bp) &&
5728             !BP_NOMCP(bp)) {
5729                 int mb_idx = BP_FW_MB_IDX(bp);
5730                 u16 drv_pulse;
5731                 u16 mcp_pulse;
5732
5733                 ++bp->fw_drv_pulse_wr_seq;
5734                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5735                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5736                 bnx2x_drv_pulse(bp);
5737
5738                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5739                              MCP_PULSE_SEQ_MASK);
5740                 /* The delta between driver pulse and mcp response
5741                  * should not get too big. If the MFW is more than 5 pulses
5742                  * behind, we should worry about it enough to generate an error
5743                  * log.
5744                  */
5745                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5746                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5747                                   drv_pulse, mcp_pulse);
5748         }
5749
5750         if (bp->state == BNX2X_STATE_OPEN)
5751                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5752
5753         /* sample pf vf bulletin board for new posts from pf */
5754         if (IS_VF(bp))
5755                 bnx2x_timer_sriov(bp);
5756
5757         mod_timer(&bp->timer, jiffies + bp->current_interval);
5758 }
5759
5760 /* end of Statistics */
5761
5762 /* nic init */
5763
5764 /*
5765  * nic init service functions
5766  */
5767
5768 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5769 {
5770         u32 i;
5771         if (!(len%4) && !(addr%4))
5772                 for (i = 0; i < len; i += 4)
5773                         REG_WR(bp, addr + i, fill);
5774         else
5775                 for (i = 0; i < len; i++)
5776                         REG_WR8(bp, addr + i, fill);
5777 }
5778
5779 /* helper: writes FP SP data to FW - data_size in dwords */
5780 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5781                                 int fw_sb_id,
5782                                 u32 *sb_data_p,
5783                                 u32 data_size)
5784 {
5785         int index;
5786         for (index = 0; index < data_size; index++)
5787                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5788                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5789                         sizeof(u32)*index,
5790                         *(sb_data_p + index));
5791 }
5792
5793 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5794 {
5795         u32 *sb_data_p;
5796         u32 data_size = 0;
5797         struct hc_status_block_data_e2 sb_data_e2;
5798         struct hc_status_block_data_e1x sb_data_e1x;
5799
5800         /* disable the function first */
5801         if (!CHIP_IS_E1x(bp)) {
5802                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5803                 sb_data_e2.common.state = SB_DISABLED;
5804                 sb_data_e2.common.p_func.vf_valid = false;
5805                 sb_data_p = (u32 *)&sb_data_e2;
5806                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5807         } else {
5808                 memset(&sb_data_e1x, 0,
5809                        sizeof(struct hc_status_block_data_e1x));
5810                 sb_data_e1x.common.state = SB_DISABLED;
5811                 sb_data_e1x.common.p_func.vf_valid = false;
5812                 sb_data_p = (u32 *)&sb_data_e1x;
5813                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5814         }
5815         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5816
5817         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5818                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5819                         CSTORM_STATUS_BLOCK_SIZE);
5820         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5821                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5822                         CSTORM_SYNC_BLOCK_SIZE);
5823 }
5824
5825 /* helper:  writes SP SB data to FW */
5826 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5827                 struct hc_sp_status_block_data *sp_sb_data)
5828 {
5829         int func = BP_FUNC(bp);
5830         int i;
5831         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5832                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5833                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5834                         i*sizeof(u32),
5835                         *((u32 *)sp_sb_data + i));
5836 }
5837
5838 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5839 {
5840         int func = BP_FUNC(bp);
5841         struct hc_sp_status_block_data sp_sb_data;
5842         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5843
5844         sp_sb_data.state = SB_DISABLED;
5845         sp_sb_data.p_func.vf_valid = false;
5846
5847         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5848
5849         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5850                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5851                         CSTORM_SP_STATUS_BLOCK_SIZE);
5852         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5853                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5854                         CSTORM_SP_SYNC_BLOCK_SIZE);
5855 }
5856
5857 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5858                                            int igu_sb_id, int igu_seg_id)
5859 {
5860         hc_sm->igu_sb_id = igu_sb_id;
5861         hc_sm->igu_seg_id = igu_seg_id;
5862         hc_sm->timer_value = 0xFF;
5863         hc_sm->time_to_expire = 0xFFFFFFFF;
5864 }
5865
5866 /* allocates state machine ids. */
5867 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5868 {
5869         /* zero out state machine indices */
5870         /* rx indices */
5871         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5872
5873         /* tx indices */
5874         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5875         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5876         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5877         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5878
5879         /* map indices */
5880         /* rx indices */
5881         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5882                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5883
5884         /* tx indices */
5885         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5886                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5887         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5888                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5889         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5890                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5891         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5892                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5893 }
5894
5895 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5896                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5897 {
5898         int igu_seg_id;
5899
5900         struct hc_status_block_data_e2 sb_data_e2;
5901         struct hc_status_block_data_e1x sb_data_e1x;
5902         struct hc_status_block_sm  *hc_sm_p;
5903         int data_size;
5904         u32 *sb_data_p;
5905
5906         if (CHIP_INT_MODE_IS_BC(bp))
5907                 igu_seg_id = HC_SEG_ACCESS_NORM;
5908         else
5909                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5910
5911         bnx2x_zero_fp_sb(bp, fw_sb_id);
5912
5913         if (!CHIP_IS_E1x(bp)) {
5914                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5915                 sb_data_e2.common.state = SB_ENABLED;
5916                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5917                 sb_data_e2.common.p_func.vf_id = vfid;
5918                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5919                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5920                 sb_data_e2.common.same_igu_sb_1b = true;
5921                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5922                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5923                 hc_sm_p = sb_data_e2.common.state_machine;
5924                 sb_data_p = (u32 *)&sb_data_e2;
5925                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5926                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5927         } else {
5928                 memset(&sb_data_e1x, 0,
5929                        sizeof(struct hc_status_block_data_e1x));
5930                 sb_data_e1x.common.state = SB_ENABLED;
5931                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5932                 sb_data_e1x.common.p_func.vf_id = 0xff;
5933                 sb_data_e1x.common.p_func.vf_valid = false;
5934                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5935                 sb_data_e1x.common.same_igu_sb_1b = true;
5936                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5937                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5938                 hc_sm_p = sb_data_e1x.common.state_machine;
5939                 sb_data_p = (u32 *)&sb_data_e1x;
5940                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5941                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5942         }
5943
5944         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5945                                        igu_sb_id, igu_seg_id);
5946         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5947                                        igu_sb_id, igu_seg_id);
5948
5949         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5950
5951         /* write indices to HW - PCI guarantees endianity of regpairs */
5952         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5953 }
5954
5955 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5956                                      u16 tx_usec, u16 rx_usec)
5957 {
5958         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5959                                     false, rx_usec);
5960         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5961                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5962                                        tx_usec);
5963         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5964                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5965                                        tx_usec);
5966         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5967                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5968                                        tx_usec);
5969 }
5970
5971 static void bnx2x_init_def_sb(struct bnx2x *bp)
5972 {
5973         struct host_sp_status_block *def_sb = bp->def_status_blk;
5974         dma_addr_t mapping = bp->def_status_blk_mapping;
5975         int igu_sp_sb_index;
5976         int igu_seg_id;
5977         int port = BP_PORT(bp);
5978         int func = BP_FUNC(bp);
5979         int reg_offset, reg_offset_en5;
5980         u64 section;
5981         int index;
5982         struct hc_sp_status_block_data sp_sb_data;
5983         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5984
5985         if (CHIP_INT_MODE_IS_BC(bp)) {
5986                 igu_sp_sb_index = DEF_SB_IGU_ID;
5987                 igu_seg_id = HC_SEG_ACCESS_DEF;
5988         } else {
5989                 igu_sp_sb_index = bp->igu_dsb_id;
5990                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5991         }
5992
5993         /* ATTN */
5994         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5995                                             atten_status_block);
5996         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5997
5998         bp->attn_state = 0;
5999
6000         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6001                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6002         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6003                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6004         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6005                 int sindex;
6006                 /* take care of sig[0]..sig[4] */
6007                 for (sindex = 0; sindex < 4; sindex++)
6008                         bp->attn_group[index].sig[sindex] =
6009                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6010
6011                 if (!CHIP_IS_E1x(bp))
6012                         /*
6013                          * enable5 is separate from the rest of the registers,
6014                          * and therefore the address skip is 4
6015                          * and not 16 between the different groups
6016                          */
6017                         bp->attn_group[index].sig[4] = REG_RD(bp,
6018                                         reg_offset_en5 + 0x4*index);
6019                 else
6020                         bp->attn_group[index].sig[4] = 0;
6021         }
6022
6023         if (bp->common.int_block == INT_BLOCK_HC) {
6024                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6025                                      HC_REG_ATTN_MSG0_ADDR_L);
6026
6027                 REG_WR(bp, reg_offset, U64_LO(section));
6028                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6029         } else if (!CHIP_IS_E1x(bp)) {
6030                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6031                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6032         }
6033
6034         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6035                                             sp_sb);
6036
6037         bnx2x_zero_sp_sb(bp);
6038
6039         /* PCI guarantees endianity of regpairs */
6040         sp_sb_data.state                = SB_ENABLED;
6041         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6042         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6043         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6044         sp_sb_data.igu_seg_id           = igu_seg_id;
6045         sp_sb_data.p_func.pf_id         = func;
6046         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6047         sp_sb_data.p_func.vf_id         = 0xff;
6048
6049         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6050
6051         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6052 }
6053
6054 void bnx2x_update_coalesce(struct bnx2x *bp)
6055 {
6056         int i;
6057
6058         for_each_eth_queue(bp, i)
6059                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6060                                          bp->tx_ticks, bp->rx_ticks);
6061 }
6062
6063 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6064 {
6065         spin_lock_init(&bp->spq_lock);
6066         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6067
6068         bp->spq_prod_idx = 0;
6069         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6070         bp->spq_prod_bd = bp->spq;
6071         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6072 }
6073
6074 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6075 {
6076         int i;
6077         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6078                 union event_ring_elem *elem =
6079                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6080
6081                 elem->next_page.addr.hi =
6082                         cpu_to_le32(U64_HI(bp->eq_mapping +
6083                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6084                 elem->next_page.addr.lo =
6085                         cpu_to_le32(U64_LO(bp->eq_mapping +
6086                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6087         }
6088         bp->eq_cons = 0;
6089         bp->eq_prod = NUM_EQ_DESC;
6090         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6091         /* we want a warning message before it gets wrought... */
6092         atomic_set(&bp->eq_spq_left,
6093                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6094 }
6095
6096 /* called with netif_addr_lock_bh() */
6097 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6098                                unsigned long rx_mode_flags,
6099                                unsigned long rx_accept_flags,
6100                                unsigned long tx_accept_flags,
6101                                unsigned long ramrod_flags)
6102 {
6103         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6104         int rc;
6105
6106         memset(&ramrod_param, 0, sizeof(ramrod_param));
6107
6108         /* Prepare ramrod parameters */
6109         ramrod_param.cid = 0;
6110         ramrod_param.cl_id = cl_id;
6111         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6112         ramrod_param.func_id = BP_FUNC(bp);
6113
6114         ramrod_param.pstate = &bp->sp_state;
6115         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6116
6117         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6118         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6119
6120         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6121
6122         ramrod_param.ramrod_flags = ramrod_flags;
6123         ramrod_param.rx_mode_flags = rx_mode_flags;
6124
6125         ramrod_param.rx_accept_flags = rx_accept_flags;
6126         ramrod_param.tx_accept_flags = tx_accept_flags;
6127
6128         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6129         if (rc < 0) {
6130                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6131                 return rc;
6132         }
6133
6134         return 0;
6135 }
6136
6137 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6138                                    unsigned long *rx_accept_flags,
6139                                    unsigned long *tx_accept_flags)
6140 {
6141         /* Clear the flags first */
6142         *rx_accept_flags = 0;
6143         *tx_accept_flags = 0;
6144
6145         switch (rx_mode) {
6146         case BNX2X_RX_MODE_NONE:
6147                 /*
6148                  * 'drop all' supersedes any accept flags that may have been
6149                  * passed to the function.
6150                  */
6151                 break;
6152         case BNX2X_RX_MODE_NORMAL:
6153                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6154                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6155                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6156
6157                 /* internal switching mode */
6158                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6159                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6160                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6161
6162                 break;
6163         case BNX2X_RX_MODE_ALLMULTI:
6164                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6165                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6166                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6167
6168                 /* internal switching mode */
6169                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6170                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6171                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6172
6173                 break;
6174         case BNX2X_RX_MODE_PROMISC:
6175                 /* According to definition of SI mode, iface in promisc mode
6176                  * should receive matched and unmatched (in resolution of port)
6177                  * unicast packets.
6178                  */
6179                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6180                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6181                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6182                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6183
6184                 /* internal switching mode */
6185                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6186                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6187
6188                 if (IS_MF_SI(bp))
6189                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6190                 else
6191                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6192
6193                 break;
6194         default:
6195                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6196                 return -EINVAL;
6197         }
6198
6199         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6200         if (rx_mode != BNX2X_RX_MODE_NONE) {
6201                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6202                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6203         }
6204
6205         return 0;
6206 }
6207
6208 /* called with netif_addr_lock_bh() */
6209 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6210 {
6211         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6212         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6213         int rc;
6214
6215         if (!NO_FCOE(bp))
6216                 /* Configure rx_mode of FCoE Queue */
6217                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6218
6219         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6220                                      &tx_accept_flags);
6221         if (rc)
6222                 return rc;
6223
6224         __set_bit(RAMROD_RX, &ramrod_flags);
6225         __set_bit(RAMROD_TX, &ramrod_flags);
6226
6227         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6228                                    rx_accept_flags, tx_accept_flags,
6229                                    ramrod_flags);
6230 }
6231
6232 static void bnx2x_init_internal_common(struct bnx2x *bp)
6233 {
6234         int i;
6235
6236         /* Zero this manually as its initialization is
6237            currently missing in the initTool */
6238         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6239                 REG_WR(bp, BAR_USTRORM_INTMEM +
6240                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6241         if (!CHIP_IS_E1x(bp)) {
6242                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6243                         CHIP_INT_MODE_IS_BC(bp) ?
6244                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6245         }
6246 }
6247
6248 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6249 {
6250         switch (load_code) {
6251         case FW_MSG_CODE_DRV_LOAD_COMMON:
6252         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6253                 bnx2x_init_internal_common(bp);
6254                 /* no break */
6255
6256         case FW_MSG_CODE_DRV_LOAD_PORT:
6257                 /* nothing to do */
6258                 /* no break */
6259
6260         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6261                 /* internal memory per function is
6262                    initialized inside bnx2x_pf_init */
6263                 break;
6264
6265         default:
6266                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6267                 break;
6268         }
6269 }
6270
6271 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6272 {
6273         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6274 }
6275
6276 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6277 {
6278         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6279 }
6280
6281 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6282 {
6283         if (CHIP_IS_E1x(fp->bp))
6284                 return BP_L_ID(fp->bp) + fp->index;
6285         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6286                 return bnx2x_fp_igu_sb_id(fp);
6287 }
6288
6289 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6290 {
6291         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6292         u8 cos;
6293         unsigned long q_type = 0;
6294         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6295         fp->rx_queue = fp_idx;
6296         fp->cid = fp_idx;
6297         fp->cl_id = bnx2x_fp_cl_id(fp);
6298         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6299         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6300         /* qZone id equals to FW (per path) client id */
6301         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6302
6303         /* init shortcut */
6304         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6305
6306         /* Setup SB indices */
6307         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6308
6309         /* Configure Queue State object */
6310         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6311         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6312
6313         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6314
6315         /* init tx data */
6316         for_each_cos_in_tx_queue(fp, cos) {
6317                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6318                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6319                                   FP_COS_TO_TXQ(fp, cos, bp),
6320                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6321                 cids[cos] = fp->txdata_ptr[cos]->cid;
6322         }
6323
6324         /* nothing more for vf to do here */
6325         if (IS_VF(bp))
6326                 return;
6327
6328         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6329                       fp->fw_sb_id, fp->igu_sb_id);
6330         bnx2x_update_fpsb_idx(fp);
6331         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6332                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6333                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6334
6335         /**
6336          * Configure classification DBs: Always enable Tx switching
6337          */
6338         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6339
6340         DP(NETIF_MSG_IFUP,
6341            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6342            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6343            fp->igu_sb_id);
6344 }
6345
6346 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6347 {
6348         int i;
6349
6350         for (i = 1; i <= NUM_TX_RINGS; i++) {
6351                 struct eth_tx_next_bd *tx_next_bd =
6352                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6353
6354                 tx_next_bd->addr_hi =
6355                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6356                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6357                 tx_next_bd->addr_lo =
6358                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6359                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6360         }
6361
6362         *txdata->tx_cons_sb = cpu_to_le16(0);
6363
6364         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6365         txdata->tx_db.data.zero_fill1 = 0;
6366         txdata->tx_db.data.prod = 0;
6367
6368         txdata->tx_pkt_prod = 0;
6369         txdata->tx_pkt_cons = 0;
6370         txdata->tx_bd_prod = 0;
6371         txdata->tx_bd_cons = 0;
6372         txdata->tx_pkt = 0;
6373 }
6374
6375 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6376 {
6377         int i;
6378
6379         for_each_tx_queue_cnic(bp, i)
6380                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6381 }
6382
6383 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6384 {
6385         int i;
6386         u8 cos;
6387
6388         for_each_eth_queue(bp, i)
6389                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6390                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6391 }
6392
6393 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6394 {
6395         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6396         unsigned long q_type = 0;
6397
6398         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6399         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6400                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6401         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6402         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6403         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6404         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6405         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6406                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6407                           fp);
6408
6409         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6410
6411         /* qZone id equals to FW (per path) client id */
6412         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6413         /* init shortcut */
6414         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6415                 bnx2x_rx_ustorm_prods_offset(fp);
6416
6417         /* Configure Queue State object */
6418         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6419         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6420
6421         /* No multi-CoS for FCoE L2 client */
6422         BUG_ON(fp->max_cos != 1);
6423
6424         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6425                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6426                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6427
6428         DP(NETIF_MSG_IFUP,
6429            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6430            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6431            fp->igu_sb_id);
6432 }
6433
6434 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6435 {
6436         if (!NO_FCOE(bp))
6437                 bnx2x_init_fcoe_fp(bp);
6438
6439         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6440                       BNX2X_VF_ID_INVALID, false,
6441                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6442
6443         /* ensure status block indices were read */
6444         rmb();
6445         bnx2x_init_rx_rings_cnic(bp);
6446         bnx2x_init_tx_rings_cnic(bp);
6447
6448         /* flush all */
6449         mb();
6450         mmiowb();
6451 }
6452
6453 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6454 {
6455         int i;
6456
6457         /* Setup NIC internals and enable interrupts */
6458         for_each_eth_queue(bp, i)
6459                 bnx2x_init_eth_fp(bp, i);
6460
6461         /* ensure status block indices were read */
6462         rmb();
6463         bnx2x_init_rx_rings(bp);
6464         bnx2x_init_tx_rings(bp);
6465
6466         if (IS_PF(bp)) {
6467                 /* Initialize MOD_ABS interrupts */
6468                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6469                                        bp->common.shmem_base,
6470                                        bp->common.shmem2_base, BP_PORT(bp));
6471
6472                 /* initialize the default status block and sp ring */
6473                 bnx2x_init_def_sb(bp);
6474                 bnx2x_update_dsb_idx(bp);
6475                 bnx2x_init_sp_ring(bp);
6476         } else {
6477                 bnx2x_memset_stats(bp);
6478         }
6479 }
6480
6481 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6482 {
6483         bnx2x_init_eq_ring(bp);
6484         bnx2x_init_internal(bp, load_code);
6485         bnx2x_pf_init(bp);
6486         bnx2x_stats_init(bp);
6487
6488         /* flush all before enabling interrupts */
6489         mb();
6490         mmiowb();
6491
6492         bnx2x_int_enable(bp);
6493
6494         /* Check for SPIO5 */
6495         bnx2x_attn_int_deasserted0(bp,
6496                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6497                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6498 }
6499
6500 /* gzip service functions */
6501 static int bnx2x_gunzip_init(struct bnx2x *bp)
6502 {
6503         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6504                                             &bp->gunzip_mapping, GFP_KERNEL);
6505         if (bp->gunzip_buf  == NULL)
6506                 goto gunzip_nomem1;
6507
6508         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6509         if (bp->strm  == NULL)
6510                 goto gunzip_nomem2;
6511
6512         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6513         if (bp->strm->workspace == NULL)
6514                 goto gunzip_nomem3;
6515
6516         return 0;
6517
6518 gunzip_nomem3:
6519         kfree(bp->strm);
6520         bp->strm = NULL;
6521
6522 gunzip_nomem2:
6523         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6524                           bp->gunzip_mapping);
6525         bp->gunzip_buf = NULL;
6526
6527 gunzip_nomem1:
6528         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6529         return -ENOMEM;
6530 }
6531
6532 static void bnx2x_gunzip_end(struct bnx2x *bp)
6533 {
6534         if (bp->strm) {
6535                 vfree(bp->strm->workspace);
6536                 kfree(bp->strm);
6537                 bp->strm = NULL;
6538         }
6539
6540         if (bp->gunzip_buf) {
6541                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6542                                   bp->gunzip_mapping);
6543                 bp->gunzip_buf = NULL;
6544         }
6545 }
6546
6547 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6548 {
6549         int n, rc;
6550
6551         /* check gzip header */
6552         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6553                 BNX2X_ERR("Bad gzip header\n");
6554                 return -EINVAL;
6555         }
6556
6557         n = 10;
6558
6559 #define FNAME                           0x8
6560
6561         if (zbuf[3] & FNAME)
6562                 while ((zbuf[n++] != 0) && (n < len));
6563
6564         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6565         bp->strm->avail_in = len - n;
6566         bp->strm->next_out = bp->gunzip_buf;
6567         bp->strm->avail_out = FW_BUF_SIZE;
6568
6569         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6570         if (rc != Z_OK)
6571                 return rc;
6572
6573         rc = zlib_inflate(bp->strm, Z_FINISH);
6574         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6575                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6576                            bp->strm->msg);
6577
6578         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6579         if (bp->gunzip_outlen & 0x3)
6580                 netdev_err(bp->dev,
6581                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6582                                 bp->gunzip_outlen);
6583         bp->gunzip_outlen >>= 2;
6584
6585         zlib_inflateEnd(bp->strm);
6586
6587         if (rc == Z_STREAM_END)
6588                 return 0;
6589
6590         return rc;
6591 }
6592
6593 /* nic load/unload */
6594
6595 /*
6596  * General service functions
6597  */
6598
6599 /* send a NIG loopback debug packet */
6600 static void bnx2x_lb_pckt(struct bnx2x *bp)
6601 {
6602         u32 wb_write[3];
6603
6604         /* Ethernet source and destination addresses */
6605         wb_write[0] = 0x55555555;
6606         wb_write[1] = 0x55555555;
6607         wb_write[2] = 0x20;             /* SOP */
6608         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6609
6610         /* NON-IP protocol */
6611         wb_write[0] = 0x09000000;
6612         wb_write[1] = 0x55555555;
6613         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6614         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6615 }
6616
6617 /* some of the internal memories
6618  * are not directly readable from the driver
6619  * to test them we send debug packets
6620  */
6621 static int bnx2x_int_mem_test(struct bnx2x *bp)
6622 {
6623         int factor;
6624         int count, i;
6625         u32 val = 0;
6626
6627         if (CHIP_REV_IS_FPGA(bp))
6628                 factor = 120;
6629         else if (CHIP_REV_IS_EMUL(bp))
6630                 factor = 200;
6631         else
6632                 factor = 1;
6633
6634         /* Disable inputs of parser neighbor blocks */
6635         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6636         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6637         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6638         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6639
6640         /*  Write 0 to parser credits for CFC search request */
6641         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6642
6643         /* send Ethernet packet */
6644         bnx2x_lb_pckt(bp);
6645
6646         /* TODO do i reset NIG statistic? */
6647         /* Wait until NIG register shows 1 packet of size 0x10 */
6648         count = 1000 * factor;
6649         while (count) {
6650
6651                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6652                 val = *bnx2x_sp(bp, wb_data[0]);
6653                 if (val == 0x10)
6654                         break;
6655
6656                 usleep_range(10000, 20000);
6657                 count--;
6658         }
6659         if (val != 0x10) {
6660                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6661                 return -1;
6662         }
6663
6664         /* Wait until PRS register shows 1 packet */
6665         count = 1000 * factor;
6666         while (count) {
6667                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6668                 if (val == 1)
6669                         break;
6670
6671                 usleep_range(10000, 20000);
6672                 count--;
6673         }
6674         if (val != 0x1) {
6675                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6676                 return -2;
6677         }
6678
6679         /* Reset and init BRB, PRS */
6680         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6681         msleep(50);
6682         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6683         msleep(50);
6684         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6685         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6686
6687         DP(NETIF_MSG_HW, "part2\n");
6688
6689         /* Disable inputs of parser neighbor blocks */
6690         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6691         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6692         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6693         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6694
6695         /* Write 0 to parser credits for CFC search request */
6696         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6697
6698         /* send 10 Ethernet packets */
6699         for (i = 0; i < 10; i++)
6700                 bnx2x_lb_pckt(bp);
6701
6702         /* Wait until NIG register shows 10 + 1
6703            packets of size 11*0x10 = 0xb0 */
6704         count = 1000 * factor;
6705         while (count) {
6706
6707                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6708                 val = *bnx2x_sp(bp, wb_data[0]);
6709                 if (val == 0xb0)
6710                         break;
6711
6712                 usleep_range(10000, 20000);
6713                 count--;
6714         }
6715         if (val != 0xb0) {
6716                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6717                 return -3;
6718         }
6719
6720         /* Wait until PRS register shows 2 packets */
6721         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6722         if (val != 2)
6723                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6724
6725         /* Write 1 to parser credits for CFC search request */
6726         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6727
6728         /* Wait until PRS register shows 3 packets */
6729         msleep(10 * factor);
6730         /* Wait until NIG register shows 1 packet of size 0x10 */
6731         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6732         if (val != 3)
6733                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6734
6735         /* clear NIG EOP FIFO */
6736         for (i = 0; i < 11; i++)
6737                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6738         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6739         if (val != 1) {
6740                 BNX2X_ERR("clear of NIG failed\n");
6741                 return -4;
6742         }
6743
6744         /* Reset and init BRB, PRS, NIG */
6745         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6746         msleep(50);
6747         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6748         msleep(50);
6749         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6750         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6751         if (!CNIC_SUPPORT(bp))
6752                 /* set NIC mode */
6753                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6754
6755         /* Enable inputs of parser neighbor blocks */
6756         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6757         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6758         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6759         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6760
6761         DP(NETIF_MSG_HW, "done\n");
6762
6763         return 0; /* OK */
6764 }
6765
6766 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6767 {
6768         u32 val;
6769
6770         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6771         if (!CHIP_IS_E1x(bp))
6772                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6773         else
6774                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6775         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6776         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6777         /*
6778          * mask read length error interrupts in brb for parser
6779          * (parsing unit and 'checksum and crc' unit)
6780          * these errors are legal (PU reads fixed length and CAC can cause
6781          * read length error on truncated packets)
6782          */
6783         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6784         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6785         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6786         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6787         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6788         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6789 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6790 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6791         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6792         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6793         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6794 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6795 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6796         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6797         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6798         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6799         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6800 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6801 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6802
6803         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6804                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6805                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6806         if (!CHIP_IS_E1x(bp))
6807                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6808                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6809         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6810
6811         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6812         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6813         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6814 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6815
6816         if (!CHIP_IS_E1x(bp))
6817                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6818                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6819
6820         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6821         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6822 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6823         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6824 }
6825
6826 static void bnx2x_reset_common(struct bnx2x *bp)
6827 {
6828         u32 val = 0x1400;
6829
6830         /* reset_common */
6831         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6832                0xd3ffff7f);
6833
6834         if (CHIP_IS_E3(bp)) {
6835                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6836                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6837         }
6838
6839         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6840 }
6841
6842 static void bnx2x_setup_dmae(struct bnx2x *bp)
6843 {
6844         bp->dmae_ready = 0;
6845         spin_lock_init(&bp->dmae_lock);
6846 }
6847
6848 static void bnx2x_init_pxp(struct bnx2x *bp)
6849 {
6850         u16 devctl;
6851         int r_order, w_order;
6852
6853         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6854         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6855         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6856         if (bp->mrrs == -1)
6857                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6858         else {
6859                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6860                 r_order = bp->mrrs;
6861         }
6862
6863         bnx2x_init_pxp_arb(bp, r_order, w_order);
6864 }
6865
6866 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6867 {
6868         int is_required;
6869         u32 val;
6870         int port;
6871
6872         if (BP_NOMCP(bp))
6873                 return;
6874
6875         is_required = 0;
6876         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6877               SHARED_HW_CFG_FAN_FAILURE_MASK;
6878
6879         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6880                 is_required = 1;
6881
6882         /*
6883          * The fan failure mechanism is usually related to the PHY type since
6884          * the power consumption of the board is affected by the PHY. Currently,
6885          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6886          */
6887         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6888                 for (port = PORT_0; port < PORT_MAX; port++) {
6889                         is_required |=
6890                                 bnx2x_fan_failure_det_req(
6891                                         bp,
6892                                         bp->common.shmem_base,
6893                                         bp->common.shmem2_base,
6894                                         port);
6895                 }
6896
6897         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6898
6899         if (is_required == 0)
6900                 return;
6901
6902         /* Fan failure is indicated by SPIO 5 */
6903         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6904
6905         /* set to active low mode */
6906         val = REG_RD(bp, MISC_REG_SPIO_INT);
6907         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6908         REG_WR(bp, MISC_REG_SPIO_INT, val);
6909
6910         /* enable interrupt to signal the IGU */
6911         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6912         val |= MISC_SPIO_SPIO5;
6913         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6914 }
6915
6916 void bnx2x_pf_disable(struct bnx2x *bp)
6917 {
6918         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6919         val &= ~IGU_PF_CONF_FUNC_EN;
6920
6921         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6922         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6923         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6924 }
6925
6926 static void bnx2x__common_init_phy(struct bnx2x *bp)
6927 {
6928         u32 shmem_base[2], shmem2_base[2];
6929         /* Avoid common init in case MFW supports LFA */
6930         if (SHMEM2_RD(bp, size) >
6931             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6932                 return;
6933         shmem_base[0] =  bp->common.shmem_base;
6934         shmem2_base[0] = bp->common.shmem2_base;
6935         if (!CHIP_IS_E1x(bp)) {
6936                 shmem_base[1] =
6937                         SHMEM2_RD(bp, other_shmem_base_addr);
6938                 shmem2_base[1] =
6939                         SHMEM2_RD(bp, other_shmem2_base_addr);
6940         }
6941         bnx2x_acquire_phy_lock(bp);
6942         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6943                               bp->common.chip_id);
6944         bnx2x_release_phy_lock(bp);
6945 }
6946
6947 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6948 {
6949         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6950         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6951         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6952         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6953         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6954
6955         /* make sure this value is 0 */
6956         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6957
6958         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6959         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6960         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6961         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6962 }
6963
6964 static void bnx2x_set_endianity(struct bnx2x *bp)
6965 {
6966 #ifdef __BIG_ENDIAN
6967         bnx2x_config_endianity(bp, 1);
6968 #else
6969         bnx2x_config_endianity(bp, 0);
6970 #endif
6971 }
6972
6973 static void bnx2x_reset_endianity(struct bnx2x *bp)
6974 {
6975         bnx2x_config_endianity(bp, 0);
6976 }
6977
6978 /**
6979  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6980  *
6981  * @bp:         driver handle
6982  */
6983 static int bnx2x_init_hw_common(struct bnx2x *bp)
6984 {
6985         u32 val;
6986
6987         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6988
6989         /*
6990          * take the RESET lock to protect undi_unload flow from accessing
6991          * registers while we're resetting the chip
6992          */
6993         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6994
6995         bnx2x_reset_common(bp);
6996         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6997
6998         val = 0xfffc;
6999         if (CHIP_IS_E3(bp)) {
7000                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7001                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7002         }
7003         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7004
7005         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7006
7007         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7008
7009         if (!CHIP_IS_E1x(bp)) {
7010                 u8 abs_func_id;
7011
7012                 /**
7013                  * 4-port mode or 2-port mode we need to turn of master-enable
7014                  * for everyone, after that, turn it back on for self.
7015                  * so, we disregard multi-function or not, and always disable
7016                  * for all functions on the given path, this means 0,2,4,6 for
7017                  * path 0 and 1,3,5,7 for path 1
7018                  */
7019                 for (abs_func_id = BP_PATH(bp);
7020                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7021                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7022                                 REG_WR(bp,
7023                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7024                                     1);
7025                                 continue;
7026                         }
7027
7028                         bnx2x_pretend_func(bp, abs_func_id);
7029                         /* clear pf enable */
7030                         bnx2x_pf_disable(bp);
7031                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7032                 }
7033         }
7034
7035         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7036         if (CHIP_IS_E1(bp)) {
7037                 /* enable HW interrupt from PXP on USDM overflow
7038                    bit 16 on INT_MASK_0 */
7039                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7040         }
7041
7042         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7043         bnx2x_init_pxp(bp);
7044         bnx2x_set_endianity(bp);
7045         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7046
7047         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7048                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7049
7050         /* let the HW do it's magic ... */
7051         msleep(100);
7052         /* finish PXP init */
7053         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7054         if (val != 1) {
7055                 BNX2X_ERR("PXP2 CFG failed\n");
7056                 return -EBUSY;
7057         }
7058         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7059         if (val != 1) {
7060                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7061                 return -EBUSY;
7062         }
7063
7064         /* Timers bug workaround E2 only. We need to set the entire ILT to
7065          * have entries with value "0" and valid bit on.
7066          * This needs to be done by the first PF that is loaded in a path
7067          * (i.e. common phase)
7068          */
7069         if (!CHIP_IS_E1x(bp)) {
7070 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7071  * (i.e. vnic3) to start even if it is marked as "scan-off".
7072  * This occurs when a different function (func2,3) is being marked
7073  * as "scan-off". Real-life scenario for example: if a driver is being
7074  * load-unloaded while func6,7 are down. This will cause the timer to access
7075  * the ilt, translate to a logical address and send a request to read/write.
7076  * Since the ilt for the function that is down is not valid, this will cause
7077  * a translation error which is unrecoverable.
7078  * The Workaround is intended to make sure that when this happens nothing fatal
7079  * will occur. The workaround:
7080  *      1.  First PF driver which loads on a path will:
7081  *              a.  After taking the chip out of reset, by using pretend,
7082  *                  it will write "0" to the following registers of
7083  *                  the other vnics.
7084  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7085  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7086  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7087  *                  And for itself it will write '1' to
7088  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7089  *                  dmae-operations (writing to pram for example.)
7090  *                  note: can be done for only function 6,7 but cleaner this
7091  *                        way.
7092  *              b.  Write zero+valid to the entire ILT.
7093  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7094  *                  VNIC3 (of that port). The range allocated will be the
7095  *                  entire ILT. This is needed to prevent  ILT range error.
7096  *      2.  Any PF driver load flow:
7097  *              a.  ILT update with the physical addresses of the allocated
7098  *                  logical pages.
7099  *              b.  Wait 20msec. - note that this timeout is needed to make
7100  *                  sure there are no requests in one of the PXP internal
7101  *                  queues with "old" ILT addresses.
7102  *              c.  PF enable in the PGLC.
7103  *              d.  Clear the was_error of the PF in the PGLC. (could have
7104  *                  occurred while driver was down)
7105  *              e.  PF enable in the CFC (WEAK + STRONG)
7106  *              f.  Timers scan enable
7107  *      3.  PF driver unload flow:
7108  *              a.  Clear the Timers scan_en.
7109  *              b.  Polling for scan_on=0 for that PF.
7110  *              c.  Clear the PF enable bit in the PXP.
7111  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7112  *              e.  Write zero+valid to all ILT entries (The valid bit must
7113  *                  stay set)
7114  *              f.  If this is VNIC 3 of a port then also init
7115  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7116  *                  to the last entry in the ILT.
7117  *
7118  *      Notes:
7119  *      Currently the PF error in the PGLC is non recoverable.
7120  *      In the future the there will be a recovery routine for this error.
7121  *      Currently attention is masked.
7122  *      Having an MCP lock on the load/unload process does not guarantee that
7123  *      there is no Timer disable during Func6/7 enable. This is because the
7124  *      Timers scan is currently being cleared by the MCP on FLR.
7125  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7126  *      there is error before clearing it. But the flow above is simpler and
7127  *      more general.
7128  *      All ILT entries are written by zero+valid and not just PF6/7
7129  *      ILT entries since in the future the ILT entries allocation for
7130  *      PF-s might be dynamic.
7131  */
7132                 struct ilt_client_info ilt_cli;
7133                 struct bnx2x_ilt ilt;
7134                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7135                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7136
7137                 /* initialize dummy TM client */
7138                 ilt_cli.start = 0;
7139                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7140                 ilt_cli.client_num = ILT_CLIENT_TM;
7141
7142                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7143                  * Step 2: set the timers first/last ilt entry to point
7144                  * to the entire range to prevent ILT range error for 3rd/4th
7145                  * vnic (this code assumes existence of the vnic)
7146                  *
7147                  * both steps performed by call to bnx2x_ilt_client_init_op()
7148                  * with dummy TM client
7149                  *
7150                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7151                  * and his brother are split registers
7152                  */
7153                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7154                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7155                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7156
7157                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7158                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7159                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7160         }
7161
7162         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7163         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7164
7165         if (!CHIP_IS_E1x(bp)) {
7166                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7167                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7168                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7169
7170                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7171
7172                 /* let the HW do it's magic ... */
7173                 do {
7174                         msleep(200);
7175                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7176                 } while (factor-- && (val != 1));
7177
7178                 if (val != 1) {
7179                         BNX2X_ERR("ATC_INIT failed\n");
7180                         return -EBUSY;
7181                 }
7182         }
7183
7184         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7185
7186         bnx2x_iov_init_dmae(bp);
7187
7188         /* clean the DMAE memory */
7189         bp->dmae_ready = 1;
7190         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7191
7192         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7193
7194         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7195
7196         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7197
7198         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7199
7200         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7201         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7202         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7203         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7204
7205         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7206
7207         /* QM queues pointers table */
7208         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7209
7210         /* soft reset pulse */
7211         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7212         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7213
7214         if (CNIC_SUPPORT(bp))
7215                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7216
7217         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7218
7219         if (!CHIP_REV_IS_SLOW(bp))
7220                 /* enable hw interrupt from doorbell Q */
7221                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7222
7223         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7224
7225         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7226         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7227
7228         if (!CHIP_IS_E1(bp))
7229                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7230
7231         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7232                 if (IS_MF_AFEX(bp)) {
7233                         /* configure that VNTag and VLAN headers must be
7234                          * received in afex mode
7235                          */
7236                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7237                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7238                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7239                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7240                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7241                 } else {
7242                         /* Bit-map indicating which L2 hdrs may appear
7243                          * after the basic Ethernet header
7244                          */
7245                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7246                                bp->path_has_ovlan ? 7 : 6);
7247                 }
7248         }
7249
7250         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7251         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7252         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7253         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7254
7255         if (!CHIP_IS_E1x(bp)) {
7256                 /* reset VFC memories */
7257                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7258                            VFC_MEMORIES_RST_REG_CAM_RST |
7259                            VFC_MEMORIES_RST_REG_RAM_RST);
7260                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7261                            VFC_MEMORIES_RST_REG_CAM_RST |
7262                            VFC_MEMORIES_RST_REG_RAM_RST);
7263
7264                 msleep(20);
7265         }
7266
7267         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7268         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7269         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7270         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7271
7272         /* sync semi rtc */
7273         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7274                0x80000000);
7275         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7276                0x80000000);
7277
7278         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7279         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7280         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7281
7282         if (!CHIP_IS_E1x(bp)) {
7283                 if (IS_MF_AFEX(bp)) {
7284                         /* configure that VNTag and VLAN headers must be
7285                          * sent in afex mode
7286                          */
7287                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7288                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7289                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7290                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7291                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7292                 } else {
7293                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7294                                bp->path_has_ovlan ? 7 : 6);
7295                 }
7296         }
7297
7298         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7299
7300         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7301
7302         if (CNIC_SUPPORT(bp)) {
7303                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7304                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7305                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7306                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7307                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7308                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7309                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7310                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7311                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7312                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7313         }
7314         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7315
7316         if (sizeof(union cdu_context) != 1024)
7317                 /* we currently assume that a context is 1024 bytes */
7318                 dev_alert(&bp->pdev->dev,
7319                           "please adjust the size of cdu_context(%ld)\n",
7320                           (long)sizeof(union cdu_context));
7321
7322         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7323         val = (4 << 24) + (0 << 12) + 1024;
7324         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7325
7326         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7327         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7328         /* enable context validation interrupt from CFC */
7329         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7330
7331         /* set the thresholds to prevent CFC/CDU race */
7332         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7333
7334         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7335
7336         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7337                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7338
7339         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7340         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7341
7342         /* Reset PCIE errors for debug */
7343         REG_WR(bp, 0x2814, 0xffffffff);
7344         REG_WR(bp, 0x3820, 0xffffffff);
7345
7346         if (!CHIP_IS_E1x(bp)) {
7347                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7348                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7349                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7350                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7351                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7352                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7353                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7354                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7355                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7356                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7357                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7358         }
7359
7360         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7361         if (!CHIP_IS_E1(bp)) {
7362                 /* in E3 this done in per-port section */
7363                 if (!CHIP_IS_E3(bp))
7364                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7365         }
7366         if (CHIP_IS_E1H(bp))
7367                 /* not applicable for E2 (and above ...) */
7368                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7369
7370         if (CHIP_REV_IS_SLOW(bp))
7371                 msleep(200);
7372
7373         /* finish CFC init */
7374         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7375         if (val != 1) {
7376                 BNX2X_ERR("CFC LL_INIT failed\n");
7377                 return -EBUSY;
7378         }
7379         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7380         if (val != 1) {
7381                 BNX2X_ERR("CFC AC_INIT failed\n");
7382                 return -EBUSY;
7383         }
7384         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7385         if (val != 1) {
7386                 BNX2X_ERR("CFC CAM_INIT failed\n");
7387                 return -EBUSY;
7388         }
7389         REG_WR(bp, CFC_REG_DEBUG0, 0);
7390
7391         if (CHIP_IS_E1(bp)) {
7392                 /* read NIG statistic
7393                    to see if this is our first up since powerup */
7394                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7395                 val = *bnx2x_sp(bp, wb_data[0]);
7396
7397                 /* do internal memory self test */
7398                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7399                         BNX2X_ERR("internal mem self test failed\n");
7400                         return -EBUSY;
7401                 }
7402         }
7403
7404         bnx2x_setup_fan_failure_detection(bp);
7405
7406         /* clear PXP2 attentions */
7407         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7408
7409         bnx2x_enable_blocks_attention(bp);
7410         bnx2x_enable_blocks_parity(bp);
7411
7412         if (!BP_NOMCP(bp)) {
7413                 if (CHIP_IS_E1x(bp))
7414                         bnx2x__common_init_phy(bp);
7415         } else
7416                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7417
7418         return 0;
7419 }
7420
7421 /**
7422  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7423  *
7424  * @bp:         driver handle
7425  */
7426 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7427 {
7428         int rc = bnx2x_init_hw_common(bp);
7429
7430         if (rc)
7431                 return rc;
7432
7433         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7434         if (!BP_NOMCP(bp))
7435                 bnx2x__common_init_phy(bp);
7436
7437         return 0;
7438 }
7439
7440 static int bnx2x_init_hw_port(struct bnx2x *bp)
7441 {
7442         int port = BP_PORT(bp);
7443         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7444         u32 low, high;
7445         u32 val, reg;
7446
7447         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7448
7449         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7450
7451         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7452         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7453         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7454
7455         /* Timers bug workaround: disables the pf_master bit in pglue at
7456          * common phase, we need to enable it here before any dmae access are
7457          * attempted. Therefore we manually added the enable-master to the
7458          * port phase (it also happens in the function phase)
7459          */
7460         if (!CHIP_IS_E1x(bp))
7461                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7462
7463         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7464         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7465         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7466         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7467
7468         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7469         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7470         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7471         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7472
7473         /* QM cid (connection) count */
7474         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7475
7476         if (CNIC_SUPPORT(bp)) {
7477                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7478                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7479                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7480         }
7481
7482         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7483
7484         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7485
7486         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7487
7488                 if (IS_MF(bp))
7489                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7490                 else if (bp->dev->mtu > 4096) {
7491                         if (bp->flags & ONE_PORT_FLAG)
7492                                 low = 160;
7493                         else {
7494                                 val = bp->dev->mtu;
7495                                 /* (24*1024 + val*4)/256 */
7496                                 low = 96 + (val/64) +
7497                                                 ((val % 64) ? 1 : 0);
7498                         }
7499                 } else
7500                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7501                 high = low + 56;        /* 14*1024/256 */
7502                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7503                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7504         }
7505
7506         if (CHIP_MODE_IS_4_PORT(bp))
7507                 REG_WR(bp, (BP_PORT(bp) ?
7508                             BRB1_REG_MAC_GUARANTIED_1 :
7509                             BRB1_REG_MAC_GUARANTIED_0), 40);
7510
7511         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7512         if (CHIP_IS_E3B0(bp)) {
7513                 if (IS_MF_AFEX(bp)) {
7514                         /* configure headers for AFEX mode */
7515                         REG_WR(bp, BP_PORT(bp) ?
7516                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7517                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7518                         REG_WR(bp, BP_PORT(bp) ?
7519                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7520                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7521                         REG_WR(bp, BP_PORT(bp) ?
7522                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7523                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7524                 } else {
7525                         /* Ovlan exists only if we are in multi-function +
7526                          * switch-dependent mode, in switch-independent there
7527                          * is no ovlan headers
7528                          */
7529                         REG_WR(bp, BP_PORT(bp) ?
7530                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7531                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7532                                (bp->path_has_ovlan ? 7 : 6));
7533                 }
7534         }
7535
7536         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7537         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7538         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7539         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7540
7541         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7542         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7543         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7544         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7545
7546         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7547         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7548
7549         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7550
7551         if (CHIP_IS_E1x(bp)) {
7552                 /* configure PBF to work without PAUSE mtu 9000 */
7553                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7554
7555                 /* update threshold */
7556                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7557                 /* update init credit */
7558                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7559
7560                 /* probe changes */
7561                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7562                 udelay(50);
7563                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7564         }
7565
7566         if (CNIC_SUPPORT(bp))
7567                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7568
7569         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7570         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7571
7572         if (CHIP_IS_E1(bp)) {
7573                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7574                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7575         }
7576         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7577
7578         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7579
7580         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7581         /* init aeu_mask_attn_func_0/1:
7582          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7583          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7584          *             bits 4-7 are used for "per vn group attention" */
7585         val = IS_MF(bp) ? 0xF7 : 0x7;
7586         /* Enable DCBX attention for all but E1 */
7587         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7588         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7589
7590         /* SCPAD_PARITY should NOT trigger close the gates */
7591         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7592         REG_WR(bp, reg,
7593                REG_RD(bp, reg) &
7594                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7595
7596         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7597         REG_WR(bp, reg,
7598                REG_RD(bp, reg) &
7599                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7600
7601         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7602
7603         if (!CHIP_IS_E1x(bp)) {
7604                 /* Bit-map indicating which L2 hdrs may appear after the
7605                  * basic Ethernet header
7606                  */
7607                 if (IS_MF_AFEX(bp))
7608                         REG_WR(bp, BP_PORT(bp) ?
7609                                NIG_REG_P1_HDRS_AFTER_BASIC :
7610                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7611                 else
7612                         REG_WR(bp, BP_PORT(bp) ?
7613                                NIG_REG_P1_HDRS_AFTER_BASIC :
7614                                NIG_REG_P0_HDRS_AFTER_BASIC,
7615                                IS_MF_SD(bp) ? 7 : 6);
7616
7617                 if (CHIP_IS_E3(bp))
7618                         REG_WR(bp, BP_PORT(bp) ?
7619                                    NIG_REG_LLH1_MF_MODE :
7620                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7621         }
7622         if (!CHIP_IS_E3(bp))
7623                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7624
7625         if (!CHIP_IS_E1(bp)) {
7626                 /* 0x2 disable mf_ov, 0x1 enable */
7627                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7628                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7629
7630                 if (!CHIP_IS_E1x(bp)) {
7631                         val = 0;
7632                         switch (bp->mf_mode) {
7633                         case MULTI_FUNCTION_SD:
7634                                 val = 1;
7635                                 break;
7636                         case MULTI_FUNCTION_SI:
7637                         case MULTI_FUNCTION_AFEX:
7638                                 val = 2;
7639                                 break;
7640                         }
7641
7642                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7643                                                   NIG_REG_LLH0_CLS_TYPE), val);
7644                 }
7645                 {
7646                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7647                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7648                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7649                 }
7650         }
7651
7652         /* If SPIO5 is set to generate interrupts, enable it for this port */
7653         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7654         if (val & MISC_SPIO_SPIO5) {
7655                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7656                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7657                 val = REG_RD(bp, reg_addr);
7658                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7659                 REG_WR(bp, reg_addr, val);
7660         }
7661
7662         return 0;
7663 }
7664
7665 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7666 {
7667         int reg;
7668         u32 wb_write[2];
7669
7670         if (CHIP_IS_E1(bp))
7671                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7672         else
7673                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7674
7675         wb_write[0] = ONCHIP_ADDR1(addr);
7676         wb_write[1] = ONCHIP_ADDR2(addr);
7677         REG_WR_DMAE(bp, reg, wb_write, 2);
7678 }
7679
7680 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7681 {
7682         u32 data, ctl, cnt = 100;
7683         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7684         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7685         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7686         u32 sb_bit =  1 << (idu_sb_id%32);
7687         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7688         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7689
7690         /* Not supported in BC mode */
7691         if (CHIP_INT_MODE_IS_BC(bp))
7692                 return;
7693
7694         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7695                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7696                 IGU_REGULAR_CLEANUP_SET                         |
7697                 IGU_REGULAR_BCLEANUP;
7698
7699         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7700               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7701               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7702
7703         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7704                          data, igu_addr_data);
7705         REG_WR(bp, igu_addr_data, data);
7706         mmiowb();
7707         barrier();
7708         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7709                           ctl, igu_addr_ctl);
7710         REG_WR(bp, igu_addr_ctl, ctl);
7711         mmiowb();
7712         barrier();
7713
7714         /* wait for clean up to finish */
7715         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7716                 msleep(20);
7717
7718         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7719                 DP(NETIF_MSG_HW,
7720                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7721                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7722         }
7723 }
7724
7725 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7726 {
7727         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7728 }
7729
7730 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7731 {
7732         u32 i, base = FUNC_ILT_BASE(func);
7733         for (i = base; i < base + ILT_PER_FUNC; i++)
7734                 bnx2x_ilt_wr(bp, i, 0);
7735 }
7736
7737 static void bnx2x_init_searcher(struct bnx2x *bp)
7738 {
7739         int port = BP_PORT(bp);
7740         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7741         /* T1 hash bits value determines the T1 number of entries */
7742         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7743 }
7744
7745 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7746 {
7747         int rc;
7748         struct bnx2x_func_state_params func_params = {NULL};
7749         struct bnx2x_func_switch_update_params *switch_update_params =
7750                 &func_params.params.switch_update;
7751
7752         /* Prepare parameters for function state transitions */
7753         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7754         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7755
7756         func_params.f_obj = &bp->func_obj;
7757         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7758
7759         /* Function parameters */
7760         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7761                   &switch_update_params->changes);
7762         if (suspend)
7763                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7764                           &switch_update_params->changes);
7765
7766         rc = bnx2x_func_state_change(bp, &func_params);
7767
7768         return rc;
7769 }
7770
7771 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7772 {
7773         int rc, i, port = BP_PORT(bp);
7774         int vlan_en = 0, mac_en[NUM_MACS];
7775
7776         /* Close input from network */
7777         if (bp->mf_mode == SINGLE_FUNCTION) {
7778                 bnx2x_set_rx_filter(&bp->link_params, 0);
7779         } else {
7780                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7781                                    NIG_REG_LLH0_FUNC_EN);
7782                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7783                           NIG_REG_LLH0_FUNC_EN, 0);
7784                 for (i = 0; i < NUM_MACS; i++) {
7785                         mac_en[i] = REG_RD(bp, port ?
7786                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7787                                               4 * i) :
7788                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7789                                               4 * i));
7790                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7791                                               4 * i) :
7792                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7793                 }
7794         }
7795
7796         /* Close BMC to host */
7797         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7798                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7799
7800         /* Suspend Tx switching to the PF. Completion of this ramrod
7801          * further guarantees that all the packets of that PF / child
7802          * VFs in BRB were processed by the Parser, so it is safe to
7803          * change the NIC_MODE register.
7804          */
7805         rc = bnx2x_func_switch_update(bp, 1);
7806         if (rc) {
7807                 BNX2X_ERR("Can't suspend tx-switching!\n");
7808                 return rc;
7809         }
7810
7811         /* Change NIC_MODE register */
7812         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7813
7814         /* Open input from network */
7815         if (bp->mf_mode == SINGLE_FUNCTION) {
7816                 bnx2x_set_rx_filter(&bp->link_params, 1);
7817         } else {
7818                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7819                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7820                 for (i = 0; i < NUM_MACS; i++) {
7821                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7822                                               4 * i) :
7823                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7824                                   mac_en[i]);
7825                 }
7826         }
7827
7828         /* Enable BMC to host */
7829         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7830                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7831
7832         /* Resume Tx switching to the PF */
7833         rc = bnx2x_func_switch_update(bp, 0);
7834         if (rc) {
7835                 BNX2X_ERR("Can't resume tx-switching!\n");
7836                 return rc;
7837         }
7838
7839         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7840         return 0;
7841 }
7842
7843 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7844 {
7845         int rc;
7846
7847         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7848
7849         if (CONFIGURE_NIC_MODE(bp)) {
7850                 /* Configure searcher as part of function hw init */
7851                 bnx2x_init_searcher(bp);
7852
7853                 /* Reset NIC mode */
7854                 rc = bnx2x_reset_nic_mode(bp);
7855                 if (rc)
7856                         BNX2X_ERR("Can't change NIC mode!\n");
7857                 return rc;
7858         }
7859
7860         return 0;
7861 }
7862
7863 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7864  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7865  * the addresses of the transaction, resulting in was-error bit set in the pci
7866  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7867  * to clear the interrupt which detected this from the pglueb and the was done
7868  * bit
7869  */
7870 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7871 {
7872         if (!CHIP_IS_E1x(bp))
7873                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7874                        1 << BP_ABS_FUNC(bp));
7875 }
7876
7877 static int bnx2x_init_hw_func(struct bnx2x *bp)
7878 {
7879         int port = BP_PORT(bp);
7880         int func = BP_FUNC(bp);
7881         int init_phase = PHASE_PF0 + func;
7882         struct bnx2x_ilt *ilt = BP_ILT(bp);
7883         u16 cdu_ilt_start;
7884         u32 addr, val;
7885         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7886         int i, main_mem_width, rc;
7887
7888         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7889
7890         /* FLR cleanup - hmmm */
7891         if (!CHIP_IS_E1x(bp)) {
7892                 rc = bnx2x_pf_flr_clnup(bp);
7893                 if (rc) {
7894                         bnx2x_fw_dump(bp);
7895                         return rc;
7896                 }
7897         }
7898
7899         /* set MSI reconfigure capability */
7900         if (bp->common.int_block == INT_BLOCK_HC) {
7901                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7902                 val = REG_RD(bp, addr);
7903                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7904                 REG_WR(bp, addr, val);
7905         }
7906
7907         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7908         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7909
7910         ilt = BP_ILT(bp);
7911         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7912
7913         if (IS_SRIOV(bp))
7914                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7915         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7916
7917         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7918          * those of the VFs, so start line should be reset
7919          */
7920         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7921         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7922                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7923                 ilt->lines[cdu_ilt_start + i].page_mapping =
7924                         bp->context[i].cxt_mapping;
7925                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7926         }
7927
7928         bnx2x_ilt_init_op(bp, INITOP_SET);
7929
7930         if (!CONFIGURE_NIC_MODE(bp)) {
7931                 bnx2x_init_searcher(bp);
7932                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7933                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7934         } else {
7935                 /* Set NIC mode */
7936                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7937                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7938         }
7939
7940         if (!CHIP_IS_E1x(bp)) {
7941                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7942
7943                 /* Turn on a single ISR mode in IGU if driver is going to use
7944                  * INT#x or MSI
7945                  */
7946                 if (!(bp->flags & USING_MSIX_FLAG))
7947                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7948                 /*
7949                  * Timers workaround bug: function init part.
7950                  * Need to wait 20msec after initializing ILT,
7951                  * needed to make sure there are no requests in
7952                  * one of the PXP internal queues with "old" ILT addresses
7953                  */
7954                 msleep(20);
7955                 /*
7956                  * Master enable - Due to WB DMAE writes performed before this
7957                  * register is re-initialized as part of the regular function
7958                  * init
7959                  */
7960                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7961                 /* Enable the function in IGU */
7962                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7963         }
7964
7965         bp->dmae_ready = 1;
7966
7967         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7968
7969         bnx2x_clean_pglue_errors(bp);
7970
7971         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7972         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7973         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7974         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7975         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7976         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7977         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7978         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7979         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7980         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7981         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7982         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7983         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7984
7985         if (!CHIP_IS_E1x(bp))
7986                 REG_WR(bp, QM_REG_PF_EN, 1);
7987
7988         if (!CHIP_IS_E1x(bp)) {
7989                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7990                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7991                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7992                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7993         }
7994         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7995
7996         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7997         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7998         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7999
8000         bnx2x_iov_init_dq(bp);
8001
8002         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8003         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8004         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8005         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8006         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8007         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8008         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8009         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8010         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8011         if (!CHIP_IS_E1x(bp))
8012                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8013
8014         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8015
8016         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8017
8018         if (!CHIP_IS_E1x(bp))
8019                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8020
8021         if (IS_MF(bp)) {
8022                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8023                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8024                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8025                                bp->mf_ov);
8026                 }
8027         }
8028
8029         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8030
8031         /* HC init per function */
8032         if (bp->common.int_block == INT_BLOCK_HC) {
8033                 if (CHIP_IS_E1H(bp)) {
8034                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8035
8036                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8037                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8038                 }
8039                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8040
8041         } else {
8042                 int num_segs, sb_idx, prod_offset;
8043
8044                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8045
8046                 if (!CHIP_IS_E1x(bp)) {
8047                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8048                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8049                 }
8050
8051                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8052
8053                 if (!CHIP_IS_E1x(bp)) {
8054                         int dsb_idx = 0;
8055                         /**
8056                          * Producer memory:
8057                          * E2 mode: address 0-135 match to the mapping memory;
8058                          * 136 - PF0 default prod; 137 - PF1 default prod;
8059                          * 138 - PF2 default prod; 139 - PF3 default prod;
8060                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8061                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8062                          * 144-147 reserved.
8063                          *
8064                          * E1.5 mode - In backward compatible mode;
8065                          * for non default SB; each even line in the memory
8066                          * holds the U producer and each odd line hold
8067                          * the C producer. The first 128 producers are for
8068                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8069                          * producers are for the DSB for each PF.
8070                          * Each PF has five segments: (the order inside each
8071                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8072                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8073                          * 144-147 attn prods;
8074                          */
8075                         /* non-default-status-blocks */
8076                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8077                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8078                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8079                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8080                                         num_segs;
8081
8082                                 for (i = 0; i < num_segs; i++) {
8083                                         addr = IGU_REG_PROD_CONS_MEMORY +
8084                                                         (prod_offset + i) * 4;
8085                                         REG_WR(bp, addr, 0);
8086                                 }
8087                                 /* send consumer update with value 0 */
8088                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8089                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8090                                 bnx2x_igu_clear_sb(bp,
8091                                                    bp->igu_base_sb + sb_idx);
8092                         }
8093
8094                         /* default-status-blocks */
8095                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8096                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8097
8098                         if (CHIP_MODE_IS_4_PORT(bp))
8099                                 dsb_idx = BP_FUNC(bp);
8100                         else
8101                                 dsb_idx = BP_VN(bp);
8102
8103                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8104                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8105                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8106
8107                         /*
8108                          * igu prods come in chunks of E1HVN_MAX (4) -
8109                          * does not matters what is the current chip mode
8110                          */
8111                         for (i = 0; i < (num_segs * E1HVN_MAX);
8112                              i += E1HVN_MAX) {
8113                                 addr = IGU_REG_PROD_CONS_MEMORY +
8114                                                         (prod_offset + i)*4;
8115                                 REG_WR(bp, addr, 0);
8116                         }
8117                         /* send consumer update with 0 */
8118                         if (CHIP_INT_MODE_IS_BC(bp)) {
8119                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8120                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8121                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8122                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8123                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8124                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8125                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8126                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8127                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8128                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8129                         } else {
8130                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8131                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8132                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8133                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8134                         }
8135                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8136
8137                         /* !!! These should become driver const once
8138                            rf-tool supports split-68 const */
8139                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8140                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8141                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8142                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8143                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8144                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8145                 }
8146         }
8147
8148         /* Reset PCIE errors for debug */
8149         REG_WR(bp, 0x2114, 0xffffffff);
8150         REG_WR(bp, 0x2120, 0xffffffff);
8151
8152         if (CHIP_IS_E1x(bp)) {
8153                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8154                 main_mem_base = HC_REG_MAIN_MEMORY +
8155                                 BP_PORT(bp) * (main_mem_size * 4);
8156                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8157                 main_mem_width = 8;
8158
8159                 val = REG_RD(bp, main_mem_prty_clr);
8160                 if (val)
8161                         DP(NETIF_MSG_HW,
8162                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8163                            val);
8164
8165                 /* Clear "false" parity errors in MSI-X table */
8166                 for (i = main_mem_base;
8167                      i < main_mem_base + main_mem_size * 4;
8168                      i += main_mem_width) {
8169                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8170                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8171                                          i, main_mem_width / 4);
8172                 }
8173                 /* Clear HC parity attention */
8174                 REG_RD(bp, main_mem_prty_clr);
8175         }
8176
8177 #ifdef BNX2X_STOP_ON_ERROR
8178         /* Enable STORMs SP logging */
8179         REG_WR8(bp, BAR_USTRORM_INTMEM +
8180                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8181         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8182                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8183         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8184                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8185         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8186                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8187 #endif
8188
8189         bnx2x_phy_probe(&bp->link_params);
8190
8191         return 0;
8192 }
8193
8194 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8195 {
8196         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8197
8198         if (!CHIP_IS_E1x(bp))
8199                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8200                                sizeof(struct host_hc_status_block_e2));
8201         else
8202                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8203                                sizeof(struct host_hc_status_block_e1x));
8204
8205         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8206 }
8207
8208 void bnx2x_free_mem(struct bnx2x *bp)
8209 {
8210         int i;
8211
8212         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8213                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8214
8215         if (IS_VF(bp))
8216                 return;
8217
8218         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8219                        sizeof(struct host_sp_status_block));
8220
8221         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8222                        sizeof(struct bnx2x_slowpath));
8223
8224         for (i = 0; i < L2_ILT_LINES(bp); i++)
8225                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8226                                bp->context[i].size);
8227         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8228
8229         BNX2X_FREE(bp->ilt->lines);
8230
8231         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8232
8233         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8234                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8235
8236         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8237
8238         bnx2x_iov_free_mem(bp);
8239 }
8240
8241 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8242 {
8243         if (!CHIP_IS_E1x(bp)) {
8244                 /* size = the status block + ramrod buffers */
8245                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8246                                                     sizeof(struct host_hc_status_block_e2));
8247                 if (!bp->cnic_sb.e2_sb)
8248                         goto alloc_mem_err;
8249         } else {
8250                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8251                                                      sizeof(struct host_hc_status_block_e1x));
8252                 if (!bp->cnic_sb.e1x_sb)
8253                         goto alloc_mem_err;
8254         }
8255
8256         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8257                 /* allocate searcher T2 table, as it wasn't allocated before */
8258                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8259                 if (!bp->t2)
8260                         goto alloc_mem_err;
8261         }
8262
8263         /* write address to which L5 should insert its values */
8264         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8265                 &bp->slowpath->drv_info_to_mcp;
8266
8267         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8268                 goto alloc_mem_err;
8269
8270         return 0;
8271
8272 alloc_mem_err:
8273         bnx2x_free_mem_cnic(bp);
8274         BNX2X_ERR("Can't allocate memory\n");
8275         return -ENOMEM;
8276 }
8277
8278 int bnx2x_alloc_mem(struct bnx2x *bp)
8279 {
8280         int i, allocated, context_size;
8281
8282         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8283                 /* allocate searcher T2 table */
8284                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8285                 if (!bp->t2)
8286                         goto alloc_mem_err;
8287         }
8288
8289         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8290                                              sizeof(struct host_sp_status_block));
8291         if (!bp->def_status_blk)
8292                 goto alloc_mem_err;
8293
8294         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8295                                        sizeof(struct bnx2x_slowpath));
8296         if (!bp->slowpath)
8297                 goto alloc_mem_err;
8298
8299         /* Allocate memory for CDU context:
8300          * This memory is allocated separately and not in the generic ILT
8301          * functions because CDU differs in few aspects:
8302          * 1. There are multiple entities allocating memory for context -
8303          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8304          * its own ILT lines.
8305          * 2. Since CDU page-size is not a single 4KB page (which is the case
8306          * for the other ILT clients), to be efficient we want to support
8307          * allocation of sub-page-size in the last entry.
8308          * 3. Context pointers are used by the driver to pass to FW / update
8309          * the context (for the other ILT clients the pointers are used just to
8310          * free the memory during unload).
8311          */
8312         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8313
8314         for (i = 0, allocated = 0; allocated < context_size; i++) {
8315                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8316                                           (context_size - allocated));
8317                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8318                                                       bp->context[i].size);
8319                 if (!bp->context[i].vcxt)
8320                         goto alloc_mem_err;
8321                 allocated += bp->context[i].size;
8322         }
8323         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8324                                  GFP_KERNEL);
8325         if (!bp->ilt->lines)
8326                 goto alloc_mem_err;
8327
8328         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8329                 goto alloc_mem_err;
8330
8331         if (bnx2x_iov_alloc_mem(bp))
8332                 goto alloc_mem_err;
8333
8334         /* Slow path ring */
8335         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8336         if (!bp->spq)
8337                 goto alloc_mem_err;
8338
8339         /* EQ */
8340         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8341                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8342         if (!bp->eq_ring)
8343                 goto alloc_mem_err;
8344
8345         return 0;
8346
8347 alloc_mem_err:
8348         bnx2x_free_mem(bp);
8349         BNX2X_ERR("Can't allocate memory\n");
8350         return -ENOMEM;
8351 }
8352
8353 /*
8354  * Init service functions
8355  */
8356
8357 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8358                       struct bnx2x_vlan_mac_obj *obj, bool set,
8359                       int mac_type, unsigned long *ramrod_flags)
8360 {
8361         int rc;
8362         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8363
8364         memset(&ramrod_param, 0, sizeof(ramrod_param));
8365
8366         /* Fill general parameters */
8367         ramrod_param.vlan_mac_obj = obj;
8368         ramrod_param.ramrod_flags = *ramrod_flags;
8369
8370         /* Fill a user request section if needed */
8371         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8372                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8373
8374                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8375
8376                 /* Set the command: ADD or DEL */
8377                 if (set)
8378                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8379                 else
8380                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8381         }
8382
8383         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8384
8385         if (rc == -EEXIST) {
8386                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8387                 /* do not treat adding same MAC as error */
8388                 rc = 0;
8389         } else if (rc < 0)
8390                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8391
8392         return rc;
8393 }
8394
8395 int bnx2x_del_all_macs(struct bnx2x *bp,
8396                        struct bnx2x_vlan_mac_obj *mac_obj,
8397                        int mac_type, bool wait_for_comp)
8398 {
8399         int rc;
8400         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8401
8402         /* Wait for completion of requested */
8403         if (wait_for_comp)
8404                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8405
8406         /* Set the mac type of addresses we want to clear */
8407         __set_bit(mac_type, &vlan_mac_flags);
8408
8409         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8410         if (rc < 0)
8411                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8412
8413         return rc;
8414 }
8415
8416 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8417 {
8418         if (IS_PF(bp)) {
8419                 unsigned long ramrod_flags = 0;
8420
8421                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8422                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8423                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8424                                          &bp->sp_objs->mac_obj, set,
8425                                          BNX2X_ETH_MAC, &ramrod_flags);
8426         } else { /* vf */
8427                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8428                                              bp->fp->index, true);
8429         }
8430 }
8431
8432 int bnx2x_setup_leading(struct bnx2x *bp)
8433 {
8434         if (IS_PF(bp))
8435                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8436         else /* VF */
8437                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8438 }
8439
8440 /**
8441  * bnx2x_set_int_mode - configure interrupt mode
8442  *
8443  * @bp:         driver handle
8444  *
8445  * In case of MSI-X it will also try to enable MSI-X.
8446  */
8447 int bnx2x_set_int_mode(struct bnx2x *bp)
8448 {
8449         int rc = 0;
8450
8451         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8452                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8453                 return -EINVAL;
8454         }
8455
8456         switch (int_mode) {
8457         case BNX2X_INT_MODE_MSIX:
8458                 /* attempt to enable msix */
8459                 rc = bnx2x_enable_msix(bp);
8460
8461                 /* msix attained */
8462                 if (!rc)
8463                         return 0;
8464
8465                 /* vfs use only msix */
8466                 if (rc && IS_VF(bp))
8467                         return rc;
8468
8469                 /* failed to enable multiple MSI-X */
8470                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8471                                bp->num_queues,
8472                                1 + bp->num_cnic_queues);
8473
8474                 /* falling through... */
8475         case BNX2X_INT_MODE_MSI:
8476                 bnx2x_enable_msi(bp);
8477
8478                 /* falling through... */
8479         case BNX2X_INT_MODE_INTX:
8480                 bp->num_ethernet_queues = 1;
8481                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8482                 BNX2X_DEV_INFO("set number of queues to 1\n");
8483                 break;
8484         default:
8485                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8486                 return -EINVAL;
8487         }
8488         return 0;
8489 }
8490
8491 /* must be called prior to any HW initializations */
8492 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8493 {
8494         if (IS_SRIOV(bp))
8495                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8496         return L2_ILT_LINES(bp);
8497 }
8498
8499 void bnx2x_ilt_set_info(struct bnx2x *bp)
8500 {
8501         struct ilt_client_info *ilt_client;
8502         struct bnx2x_ilt *ilt = BP_ILT(bp);
8503         u16 line = 0;
8504
8505         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8506         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8507
8508         /* CDU */
8509         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8510         ilt_client->client_num = ILT_CLIENT_CDU;
8511         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8512         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8513         ilt_client->start = line;
8514         line += bnx2x_cid_ilt_lines(bp);
8515
8516         if (CNIC_SUPPORT(bp))
8517                 line += CNIC_ILT_LINES;
8518         ilt_client->end = line - 1;
8519
8520         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8521            ilt_client->start,
8522            ilt_client->end,
8523            ilt_client->page_size,
8524            ilt_client->flags,
8525            ilog2(ilt_client->page_size >> 12));
8526
8527         /* QM */
8528         if (QM_INIT(bp->qm_cid_count)) {
8529                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8530                 ilt_client->client_num = ILT_CLIENT_QM;
8531                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8532                 ilt_client->flags = 0;
8533                 ilt_client->start = line;
8534
8535                 /* 4 bytes for each cid */
8536                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8537                                                          QM_ILT_PAGE_SZ);
8538
8539                 ilt_client->end = line - 1;
8540
8541                 DP(NETIF_MSG_IFUP,
8542                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8543                    ilt_client->start,
8544                    ilt_client->end,
8545                    ilt_client->page_size,
8546                    ilt_client->flags,
8547                    ilog2(ilt_client->page_size >> 12));
8548         }
8549
8550         if (CNIC_SUPPORT(bp)) {
8551                 /* SRC */
8552                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8553                 ilt_client->client_num = ILT_CLIENT_SRC;
8554                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8555                 ilt_client->flags = 0;
8556                 ilt_client->start = line;
8557                 line += SRC_ILT_LINES;
8558                 ilt_client->end = line - 1;
8559
8560                 DP(NETIF_MSG_IFUP,
8561                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8562                    ilt_client->start,
8563                    ilt_client->end,
8564                    ilt_client->page_size,
8565                    ilt_client->flags,
8566                    ilog2(ilt_client->page_size >> 12));
8567
8568                 /* TM */
8569                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8570                 ilt_client->client_num = ILT_CLIENT_TM;
8571                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8572                 ilt_client->flags = 0;
8573                 ilt_client->start = line;
8574                 line += TM_ILT_LINES;
8575                 ilt_client->end = line - 1;
8576
8577                 DP(NETIF_MSG_IFUP,
8578                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8579                    ilt_client->start,
8580                    ilt_client->end,
8581                    ilt_client->page_size,
8582                    ilt_client->flags,
8583                    ilog2(ilt_client->page_size >> 12));
8584         }
8585
8586         BUG_ON(line > ILT_MAX_LINES);
8587 }
8588
8589 /**
8590  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8591  *
8592  * @bp:                 driver handle
8593  * @fp:                 pointer to fastpath
8594  * @init_params:        pointer to parameters structure
8595  *
8596  * parameters configured:
8597  *      - HC configuration
8598  *      - Queue's CDU context
8599  */
8600 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8601         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8602 {
8603         u8 cos;
8604         int cxt_index, cxt_offset;
8605
8606         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8607         if (!IS_FCOE_FP(fp)) {
8608                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8609                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8610
8611                 /* If HC is supported, enable host coalescing in the transition
8612                  * to INIT state.
8613                  */
8614                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8615                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8616
8617                 /* HC rate */
8618                 init_params->rx.hc_rate = bp->rx_ticks ?
8619                         (1000000 / bp->rx_ticks) : 0;
8620                 init_params->tx.hc_rate = bp->tx_ticks ?
8621                         (1000000 / bp->tx_ticks) : 0;
8622
8623                 /* FW SB ID */
8624                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8625                         fp->fw_sb_id;
8626
8627                 /*
8628                  * CQ index among the SB indices: FCoE clients uses the default
8629                  * SB, therefore it's different.
8630                  */
8631                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8632                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8633         }
8634
8635         /* set maximum number of COSs supported by this queue */
8636         init_params->max_cos = fp->max_cos;
8637
8638         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8639             fp->index, init_params->max_cos);
8640
8641         /* set the context pointers queue object */
8642         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8643                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8644                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8645                                 ILT_PAGE_CIDS);
8646                 init_params->cxts[cos] =
8647                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8648         }
8649 }
8650
8651 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8652                         struct bnx2x_queue_state_params *q_params,
8653                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8654                         int tx_index, bool leading)
8655 {
8656         memset(tx_only_params, 0, sizeof(*tx_only_params));
8657
8658         /* Set the command */
8659         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8660
8661         /* Set tx-only QUEUE flags: don't zero statistics */
8662         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8663
8664         /* choose the index of the cid to send the slow path on */
8665         tx_only_params->cid_index = tx_index;
8666
8667         /* Set general TX_ONLY_SETUP parameters */
8668         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8669
8670         /* Set Tx TX_ONLY_SETUP parameters */
8671         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8672
8673         DP(NETIF_MSG_IFUP,
8674            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8675            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8676            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8677            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8678
8679         /* send the ramrod */
8680         return bnx2x_queue_state_change(bp, q_params);
8681 }
8682
8683 /**
8684  * bnx2x_setup_queue - setup queue
8685  *
8686  * @bp:         driver handle
8687  * @fp:         pointer to fastpath
8688  * @leading:    is leading
8689  *
8690  * This function performs 2 steps in a Queue state machine
8691  *      actually: 1) RESET->INIT 2) INIT->SETUP
8692  */
8693
8694 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8695                        bool leading)
8696 {
8697         struct bnx2x_queue_state_params q_params = {NULL};
8698         struct bnx2x_queue_setup_params *setup_params =
8699                                                 &q_params.params.setup;
8700         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8701                                                 &q_params.params.tx_only;
8702         int rc;
8703         u8 tx_index;
8704
8705         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8706
8707         /* reset IGU state skip FCoE L2 queue */
8708         if (!IS_FCOE_FP(fp))
8709                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8710                              IGU_INT_ENABLE, 0);
8711
8712         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8713         /* We want to wait for completion in this context */
8714         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8715
8716         /* Prepare the INIT parameters */
8717         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8718
8719         /* Set the command */
8720         q_params.cmd = BNX2X_Q_CMD_INIT;
8721
8722         /* Change the state to INIT */
8723         rc = bnx2x_queue_state_change(bp, &q_params);
8724         if (rc) {
8725                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8726                 return rc;
8727         }
8728
8729         DP(NETIF_MSG_IFUP, "init complete\n");
8730
8731         /* Now move the Queue to the SETUP state... */
8732         memset(setup_params, 0, sizeof(*setup_params));
8733
8734         /* Set QUEUE flags */
8735         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8736
8737         /* Set general SETUP parameters */
8738         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8739                                 FIRST_TX_COS_INDEX);
8740
8741         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8742                             &setup_params->rxq_params);
8743
8744         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8745                            FIRST_TX_COS_INDEX);
8746
8747         /* Set the command */
8748         q_params.cmd = BNX2X_Q_CMD_SETUP;
8749
8750         if (IS_FCOE_FP(fp))
8751                 bp->fcoe_init = true;
8752
8753         /* Change the state to SETUP */
8754         rc = bnx2x_queue_state_change(bp, &q_params);
8755         if (rc) {
8756                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8757                 return rc;
8758         }
8759
8760         /* loop through the relevant tx-only indices */
8761         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8762               tx_index < fp->max_cos;
8763               tx_index++) {
8764
8765                 /* prepare and send tx-only ramrod*/
8766                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8767                                           tx_only_params, tx_index, leading);
8768                 if (rc) {
8769                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8770                                   fp->index, tx_index);
8771                         return rc;
8772                 }
8773         }
8774
8775         return rc;
8776 }
8777
8778 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8779 {
8780         struct bnx2x_fastpath *fp = &bp->fp[index];
8781         struct bnx2x_fp_txdata *txdata;
8782         struct bnx2x_queue_state_params q_params = {NULL};
8783         int rc, tx_index;
8784
8785         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8786
8787         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8788         /* We want to wait for completion in this context */
8789         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8790
8791         /* close tx-only connections */
8792         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8793              tx_index < fp->max_cos;
8794              tx_index++){
8795
8796                 /* ascertain this is a normal queue*/
8797                 txdata = fp->txdata_ptr[tx_index];
8798
8799                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8800                                                         txdata->txq_index);
8801
8802                 /* send halt terminate on tx-only connection */
8803                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8804                 memset(&q_params.params.terminate, 0,
8805                        sizeof(q_params.params.terminate));
8806                 q_params.params.terminate.cid_index = tx_index;
8807
8808                 rc = bnx2x_queue_state_change(bp, &q_params);
8809                 if (rc)
8810                         return rc;
8811
8812                 /* send halt terminate on tx-only connection */
8813                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8814                 memset(&q_params.params.cfc_del, 0,
8815                        sizeof(q_params.params.cfc_del));
8816                 q_params.params.cfc_del.cid_index = tx_index;
8817                 rc = bnx2x_queue_state_change(bp, &q_params);
8818                 if (rc)
8819                         return rc;
8820         }
8821         /* Stop the primary connection: */
8822         /* ...halt the connection */
8823         q_params.cmd = BNX2X_Q_CMD_HALT;
8824         rc = bnx2x_queue_state_change(bp, &q_params);
8825         if (rc)
8826                 return rc;
8827
8828         /* ...terminate the connection */
8829         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8830         memset(&q_params.params.terminate, 0,
8831                sizeof(q_params.params.terminate));
8832         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8833         rc = bnx2x_queue_state_change(bp, &q_params);
8834         if (rc)
8835                 return rc;
8836         /* ...delete cfc entry */
8837         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8838         memset(&q_params.params.cfc_del, 0,
8839                sizeof(q_params.params.cfc_del));
8840         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8841         return bnx2x_queue_state_change(bp, &q_params);
8842 }
8843
8844 static void bnx2x_reset_func(struct bnx2x *bp)
8845 {
8846         int port = BP_PORT(bp);
8847         int func = BP_FUNC(bp);
8848         int i;
8849
8850         /* Disable the function in the FW */
8851         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8852         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8853         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8854         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8855
8856         /* FP SBs */
8857         for_each_eth_queue(bp, i) {
8858                 struct bnx2x_fastpath *fp = &bp->fp[i];
8859                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8860                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8861                            SB_DISABLED);
8862         }
8863
8864         if (CNIC_LOADED(bp))
8865                 /* CNIC SB */
8866                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8867                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8868                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8869
8870         /* SP SB */
8871         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8872                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8873                 SB_DISABLED);
8874
8875         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8876                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8877                        0);
8878
8879         /* Configure IGU */
8880         if (bp->common.int_block == INT_BLOCK_HC) {
8881                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8882                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8883         } else {
8884                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8885                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8886         }
8887
8888         if (CNIC_LOADED(bp)) {
8889                 /* Disable Timer scan */
8890                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8891                 /*
8892                  * Wait for at least 10ms and up to 2 second for the timers
8893                  * scan to complete
8894                  */
8895                 for (i = 0; i < 200; i++) {
8896                         usleep_range(10000, 20000);
8897                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8898                                 break;
8899                 }
8900         }
8901         /* Clear ILT */
8902         bnx2x_clear_func_ilt(bp, func);
8903
8904         /* Timers workaround bug for E2: if this is vnic-3,
8905          * we need to set the entire ilt range for this timers.
8906          */
8907         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8908                 struct ilt_client_info ilt_cli;
8909                 /* use dummy TM client */
8910                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8911                 ilt_cli.start = 0;
8912                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8913                 ilt_cli.client_num = ILT_CLIENT_TM;
8914
8915                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8916         }
8917
8918         /* this assumes that reset_port() called before reset_func()*/
8919         if (!CHIP_IS_E1x(bp))
8920                 bnx2x_pf_disable(bp);
8921
8922         bp->dmae_ready = 0;
8923 }
8924
8925 static void bnx2x_reset_port(struct bnx2x *bp)
8926 {
8927         int port = BP_PORT(bp);
8928         u32 val;
8929
8930         /* Reset physical Link */
8931         bnx2x__link_reset(bp);
8932
8933         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8934
8935         /* Do not rcv packets to BRB */
8936         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8937         /* Do not direct rcv packets that are not for MCP to the BRB */
8938         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8939                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8940
8941         /* Configure AEU */
8942         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8943
8944         msleep(100);
8945         /* Check for BRB port occupancy */
8946         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8947         if (val)
8948                 DP(NETIF_MSG_IFDOWN,
8949                    "BRB1 is not empty  %d blocks are occupied\n", val);
8950
8951         /* TODO: Close Doorbell port? */
8952 }
8953
8954 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8955 {
8956         struct bnx2x_func_state_params func_params = {NULL};
8957
8958         /* Prepare parameters for function state transitions */
8959         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8960
8961         func_params.f_obj = &bp->func_obj;
8962         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8963
8964         func_params.params.hw_init.load_phase = load_code;
8965
8966         return bnx2x_func_state_change(bp, &func_params);
8967 }
8968
8969 static int bnx2x_func_stop(struct bnx2x *bp)
8970 {
8971         struct bnx2x_func_state_params func_params = {NULL};
8972         int rc;
8973
8974         /* Prepare parameters for function state transitions */
8975         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8976         func_params.f_obj = &bp->func_obj;
8977         func_params.cmd = BNX2X_F_CMD_STOP;
8978
8979         /*
8980          * Try to stop the function the 'good way'. If fails (in case
8981          * of a parity error during bnx2x_chip_cleanup()) and we are
8982          * not in a debug mode, perform a state transaction in order to
8983          * enable further HW_RESET transaction.
8984          */
8985         rc = bnx2x_func_state_change(bp, &func_params);
8986         if (rc) {
8987 #ifdef BNX2X_STOP_ON_ERROR
8988                 return rc;
8989 #else
8990                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8991                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8992                 return bnx2x_func_state_change(bp, &func_params);
8993 #endif
8994         }
8995
8996         return 0;
8997 }
8998
8999 /**
9000  * bnx2x_send_unload_req - request unload mode from the MCP.
9001  *
9002  * @bp:                 driver handle
9003  * @unload_mode:        requested function's unload mode
9004  *
9005  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9006  */
9007 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9008 {
9009         u32 reset_code = 0;
9010         int port = BP_PORT(bp);
9011
9012         /* Select the UNLOAD request mode */
9013         if (unload_mode == UNLOAD_NORMAL)
9014                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9015
9016         else if (bp->flags & NO_WOL_FLAG)
9017                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9018
9019         else if (bp->wol) {
9020                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9021                 u8 *mac_addr = bp->dev->dev_addr;
9022                 struct pci_dev *pdev = bp->pdev;
9023                 u32 val;
9024                 u16 pmc;
9025
9026                 /* The mac address is written to entries 1-4 to
9027                  * preserve entry 0 which is used by the PMF
9028                  */
9029                 u8 entry = (BP_VN(bp) + 1)*8;
9030
9031                 val = (mac_addr[0] << 8) | mac_addr[1];
9032                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9033
9034                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9035                       (mac_addr[4] << 8) | mac_addr[5];
9036                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9037
9038                 /* Enable the PME and clear the status */
9039                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9040                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9041                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9042
9043                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9044
9045         } else
9046                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9047
9048         /* Send the request to the MCP */
9049         if (!BP_NOMCP(bp))
9050                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9051         else {
9052                 int path = BP_PATH(bp);
9053
9054                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9055                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9056                    bnx2x_load_count[path][2]);
9057                 bnx2x_load_count[path][0]--;
9058                 bnx2x_load_count[path][1 + port]--;
9059                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9060                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9061                    bnx2x_load_count[path][2]);
9062                 if (bnx2x_load_count[path][0] == 0)
9063                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9064                 else if (bnx2x_load_count[path][1 + port] == 0)
9065                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9066                 else
9067                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9068         }
9069
9070         return reset_code;
9071 }
9072
9073 /**
9074  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9075  *
9076  * @bp:         driver handle
9077  * @keep_link:          true iff link should be kept up
9078  */
9079 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9080 {
9081         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9082
9083         /* Report UNLOAD_DONE to MCP */
9084         if (!BP_NOMCP(bp))
9085                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9086 }
9087
9088 static int bnx2x_func_wait_started(struct bnx2x *bp)
9089 {
9090         int tout = 50;
9091         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9092
9093         if (!bp->port.pmf)
9094                 return 0;
9095
9096         /*
9097          * (assumption: No Attention from MCP at this stage)
9098          * PMF probably in the middle of TX disable/enable transaction
9099          * 1. Sync IRS for default SB
9100          * 2. Sync SP queue - this guarantees us that attention handling started
9101          * 3. Wait, that TX disable/enable transaction completes
9102          *
9103          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9104          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9105          * received completion for the transaction the state is TX_STOPPED.
9106          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9107          * transaction.
9108          */
9109
9110         /* make sure default SB ISR is done */
9111         if (msix)
9112                 synchronize_irq(bp->msix_table[0].vector);
9113         else
9114                 synchronize_irq(bp->pdev->irq);
9115
9116         flush_workqueue(bnx2x_wq);
9117         flush_workqueue(bnx2x_iov_wq);
9118
9119         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9120                                 BNX2X_F_STATE_STARTED && tout--)
9121                 msleep(20);
9122
9123         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9124                                                 BNX2X_F_STATE_STARTED) {
9125 #ifdef BNX2X_STOP_ON_ERROR
9126                 BNX2X_ERR("Wrong function state\n");
9127                 return -EBUSY;
9128 #else
9129                 /*
9130                  * Failed to complete the transaction in a "good way"
9131                  * Force both transactions with CLR bit
9132                  */
9133                 struct bnx2x_func_state_params func_params = {NULL};
9134
9135                 DP(NETIF_MSG_IFDOWN,
9136                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9137
9138                 func_params.f_obj = &bp->func_obj;
9139                 __set_bit(RAMROD_DRV_CLR_ONLY,
9140                                         &func_params.ramrod_flags);
9141
9142                 /* STARTED-->TX_ST0PPED */
9143                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9144                 bnx2x_func_state_change(bp, &func_params);
9145
9146                 /* TX_ST0PPED-->STARTED */
9147                 func_params.cmd = BNX2X_F_CMD_TX_START;
9148                 return bnx2x_func_state_change(bp, &func_params);
9149 #endif
9150         }
9151
9152         return 0;
9153 }
9154
9155 static void bnx2x_disable_ptp(struct bnx2x *bp)
9156 {
9157         int port = BP_PORT(bp);
9158
9159         /* Disable sending PTP packets to host */
9160         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9161                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9162
9163         /* Reset PTP event detection rules */
9164         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9165                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9166         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9167                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9168         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9169                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9170         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9171                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9172
9173         /* Disable the PTP feature */
9174         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9175                NIG_REG_P0_PTP_EN, 0x0);
9176 }
9177
9178 /* Called during unload, to stop PTP-related stuff */
9179 static void bnx2x_stop_ptp(struct bnx2x *bp)
9180 {
9181         /* Cancel PTP work queue. Should be done after the Tx queues are
9182          * drained to prevent additional scheduling.
9183          */
9184         cancel_work_sync(&bp->ptp_task);
9185
9186         if (bp->ptp_tx_skb) {
9187                 dev_kfree_skb_any(bp->ptp_tx_skb);
9188                 bp->ptp_tx_skb = NULL;
9189         }
9190
9191         /* Disable PTP in HW */
9192         bnx2x_disable_ptp(bp);
9193
9194         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9195 }
9196
9197 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9198 {
9199         int port = BP_PORT(bp);
9200         int i, rc = 0;
9201         u8 cos;
9202         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9203         u32 reset_code;
9204
9205         /* Wait until tx fastpath tasks complete */
9206         for_each_tx_queue(bp, i) {
9207                 struct bnx2x_fastpath *fp = &bp->fp[i];
9208
9209                 for_each_cos_in_tx_queue(fp, cos)
9210                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9211 #ifdef BNX2X_STOP_ON_ERROR
9212                 if (rc)
9213                         return;
9214 #endif
9215         }
9216
9217         /* Give HW time to discard old tx messages */
9218         usleep_range(1000, 2000);
9219
9220         /* Clean all ETH MACs */
9221         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9222                                 false);
9223         if (rc < 0)
9224                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9225
9226         /* Clean up UC list  */
9227         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9228                                 true);
9229         if (rc < 0)
9230                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9231                           rc);
9232
9233         /* Disable LLH */
9234         if (!CHIP_IS_E1(bp))
9235                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9236
9237         /* Set "drop all" (stop Rx).
9238          * We need to take a netif_addr_lock() here in order to prevent
9239          * a race between the completion code and this code.
9240          */
9241         netif_addr_lock_bh(bp->dev);
9242         /* Schedule the rx_mode command */
9243         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9244                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9245         else
9246                 bnx2x_set_storm_rx_mode(bp);
9247
9248         /* Cleanup multicast configuration */
9249         rparam.mcast_obj = &bp->mcast_obj;
9250         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9251         if (rc < 0)
9252                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9253
9254         netif_addr_unlock_bh(bp->dev);
9255
9256         bnx2x_iov_chip_cleanup(bp);
9257
9258         /*
9259          * Send the UNLOAD_REQUEST to the MCP. This will return if
9260          * this function should perform FUNC, PORT or COMMON HW
9261          * reset.
9262          */
9263         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9264
9265         /*
9266          * (assumption: No Attention from MCP at this stage)
9267          * PMF probably in the middle of TX disable/enable transaction
9268          */
9269         rc = bnx2x_func_wait_started(bp);
9270         if (rc) {
9271                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9272 #ifdef BNX2X_STOP_ON_ERROR
9273                 return;
9274 #endif
9275         }
9276
9277         /* Close multi and leading connections
9278          * Completions for ramrods are collected in a synchronous way
9279          */
9280         for_each_eth_queue(bp, i)
9281                 if (bnx2x_stop_queue(bp, i))
9282 #ifdef BNX2X_STOP_ON_ERROR
9283                         return;
9284 #else
9285                         goto unload_error;
9286 #endif
9287
9288         if (CNIC_LOADED(bp)) {
9289                 for_each_cnic_queue(bp, i)
9290                         if (bnx2x_stop_queue(bp, i))
9291 #ifdef BNX2X_STOP_ON_ERROR
9292                                 return;
9293 #else
9294                                 goto unload_error;
9295 #endif
9296         }
9297
9298         /* If SP settings didn't get completed so far - something
9299          * very wrong has happen.
9300          */
9301         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9302                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9303
9304 #ifndef BNX2X_STOP_ON_ERROR
9305 unload_error:
9306 #endif
9307         rc = bnx2x_func_stop(bp);
9308         if (rc) {
9309                 BNX2X_ERR("Function stop failed!\n");
9310 #ifdef BNX2X_STOP_ON_ERROR
9311                 return;
9312 #endif
9313         }
9314
9315         /* stop_ptp should be after the Tx queues are drained to prevent
9316          * scheduling to the cancelled PTP work queue. It should also be after
9317          * function stop ramrod is sent, since as part of this ramrod FW access
9318          * PTP registers.
9319          */
9320         if (bp->flags & PTP_SUPPORTED)
9321                 bnx2x_stop_ptp(bp);
9322
9323         /* Disable HW interrupts, NAPI */
9324         bnx2x_netif_stop(bp, 1);
9325         /* Delete all NAPI objects */
9326         bnx2x_del_all_napi(bp);
9327         if (CNIC_LOADED(bp))
9328                 bnx2x_del_all_napi_cnic(bp);
9329
9330         /* Release IRQs */
9331         bnx2x_free_irq(bp);
9332
9333         /* Reset the chip */
9334         rc = bnx2x_reset_hw(bp, reset_code);
9335         if (rc)
9336                 BNX2X_ERR("HW_RESET failed\n");
9337
9338         /* Report UNLOAD_DONE to MCP */
9339         bnx2x_send_unload_done(bp, keep_link);
9340 }
9341
9342 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9343 {
9344         u32 val;
9345
9346         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9347
9348         if (CHIP_IS_E1(bp)) {
9349                 int port = BP_PORT(bp);
9350                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9351                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9352
9353                 val = REG_RD(bp, addr);
9354                 val &= ~(0x300);
9355                 REG_WR(bp, addr, val);
9356         } else {
9357                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9358                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9359                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9360                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9361         }
9362 }
9363
9364 /* Close gates #2, #3 and #4: */
9365 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9366 {
9367         u32 val;
9368
9369         /* Gates #2 and #4a are closed/opened for "not E1" only */
9370         if (!CHIP_IS_E1(bp)) {
9371                 /* #4 */
9372                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9373                 /* #2 */
9374                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9375         }
9376
9377         /* #3 */
9378         if (CHIP_IS_E1x(bp)) {
9379                 /* Prevent interrupts from HC on both ports */
9380                 val = REG_RD(bp, HC_REG_CONFIG_1);
9381                 REG_WR(bp, HC_REG_CONFIG_1,
9382                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9383                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9384
9385                 val = REG_RD(bp, HC_REG_CONFIG_0);
9386                 REG_WR(bp, HC_REG_CONFIG_0,
9387                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9388                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9389         } else {
9390                 /* Prevent incoming interrupts in IGU */
9391                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9392
9393                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9394                        (!close) ?
9395                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9396                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9397         }
9398
9399         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9400                 close ? "closing" : "opening");
9401         mmiowb();
9402 }
9403
9404 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9405
9406 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9407 {
9408         /* Do some magic... */
9409         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9410         *magic_val = val & SHARED_MF_CLP_MAGIC;
9411         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9412 }
9413
9414 /**
9415  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9416  *
9417  * @bp:         driver handle
9418  * @magic_val:  old value of the `magic' bit.
9419  */
9420 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9421 {
9422         /* Restore the `magic' bit value... */
9423         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9424         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9425                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9426 }
9427
9428 /**
9429  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9430  *
9431  * @bp:         driver handle
9432  * @magic_val:  old value of 'magic' bit.
9433  *
9434  * Takes care of CLP configurations.
9435  */
9436 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9437 {
9438         u32 shmem;
9439         u32 validity_offset;
9440
9441         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9442
9443         /* Set `magic' bit in order to save MF config */
9444         if (!CHIP_IS_E1(bp))
9445                 bnx2x_clp_reset_prep(bp, magic_val);
9446
9447         /* Get shmem offset */
9448         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9449         validity_offset =
9450                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9451
9452         /* Clear validity map flags */
9453         if (shmem > 0)
9454                 REG_WR(bp, shmem + validity_offset, 0);
9455 }
9456
9457 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9458 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9459
9460 /**
9461  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9462  *
9463  * @bp: driver handle
9464  */
9465 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9466 {
9467         /* special handling for emulation and FPGA,
9468            wait 10 times longer */
9469         if (CHIP_REV_IS_SLOW(bp))
9470                 msleep(MCP_ONE_TIMEOUT*10);
9471         else
9472                 msleep(MCP_ONE_TIMEOUT);
9473 }
9474
9475 /*
9476  * initializes bp->common.shmem_base and waits for validity signature to appear
9477  */
9478 static int bnx2x_init_shmem(struct bnx2x *bp)
9479 {
9480         int cnt = 0;
9481         u32 val = 0;
9482
9483         do {
9484                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9485                 if (bp->common.shmem_base) {
9486                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9487                         if (val & SHR_MEM_VALIDITY_MB)
9488                                 return 0;
9489                 }
9490
9491                 bnx2x_mcp_wait_one(bp);
9492
9493         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9494
9495         BNX2X_ERR("BAD MCP validity signature\n");
9496
9497         return -ENODEV;
9498 }
9499
9500 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9501 {
9502         int rc = bnx2x_init_shmem(bp);
9503
9504         /* Restore the `magic' bit value */
9505         if (!CHIP_IS_E1(bp))
9506                 bnx2x_clp_reset_done(bp, magic_val);
9507
9508         return rc;
9509 }
9510
9511 static void bnx2x_pxp_prep(struct bnx2x *bp)
9512 {
9513         if (!CHIP_IS_E1(bp)) {
9514                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9515                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9516                 mmiowb();
9517         }
9518 }
9519
9520 /*
9521  * Reset the whole chip except for:
9522  *      - PCIE core
9523  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9524  *              one reset bit)
9525  *      - IGU
9526  *      - MISC (including AEU)
9527  *      - GRC
9528  *      - RBCN, RBCP
9529  */
9530 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9531 {
9532         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9533         u32 global_bits2, stay_reset2;
9534
9535         /*
9536          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9537          * (per chip) blocks.
9538          */
9539         global_bits2 =
9540                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9541                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9542
9543         /* Don't reset the following blocks.
9544          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9545          *            reset, as in 4 port device they might still be owned
9546          *            by the MCP (there is only one leader per path).
9547          */
9548         not_reset_mask1 =
9549                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9550                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9551                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9552
9553         not_reset_mask2 =
9554                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9555                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9556                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9557                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9558                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9559                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9560                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9561                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9562                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9563                 MISC_REGISTERS_RESET_REG_2_PGLC |
9564                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9565                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9566                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9567                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9568                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9569                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9570
9571         /*
9572          * Keep the following blocks in reset:
9573          *  - all xxMACs are handled by the bnx2x_link code.
9574          */
9575         stay_reset2 =
9576                 MISC_REGISTERS_RESET_REG_2_XMAC |
9577                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9578
9579         /* Full reset masks according to the chip */
9580         reset_mask1 = 0xffffffff;
9581
9582         if (CHIP_IS_E1(bp))
9583                 reset_mask2 = 0xffff;
9584         else if (CHIP_IS_E1H(bp))
9585                 reset_mask2 = 0x1ffff;
9586         else if (CHIP_IS_E2(bp))
9587                 reset_mask2 = 0xfffff;
9588         else /* CHIP_IS_E3 */
9589                 reset_mask2 = 0x3ffffff;
9590
9591         /* Don't reset global blocks unless we need to */
9592         if (!global)
9593                 reset_mask2 &= ~global_bits2;
9594
9595         /*
9596          * In case of attention in the QM, we need to reset PXP
9597          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9598          * because otherwise QM reset would release 'close the gates' shortly
9599          * before resetting the PXP, then the PSWRQ would send a write
9600          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9601          * read the payload data from PSWWR, but PSWWR would not
9602          * respond. The write queue in PGLUE would stuck, dmae commands
9603          * would not return. Therefore it's important to reset the second
9604          * reset register (containing the
9605          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9606          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9607          * bit).
9608          */
9609         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9610                reset_mask2 & (~not_reset_mask2));
9611
9612         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9613                reset_mask1 & (~not_reset_mask1));
9614
9615         barrier();
9616         mmiowb();
9617
9618         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9619                reset_mask2 & (~stay_reset2));
9620
9621         barrier();
9622         mmiowb();
9623
9624         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9625         mmiowb();
9626 }
9627
9628 /**
9629  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9630  * It should get cleared in no more than 1s.
9631  *
9632  * @bp: driver handle
9633  *
9634  * It should get cleared in no more than 1s. Returns 0 if
9635  * pending writes bit gets cleared.
9636  */
9637 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9638 {
9639         u32 cnt = 1000;
9640         u32 pend_bits = 0;
9641
9642         do {
9643                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9644
9645                 if (pend_bits == 0)
9646                         break;
9647
9648                 usleep_range(1000, 2000);
9649         } while (cnt-- > 0);
9650
9651         if (cnt <= 0) {
9652                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9653                           pend_bits);
9654                 return -EBUSY;
9655         }
9656
9657         return 0;
9658 }
9659
9660 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9661 {
9662         int cnt = 1000;
9663         u32 val = 0;
9664         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9665         u32 tags_63_32 = 0;
9666
9667         /* Empty the Tetris buffer, wait for 1s */
9668         do {
9669                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9670                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9671                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9672                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9673                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9674                 if (CHIP_IS_E3(bp))
9675                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9676
9677                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9678                     ((port_is_idle_0 & 0x1) == 0x1) &&
9679                     ((port_is_idle_1 & 0x1) == 0x1) &&
9680                     (pgl_exp_rom2 == 0xffffffff) &&
9681                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9682                         break;
9683                 usleep_range(1000, 2000);
9684         } while (cnt-- > 0);
9685
9686         if (cnt <= 0) {
9687                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9688                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9689                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9690                           pgl_exp_rom2);
9691                 return -EAGAIN;
9692         }
9693
9694         barrier();
9695
9696         /* Close gates #2, #3 and #4 */
9697         bnx2x_set_234_gates(bp, true);
9698
9699         /* Poll for IGU VQs for 57712 and newer chips */
9700         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9701                 return -EAGAIN;
9702
9703         /* TBD: Indicate that "process kill" is in progress to MCP */
9704
9705         /* Clear "unprepared" bit */
9706         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9707         barrier();
9708
9709         /* Make sure all is written to the chip before the reset */
9710         mmiowb();
9711
9712         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9713          * PSWHST, GRC and PSWRD Tetris buffer.
9714          */
9715         usleep_range(1000, 2000);
9716
9717         /* Prepare to chip reset: */
9718         /* MCP */
9719         if (global)
9720                 bnx2x_reset_mcp_prep(bp, &val);
9721
9722         /* PXP */
9723         bnx2x_pxp_prep(bp);
9724         barrier();
9725
9726         /* reset the chip */
9727         bnx2x_process_kill_chip_reset(bp, global);
9728         barrier();
9729
9730         /* clear errors in PGB */
9731         if (!CHIP_IS_E1x(bp))
9732                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9733
9734         /* Recover after reset: */
9735         /* MCP */
9736         if (global && bnx2x_reset_mcp_comp(bp, val))
9737                 return -EAGAIN;
9738
9739         /* TBD: Add resetting the NO_MCP mode DB here */
9740
9741         /* Open the gates #2, #3 and #4 */
9742         bnx2x_set_234_gates(bp, false);
9743
9744         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9745          * reset state, re-enable attentions. */
9746
9747         return 0;
9748 }
9749
9750 static int bnx2x_leader_reset(struct bnx2x *bp)
9751 {
9752         int rc = 0;
9753         bool global = bnx2x_reset_is_global(bp);
9754         u32 load_code;
9755
9756         /* if not going to reset MCP - load "fake" driver to reset HW while
9757          * driver is owner of the HW
9758          */
9759         if (!global && !BP_NOMCP(bp)) {
9760                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9761                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9762                 if (!load_code) {
9763                         BNX2X_ERR("MCP response failure, aborting\n");
9764                         rc = -EAGAIN;
9765                         goto exit_leader_reset;
9766                 }
9767                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9768                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9769                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9770                         rc = -EAGAIN;
9771                         goto exit_leader_reset2;
9772                 }
9773                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9774                 if (!load_code) {
9775                         BNX2X_ERR("MCP response failure, aborting\n");
9776                         rc = -EAGAIN;
9777                         goto exit_leader_reset2;
9778                 }
9779         }
9780
9781         /* Try to recover after the failure */
9782         if (bnx2x_process_kill(bp, global)) {
9783                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9784                           BP_PATH(bp));
9785                 rc = -EAGAIN;
9786                 goto exit_leader_reset2;
9787         }
9788
9789         /*
9790          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9791          * state.
9792          */
9793         bnx2x_set_reset_done(bp);
9794         if (global)
9795                 bnx2x_clear_reset_global(bp);
9796
9797 exit_leader_reset2:
9798         /* unload "fake driver" if it was loaded */
9799         if (!global && !BP_NOMCP(bp)) {
9800                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9801                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9802         }
9803 exit_leader_reset:
9804         bp->is_leader = 0;
9805         bnx2x_release_leader_lock(bp);
9806         smp_mb();
9807         return rc;
9808 }
9809
9810 static void bnx2x_recovery_failed(struct bnx2x *bp)
9811 {
9812         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9813
9814         /* Disconnect this device */
9815         netif_device_detach(bp->dev);
9816
9817         /*
9818          * Block ifup for all function on this engine until "process kill"
9819          * or power cycle.
9820          */
9821         bnx2x_set_reset_in_progress(bp);
9822
9823         /* Shut down the power */
9824         bnx2x_set_power_state(bp, PCI_D3hot);
9825
9826         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9827
9828         smp_mb();
9829 }
9830
9831 /*
9832  * Assumption: runs under rtnl lock. This together with the fact
9833  * that it's called only from bnx2x_sp_rtnl() ensure that it
9834  * will never be called when netif_running(bp->dev) is false.
9835  */
9836 static void bnx2x_parity_recover(struct bnx2x *bp)
9837 {
9838         bool global = false;
9839         u32 error_recovered, error_unrecovered;
9840         bool is_parity;
9841
9842         DP(NETIF_MSG_HW, "Handling parity\n");
9843         while (1) {
9844                 switch (bp->recovery_state) {
9845                 case BNX2X_RECOVERY_INIT:
9846                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9847                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9848                         WARN_ON(!is_parity);
9849
9850                         /* Try to get a LEADER_LOCK HW lock */
9851                         if (bnx2x_trylock_leader_lock(bp)) {
9852                                 bnx2x_set_reset_in_progress(bp);
9853                                 /*
9854                                  * Check if there is a global attention and if
9855                                  * there was a global attention, set the global
9856                                  * reset bit.
9857                                  */
9858
9859                                 if (global)
9860                                         bnx2x_set_reset_global(bp);
9861
9862                                 bp->is_leader = 1;
9863                         }
9864
9865                         /* Stop the driver */
9866                         /* If interface has been removed - break */
9867                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9868                                 return;
9869
9870                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9871
9872                         /* Ensure "is_leader", MCP command sequence and
9873                          * "recovery_state" update values are seen on other
9874                          * CPUs.
9875                          */
9876                         smp_mb();
9877                         break;
9878
9879                 case BNX2X_RECOVERY_WAIT:
9880                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9881                         if (bp->is_leader) {
9882                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9883                                 bool other_load_status =
9884                                         bnx2x_get_load_status(bp, other_engine);
9885                                 bool load_status =
9886                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9887                                 global = bnx2x_reset_is_global(bp);
9888
9889                                 /*
9890                                  * In case of a parity in a global block, let
9891                                  * the first leader that performs a
9892                                  * leader_reset() reset the global blocks in
9893                                  * order to clear global attentions. Otherwise
9894                                  * the gates will remain closed for that
9895                                  * engine.
9896                                  */
9897                                 if (load_status ||
9898                                     (global && other_load_status)) {
9899                                         /* Wait until all other functions get
9900                                          * down.
9901                                          */
9902                                         schedule_delayed_work(&bp->sp_rtnl_task,
9903                                                                 HZ/10);
9904                                         return;
9905                                 } else {
9906                                         /* If all other functions got down -
9907                                          * try to bring the chip back to
9908                                          * normal. In any case it's an exit
9909                                          * point for a leader.
9910                                          */
9911                                         if (bnx2x_leader_reset(bp)) {
9912                                                 bnx2x_recovery_failed(bp);
9913                                                 return;
9914                                         }
9915
9916                                         /* If we are here, means that the
9917                                          * leader has succeeded and doesn't
9918                                          * want to be a leader any more. Try
9919                                          * to continue as a none-leader.
9920                                          */
9921                                         break;
9922                                 }
9923                         } else { /* non-leader */
9924                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9925                                         /* Try to get a LEADER_LOCK HW lock as
9926                                          * long as a former leader may have
9927                                          * been unloaded by the user or
9928                                          * released a leadership by another
9929                                          * reason.
9930                                          */
9931                                         if (bnx2x_trylock_leader_lock(bp)) {
9932                                                 /* I'm a leader now! Restart a
9933                                                  * switch case.
9934                                                  */
9935                                                 bp->is_leader = 1;
9936                                                 break;
9937                                         }
9938
9939                                         schedule_delayed_work(&bp->sp_rtnl_task,
9940                                                                 HZ/10);
9941                                         return;
9942
9943                                 } else {
9944                                         /*
9945                                          * If there was a global attention, wait
9946                                          * for it to be cleared.
9947                                          */
9948                                         if (bnx2x_reset_is_global(bp)) {
9949                                                 schedule_delayed_work(
9950                                                         &bp->sp_rtnl_task,
9951                                                         HZ/10);
9952                                                 return;
9953                                         }
9954
9955                                         error_recovered =
9956                                           bp->eth_stats.recoverable_error;
9957                                         error_unrecovered =
9958                                           bp->eth_stats.unrecoverable_error;
9959                                         bp->recovery_state =
9960                                                 BNX2X_RECOVERY_NIC_LOADING;
9961                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9962                                                 error_unrecovered++;
9963                                                 netdev_err(bp->dev,
9964                                                            "Recovery failed. Power cycle needed\n");
9965                                                 /* Disconnect this device */
9966                                                 netif_device_detach(bp->dev);
9967                                                 /* Shut down the power */
9968                                                 bnx2x_set_power_state(
9969                                                         bp, PCI_D3hot);
9970                                                 smp_mb();
9971                                         } else {
9972                                                 bp->recovery_state =
9973                                                         BNX2X_RECOVERY_DONE;
9974                                                 error_recovered++;
9975                                                 smp_mb();
9976                                         }
9977                                         bp->eth_stats.recoverable_error =
9978                                                 error_recovered;
9979                                         bp->eth_stats.unrecoverable_error =
9980                                                 error_unrecovered;
9981
9982                                         return;
9983                                 }
9984                         }
9985                 default:
9986                         return;
9987                 }
9988         }
9989 }
9990
9991 static int bnx2x_close(struct net_device *dev);
9992
9993 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9994  * scheduled on a general queue in order to prevent a dead lock.
9995  */
9996 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9997 {
9998         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9999
10000         rtnl_lock();
10001
10002         if (!netif_running(bp->dev)) {
10003                 rtnl_unlock();
10004                 return;
10005         }
10006
10007         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10008 #ifdef BNX2X_STOP_ON_ERROR
10009                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10010                           "you will need to reboot when done\n");
10011                 goto sp_rtnl_not_reset;
10012 #endif
10013                 /*
10014                  * Clear all pending SP commands as we are going to reset the
10015                  * function anyway.
10016                  */
10017                 bp->sp_rtnl_state = 0;
10018                 smp_mb();
10019
10020                 bnx2x_parity_recover(bp);
10021
10022                 rtnl_unlock();
10023                 return;
10024         }
10025
10026         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10027 #ifdef BNX2X_STOP_ON_ERROR
10028                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10029                           "you will need to reboot when done\n");
10030                 goto sp_rtnl_not_reset;
10031 #endif
10032
10033                 /*
10034                  * Clear all pending SP commands as we are going to reset the
10035                  * function anyway.
10036                  */
10037                 bp->sp_rtnl_state = 0;
10038                 smp_mb();
10039
10040                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10041                 bnx2x_nic_load(bp, LOAD_NORMAL);
10042
10043                 rtnl_unlock();
10044                 return;
10045         }
10046 #ifdef BNX2X_STOP_ON_ERROR
10047 sp_rtnl_not_reset:
10048 #endif
10049         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10050                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10051         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10052                 bnx2x_after_function_update(bp);
10053         /*
10054          * in case of fan failure we need to reset id if the "stop on error"
10055          * debug flag is set, since we trying to prevent permanent overheating
10056          * damage
10057          */
10058         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10059                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10060                 netif_device_detach(bp->dev);
10061                 bnx2x_close(bp->dev);
10062                 rtnl_unlock();
10063                 return;
10064         }
10065
10066         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10067                 DP(BNX2X_MSG_SP,
10068                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10069                 bnx2x_vfpf_set_mcast(bp->dev);
10070         }
10071         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10072                                &bp->sp_rtnl_state)){
10073                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10074                         bnx2x_tx_disable(bp);
10075                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10076                 }
10077         }
10078
10079         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10080                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10081                 bnx2x_set_rx_mode_inner(bp);
10082         }
10083
10084         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10085                                &bp->sp_rtnl_state))
10086                 bnx2x_pf_set_vfs_vlan(bp);
10087
10088         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10089                 bnx2x_dcbx_stop_hw_tx(bp);
10090                 bnx2x_dcbx_resume_hw_tx(bp);
10091         }
10092
10093         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10094                                &bp->sp_rtnl_state))
10095                 bnx2x_update_mng_version(bp);
10096
10097         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10098          * can be called from other contexts as well)
10099          */
10100         rtnl_unlock();
10101
10102         /* enable SR-IOV if applicable */
10103         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10104                                                &bp->sp_rtnl_state)) {
10105                 bnx2x_disable_sriov(bp);
10106                 bnx2x_enable_sriov(bp);
10107         }
10108 }
10109
10110 static void bnx2x_period_task(struct work_struct *work)
10111 {
10112         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10113
10114         if (!netif_running(bp->dev))
10115                 goto period_task_exit;
10116
10117         if (CHIP_REV_IS_SLOW(bp)) {
10118                 BNX2X_ERR("period task called on emulation, ignoring\n");
10119                 goto period_task_exit;
10120         }
10121
10122         bnx2x_acquire_phy_lock(bp);
10123         /*
10124          * The barrier is needed to ensure the ordering between the writing to
10125          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10126          * the reading here.
10127          */
10128         smp_mb();
10129         if (bp->port.pmf) {
10130                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10131
10132                 /* Re-queue task in 1 sec */
10133                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10134         }
10135
10136         bnx2x_release_phy_lock(bp);
10137 period_task_exit:
10138         return;
10139 }
10140
10141 /*
10142  * Init service functions
10143  */
10144
10145 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10146 {
10147         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10148         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10149         return base + (BP_ABS_FUNC(bp)) * stride;
10150 }
10151
10152 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10153                                          u8 port, u32 reset_reg,
10154                                          struct bnx2x_mac_vals *vals)
10155 {
10156         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10157         u32 base_addr;
10158
10159         if (!(mask & reset_reg))
10160                 return false;
10161
10162         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10163         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10164         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10165         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10166         REG_WR(bp, vals->umac_addr[port], 0);
10167
10168         return true;
10169 }
10170
10171 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10172                                         struct bnx2x_mac_vals *vals)
10173 {
10174         u32 val, base_addr, offset, mask, reset_reg;
10175         bool mac_stopped = false;
10176         u8 port = BP_PORT(bp);
10177
10178         /* reset addresses as they also mark which values were changed */
10179         memset(vals, 0, sizeof(*vals));
10180
10181         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10182
10183         if (!CHIP_IS_E3(bp)) {
10184                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10185                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10186                 if ((mask & reset_reg) && val) {
10187                         u32 wb_data[2];
10188                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10189                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10190                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10191                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10192                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10193
10194                         /*
10195                          * use rd/wr since we cannot use dmae. This is safe
10196                          * since MCP won't access the bus due to the request
10197                          * to unload, and no function on the path can be
10198                          * loaded at this time.
10199                          */
10200                         wb_data[0] = REG_RD(bp, base_addr + offset);
10201                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10202                         vals->bmac_addr = base_addr + offset;
10203                         vals->bmac_val[0] = wb_data[0];
10204                         vals->bmac_val[1] = wb_data[1];
10205                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10206                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10207                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10208                 }
10209                 BNX2X_DEV_INFO("Disable emac Rx\n");
10210                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10211                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10212                 REG_WR(bp, vals->emac_addr, 0);
10213                 mac_stopped = true;
10214         } else {
10215                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10216                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10217                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10218                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10219                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10220                                val & ~(1 << 1));
10221                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10222                                val | (1 << 1));
10223                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10224                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10225                         REG_WR(bp, vals->xmac_addr, 0);
10226                         mac_stopped = true;
10227                 }
10228
10229                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10230                                                             reset_reg, vals);
10231                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10232                                                             reset_reg, vals);
10233         }
10234
10235         if (mac_stopped)
10236                 msleep(20);
10237 }
10238
10239 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10240 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10241                                         0x1848 + ((f) << 4))
10242 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10243 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10244 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10245
10246 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10247 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10248 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10249
10250 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10251 {
10252         /* UNDI marks its presence in DORQ -
10253          * it initializes CID offset for normal bell to 0x7
10254          */
10255         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10256             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10257                 return false;
10258
10259         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10260                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10261                 return true;
10262         }
10263
10264         return false;
10265 }
10266
10267 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10268 {
10269         u16 rcq, bd;
10270         u32 addr, tmp_reg;
10271
10272         if (BP_FUNC(bp) < 2)
10273                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10274         else
10275                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10276
10277         tmp_reg = REG_RD(bp, addr);
10278         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10279         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10280
10281         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10282         REG_WR(bp, addr, tmp_reg);
10283
10284         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10285                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10286 }
10287
10288 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10289 {
10290         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10291                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10292         if (!rc) {
10293                 BNX2X_ERR("MCP response failure, aborting\n");
10294                 return -EBUSY;
10295         }
10296
10297         return 0;
10298 }
10299
10300 static struct bnx2x_prev_path_list *
10301                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10302 {
10303         struct bnx2x_prev_path_list *tmp_list;
10304
10305         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10306                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10307                     bp->pdev->bus->number == tmp_list->bus &&
10308                     BP_PATH(bp) == tmp_list->path)
10309                         return tmp_list;
10310
10311         return NULL;
10312 }
10313
10314 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10315 {
10316         struct bnx2x_prev_path_list *tmp_list;
10317         int rc;
10318
10319         rc = down_interruptible(&bnx2x_prev_sem);
10320         if (rc) {
10321                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10322                 return rc;
10323         }
10324
10325         tmp_list = bnx2x_prev_path_get_entry(bp);
10326         if (tmp_list) {
10327                 tmp_list->aer = 1;
10328                 rc = 0;
10329         } else {
10330                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10331                           BP_PATH(bp));
10332         }
10333
10334         up(&bnx2x_prev_sem);
10335
10336         return rc;
10337 }
10338
10339 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10340 {
10341         struct bnx2x_prev_path_list *tmp_list;
10342         bool rc = false;
10343
10344         if (down_trylock(&bnx2x_prev_sem))
10345                 return false;
10346
10347         tmp_list = bnx2x_prev_path_get_entry(bp);
10348         if (tmp_list) {
10349                 if (tmp_list->aer) {
10350                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10351                            BP_PATH(bp));
10352                 } else {
10353                         rc = true;
10354                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10355                                        BP_PATH(bp));
10356                 }
10357         }
10358
10359         up(&bnx2x_prev_sem);
10360
10361         return rc;
10362 }
10363
10364 bool bnx2x_port_after_undi(struct bnx2x *bp)
10365 {
10366         struct bnx2x_prev_path_list *entry;
10367         bool val;
10368
10369         down(&bnx2x_prev_sem);
10370
10371         entry = bnx2x_prev_path_get_entry(bp);
10372         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10373
10374         up(&bnx2x_prev_sem);
10375
10376         return val;
10377 }
10378
10379 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10380 {
10381         struct bnx2x_prev_path_list *tmp_list;
10382         int rc;
10383
10384         rc = down_interruptible(&bnx2x_prev_sem);
10385         if (rc) {
10386                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10387                 return rc;
10388         }
10389
10390         /* Check whether the entry for this path already exists */
10391         tmp_list = bnx2x_prev_path_get_entry(bp);
10392         if (tmp_list) {
10393                 if (!tmp_list->aer) {
10394                         BNX2X_ERR("Re-Marking the path.\n");
10395                 } else {
10396                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10397                            BP_PATH(bp));
10398                         tmp_list->aer = 0;
10399                 }
10400                 up(&bnx2x_prev_sem);
10401                 return 0;
10402         }
10403         up(&bnx2x_prev_sem);
10404
10405         /* Create an entry for this path and add it */
10406         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10407         if (!tmp_list) {
10408                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10409                 return -ENOMEM;
10410         }
10411
10412         tmp_list->bus = bp->pdev->bus->number;
10413         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10414         tmp_list->path = BP_PATH(bp);
10415         tmp_list->aer = 0;
10416         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10417
10418         rc = down_interruptible(&bnx2x_prev_sem);
10419         if (rc) {
10420                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10421                 kfree(tmp_list);
10422         } else {
10423                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10424                    BP_PATH(bp));
10425                 list_add(&tmp_list->list, &bnx2x_prev_list);
10426                 up(&bnx2x_prev_sem);
10427         }
10428
10429         return rc;
10430 }
10431
10432 static int bnx2x_do_flr(struct bnx2x *bp)
10433 {
10434         struct pci_dev *dev = bp->pdev;
10435
10436         if (CHIP_IS_E1x(bp)) {
10437                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10438                 return -EINVAL;
10439         }
10440
10441         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10442         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10443                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10444                           bp->common.bc_ver);
10445                 return -EINVAL;
10446         }
10447
10448         if (!pci_wait_for_pending_transaction(dev))
10449                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10450
10451         BNX2X_DEV_INFO("Initiating FLR\n");
10452         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10453
10454         return 0;
10455 }
10456
10457 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10458 {
10459         int rc;
10460
10461         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10462
10463         /* Test if previous unload process was already finished for this path */
10464         if (bnx2x_prev_is_path_marked(bp))
10465                 return bnx2x_prev_mcp_done(bp);
10466
10467         BNX2X_DEV_INFO("Path is unmarked\n");
10468
10469         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10470         if (bnx2x_prev_is_after_undi(bp))
10471                 goto out;
10472
10473         /* If function has FLR capabilities, and existing FW version matches
10474          * the one required, then FLR will be sufficient to clean any residue
10475          * left by previous driver
10476          */
10477         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10478
10479         if (!rc) {
10480                 /* fw version is good */
10481                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10482                 rc = bnx2x_do_flr(bp);
10483         }
10484
10485         if (!rc) {
10486                 /* FLR was performed */
10487                 BNX2X_DEV_INFO("FLR successful\n");
10488                 return 0;
10489         }
10490
10491         BNX2X_DEV_INFO("Could not FLR\n");
10492
10493 out:
10494         /* Close the MCP request, return failure*/
10495         rc = bnx2x_prev_mcp_done(bp);
10496         if (!rc)
10497                 rc = BNX2X_PREV_WAIT_NEEDED;
10498
10499         return rc;
10500 }
10501
10502 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10503 {
10504         u32 reset_reg, tmp_reg = 0, rc;
10505         bool prev_undi = false;
10506         struct bnx2x_mac_vals mac_vals;
10507
10508         /* It is possible a previous function received 'common' answer,
10509          * but hasn't loaded yet, therefore creating a scenario of
10510          * multiple functions receiving 'common' on the same path.
10511          */
10512         BNX2X_DEV_INFO("Common unload Flow\n");
10513
10514         memset(&mac_vals, 0, sizeof(mac_vals));
10515
10516         if (bnx2x_prev_is_path_marked(bp))
10517                 return bnx2x_prev_mcp_done(bp);
10518
10519         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10520
10521         /* Reset should be performed after BRB is emptied */
10522         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10523                 u32 timer_count = 1000;
10524
10525                 /* Close the MAC Rx to prevent BRB from filling up */
10526                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10527
10528                 /* close LLH filters for both ports towards the BRB */
10529                 bnx2x_set_rx_filter(&bp->link_params, 0);
10530                 bp->link_params.port ^= 1;
10531                 bnx2x_set_rx_filter(&bp->link_params, 0);
10532                 bp->link_params.port ^= 1;
10533
10534                 /* Check if the UNDI driver was previously loaded */
10535                 if (bnx2x_prev_is_after_undi(bp)) {
10536                         prev_undi = true;
10537                         /* clear the UNDI indication */
10538                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10539                         /* clear possible idle check errors */
10540                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10541                 }
10542                 if (!CHIP_IS_E1x(bp))
10543                         /* block FW from writing to host */
10544                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10545
10546                 /* wait until BRB is empty */
10547                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10548                 while (timer_count) {
10549                         u32 prev_brb = tmp_reg;
10550
10551                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10552                         if (!tmp_reg)
10553                                 break;
10554
10555                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10556
10557                         /* reset timer as long as BRB actually gets emptied */
10558                         if (prev_brb > tmp_reg)
10559                                 timer_count = 1000;
10560                         else
10561                                 timer_count--;
10562
10563                         /* If UNDI resides in memory, manually increment it */
10564                         if (prev_undi)
10565                                 bnx2x_prev_unload_undi_inc(bp, 1);
10566
10567                         udelay(10);
10568                 }
10569
10570                 if (!timer_count)
10571                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10572         }
10573
10574         /* No packets are in the pipeline, path is ready for reset */
10575         bnx2x_reset_common(bp);
10576
10577         if (mac_vals.xmac_addr)
10578                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10579         if (mac_vals.umac_addr[0])
10580                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10581         if (mac_vals.umac_addr[1])
10582                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10583         if (mac_vals.emac_addr)
10584                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10585         if (mac_vals.bmac_addr) {
10586                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10587                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10588         }
10589
10590         rc = bnx2x_prev_mark_path(bp, prev_undi);
10591         if (rc) {
10592                 bnx2x_prev_mcp_done(bp);
10593                 return rc;
10594         }
10595
10596         return bnx2x_prev_mcp_done(bp);
10597 }
10598
10599 static int bnx2x_prev_unload(struct bnx2x *bp)
10600 {
10601         int time_counter = 10;
10602         u32 rc, fw, hw_lock_reg, hw_lock_val;
10603         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10604
10605         /* clear hw from errors which may have resulted from an interrupted
10606          * dmae transaction.
10607          */
10608         bnx2x_clean_pglue_errors(bp);
10609
10610         /* Release previously held locks */
10611         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10612                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10613                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10614
10615         hw_lock_val = REG_RD(bp, hw_lock_reg);
10616         if (hw_lock_val) {
10617                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10618                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10619                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10620                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10621                 }
10622
10623                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10624                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10625         } else
10626                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10627
10628         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10629                 BNX2X_DEV_INFO("Release previously held alr\n");
10630                 bnx2x_release_alr(bp);
10631         }
10632
10633         do {
10634                 int aer = 0;
10635                 /* Lock MCP using an unload request */
10636                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10637                 if (!fw) {
10638                         BNX2X_ERR("MCP response failure, aborting\n");
10639                         rc = -EBUSY;
10640                         break;
10641                 }
10642
10643                 rc = down_interruptible(&bnx2x_prev_sem);
10644                 if (rc) {
10645                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10646                                   rc);
10647                 } else {
10648                         /* If Path is marked by EEH, ignore unload status */
10649                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10650                                  bnx2x_prev_path_get_entry(bp)->aer);
10651                         up(&bnx2x_prev_sem);
10652                 }
10653
10654                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10655                         rc = bnx2x_prev_unload_common(bp);
10656                         break;
10657                 }
10658
10659                 /* non-common reply from MCP might require looping */
10660                 rc = bnx2x_prev_unload_uncommon(bp);
10661                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10662                         break;
10663
10664                 msleep(20);
10665         } while (--time_counter);
10666
10667         if (!time_counter || rc) {
10668                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10669                 rc = -EPROBE_DEFER;
10670         }
10671
10672         /* Mark function if its port was used to boot from SAN */
10673         if (bnx2x_port_after_undi(bp))
10674                 bp->link_params.feature_config_flags |=
10675                         FEATURE_CONFIG_BOOT_FROM_SAN;
10676
10677         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10678
10679         return rc;
10680 }
10681
10682 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10683 {
10684         u32 val, val2, val3, val4, id, boot_mode;
10685         u16 pmc;
10686
10687         /* Get the chip revision id and number. */
10688         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10689         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10690         id = ((val & 0xffff) << 16);
10691         val = REG_RD(bp, MISC_REG_CHIP_REV);
10692         id |= ((val & 0xf) << 12);
10693
10694         /* Metal is read from PCI regs, but we can't access >=0x400 from
10695          * the configuration space (so we need to reg_rd)
10696          */
10697         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10698         id |= (((val >> 24) & 0xf) << 4);
10699         val = REG_RD(bp, MISC_REG_BOND_ID);
10700         id |= (val & 0xf);
10701         bp->common.chip_id = id;
10702
10703         /* force 57811 according to MISC register */
10704         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10705                 if (CHIP_IS_57810(bp))
10706                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10707                                 (bp->common.chip_id & 0x0000FFFF);
10708                 else if (CHIP_IS_57810_MF(bp))
10709                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10710                                 (bp->common.chip_id & 0x0000FFFF);
10711                 bp->common.chip_id |= 0x1;
10712         }
10713
10714         /* Set doorbell size */
10715         bp->db_size = (1 << BNX2X_DB_SHIFT);
10716
10717         if (!CHIP_IS_E1x(bp)) {
10718                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10719                 if ((val & 1) == 0)
10720                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10721                 else
10722                         val = (val >> 1) & 1;
10723                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10724                                                        "2_PORT_MODE");
10725                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10726                                                  CHIP_2_PORT_MODE;
10727
10728                 if (CHIP_MODE_IS_4_PORT(bp))
10729                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10730                 else
10731                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10732         } else {
10733                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10734                 bp->pfid = bp->pf_num;                  /* 0..7 */
10735         }
10736
10737         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10738
10739         bp->link_params.chip_id = bp->common.chip_id;
10740         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10741
10742         val = (REG_RD(bp, 0x2874) & 0x55);
10743         if ((bp->common.chip_id & 0x1) ||
10744             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10745                 bp->flags |= ONE_PORT_FLAG;
10746                 BNX2X_DEV_INFO("single port device\n");
10747         }
10748
10749         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10750         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10751                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10752         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10753                        bp->common.flash_size, bp->common.flash_size);
10754
10755         bnx2x_init_shmem(bp);
10756
10757         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10758                                         MISC_REG_GENERIC_CR_1 :
10759                                         MISC_REG_GENERIC_CR_0));
10760
10761         bp->link_params.shmem_base = bp->common.shmem_base;
10762         bp->link_params.shmem2_base = bp->common.shmem2_base;
10763         if (SHMEM2_RD(bp, size) >
10764             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10765                 bp->link_params.lfa_base =
10766                 REG_RD(bp, bp->common.shmem2_base +
10767                        (u32)offsetof(struct shmem2_region,
10768                                      lfa_host_addr[BP_PORT(bp)]));
10769         else
10770                 bp->link_params.lfa_base = 0;
10771         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10772                        bp->common.shmem_base, bp->common.shmem2_base);
10773
10774         if (!bp->common.shmem_base) {
10775                 BNX2X_DEV_INFO("MCP not active\n");
10776                 bp->flags |= NO_MCP_FLAG;
10777                 return;
10778         }
10779
10780         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10781         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10782
10783         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10784                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10785                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10786
10787         bp->link_params.feature_config_flags = 0;
10788         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10789         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10790                 bp->link_params.feature_config_flags |=
10791                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10792         else
10793                 bp->link_params.feature_config_flags &=
10794                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10795
10796         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10797         bp->common.bc_ver = val;
10798         BNX2X_DEV_INFO("bc_ver %X\n", val);
10799         if (val < BNX2X_BC_VER) {
10800                 /* for now only warn
10801                  * later we might need to enforce this */
10802                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10803                           BNX2X_BC_VER, val);
10804         }
10805         bp->link_params.feature_config_flags |=
10806                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10807                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10808
10809         bp->link_params.feature_config_flags |=
10810                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10811                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10812         bp->link_params.feature_config_flags |=
10813                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10814                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10815         bp->link_params.feature_config_flags |=
10816                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10817                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10818
10819         bp->link_params.feature_config_flags |=
10820                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10821                 FEATURE_CONFIG_MT_SUPPORT : 0;
10822
10823         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10824                         BC_SUPPORTS_PFC_STATS : 0;
10825
10826         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10827                         BC_SUPPORTS_FCOE_FEATURES : 0;
10828
10829         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10830                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10831
10832         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10833                         BC_SUPPORTS_RMMOD_CMD : 0;
10834
10835         boot_mode = SHMEM_RD(bp,
10836                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10837                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10838         switch (boot_mode) {
10839         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10840                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10841                 break;
10842         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10843                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10844                 break;
10845         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10846                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10847                 break;
10848         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10849                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10850                 break;
10851         }
10852
10853         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10854         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10855
10856         BNX2X_DEV_INFO("%sWoL capable\n",
10857                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10858
10859         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10860         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10861         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10862         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10863
10864         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10865                  val, val2, val3, val4);
10866 }
10867
10868 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10869 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10870
10871 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10872 {
10873         int pfid = BP_FUNC(bp);
10874         int igu_sb_id;
10875         u32 val;
10876         u8 fid, igu_sb_cnt = 0;
10877
10878         bp->igu_base_sb = 0xff;
10879         if (CHIP_INT_MODE_IS_BC(bp)) {
10880                 int vn = BP_VN(bp);
10881                 igu_sb_cnt = bp->igu_sb_cnt;
10882                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10883                         FP_SB_MAX_E1x;
10884
10885                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10886                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10887
10888                 return 0;
10889         }
10890
10891         /* IGU in normal mode - read CAM */
10892         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10893              igu_sb_id++) {
10894                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10895                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10896                         continue;
10897                 fid = IGU_FID(val);
10898                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10899                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10900                                 continue;
10901                         if (IGU_VEC(val) == 0)
10902                                 /* default status block */
10903                                 bp->igu_dsb_id = igu_sb_id;
10904                         else {
10905                                 if (bp->igu_base_sb == 0xff)
10906                                         bp->igu_base_sb = igu_sb_id;
10907                                 igu_sb_cnt++;
10908                         }
10909                 }
10910         }
10911
10912 #ifdef CONFIG_PCI_MSI
10913         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10914          * optional that number of CAM entries will not be equal to the value
10915          * advertised in PCI.
10916          * Driver should use the minimal value of both as the actual status
10917          * block count
10918          */
10919         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10920 #endif
10921
10922         if (igu_sb_cnt == 0) {
10923                 BNX2X_ERR("CAM configuration error\n");
10924                 return -EINVAL;
10925         }
10926
10927         return 0;
10928 }
10929
10930 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10931 {
10932         int cfg_size = 0, idx, port = BP_PORT(bp);
10933
10934         /* Aggregation of supported attributes of all external phys */
10935         bp->port.supported[0] = 0;
10936         bp->port.supported[1] = 0;
10937         switch (bp->link_params.num_phys) {
10938         case 1:
10939                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10940                 cfg_size = 1;
10941                 break;
10942         case 2:
10943                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10944                 cfg_size = 1;
10945                 break;
10946         case 3:
10947                 if (bp->link_params.multi_phy_config &
10948                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10949                         bp->port.supported[1] =
10950                                 bp->link_params.phy[EXT_PHY1].supported;
10951                         bp->port.supported[0] =
10952                                 bp->link_params.phy[EXT_PHY2].supported;
10953                 } else {
10954                         bp->port.supported[0] =
10955                                 bp->link_params.phy[EXT_PHY1].supported;
10956                         bp->port.supported[1] =
10957                                 bp->link_params.phy[EXT_PHY2].supported;
10958                 }
10959                 cfg_size = 2;
10960                 break;
10961         }
10962
10963         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10964                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10965                            SHMEM_RD(bp,
10966                            dev_info.port_hw_config[port].external_phy_config),
10967                            SHMEM_RD(bp,
10968                            dev_info.port_hw_config[port].external_phy_config2));
10969                         return;
10970         }
10971
10972         if (CHIP_IS_E3(bp))
10973                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10974         else {
10975                 switch (switch_cfg) {
10976                 case SWITCH_CFG_1G:
10977                         bp->port.phy_addr = REG_RD(
10978                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10979                         break;
10980                 case SWITCH_CFG_10G:
10981                         bp->port.phy_addr = REG_RD(
10982                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10983                         break;
10984                 default:
10985                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10986                                   bp->port.link_config[0]);
10987                         return;
10988                 }
10989         }
10990         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10991         /* mask what we support according to speed_cap_mask per configuration */
10992         for (idx = 0; idx < cfg_size; idx++) {
10993                 if (!(bp->link_params.speed_cap_mask[idx] &
10994                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10995                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10996
10997                 if (!(bp->link_params.speed_cap_mask[idx] &
10998                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10999                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11000
11001                 if (!(bp->link_params.speed_cap_mask[idx] &
11002                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11003                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11004
11005                 if (!(bp->link_params.speed_cap_mask[idx] &
11006                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11007                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11008
11009                 if (!(bp->link_params.speed_cap_mask[idx] &
11010                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11011                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11012                                                      SUPPORTED_1000baseT_Full);
11013
11014                 if (!(bp->link_params.speed_cap_mask[idx] &
11015                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11016                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11017
11018                 if (!(bp->link_params.speed_cap_mask[idx] &
11019                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11020                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11021
11022                 if (!(bp->link_params.speed_cap_mask[idx] &
11023                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11024                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11025         }
11026
11027         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11028                        bp->port.supported[1]);
11029 }
11030
11031 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11032 {
11033         u32 link_config, idx, cfg_size = 0;
11034         bp->port.advertising[0] = 0;
11035         bp->port.advertising[1] = 0;
11036         switch (bp->link_params.num_phys) {
11037         case 1:
11038         case 2:
11039                 cfg_size = 1;
11040                 break;
11041         case 3:
11042                 cfg_size = 2;
11043                 break;
11044         }
11045         for (idx = 0; idx < cfg_size; idx++) {
11046                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11047                 link_config = bp->port.link_config[idx];
11048                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11049                 case PORT_FEATURE_LINK_SPEED_AUTO:
11050                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11051                                 bp->link_params.req_line_speed[idx] =
11052                                         SPEED_AUTO_NEG;
11053                                 bp->port.advertising[idx] |=
11054                                         bp->port.supported[idx];
11055                                 if (bp->link_params.phy[EXT_PHY1].type ==
11056                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11057                                         bp->port.advertising[idx] |=
11058                                         (SUPPORTED_100baseT_Half |
11059                                          SUPPORTED_100baseT_Full);
11060                         } else {
11061                                 /* force 10G, no AN */
11062                                 bp->link_params.req_line_speed[idx] =
11063                                         SPEED_10000;
11064                                 bp->port.advertising[idx] |=
11065                                         (ADVERTISED_10000baseT_Full |
11066                                          ADVERTISED_FIBRE);
11067                                 continue;
11068                         }
11069                         break;
11070
11071                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11072                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11073                                 bp->link_params.req_line_speed[idx] =
11074                                         SPEED_10;
11075                                 bp->port.advertising[idx] |=
11076                                         (ADVERTISED_10baseT_Full |
11077                                          ADVERTISED_TP);
11078                         } else {
11079                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11080                                             link_config,
11081                                     bp->link_params.speed_cap_mask[idx]);
11082                                 return;
11083                         }
11084                         break;
11085
11086                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11087                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11088                                 bp->link_params.req_line_speed[idx] =
11089                                         SPEED_10;
11090                                 bp->link_params.req_duplex[idx] =
11091                                         DUPLEX_HALF;
11092                                 bp->port.advertising[idx] |=
11093                                         (ADVERTISED_10baseT_Half |
11094                                          ADVERTISED_TP);
11095                         } else {
11096                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11097                                             link_config,
11098                                           bp->link_params.speed_cap_mask[idx]);
11099                                 return;
11100                         }
11101                         break;
11102
11103                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11104                         if (bp->port.supported[idx] &
11105                             SUPPORTED_100baseT_Full) {
11106                                 bp->link_params.req_line_speed[idx] =
11107                                         SPEED_100;
11108                                 bp->port.advertising[idx] |=
11109                                         (ADVERTISED_100baseT_Full |
11110                                          ADVERTISED_TP);
11111                         } else {
11112                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11113                                             link_config,
11114                                           bp->link_params.speed_cap_mask[idx]);
11115                                 return;
11116                         }
11117                         break;
11118
11119                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11120                         if (bp->port.supported[idx] &
11121                             SUPPORTED_100baseT_Half) {
11122                                 bp->link_params.req_line_speed[idx] =
11123                                                                 SPEED_100;
11124                                 bp->link_params.req_duplex[idx] =
11125                                                                 DUPLEX_HALF;
11126                                 bp->port.advertising[idx] |=
11127                                         (ADVERTISED_100baseT_Half |
11128                                          ADVERTISED_TP);
11129                         } else {
11130                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11131                                     link_config,
11132                                     bp->link_params.speed_cap_mask[idx]);
11133                                 return;
11134                         }
11135                         break;
11136
11137                 case PORT_FEATURE_LINK_SPEED_1G:
11138                         if (bp->port.supported[idx] &
11139                             SUPPORTED_1000baseT_Full) {
11140                                 bp->link_params.req_line_speed[idx] =
11141                                         SPEED_1000;
11142                                 bp->port.advertising[idx] |=
11143                                         (ADVERTISED_1000baseT_Full |
11144                                          ADVERTISED_TP);
11145                         } else {
11146                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11147                                     link_config,
11148                                     bp->link_params.speed_cap_mask[idx]);
11149                                 return;
11150                         }
11151                         break;
11152
11153                 case PORT_FEATURE_LINK_SPEED_2_5G:
11154                         if (bp->port.supported[idx] &
11155                             SUPPORTED_2500baseX_Full) {
11156                                 bp->link_params.req_line_speed[idx] =
11157                                         SPEED_2500;
11158                                 bp->port.advertising[idx] |=
11159                                         (ADVERTISED_2500baseX_Full |
11160                                                 ADVERTISED_TP);
11161                         } else {
11162                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11163                                     link_config,
11164                                     bp->link_params.speed_cap_mask[idx]);
11165                                 return;
11166                         }
11167                         break;
11168
11169                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11170                         if (bp->port.supported[idx] &
11171                             SUPPORTED_10000baseT_Full) {
11172                                 bp->link_params.req_line_speed[idx] =
11173                                         SPEED_10000;
11174                                 bp->port.advertising[idx] |=
11175                                         (ADVERTISED_10000baseT_Full |
11176                                                 ADVERTISED_FIBRE);
11177                         } else {
11178                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11179                                     link_config,
11180                                     bp->link_params.speed_cap_mask[idx]);
11181                                 return;
11182                         }
11183                         break;
11184                 case PORT_FEATURE_LINK_SPEED_20G:
11185                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11186
11187                         break;
11188                 default:
11189                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11190                                   link_config);
11191                                 bp->link_params.req_line_speed[idx] =
11192                                                         SPEED_AUTO_NEG;
11193                                 bp->port.advertising[idx] =
11194                                                 bp->port.supported[idx];
11195                         break;
11196                 }
11197
11198                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11199                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11200                 if (bp->link_params.req_flow_ctrl[idx] ==
11201                     BNX2X_FLOW_CTRL_AUTO) {
11202                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11203                                 bp->link_params.req_flow_ctrl[idx] =
11204                                                         BNX2X_FLOW_CTRL_NONE;
11205                         else
11206                                 bnx2x_set_requested_fc(bp);
11207                 }
11208
11209                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11210                                bp->link_params.req_line_speed[idx],
11211                                bp->link_params.req_duplex[idx],
11212                                bp->link_params.req_flow_ctrl[idx],
11213                                bp->port.advertising[idx]);
11214         }
11215 }
11216
11217 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11218 {
11219         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11220         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11221         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11222         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11223 }
11224
11225 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11226 {
11227         int port = BP_PORT(bp);
11228         u32 config;
11229         u32 ext_phy_type, ext_phy_config, eee_mode;
11230
11231         bp->link_params.bp = bp;
11232         bp->link_params.port = port;
11233
11234         bp->link_params.lane_config =
11235                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11236
11237         bp->link_params.speed_cap_mask[0] =
11238                 SHMEM_RD(bp,
11239                          dev_info.port_hw_config[port].speed_capability_mask) &
11240                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11241         bp->link_params.speed_cap_mask[1] =
11242                 SHMEM_RD(bp,
11243                          dev_info.port_hw_config[port].speed_capability_mask2) &
11244                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11245         bp->port.link_config[0] =
11246                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11247
11248         bp->port.link_config[1] =
11249                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11250
11251         bp->link_params.multi_phy_config =
11252                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11253         /* If the device is capable of WoL, set the default state according
11254          * to the HW
11255          */
11256         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11257         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11258                    (config & PORT_FEATURE_WOL_ENABLED));
11259
11260         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11261             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11262                 bp->flags |= NO_ISCSI_FLAG;
11263         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11264             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11265                 bp->flags |= NO_FCOE_FLAG;
11266
11267         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11268                        bp->link_params.lane_config,
11269                        bp->link_params.speed_cap_mask[0],
11270                        bp->port.link_config[0]);
11271
11272         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11273                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11274         bnx2x_phy_probe(&bp->link_params);
11275         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11276
11277         bnx2x_link_settings_requested(bp);
11278
11279         /*
11280          * If connected directly, work with the internal PHY, otherwise, work
11281          * with the external PHY
11282          */
11283         ext_phy_config =
11284                 SHMEM_RD(bp,
11285                          dev_info.port_hw_config[port].external_phy_config);
11286         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11287         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11288                 bp->mdio.prtad = bp->port.phy_addr;
11289
11290         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11291                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11292                 bp->mdio.prtad =
11293                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11294
11295         /* Configure link feature according to nvram value */
11296         eee_mode = (((SHMEM_RD(bp, dev_info.
11297                       port_feature_config[port].eee_power_mode)) &
11298                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11299                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11300         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11301                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11302                                            EEE_MODE_ENABLE_LPI |
11303                                            EEE_MODE_OUTPUT_TIME;
11304         } else {
11305                 bp->link_params.eee_mode = 0;
11306         }
11307 }
11308
11309 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11310 {
11311         u32 no_flags = NO_ISCSI_FLAG;
11312         int port = BP_PORT(bp);
11313         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11314                                 drv_lic_key[port].max_iscsi_conn);
11315
11316         if (!CNIC_SUPPORT(bp)) {
11317                 bp->flags |= no_flags;
11318                 return;
11319         }
11320
11321         /* Get the number of maximum allowed iSCSI connections */
11322         bp->cnic_eth_dev.max_iscsi_conn =
11323                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11324                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11325
11326         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11327                        bp->cnic_eth_dev.max_iscsi_conn);
11328
11329         /*
11330          * If maximum allowed number of connections is zero -
11331          * disable the feature.
11332          */
11333         if (!bp->cnic_eth_dev.max_iscsi_conn)
11334                 bp->flags |= no_flags;
11335 }
11336
11337 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11338 {
11339         /* Port info */
11340         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11341                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11342         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11343                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11344
11345         /* Node info */
11346         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11347                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11348         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11349                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11350 }
11351
11352 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11353 {
11354         u8 count = 0;
11355
11356         if (IS_MF(bp)) {
11357                 u8 fid;
11358
11359                 /* iterate over absolute function ids for this path: */
11360                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11361                         if (IS_MF_SD(bp)) {
11362                                 u32 cfg = MF_CFG_RD(bp,
11363                                                     func_mf_config[fid].config);
11364
11365                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11366                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11367                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11368                                         count++;
11369                         } else {
11370                                 u32 cfg = MF_CFG_RD(bp,
11371                                                     func_ext_config[fid].
11372                                                                       func_cfg);
11373
11374                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11375                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11376                                         count++;
11377                         }
11378                 }
11379         } else { /* SF */
11380                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11381
11382                 for (port = 0; port < port_cnt; port++) {
11383                         u32 lic = SHMEM_RD(bp,
11384                                            drv_lic_key[port].max_fcoe_conn) ^
11385                                   FW_ENCODE_32BIT_PATTERN;
11386                         if (lic)
11387                                 count++;
11388                 }
11389         }
11390
11391         return count;
11392 }
11393
11394 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11395 {
11396         int port = BP_PORT(bp);
11397         int func = BP_ABS_FUNC(bp);
11398         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11399                                 drv_lic_key[port].max_fcoe_conn);
11400         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11401
11402         if (!CNIC_SUPPORT(bp)) {
11403                 bp->flags |= NO_FCOE_FLAG;
11404                 return;
11405         }
11406
11407         /* Get the number of maximum allowed FCoE connections */
11408         bp->cnic_eth_dev.max_fcoe_conn =
11409                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11410                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11411
11412         /* Calculate the number of maximum allowed FCoE tasks */
11413         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11414
11415         /* check if FCoE resources must be shared between different functions */
11416         if (num_fcoe_func)
11417                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11418
11419         /* Read the WWN: */
11420         if (!IS_MF(bp)) {
11421                 /* Port info */
11422                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11423                         SHMEM_RD(bp,
11424                                  dev_info.port_hw_config[port].
11425                                  fcoe_wwn_port_name_upper);
11426                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11427                         SHMEM_RD(bp,
11428                                  dev_info.port_hw_config[port].
11429                                  fcoe_wwn_port_name_lower);
11430
11431                 /* Node info */
11432                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11433                         SHMEM_RD(bp,
11434                                  dev_info.port_hw_config[port].
11435                                  fcoe_wwn_node_name_upper);
11436                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11437                         SHMEM_RD(bp,
11438                                  dev_info.port_hw_config[port].
11439                                  fcoe_wwn_node_name_lower);
11440         } else if (!IS_MF_SD(bp)) {
11441                 /* Read the WWN info only if the FCoE feature is enabled for
11442                  * this function.
11443                  */
11444                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11445                         bnx2x_get_ext_wwn_info(bp, func);
11446         } else {
11447                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11448                         bnx2x_get_ext_wwn_info(bp, func);
11449         }
11450
11451         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11452
11453         /*
11454          * If maximum allowed number of connections is zero -
11455          * disable the feature.
11456          */
11457         if (!bp->cnic_eth_dev.max_fcoe_conn)
11458                 bp->flags |= NO_FCOE_FLAG;
11459 }
11460
11461 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11462 {
11463         /*
11464          * iSCSI may be dynamically disabled but reading
11465          * info here we will decrease memory usage by driver
11466          * if the feature is disabled for good
11467          */
11468         bnx2x_get_iscsi_info(bp);
11469         bnx2x_get_fcoe_info(bp);
11470 }
11471
11472 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11473 {
11474         u32 val, val2;
11475         int func = BP_ABS_FUNC(bp);
11476         int port = BP_PORT(bp);
11477         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11478         u8 *fip_mac = bp->fip_mac;
11479
11480         if (IS_MF(bp)) {
11481                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11482                  * FCoE MAC then the appropriate feature should be disabled.
11483                  * In non SD mode features configuration comes from struct
11484                  * func_ext_config.
11485                  */
11486                 if (!IS_MF_SD(bp)) {
11487                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11488                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11489                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11490                                                  iscsi_mac_addr_upper);
11491                                 val = MF_CFG_RD(bp, func_ext_config[func].
11492                                                 iscsi_mac_addr_lower);
11493                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11494                                 BNX2X_DEV_INFO
11495                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11496                         } else {
11497                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11498                         }
11499
11500                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11501                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11502                                                  fcoe_mac_addr_upper);
11503                                 val = MF_CFG_RD(bp, func_ext_config[func].
11504                                                 fcoe_mac_addr_lower);
11505                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11506                                 BNX2X_DEV_INFO
11507                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11508                         } else {
11509                                 bp->flags |= NO_FCOE_FLAG;
11510                         }
11511
11512                         bp->mf_ext_config = cfg;
11513
11514                 } else { /* SD MODE */
11515                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11516                                 /* use primary mac as iscsi mac */
11517                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11518
11519                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11520                                 BNX2X_DEV_INFO
11521                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11522                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11523                                 /* use primary mac as fip mac */
11524                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11525                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11526                                 BNX2X_DEV_INFO
11527                                         ("Read FIP MAC: %pM\n", fip_mac);
11528                         }
11529                 }
11530
11531                 /* If this is a storage-only interface, use SAN mac as
11532                  * primary MAC. Notice that for SD this is already the case,
11533                  * as the SAN mac was copied from the primary MAC.
11534                  */
11535                 if (IS_MF_FCOE_AFEX(bp))
11536                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11537         } else {
11538                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11539                                 iscsi_mac_upper);
11540                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11541                                iscsi_mac_lower);
11542                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11543
11544                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11545                                 fcoe_fip_mac_upper);
11546                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11547                                fcoe_fip_mac_lower);
11548                 bnx2x_set_mac_buf(fip_mac, val, val2);
11549         }
11550
11551         /* Disable iSCSI OOO if MAC configuration is invalid. */
11552         if (!is_valid_ether_addr(iscsi_mac)) {
11553                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11554                 eth_zero_addr(iscsi_mac);
11555         }
11556
11557         /* Disable FCoE if MAC configuration is invalid. */
11558         if (!is_valid_ether_addr(fip_mac)) {
11559                 bp->flags |= NO_FCOE_FLAG;
11560                 eth_zero_addr(bp->fip_mac);
11561         }
11562 }
11563
11564 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11565 {
11566         u32 val, val2;
11567         int func = BP_ABS_FUNC(bp);
11568         int port = BP_PORT(bp);
11569
11570         /* Zero primary MAC configuration */
11571         eth_zero_addr(bp->dev->dev_addr);
11572
11573         if (BP_NOMCP(bp)) {
11574                 BNX2X_ERROR("warning: random MAC workaround active\n");
11575                 eth_hw_addr_random(bp->dev);
11576         } else if (IS_MF(bp)) {
11577                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11578                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11579                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11580                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11581                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11582
11583                 if (CNIC_SUPPORT(bp))
11584                         bnx2x_get_cnic_mac_hwinfo(bp);
11585         } else {
11586                 /* in SF read MACs from port configuration */
11587                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11588                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11589                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11590
11591                 if (CNIC_SUPPORT(bp))
11592                         bnx2x_get_cnic_mac_hwinfo(bp);
11593         }
11594
11595         if (!BP_NOMCP(bp)) {
11596                 /* Read physical port identifier from shmem */
11597                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11598                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11599                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11600                 bp->flags |= HAS_PHYS_PORT_ID;
11601         }
11602
11603         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11604
11605         if (!is_valid_ether_addr(bp->dev->dev_addr))
11606                 dev_err(&bp->pdev->dev,
11607                         "bad Ethernet MAC address configuration: %pM\n"
11608                         "change it manually before bringing up the appropriate network interface\n",
11609                         bp->dev->dev_addr);
11610 }
11611
11612 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11613 {
11614         int tmp;
11615         u32 cfg;
11616
11617         if (IS_VF(bp))
11618                 return false;
11619
11620         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11621                 /* Take function: tmp = func */
11622                 tmp = BP_ABS_FUNC(bp);
11623                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11624                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11625         } else {
11626                 /* Take port: tmp = port */
11627                 tmp = BP_PORT(bp);
11628                 cfg = SHMEM_RD(bp,
11629                                dev_info.port_hw_config[tmp].generic_features);
11630                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11631         }
11632         return cfg;
11633 }
11634
11635 static void validate_set_si_mode(struct bnx2x *bp)
11636 {
11637         u8 func = BP_ABS_FUNC(bp);
11638         u32 val;
11639
11640         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11641
11642         /* check for legal mac (upper bytes) */
11643         if (val != 0xffff) {
11644                 bp->mf_mode = MULTI_FUNCTION_SI;
11645                 bp->mf_config[BP_VN(bp)] =
11646                         MF_CFG_RD(bp, func_mf_config[func].config);
11647         } else
11648                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11649 }
11650
11651 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11652 {
11653         int /*abs*/func = BP_ABS_FUNC(bp);
11654         int vn;
11655         u32 val = 0, val2 = 0;
11656         int rc = 0;
11657
11658         /* Validate that chip access is feasible */
11659         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11660                 dev_err(&bp->pdev->dev,
11661                         "Chip read returns all Fs. Preventing probe from continuing\n");
11662                 return -EINVAL;
11663         }
11664
11665         bnx2x_get_common_hwinfo(bp);
11666
11667         /*
11668          * initialize IGU parameters
11669          */
11670         if (CHIP_IS_E1x(bp)) {
11671                 bp->common.int_block = INT_BLOCK_HC;
11672
11673                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11674                 bp->igu_base_sb = 0;
11675         } else {
11676                 bp->common.int_block = INT_BLOCK_IGU;
11677
11678                 /* do not allow device reset during IGU info processing */
11679                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11680
11681                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11682
11683                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11684                         int tout = 5000;
11685
11686                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11687
11688                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11689                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11690                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11691
11692                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11693                                 tout--;
11694                                 usleep_range(1000, 2000);
11695                         }
11696
11697                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11698                                 dev_err(&bp->pdev->dev,
11699                                         "FORCING Normal Mode failed!!!\n");
11700                                 bnx2x_release_hw_lock(bp,
11701                                                       HW_LOCK_RESOURCE_RESET);
11702                                 return -EPERM;
11703                         }
11704                 }
11705
11706                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11707                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11708                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11709                 } else
11710                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11711
11712                 rc = bnx2x_get_igu_cam_info(bp);
11713                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11714                 if (rc)
11715                         return rc;
11716         }
11717
11718         /*
11719          * set base FW non-default (fast path) status block id, this value is
11720          * used to initialize the fw_sb_id saved on the fp/queue structure to
11721          * determine the id used by the FW.
11722          */
11723         if (CHIP_IS_E1x(bp))
11724                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11725         else /*
11726               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11727               * the same queue are indicated on the same IGU SB). So we prefer
11728               * FW and IGU SBs to be the same value.
11729               */
11730                 bp->base_fw_ndsb = bp->igu_base_sb;
11731
11732         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11733                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11734                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11735
11736         /*
11737          * Initialize MF configuration
11738          */
11739
11740         bp->mf_ov = 0;
11741         bp->mf_mode = 0;
11742         bp->mf_sub_mode = 0;
11743         vn = BP_VN(bp);
11744
11745         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11746                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11747                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11748                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11749
11750                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11751                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11752                 else
11753                         bp->common.mf_cfg_base = bp->common.shmem_base +
11754                                 offsetof(struct shmem_region, func_mb) +
11755                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11756                 /*
11757                  * get mf configuration:
11758                  * 1. Existence of MF configuration
11759                  * 2. MAC address must be legal (check only upper bytes)
11760                  *    for  Switch-Independent mode;
11761                  *    OVLAN must be legal for Switch-Dependent mode
11762                  * 3. SF_MODE configures specific MF mode
11763                  */
11764                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11765                         /* get mf configuration */
11766                         val = SHMEM_RD(bp,
11767                                        dev_info.shared_feature_config.config);
11768                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11769
11770                         switch (val) {
11771                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11772                                 validate_set_si_mode(bp);
11773                                 break;
11774                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11775                                 if ((!CHIP_IS_E1x(bp)) &&
11776                                     (MF_CFG_RD(bp, func_mf_config[func].
11777                                                mac_upper) != 0xffff) &&
11778                                     (SHMEM2_HAS(bp,
11779                                                 afex_driver_support))) {
11780                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11781                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11782                                                 func_mf_config[func].config);
11783                                 } else {
11784                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11785                                 }
11786                                 break;
11787                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11788                                 /* get OV configuration */
11789                                 val = MF_CFG_RD(bp,
11790                                         func_mf_config[FUNC_0].e1hov_tag);
11791                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11792
11793                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11794                                         bp->mf_mode = MULTI_FUNCTION_SD;
11795                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11796                                                 func_mf_config[func].config);
11797                                 } else
11798                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11799                                 break;
11800                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11801                                 bp->mf_mode = MULTI_FUNCTION_SD;
11802                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11803                                 bp->mf_config[vn] =
11804                                         MF_CFG_RD(bp,
11805                                                   func_mf_config[func].config);
11806                                 break;
11807                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11808                                 bp->mf_config[vn] = 0;
11809                                 break;
11810                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11811                                 val2 = SHMEM_RD(bp,
11812                                         dev_info.shared_hw_config.config_3);
11813                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11814                                 switch (val2) {
11815                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11816                                         validate_set_si_mode(bp);
11817                                         bp->mf_sub_mode =
11818                                                         SUB_MF_MODE_NPAR1_DOT_5;
11819                                         break;
11820                                 default:
11821                                         /* Unknown configuration */
11822                                         bp->mf_config[vn] = 0;
11823                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11824                                                        val);
11825                                 }
11826                                 break;
11827                         default:
11828                                 /* Unknown configuration: reset mf_config */
11829                                 bp->mf_config[vn] = 0;
11830                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11831                         }
11832                 }
11833
11834                 BNX2X_DEV_INFO("%s function mode\n",
11835                                IS_MF(bp) ? "multi" : "single");
11836
11837                 switch (bp->mf_mode) {
11838                 case MULTI_FUNCTION_SD:
11839                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11840                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11841                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11842                                 bp->mf_ov = val;
11843                                 bp->path_has_ovlan = true;
11844
11845                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11846                                                func, bp->mf_ov, bp->mf_ov);
11847                         } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
11848                                 dev_err(&bp->pdev->dev,
11849                                         "Unexpected - no valid MF OV for func %d in UFP mode\n",
11850                                         func);
11851                                 bp->path_has_ovlan = true;
11852                         } else {
11853                                 dev_err(&bp->pdev->dev,
11854                                         "No valid MF OV for func %d, aborting\n",
11855                                         func);
11856                                 return -EPERM;
11857                         }
11858                         break;
11859                 case MULTI_FUNCTION_AFEX:
11860                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11861                         break;
11862                 case MULTI_FUNCTION_SI:
11863                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11864                                        func);
11865                         break;
11866                 default:
11867                         if (vn) {
11868                                 dev_err(&bp->pdev->dev,
11869                                         "VN %d is in a single function mode, aborting\n",
11870                                         vn);
11871                                 return -EPERM;
11872                         }
11873                         break;
11874                 }
11875
11876                 /* check if other port on the path needs ovlan:
11877                  * Since MF configuration is shared between ports
11878                  * Possible mixed modes are only
11879                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11880                  */
11881                 if (CHIP_MODE_IS_4_PORT(bp) &&
11882                     !bp->path_has_ovlan &&
11883                     !IS_MF(bp) &&
11884                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11885                         u8 other_port = !BP_PORT(bp);
11886                         u8 other_func = BP_PATH(bp) + 2*other_port;
11887                         val = MF_CFG_RD(bp,
11888                                         func_mf_config[other_func].e1hov_tag);
11889                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11890                                 bp->path_has_ovlan = true;
11891                 }
11892         }
11893
11894         /* adjust igu_sb_cnt to MF for E1H */
11895         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11896                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11897
11898         /* port info */
11899         bnx2x_get_port_hwinfo(bp);
11900
11901         /* Get MAC addresses */
11902         bnx2x_get_mac_hwinfo(bp);
11903
11904         bnx2x_get_cnic_info(bp);
11905
11906         return rc;
11907 }
11908
11909 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11910 {
11911         int cnt, i, block_end, rodi;
11912         char vpd_start[BNX2X_VPD_LEN+1];
11913         char str_id_reg[VENDOR_ID_LEN+1];
11914         char str_id_cap[VENDOR_ID_LEN+1];
11915         char *vpd_data;
11916         char *vpd_extended_data = NULL;
11917         u8 len;
11918
11919         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11920         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11921
11922         if (cnt < BNX2X_VPD_LEN)
11923                 goto out_not_found;
11924
11925         /* VPD RO tag should be first tag after identifier string, hence
11926          * we should be able to find it in first BNX2X_VPD_LEN chars
11927          */
11928         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11929                              PCI_VPD_LRDT_RO_DATA);
11930         if (i < 0)
11931                 goto out_not_found;
11932
11933         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11934                     pci_vpd_lrdt_size(&vpd_start[i]);
11935
11936         i += PCI_VPD_LRDT_TAG_SIZE;
11937
11938         if (block_end > BNX2X_VPD_LEN) {
11939                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11940                 if (vpd_extended_data  == NULL)
11941                         goto out_not_found;
11942
11943                 /* read rest of vpd image into vpd_extended_data */
11944                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11945                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11946                                    block_end - BNX2X_VPD_LEN,
11947                                    vpd_extended_data + BNX2X_VPD_LEN);
11948                 if (cnt < (block_end - BNX2X_VPD_LEN))
11949                         goto out_not_found;
11950                 vpd_data = vpd_extended_data;
11951         } else
11952                 vpd_data = vpd_start;
11953
11954         /* now vpd_data holds full vpd content in both cases */
11955
11956         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11957                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11958         if (rodi < 0)
11959                 goto out_not_found;
11960
11961         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11962
11963         if (len != VENDOR_ID_LEN)
11964                 goto out_not_found;
11965
11966         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11967
11968         /* vendor specific info */
11969         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11970         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11971         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11972             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11973
11974                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11975                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11976                 if (rodi >= 0) {
11977                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11978
11979                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11980
11981                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11982                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11983                                 bp->fw_ver[len] = ' ';
11984                         }
11985                 }
11986                 kfree(vpd_extended_data);
11987                 return;
11988         }
11989 out_not_found:
11990         kfree(vpd_extended_data);
11991         return;
11992 }
11993
11994 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11995 {
11996         u32 flags = 0;
11997
11998         if (CHIP_REV_IS_FPGA(bp))
11999                 SET_FLAGS(flags, MODE_FPGA);
12000         else if (CHIP_REV_IS_EMUL(bp))
12001                 SET_FLAGS(flags, MODE_EMUL);
12002         else
12003                 SET_FLAGS(flags, MODE_ASIC);
12004
12005         if (CHIP_MODE_IS_4_PORT(bp))
12006                 SET_FLAGS(flags, MODE_PORT4);
12007         else
12008                 SET_FLAGS(flags, MODE_PORT2);
12009
12010         if (CHIP_IS_E2(bp))
12011                 SET_FLAGS(flags, MODE_E2);
12012         else if (CHIP_IS_E3(bp)) {
12013                 SET_FLAGS(flags, MODE_E3);
12014                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12015                         SET_FLAGS(flags, MODE_E3_A0);
12016                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12017                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12018         }
12019
12020         if (IS_MF(bp)) {
12021                 SET_FLAGS(flags, MODE_MF);
12022                 switch (bp->mf_mode) {
12023                 case MULTI_FUNCTION_SD:
12024                         SET_FLAGS(flags, MODE_MF_SD);
12025                         break;
12026                 case MULTI_FUNCTION_SI:
12027                         SET_FLAGS(flags, MODE_MF_SI);
12028                         break;
12029                 case MULTI_FUNCTION_AFEX:
12030                         SET_FLAGS(flags, MODE_MF_AFEX);
12031                         break;
12032                 }
12033         } else
12034                 SET_FLAGS(flags, MODE_SF);
12035
12036 #if defined(__LITTLE_ENDIAN)
12037         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12038 #else /*(__BIG_ENDIAN)*/
12039         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12040 #endif
12041         INIT_MODE_FLAGS(bp) = flags;
12042 }
12043
12044 static int bnx2x_init_bp(struct bnx2x *bp)
12045 {
12046         int func;
12047         int rc;
12048
12049         mutex_init(&bp->port.phy_mutex);
12050         mutex_init(&bp->fw_mb_mutex);
12051         mutex_init(&bp->drv_info_mutex);
12052         sema_init(&bp->stats_lock, 1);
12053         bp->drv_info_mng_owner = false;
12054
12055         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12056         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12057         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12058         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12059         if (IS_PF(bp)) {
12060                 rc = bnx2x_get_hwinfo(bp);
12061                 if (rc)
12062                         return rc;
12063         } else {
12064                 eth_zero_addr(bp->dev->dev_addr);
12065         }
12066
12067         bnx2x_set_modes_bitmap(bp);
12068
12069         rc = bnx2x_alloc_mem_bp(bp);
12070         if (rc)
12071                 return rc;
12072
12073         bnx2x_read_fwinfo(bp);
12074
12075         func = BP_FUNC(bp);
12076
12077         /* need to reset chip if undi was active */
12078         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12079                 /* init fw_seq */
12080                 bp->fw_seq =
12081                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12082                                                         DRV_MSG_SEQ_NUMBER_MASK;
12083                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12084
12085                 rc = bnx2x_prev_unload(bp);
12086                 if (rc) {
12087                         bnx2x_free_mem_bp(bp);
12088                         return rc;
12089                 }
12090         }
12091
12092         if (CHIP_REV_IS_FPGA(bp))
12093                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12094
12095         if (BP_NOMCP(bp) && (func == 0))
12096                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12097
12098         bp->disable_tpa = disable_tpa;
12099         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12100         /* Reduce memory usage in kdump environment by disabling TPA */
12101         bp->disable_tpa |= is_kdump_kernel();
12102
12103         /* Set TPA flags */
12104         if (bp->disable_tpa) {
12105                 bp->dev->hw_features &= ~NETIF_F_LRO;
12106                 bp->dev->features &= ~NETIF_F_LRO;
12107         }
12108
12109         if (CHIP_IS_E1(bp))
12110                 bp->dropless_fc = 0;
12111         else
12112                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12113
12114         bp->mrrs = mrrs;
12115
12116         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12117         if (IS_VF(bp))
12118                 bp->rx_ring_size = MAX_RX_AVAIL;
12119
12120         /* make sure that the numbers are in the right granularity */
12121         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12122         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12123
12124         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12125
12126         init_timer(&bp->timer);
12127         bp->timer.expires = jiffies + bp->current_interval;
12128         bp->timer.data = (unsigned long) bp;
12129         bp->timer.function = bnx2x_timer;
12130
12131         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12132             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12133             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12134             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12135                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12136                 bnx2x_dcbx_init_params(bp);
12137         } else {
12138                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12139         }
12140
12141         if (CHIP_IS_E1x(bp))
12142                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12143         else
12144                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12145
12146         /* multiple tx priority */
12147         if (IS_VF(bp))
12148                 bp->max_cos = 1;
12149         else if (CHIP_IS_E1x(bp))
12150                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12151         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12152                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12153         else if (CHIP_IS_E3B0(bp))
12154                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12155         else
12156                 BNX2X_ERR("unknown chip %x revision %x\n",
12157                           CHIP_NUM(bp), CHIP_REV(bp));
12158         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12159
12160         /* We need at least one default status block for slow-path events,
12161          * second status block for the L2 queue, and a third status block for
12162          * CNIC if supported.
12163          */
12164         if (IS_VF(bp))
12165                 bp->min_msix_vec_cnt = 1;
12166         else if (CNIC_SUPPORT(bp))
12167                 bp->min_msix_vec_cnt = 3;
12168         else /* PF w/o cnic */
12169                 bp->min_msix_vec_cnt = 2;
12170         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12171
12172         bp->dump_preset_idx = 1;
12173
12174         if (CHIP_IS_E3B0(bp))
12175                 bp->flags |= PTP_SUPPORTED;
12176
12177         return rc;
12178 }
12179
12180 /****************************************************************************
12181 * General service functions
12182 ****************************************************************************/
12183
12184 /*
12185  * net_device service functions
12186  */
12187
12188 /* called with rtnl_lock */
12189 static int bnx2x_open(struct net_device *dev)
12190 {
12191         struct bnx2x *bp = netdev_priv(dev);
12192         int rc;
12193
12194         bp->stats_init = true;
12195
12196         netif_carrier_off(dev);
12197
12198         bnx2x_set_power_state(bp, PCI_D0);
12199
12200         /* If parity had happen during the unload, then attentions
12201          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12202          * want the first function loaded on the current engine to
12203          * complete the recovery.
12204          * Parity recovery is only relevant for PF driver.
12205          */
12206         if (IS_PF(bp)) {
12207                 int other_engine = BP_PATH(bp) ? 0 : 1;
12208                 bool other_load_status, load_status;
12209                 bool global = false;
12210
12211                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12212                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12213                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12214                     bnx2x_chk_parity_attn(bp, &global, true)) {
12215                         do {
12216                                 /* If there are attentions and they are in a
12217                                  * global blocks, set the GLOBAL_RESET bit
12218                                  * regardless whether it will be this function
12219                                  * that will complete the recovery or not.
12220                                  */
12221                                 if (global)
12222                                         bnx2x_set_reset_global(bp);
12223
12224                                 /* Only the first function on the current
12225                                  * engine should try to recover in open. In case
12226                                  * of attentions in global blocks only the first
12227                                  * in the chip should try to recover.
12228                                  */
12229                                 if ((!load_status &&
12230                                      (!global || !other_load_status)) &&
12231                                       bnx2x_trylock_leader_lock(bp) &&
12232                                       !bnx2x_leader_reset(bp)) {
12233                                         netdev_info(bp->dev,
12234                                                     "Recovered in open\n");
12235                                         break;
12236                                 }
12237
12238                                 /* recovery has failed... */
12239                                 bnx2x_set_power_state(bp, PCI_D3hot);
12240                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12241
12242                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12243                                           "If you still see this message after a few retries then power cycle is required.\n");
12244
12245                                 return -EAGAIN;
12246                         } while (0);
12247                 }
12248         }
12249
12250         bp->recovery_state = BNX2X_RECOVERY_DONE;
12251         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12252         if (rc)
12253                 return rc;
12254         return 0;
12255 }
12256
12257 /* called with rtnl_lock */
12258 static int bnx2x_close(struct net_device *dev)
12259 {
12260         struct bnx2x *bp = netdev_priv(dev);
12261
12262         /* Unload the driver, release IRQs */
12263         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12264
12265         return 0;
12266 }
12267
12268 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12269                                       struct bnx2x_mcast_ramrod_params *p)
12270 {
12271         int mc_count = netdev_mc_count(bp->dev);
12272         struct bnx2x_mcast_list_elem *mc_mac =
12273                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12274         struct netdev_hw_addr *ha;
12275
12276         if (!mc_mac)
12277                 return -ENOMEM;
12278
12279         INIT_LIST_HEAD(&p->mcast_list);
12280
12281         netdev_for_each_mc_addr(ha, bp->dev) {
12282                 mc_mac->mac = bnx2x_mc_addr(ha);
12283                 list_add_tail(&mc_mac->link, &p->mcast_list);
12284                 mc_mac++;
12285         }
12286
12287         p->mcast_list_len = mc_count;
12288
12289         return 0;
12290 }
12291
12292 static void bnx2x_free_mcast_macs_list(
12293         struct bnx2x_mcast_ramrod_params *p)
12294 {
12295         struct bnx2x_mcast_list_elem *mc_mac =
12296                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12297                                  link);
12298
12299         WARN_ON(!mc_mac);
12300         kfree(mc_mac);
12301 }
12302
12303 /**
12304  * bnx2x_set_uc_list - configure a new unicast MACs list.
12305  *
12306  * @bp: driver handle
12307  *
12308  * We will use zero (0) as a MAC type for these MACs.
12309  */
12310 static int bnx2x_set_uc_list(struct bnx2x *bp)
12311 {
12312         int rc;
12313         struct net_device *dev = bp->dev;
12314         struct netdev_hw_addr *ha;
12315         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12316         unsigned long ramrod_flags = 0;
12317
12318         /* First schedule a cleanup up of old configuration */
12319         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12320         if (rc < 0) {
12321                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12322                 return rc;
12323         }
12324
12325         netdev_for_each_uc_addr(ha, dev) {
12326                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12327                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12328                 if (rc == -EEXIST) {
12329                         DP(BNX2X_MSG_SP,
12330                            "Failed to schedule ADD operations: %d\n", rc);
12331                         /* do not treat adding same MAC as error */
12332                         rc = 0;
12333
12334                 } else if (rc < 0) {
12335
12336                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12337                                   rc);
12338                         return rc;
12339                 }
12340         }
12341
12342         /* Execute the pending commands */
12343         __set_bit(RAMROD_CONT, &ramrod_flags);
12344         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12345                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12346 }
12347
12348 static int bnx2x_set_mc_list(struct bnx2x *bp)
12349 {
12350         struct net_device *dev = bp->dev;
12351         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12352         int rc = 0;
12353
12354         rparam.mcast_obj = &bp->mcast_obj;
12355
12356         /* first, clear all configured multicast MACs */
12357         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12358         if (rc < 0) {
12359                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12360                 return rc;
12361         }
12362
12363         /* then, configure a new MACs list */
12364         if (netdev_mc_count(dev)) {
12365                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12366                 if (rc) {
12367                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12368                                   rc);
12369                         return rc;
12370                 }
12371
12372                 /* Now add the new MACs */
12373                 rc = bnx2x_config_mcast(bp, &rparam,
12374                                         BNX2X_MCAST_CMD_ADD);
12375                 if (rc < 0)
12376                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12377                                   rc);
12378
12379                 bnx2x_free_mcast_macs_list(&rparam);
12380         }
12381
12382         return rc;
12383 }
12384
12385 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12386 static void bnx2x_set_rx_mode(struct net_device *dev)
12387 {
12388         struct bnx2x *bp = netdev_priv(dev);
12389
12390         if (bp->state != BNX2X_STATE_OPEN) {
12391                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12392                 return;
12393         } else {
12394                 /* Schedule an SP task to handle rest of change */
12395                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12396                                        NETIF_MSG_IFUP);
12397         }
12398 }
12399
12400 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12401 {
12402         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12403
12404         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12405
12406         netif_addr_lock_bh(bp->dev);
12407
12408         if (bp->dev->flags & IFF_PROMISC) {
12409                 rx_mode = BNX2X_RX_MODE_PROMISC;
12410         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12411                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12412                     CHIP_IS_E1(bp))) {
12413                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12414         } else {
12415                 if (IS_PF(bp)) {
12416                         /* some multicasts */
12417                         if (bnx2x_set_mc_list(bp) < 0)
12418                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12419
12420                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12421                         netif_addr_unlock_bh(bp->dev);
12422                         if (bnx2x_set_uc_list(bp) < 0)
12423                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12424                         netif_addr_lock_bh(bp->dev);
12425                 } else {
12426                         /* configuring mcast to a vf involves sleeping (when we
12427                          * wait for the pf's response).
12428                          */
12429                         bnx2x_schedule_sp_rtnl(bp,
12430                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12431                 }
12432         }
12433
12434         bp->rx_mode = rx_mode;
12435         /* handle ISCSI SD mode */
12436         if (IS_MF_ISCSI_ONLY(bp))
12437                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12438
12439         /* Schedule the rx_mode command */
12440         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12441                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12442                 netif_addr_unlock_bh(bp->dev);
12443                 return;
12444         }
12445
12446         if (IS_PF(bp)) {
12447                 bnx2x_set_storm_rx_mode(bp);
12448                 netif_addr_unlock_bh(bp->dev);
12449         } else {
12450                 /* VF will need to request the PF to make this change, and so
12451                  * the VF needs to release the bottom-half lock prior to the
12452                  * request (as it will likely require sleep on the VF side)
12453                  */
12454                 netif_addr_unlock_bh(bp->dev);
12455                 bnx2x_vfpf_storm_rx_mode(bp);
12456         }
12457 }
12458
12459 /* called with rtnl_lock */
12460 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12461                            int devad, u16 addr)
12462 {
12463         struct bnx2x *bp = netdev_priv(netdev);
12464         u16 value;
12465         int rc;
12466
12467         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12468            prtad, devad, addr);
12469
12470         /* The HW expects different devad if CL22 is used */
12471         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12472
12473         bnx2x_acquire_phy_lock(bp);
12474         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12475         bnx2x_release_phy_lock(bp);
12476         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12477
12478         if (!rc)
12479                 rc = value;
12480         return rc;
12481 }
12482
12483 /* called with rtnl_lock */
12484 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12485                             u16 addr, u16 value)
12486 {
12487         struct bnx2x *bp = netdev_priv(netdev);
12488         int rc;
12489
12490         DP(NETIF_MSG_LINK,
12491            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12492            prtad, devad, addr, value);
12493
12494         /* The HW expects different devad if CL22 is used */
12495         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12496
12497         bnx2x_acquire_phy_lock(bp);
12498         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12499         bnx2x_release_phy_lock(bp);
12500         return rc;
12501 }
12502
12503 /* called with rtnl_lock */
12504 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12505 {
12506         struct bnx2x *bp = netdev_priv(dev);
12507         struct mii_ioctl_data *mdio = if_mii(ifr);
12508
12509         if (!netif_running(dev))
12510                 return -EAGAIN;
12511
12512         switch (cmd) {
12513         case SIOCSHWTSTAMP:
12514                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12515         default:
12516                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12517                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12518                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12519         }
12520 }
12521
12522 #ifdef CONFIG_NET_POLL_CONTROLLER
12523 static void poll_bnx2x(struct net_device *dev)
12524 {
12525         struct bnx2x *bp = netdev_priv(dev);
12526         int i;
12527
12528         for_each_eth_queue(bp, i) {
12529                 struct bnx2x_fastpath *fp = &bp->fp[i];
12530                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12531         }
12532 }
12533 #endif
12534
12535 static int bnx2x_validate_addr(struct net_device *dev)
12536 {
12537         struct bnx2x *bp = netdev_priv(dev);
12538
12539         /* query the bulletin board for mac address configured by the PF */
12540         if (IS_VF(bp))
12541                 bnx2x_sample_bulletin(bp);
12542
12543         if (!is_valid_ether_addr(dev->dev_addr)) {
12544                 BNX2X_ERR("Non-valid Ethernet address\n");
12545                 return -EADDRNOTAVAIL;
12546         }
12547         return 0;
12548 }
12549
12550 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12551                                   struct netdev_phys_item_id *ppid)
12552 {
12553         struct bnx2x *bp = netdev_priv(netdev);
12554
12555         if (!(bp->flags & HAS_PHYS_PORT_ID))
12556                 return -EOPNOTSUPP;
12557
12558         ppid->id_len = sizeof(bp->phys_port_id);
12559         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12560
12561         return 0;
12562 }
12563
12564 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12565                                               struct net_device *dev,
12566                                               netdev_features_t features)
12567 {
12568         features = vlan_features_check(skb, features);
12569         return vxlan_features_check(skb, features);
12570 }
12571
12572 static const struct net_device_ops bnx2x_netdev_ops = {
12573         .ndo_open               = bnx2x_open,
12574         .ndo_stop               = bnx2x_close,
12575         .ndo_start_xmit         = bnx2x_start_xmit,
12576         .ndo_select_queue       = bnx2x_select_queue,
12577         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12578         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12579         .ndo_validate_addr      = bnx2x_validate_addr,
12580         .ndo_do_ioctl           = bnx2x_ioctl,
12581         .ndo_change_mtu         = bnx2x_change_mtu,
12582         .ndo_fix_features       = bnx2x_fix_features,
12583         .ndo_set_features       = bnx2x_set_features,
12584         .ndo_tx_timeout         = bnx2x_tx_timeout,
12585 #ifdef CONFIG_NET_POLL_CONTROLLER
12586         .ndo_poll_controller    = poll_bnx2x,
12587 #endif
12588         .ndo_setup_tc           = bnx2x_setup_tc,
12589 #ifdef CONFIG_BNX2X_SRIOV
12590         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12591         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12592         .ndo_get_vf_config      = bnx2x_get_vf_config,
12593 #endif
12594 #ifdef NETDEV_FCOE_WWNN
12595         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12596 #endif
12597
12598 #ifdef CONFIG_NET_RX_BUSY_POLL
12599         .ndo_busy_poll          = bnx2x_low_latency_recv,
12600 #endif
12601         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12602         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
12603         .ndo_features_check     = bnx2x_features_check,
12604 };
12605
12606 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12607 {
12608         struct device *dev = &bp->pdev->dev;
12609
12610         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12611             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12612                 dev_err(dev, "System does not support DMA, aborting\n");
12613                 return -EIO;
12614         }
12615
12616         return 0;
12617 }
12618
12619 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12620 {
12621         if (bp->flags & AER_ENABLED) {
12622                 pci_disable_pcie_error_reporting(bp->pdev);
12623                 bp->flags &= ~AER_ENABLED;
12624         }
12625 }
12626
12627 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12628                           struct net_device *dev, unsigned long board_type)
12629 {
12630         int rc;
12631         u32 pci_cfg_dword;
12632         bool chip_is_e1x = (board_type == BCM57710 ||
12633                             board_type == BCM57711 ||
12634                             board_type == BCM57711E);
12635
12636         SET_NETDEV_DEV(dev, &pdev->dev);
12637
12638         bp->dev = dev;
12639         bp->pdev = pdev;
12640
12641         rc = pci_enable_device(pdev);
12642         if (rc) {
12643                 dev_err(&bp->pdev->dev,
12644                         "Cannot enable PCI device, aborting\n");
12645                 goto err_out;
12646         }
12647
12648         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12649                 dev_err(&bp->pdev->dev,
12650                         "Cannot find PCI device base address, aborting\n");
12651                 rc = -ENODEV;
12652                 goto err_out_disable;
12653         }
12654
12655         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12656                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12657                 rc = -ENODEV;
12658                 goto err_out_disable;
12659         }
12660
12661         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12662         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12663             PCICFG_REVESION_ID_ERROR_VAL) {
12664                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12665                 rc = -ENODEV;
12666                 goto err_out_disable;
12667         }
12668
12669         if (atomic_read(&pdev->enable_cnt) == 1) {
12670                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12671                 if (rc) {
12672                         dev_err(&bp->pdev->dev,
12673                                 "Cannot obtain PCI resources, aborting\n");
12674                         goto err_out_disable;
12675                 }
12676
12677                 pci_set_master(pdev);
12678                 pci_save_state(pdev);
12679         }
12680
12681         if (IS_PF(bp)) {
12682                 if (!pdev->pm_cap) {
12683                         dev_err(&bp->pdev->dev,
12684                                 "Cannot find power management capability, aborting\n");
12685                         rc = -EIO;
12686                         goto err_out_release;
12687                 }
12688         }
12689
12690         if (!pci_is_pcie(pdev)) {
12691                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12692                 rc = -EIO;
12693                 goto err_out_release;
12694         }
12695
12696         rc = bnx2x_set_coherency_mask(bp);
12697         if (rc)
12698                 goto err_out_release;
12699
12700         dev->mem_start = pci_resource_start(pdev, 0);
12701         dev->base_addr = dev->mem_start;
12702         dev->mem_end = pci_resource_end(pdev, 0);
12703
12704         dev->irq = pdev->irq;
12705
12706         bp->regview = pci_ioremap_bar(pdev, 0);
12707         if (!bp->regview) {
12708                 dev_err(&bp->pdev->dev,
12709                         "Cannot map register space, aborting\n");
12710                 rc = -ENOMEM;
12711                 goto err_out_release;
12712         }
12713
12714         /* In E1/E1H use pci device function given by kernel.
12715          * In E2/E3 read physical function from ME register since these chips
12716          * support Physical Device Assignment where kernel BDF maybe arbitrary
12717          * (depending on hypervisor).
12718          */
12719         if (chip_is_e1x) {
12720                 bp->pf_num = PCI_FUNC(pdev->devfn);
12721         } else {
12722                 /* chip is E2/3*/
12723                 pci_read_config_dword(bp->pdev,
12724                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12725                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12726                                   ME_REG_ABS_PF_NUM_SHIFT);
12727         }
12728         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12729
12730         /* clean indirect addresses */
12731         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12732                                PCICFG_VENDOR_ID_OFFSET);
12733
12734         /* Set PCIe reset type to fundamental for EEH recovery */
12735         pdev->needs_freset = 1;
12736
12737         /* AER (Advanced Error reporting) configuration */
12738         rc = pci_enable_pcie_error_reporting(pdev);
12739         if (!rc)
12740                 bp->flags |= AER_ENABLED;
12741         else
12742                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12743
12744         /*
12745          * Clean the following indirect addresses for all functions since it
12746          * is not used by the driver.
12747          */
12748         if (IS_PF(bp)) {
12749                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12750                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12751                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12752                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12753
12754                 if (chip_is_e1x) {
12755                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12756                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12757                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12758                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12759                 }
12760
12761                 /* Enable internal target-read (in case we are probed after PF
12762                  * FLR). Must be done prior to any BAR read access. Only for
12763                  * 57712 and up
12764                  */
12765                 if (!chip_is_e1x)
12766                         REG_WR(bp,
12767                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12768         }
12769
12770         dev->watchdog_timeo = TX_TIMEOUT;
12771
12772         dev->netdev_ops = &bnx2x_netdev_ops;
12773         bnx2x_set_ethtool_ops(bp, dev);
12774
12775         dev->priv_flags |= IFF_UNICAST_FLT;
12776
12777         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12778                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12779                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12780                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12781         if (!chip_is_e1x) {
12782                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12783                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12784                 dev->hw_enc_features =
12785                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12786                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12787                         NETIF_F_GSO_IPIP |
12788                         NETIF_F_GSO_SIT |
12789                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12790         }
12791
12792         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12793                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12794
12795         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12796         dev->features |= NETIF_F_HIGHDMA;
12797
12798         /* Add Loopback capability to the device */
12799         dev->hw_features |= NETIF_F_LOOPBACK;
12800
12801 #ifdef BCM_DCBNL
12802         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12803 #endif
12804
12805         /* get_port_hwinfo() will set prtad and mmds properly */
12806         bp->mdio.prtad = MDIO_PRTAD_NONE;
12807         bp->mdio.mmds = 0;
12808         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12809         bp->mdio.dev = dev;
12810         bp->mdio.mdio_read = bnx2x_mdio_read;
12811         bp->mdio.mdio_write = bnx2x_mdio_write;
12812
12813         return 0;
12814
12815 err_out_release:
12816         if (atomic_read(&pdev->enable_cnt) == 1)
12817                 pci_release_regions(pdev);
12818
12819 err_out_disable:
12820         pci_disable_device(pdev);
12821
12822 err_out:
12823         return rc;
12824 }
12825
12826 /*(DEBLOBBED)*/
12827
12828 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12829 {
12830         const __be32 *source = (const __be32 *)_source;
12831         u32 *target = (u32 *)_target;
12832         u32 i;
12833
12834         for (i = 0; i < n/4; i++)
12835                 target[i] = be32_to_cpu(source[i]);
12836 }
12837
12838 /*
12839    Ops array is stored in the following format:
12840    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12841  */
12842 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12843 {
12844         const __be32 *source = (const __be32 *)_source;
12845         struct raw_op *target = (struct raw_op *)_target;
12846         u32 i, j, tmp;
12847
12848         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12849                 tmp = be32_to_cpu(source[j]);
12850                 target[i].op = (tmp >> 24) & 0xff;
12851                 target[i].offset = tmp & 0xffffff;
12852                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12853         }
12854 }
12855
12856 /* IRO array is stored in the following format:
12857  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12858  */
12859 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12860 {
12861         const __be32 *source = (const __be32 *)_source;
12862         struct iro *target = (struct iro *)_target;
12863         u32 i, j, tmp;
12864
12865         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12866                 target[i].base = be32_to_cpu(source[j]);
12867                 j++;
12868                 tmp = be32_to_cpu(source[j]);
12869                 target[i].m1 = (tmp >> 16) & 0xffff;
12870                 target[i].m2 = tmp & 0xffff;
12871                 j++;
12872                 tmp = be32_to_cpu(source[j]);
12873                 target[i].m3 = (tmp >> 16) & 0xffff;
12874                 target[i].size = tmp & 0xffff;
12875                 j++;
12876         }
12877 }
12878
12879 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12880 {
12881         const __be16 *source = (const __be16 *)_source;
12882         u16 *target = (u16 *)_target;
12883         u32 i;
12884
12885         for (i = 0; i < n/2; i++)
12886                 target[i] = be16_to_cpu(source[i]);
12887 }
12888
12889 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12890 do {                                                                    \
12891         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12892         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12893         if (!bp->arr)                                                   \
12894                 goto lbl;                                               \
12895         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12896              (u8 *)bp->arr, len);                                       \
12897 } while (0)
12898
12899 static int bnx2x_init_firmware(struct bnx2x *bp)
12900 {
12901         const char *fw_file_name;
12902         struct bnx2x_fw_file_hdr *fw_hdr;
12903         int rc;
12904
12905         if (bp->firmware)
12906                 return 0;
12907
12908         if (CHIP_IS_E1(bp))
12909                 fw_file_name = FW_FILE_NAME_E1;
12910         else if (CHIP_IS_E1H(bp))
12911                 fw_file_name = FW_FILE_NAME_E1H;
12912         else if (!CHIP_IS_E1x(bp))
12913                 fw_file_name = FW_FILE_NAME_E2;
12914         else {
12915                 BNX2X_ERR("Unsupported chip revision\n");
12916                 return -EINVAL;
12917         }
12918         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12919
12920         rc = reject_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12921         if (rc) {
12922                 BNX2X_ERR("Can't load firmware file %s\n",
12923                           fw_file_name);
12924                 goto request_firmware_exit;
12925         }
12926
12927         /*(DEBLOBBED)*/
12928         if (rc) {
12929                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12930                 goto request_firmware_exit;
12931         }
12932
12933         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12934
12935         /* Initialize the pointers to the init arrays */
12936         /* Blob */
12937         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12938
12939         /* Opcodes */
12940         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12941
12942         /* Offsets */
12943         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12944                             be16_to_cpu_n);
12945
12946         /* STORMs firmware */
12947         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12948                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12949         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12950                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12951         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12952                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12953         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12954                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12955         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12956                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12957         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12958                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12959         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12960                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12961         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12962                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12963         /* IRO */
12964         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12965
12966         return 0;
12967
12968 iro_alloc_err:
12969         kfree(bp->init_ops_offsets);
12970 init_offsets_alloc_err:
12971         kfree(bp->init_ops);
12972 init_ops_alloc_err:
12973         kfree(bp->init_data);
12974 request_firmware_exit:
12975         release_firmware(bp->firmware);
12976         bp->firmware = NULL;
12977
12978         return rc;
12979 }
12980
12981 static void bnx2x_release_firmware(struct bnx2x *bp)
12982 {
12983         kfree(bp->init_ops_offsets);
12984         kfree(bp->init_ops);
12985         kfree(bp->init_data);
12986         release_firmware(bp->firmware);
12987         bp->firmware = NULL;
12988 }
12989
12990 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12991         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12992         .init_hw_cmn      = bnx2x_init_hw_common,
12993         .init_hw_port     = bnx2x_init_hw_port,
12994         .init_hw_func     = bnx2x_init_hw_func,
12995
12996         .reset_hw_cmn     = bnx2x_reset_common,
12997         .reset_hw_port    = bnx2x_reset_port,
12998         .reset_hw_func    = bnx2x_reset_func,
12999
13000         .gunzip_init      = bnx2x_gunzip_init,
13001         .gunzip_end       = bnx2x_gunzip_end,
13002
13003         .init_fw          = bnx2x_init_firmware,
13004         .release_fw       = bnx2x_release_firmware,
13005 };
13006
13007 void bnx2x__init_func_obj(struct bnx2x *bp)
13008 {
13009         /* Prepare DMAE related driver resources */
13010         bnx2x_setup_dmae(bp);
13011
13012         bnx2x_init_func_obj(bp, &bp->func_obj,
13013                             bnx2x_sp(bp, func_rdata),
13014                             bnx2x_sp_mapping(bp, func_rdata),
13015                             bnx2x_sp(bp, func_afex_rdata),
13016                             bnx2x_sp_mapping(bp, func_afex_rdata),
13017                             &bnx2x_func_sp_drv);
13018 }
13019
13020 /* must be called after sriov-enable */
13021 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13022 {
13023         int cid_count = BNX2X_L2_MAX_CID(bp);
13024
13025         if (IS_SRIOV(bp))
13026                 cid_count += BNX2X_VF_CIDS;
13027
13028         if (CNIC_SUPPORT(bp))
13029                 cid_count += CNIC_CID_MAX;
13030
13031         return roundup(cid_count, QM_CID_ROUND);
13032 }
13033
13034 /**
13035  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13036  *
13037  * @dev:        pci device
13038  *
13039  */
13040 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13041 {
13042         int index;
13043         u16 control = 0;
13044
13045         /*
13046          * If MSI-X is not supported - return number of SBs needed to support
13047          * one fast path queue: one FP queue + SB for CNIC
13048          */
13049         if (!pdev->msix_cap) {
13050                 dev_info(&pdev->dev, "no msix capability found\n");
13051                 return 1 + cnic_cnt;
13052         }
13053         dev_info(&pdev->dev, "msix capability found\n");
13054
13055         /*
13056          * The value in the PCI configuration space is the index of the last
13057          * entry, namely one less than the actual size of the table, which is
13058          * exactly what we want to return from this function: number of all SBs
13059          * without the default SB.
13060          * For VFs there is no default SB, then we return (index+1).
13061          */
13062         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13063
13064         index = control & PCI_MSIX_FLAGS_QSIZE;
13065
13066         return index;
13067 }
13068
13069 static int set_max_cos_est(int chip_id)
13070 {
13071         switch (chip_id) {
13072         case BCM57710:
13073         case BCM57711:
13074         case BCM57711E:
13075                 return BNX2X_MULTI_TX_COS_E1X;
13076         case BCM57712:
13077         case BCM57712_MF:
13078                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13079         case BCM57800:
13080         case BCM57800_MF:
13081         case BCM57810:
13082         case BCM57810_MF:
13083         case BCM57840_4_10:
13084         case BCM57840_2_20:
13085         case BCM57840_O:
13086         case BCM57840_MFO:
13087         case BCM57840_MF:
13088         case BCM57811:
13089         case BCM57811_MF:
13090                 return BNX2X_MULTI_TX_COS_E3B0;
13091         case BCM57712_VF:
13092         case BCM57800_VF:
13093         case BCM57810_VF:
13094         case BCM57840_VF:
13095         case BCM57811_VF:
13096                 return 1;
13097         default:
13098                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13099                 return -ENODEV;
13100         }
13101 }
13102
13103 static int set_is_vf(int chip_id)
13104 {
13105         switch (chip_id) {
13106         case BCM57712_VF:
13107         case BCM57800_VF:
13108         case BCM57810_VF:
13109         case BCM57840_VF:
13110         case BCM57811_VF:
13111                 return true;
13112         default:
13113                 return false;
13114         }
13115 }
13116
13117 /* nig_tsgen registers relative address */
13118 #define tsgen_ctrl 0x0
13119 #define tsgen_freecount 0x10
13120 #define tsgen_synctime_t0 0x20
13121 #define tsgen_offset_t0 0x28
13122 #define tsgen_drift_t0 0x30
13123 #define tsgen_synctime_t1 0x58
13124 #define tsgen_offset_t1 0x60
13125 #define tsgen_drift_t1 0x68
13126
13127 /* FW workaround for setting drift */
13128 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13129                                           int best_val, int best_period)
13130 {
13131         struct bnx2x_func_state_params func_params = {NULL};
13132         struct bnx2x_func_set_timesync_params *set_timesync_params =
13133                 &func_params.params.set_timesync;
13134
13135         /* Prepare parameters for function state transitions */
13136         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13137         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13138
13139         func_params.f_obj = &bp->func_obj;
13140         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13141
13142         /* Function parameters */
13143         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13144         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13145         set_timesync_params->add_sub_drift_adjust_value =
13146                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13147         set_timesync_params->drift_adjust_value = best_val;
13148         set_timesync_params->drift_adjust_period = best_period;
13149
13150         return bnx2x_func_state_change(bp, &func_params);
13151 }
13152
13153 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13154 {
13155         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13156         int rc;
13157         int drift_dir = 1;
13158         int val, period, period1, period2, dif, dif1, dif2;
13159         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13160
13161         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13162
13163         if (!netif_running(bp->dev)) {
13164                 DP(BNX2X_MSG_PTP,
13165                    "PTP adjfreq called while the interface is down\n");
13166                 return -EFAULT;
13167         }
13168
13169         if (ppb < 0) {
13170                 ppb = -ppb;
13171                 drift_dir = 0;
13172         }
13173
13174         if (ppb == 0) {
13175                 best_val = 1;
13176                 best_period = 0x1FFFFFF;
13177         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13178                 best_val = 31;
13179                 best_period = 1;
13180         } else {
13181                 /* Changed not to allow val = 8, 16, 24 as these values
13182                  * are not supported in workaround.
13183                  */
13184                 for (val = 0; val <= 31; val++) {
13185                         if ((val & 0x7) == 0)
13186                                 continue;
13187                         period1 = val * 1000000 / ppb;
13188                         period2 = period1 + 1;
13189                         if (period1 != 0)
13190                                 dif1 = ppb - (val * 1000000 / period1);
13191                         else
13192                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13193                         if (dif1 < 0)
13194                                 dif1 = -dif1;
13195                         dif2 = ppb - (val * 1000000 / period2);
13196                         if (dif2 < 0)
13197                                 dif2 = -dif2;
13198                         dif = (dif1 < dif2) ? dif1 : dif2;
13199                         period = (dif1 < dif2) ? period1 : period2;
13200                         if (dif < best_dif) {
13201                                 best_dif = dif;
13202                                 best_val = val;
13203                                 best_period = period;
13204                         }
13205                 }
13206         }
13207
13208         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13209                                             best_period);
13210         if (rc) {
13211                 BNX2X_ERR("Failed to set drift\n");
13212                 return -EFAULT;
13213         }
13214
13215         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13216            best_period);
13217
13218         return 0;
13219 }
13220
13221 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13222 {
13223         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13224
13225         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13226
13227         timecounter_adjtime(&bp->timecounter, delta);
13228
13229         return 0;
13230 }
13231
13232 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13233 {
13234         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13235         u64 ns;
13236
13237         ns = timecounter_read(&bp->timecounter);
13238
13239         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13240
13241         *ts = ns_to_timespec64(ns);
13242
13243         return 0;
13244 }
13245
13246 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13247                              const struct timespec64 *ts)
13248 {
13249         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13250         u64 ns;
13251
13252         ns = timespec64_to_ns(ts);
13253
13254         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13255
13256         /* Re-init the timecounter */
13257         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13258
13259         return 0;
13260 }
13261
13262 /* Enable (or disable) ancillary features of the phc subsystem */
13263 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13264                             struct ptp_clock_request *rq, int on)
13265 {
13266         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13267
13268         BNX2X_ERR("PHC ancillary features are not supported\n");
13269         return -ENOTSUPP;
13270 }
13271
13272 static void bnx2x_register_phc(struct bnx2x *bp)
13273 {
13274         /* Fill the ptp_clock_info struct and register PTP clock*/
13275         bp->ptp_clock_info.owner = THIS_MODULE;
13276         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13277         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13278         bp->ptp_clock_info.n_alarm = 0;
13279         bp->ptp_clock_info.n_ext_ts = 0;
13280         bp->ptp_clock_info.n_per_out = 0;
13281         bp->ptp_clock_info.pps = 0;
13282         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13283         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13284         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13285         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13286         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13287
13288         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13289         if (IS_ERR(bp->ptp_clock)) {
13290                 bp->ptp_clock = NULL;
13291                 BNX2X_ERR("PTP clock registeration failed\n");
13292         }
13293 }
13294
13295 static int bnx2x_init_one(struct pci_dev *pdev,
13296                                     const struct pci_device_id *ent)
13297 {
13298         struct net_device *dev = NULL;
13299         struct bnx2x *bp;
13300         enum pcie_link_width pcie_width;
13301         enum pci_bus_speed pcie_speed;
13302         int rc, max_non_def_sbs;
13303         int rx_count, tx_count, rss_count, doorbell_size;
13304         int max_cos_est;
13305         bool is_vf;
13306         int cnic_cnt;
13307
13308         /* Management FW 'remembers' living interfaces. Allow it some time
13309          * to forget previously living interfaces, allowing a proper re-load.
13310          */
13311         if (is_kdump_kernel()) {
13312                 ktime_t now = ktime_get_boottime();
13313                 ktime_t fw_ready_time = ktime_set(5, 0);
13314
13315                 if (ktime_before(now, fw_ready_time))
13316                         msleep(ktime_ms_delta(fw_ready_time, now));
13317         }
13318
13319         /* An estimated maximum supported CoS number according to the chip
13320          * version.
13321          * We will try to roughly estimate the maximum number of CoSes this chip
13322          * may support in order to minimize the memory allocated for Tx
13323          * netdev_queue's. This number will be accurately calculated during the
13324          * initialization of bp->max_cos based on the chip versions AND chip
13325          * revision in the bnx2x_init_bp().
13326          */
13327         max_cos_est = set_max_cos_est(ent->driver_data);
13328         if (max_cos_est < 0)
13329                 return max_cos_est;
13330         is_vf = set_is_vf(ent->driver_data);
13331         cnic_cnt = is_vf ? 0 : 1;
13332
13333         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13334
13335         /* add another SB for VF as it has no default SB */
13336         max_non_def_sbs += is_vf ? 1 : 0;
13337
13338         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13339         rss_count = max_non_def_sbs - cnic_cnt;
13340
13341         if (rss_count < 1)
13342                 return -EINVAL;
13343
13344         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13345         rx_count = rss_count + cnic_cnt;
13346
13347         /* Maximum number of netdev Tx queues:
13348          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13349          */
13350         tx_count = rss_count * max_cos_est + cnic_cnt;
13351
13352         /* dev zeroed in init_etherdev */
13353         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13354         if (!dev)
13355                 return -ENOMEM;
13356
13357         bp = netdev_priv(dev);
13358
13359         bp->flags = 0;
13360         if (is_vf)
13361                 bp->flags |= IS_VF_FLAG;
13362
13363         bp->igu_sb_cnt = max_non_def_sbs;
13364         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13365         bp->msg_enable = debug;
13366         bp->cnic_support = cnic_cnt;
13367         bp->cnic_probe = bnx2x_cnic_probe;
13368
13369         pci_set_drvdata(pdev, dev);
13370
13371         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13372         if (rc < 0) {
13373                 free_netdev(dev);
13374                 return rc;
13375         }
13376
13377         BNX2X_DEV_INFO("This is a %s function\n",
13378                        IS_PF(bp) ? "physical" : "virtual");
13379         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13380         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13381         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13382                        tx_count, rx_count);
13383
13384         rc = bnx2x_init_bp(bp);
13385         if (rc)
13386                 goto init_one_exit;
13387
13388         /* Map doorbells here as we need the real value of bp->max_cos which
13389          * is initialized in bnx2x_init_bp() to determine the number of
13390          * l2 connections.
13391          */
13392         if (IS_VF(bp)) {
13393                 bp->doorbells = bnx2x_vf_doorbells(bp);
13394                 rc = bnx2x_vf_pci_alloc(bp);
13395                 if (rc)
13396                         goto init_one_exit;
13397         } else {
13398                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13399                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13400                         dev_err(&bp->pdev->dev,
13401                                 "Cannot map doorbells, bar size too small, aborting\n");
13402                         rc = -ENOMEM;
13403                         goto init_one_exit;
13404                 }
13405                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13406                                                 doorbell_size);
13407         }
13408         if (!bp->doorbells) {
13409                 dev_err(&bp->pdev->dev,
13410                         "Cannot map doorbell space, aborting\n");
13411                 rc = -ENOMEM;
13412                 goto init_one_exit;
13413         }
13414
13415         if (IS_VF(bp)) {
13416                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13417                 if (rc)
13418                         goto init_one_exit;
13419         }
13420
13421         /* Enable SRIOV if capability found in configuration space */
13422         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13423         if (rc)
13424                 goto init_one_exit;
13425
13426         /* calc qm_cid_count */
13427         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13428         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13429
13430         /* disable FCOE L2 queue for E1x*/
13431         if (CHIP_IS_E1x(bp))
13432                 bp->flags |= NO_FCOE_FLAG;
13433
13434         /* Set bp->num_queues for MSI-X mode*/
13435         bnx2x_set_num_queues(bp);
13436
13437         /* Configure interrupt mode: try to enable MSI-X/MSI if
13438          * needed.
13439          */
13440         rc = bnx2x_set_int_mode(bp);
13441         if (rc) {
13442                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13443                 goto init_one_exit;
13444         }
13445         BNX2X_DEV_INFO("set interrupts successfully\n");
13446
13447         /* register the net device */
13448         rc = register_netdev(dev);
13449         if (rc) {
13450                 dev_err(&pdev->dev, "Cannot register net device\n");
13451                 goto init_one_exit;
13452         }
13453         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13454
13455         if (!NO_FCOE(bp)) {
13456                 /* Add storage MAC address */
13457                 rtnl_lock();
13458                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13459                 rtnl_unlock();
13460         }
13461         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13462             pcie_speed == PCI_SPEED_UNKNOWN ||
13463             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13464                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13465         else
13466                 BNX2X_DEV_INFO(
13467                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13468                        board_info[ent->driver_data].name,
13469                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13470                        pcie_width,
13471                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13472                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13473                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13474                        "Unknown",
13475                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13476
13477         bnx2x_register_phc(bp);
13478
13479         return 0;
13480
13481 init_one_exit:
13482         bnx2x_disable_pcie_error_reporting(bp);
13483
13484         if (bp->regview)
13485                 iounmap(bp->regview);
13486
13487         if (IS_PF(bp) && bp->doorbells)
13488                 iounmap(bp->doorbells);
13489
13490         free_netdev(dev);
13491
13492         if (atomic_read(&pdev->enable_cnt) == 1)
13493                 pci_release_regions(pdev);
13494
13495         pci_disable_device(pdev);
13496
13497         return rc;
13498 }
13499
13500 static void __bnx2x_remove(struct pci_dev *pdev,
13501                            struct net_device *dev,
13502                            struct bnx2x *bp,
13503                            bool remove_netdev)
13504 {
13505         if (bp->ptp_clock) {
13506                 ptp_clock_unregister(bp->ptp_clock);
13507                 bp->ptp_clock = NULL;
13508         }
13509
13510         /* Delete storage MAC address */
13511         if (!NO_FCOE(bp)) {
13512                 rtnl_lock();
13513                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13514                 rtnl_unlock();
13515         }
13516
13517 #ifdef BCM_DCBNL
13518         /* Delete app tlvs from dcbnl */
13519         bnx2x_dcbnl_update_applist(bp, true);
13520 #endif
13521
13522         if (IS_PF(bp) &&
13523             !BP_NOMCP(bp) &&
13524             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13525                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13526
13527         /* Close the interface - either directly or implicitly */
13528         if (remove_netdev) {
13529                 unregister_netdev(dev);
13530         } else {
13531                 rtnl_lock();
13532                 dev_close(dev);
13533                 rtnl_unlock();
13534         }
13535
13536         bnx2x_iov_remove_one(bp);
13537
13538         /* Power on: we can't let PCI layer write to us while we are in D3 */
13539         if (IS_PF(bp)) {
13540                 bnx2x_set_power_state(bp, PCI_D0);
13541
13542                 /* Set endianity registers to reset values in case next driver
13543                  * boots in different endianty environment.
13544                  */
13545                 bnx2x_reset_endianity(bp);
13546         }
13547
13548         /* Disable MSI/MSI-X */
13549         bnx2x_disable_msi(bp);
13550
13551         /* Power off */
13552         if (IS_PF(bp))
13553                 bnx2x_set_power_state(bp, PCI_D3hot);
13554
13555         /* Make sure RESET task is not scheduled before continuing */
13556         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13557
13558         /* send message via vfpf channel to release the resources of this vf */
13559         if (IS_VF(bp))
13560                 bnx2x_vfpf_release(bp);
13561
13562         /* Assumes no further PCIe PM changes will occur */
13563         if (system_state == SYSTEM_POWER_OFF) {
13564                 pci_wake_from_d3(pdev, bp->wol);
13565                 pci_set_power_state(pdev, PCI_D3hot);
13566         }
13567
13568         bnx2x_disable_pcie_error_reporting(bp);
13569         if (remove_netdev) {
13570                 if (bp->regview)
13571                         iounmap(bp->regview);
13572
13573                 /* For vfs, doorbells are part of the regview and were unmapped
13574                  * along with it. FW is only loaded by PF.
13575                  */
13576                 if (IS_PF(bp)) {
13577                         if (bp->doorbells)
13578                                 iounmap(bp->doorbells);
13579
13580                         bnx2x_release_firmware(bp);
13581                 } else {
13582                         bnx2x_vf_pci_dealloc(bp);
13583                 }
13584                 bnx2x_free_mem_bp(bp);
13585
13586                 free_netdev(dev);
13587
13588                 if (atomic_read(&pdev->enable_cnt) == 1)
13589                         pci_release_regions(pdev);
13590
13591                 pci_disable_device(pdev);
13592         }
13593 }
13594
13595 static void bnx2x_remove_one(struct pci_dev *pdev)
13596 {
13597         struct net_device *dev = pci_get_drvdata(pdev);
13598         struct bnx2x *bp;
13599
13600         if (!dev) {
13601                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13602                 return;
13603         }
13604         bp = netdev_priv(dev);
13605
13606         __bnx2x_remove(pdev, dev, bp, true);
13607 }
13608
13609 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13610 {
13611         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13612
13613         bp->rx_mode = BNX2X_RX_MODE_NONE;
13614
13615         if (CNIC_LOADED(bp))
13616                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13617
13618         /* Stop Tx */
13619         bnx2x_tx_disable(bp);
13620         /* Delete all NAPI objects */
13621         bnx2x_del_all_napi(bp);
13622         if (CNIC_LOADED(bp))
13623                 bnx2x_del_all_napi_cnic(bp);
13624         netdev_reset_tc(bp->dev);
13625
13626         del_timer_sync(&bp->timer);
13627         cancel_delayed_work_sync(&bp->sp_task);
13628         cancel_delayed_work_sync(&bp->period_task);
13629
13630         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
13631                 bp->stats_state = STATS_STATE_DISABLED;
13632                 up(&bp->stats_lock);
13633         }
13634
13635         bnx2x_save_statistics(bp);
13636
13637         netif_carrier_off(bp->dev);
13638
13639         return 0;
13640 }
13641
13642 /**
13643  * bnx2x_io_error_detected - called when PCI error is detected
13644  * @pdev: Pointer to PCI device
13645  * @state: The current pci connection state
13646  *
13647  * This function is called after a PCI bus error affecting
13648  * this device has been detected.
13649  */
13650 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13651                                                 pci_channel_state_t state)
13652 {
13653         struct net_device *dev = pci_get_drvdata(pdev);
13654         struct bnx2x *bp = netdev_priv(dev);
13655
13656         rtnl_lock();
13657
13658         BNX2X_ERR("IO error detected\n");
13659
13660         netif_device_detach(dev);
13661
13662         if (state == pci_channel_io_perm_failure) {
13663                 rtnl_unlock();
13664                 return PCI_ERS_RESULT_DISCONNECT;
13665         }
13666
13667         if (netif_running(dev))
13668                 bnx2x_eeh_nic_unload(bp);
13669
13670         bnx2x_prev_path_mark_eeh(bp);
13671
13672         pci_disable_device(pdev);
13673
13674         rtnl_unlock();
13675
13676         /* Request a slot reset */
13677         return PCI_ERS_RESULT_NEED_RESET;
13678 }
13679
13680 /**
13681  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13682  * @pdev: Pointer to PCI device
13683  *
13684  * Restart the card from scratch, as if from a cold-boot.
13685  */
13686 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13687 {
13688         struct net_device *dev = pci_get_drvdata(pdev);
13689         struct bnx2x *bp = netdev_priv(dev);
13690         int i;
13691
13692         rtnl_lock();
13693         BNX2X_ERR("IO slot reset initializing...\n");
13694         if (pci_enable_device(pdev)) {
13695                 dev_err(&pdev->dev,
13696                         "Cannot re-enable PCI device after reset\n");
13697                 rtnl_unlock();
13698                 return PCI_ERS_RESULT_DISCONNECT;
13699         }
13700
13701         pci_set_master(pdev);
13702         pci_restore_state(pdev);
13703         pci_save_state(pdev);
13704
13705         if (netif_running(dev))
13706                 bnx2x_set_power_state(bp, PCI_D0);
13707
13708         if (netif_running(dev)) {
13709                 BNX2X_ERR("IO slot reset --> driver unload\n");
13710
13711                 /* MCP should have been reset; Need to wait for validity */
13712                 bnx2x_init_shmem(bp);
13713
13714                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13715                         u32 v;
13716
13717                         v = SHMEM2_RD(bp,
13718                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13719                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13720                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13721                 }
13722                 bnx2x_drain_tx_queues(bp);
13723                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13724                 bnx2x_netif_stop(bp, 1);
13725                 bnx2x_free_irq(bp);
13726
13727                 /* Report UNLOAD_DONE to MCP */
13728                 bnx2x_send_unload_done(bp, true);
13729
13730                 bp->sp_state = 0;
13731                 bp->port.pmf = 0;
13732
13733                 bnx2x_prev_unload(bp);
13734
13735                 /* We should have reseted the engine, so It's fair to
13736                  * assume the FW will no longer write to the bnx2x driver.
13737                  */
13738                 bnx2x_squeeze_objects(bp);
13739                 bnx2x_free_skbs(bp);
13740                 for_each_rx_queue(bp, i)
13741                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13742                 bnx2x_free_fp_mem(bp);
13743                 bnx2x_free_mem(bp);
13744
13745                 bp->state = BNX2X_STATE_CLOSED;
13746         }
13747
13748         rtnl_unlock();
13749
13750         /* If AER, perform cleanup of the PCIe registers */
13751         if (bp->flags & AER_ENABLED) {
13752                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13753                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13754                 else
13755                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13756         }
13757
13758         return PCI_ERS_RESULT_RECOVERED;
13759 }
13760
13761 /**
13762  * bnx2x_io_resume - called when traffic can start flowing again
13763  * @pdev: Pointer to PCI device
13764  *
13765  * This callback is called when the error recovery driver tells us that
13766  * its OK to resume normal operation.
13767  */
13768 static void bnx2x_io_resume(struct pci_dev *pdev)
13769 {
13770         struct net_device *dev = pci_get_drvdata(pdev);
13771         struct bnx2x *bp = netdev_priv(dev);
13772
13773         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13774                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13775                 return;
13776         }
13777
13778         rtnl_lock();
13779
13780         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13781                                                         DRV_MSG_SEQ_NUMBER_MASK;
13782
13783         if (netif_running(dev))
13784                 bnx2x_nic_load(bp, LOAD_NORMAL);
13785
13786         netif_device_attach(dev);
13787
13788         rtnl_unlock();
13789 }
13790
13791 static const struct pci_error_handlers bnx2x_err_handler = {
13792         .error_detected = bnx2x_io_error_detected,
13793         .slot_reset     = bnx2x_io_slot_reset,
13794         .resume         = bnx2x_io_resume,
13795 };
13796
13797 static void bnx2x_shutdown(struct pci_dev *pdev)
13798 {
13799         struct net_device *dev = pci_get_drvdata(pdev);
13800         struct bnx2x *bp;
13801
13802         if (!dev)
13803                 return;
13804
13805         bp = netdev_priv(dev);
13806         if (!bp)
13807                 return;
13808
13809         rtnl_lock();
13810         netif_device_detach(dev);
13811         rtnl_unlock();
13812
13813         /* Don't remove the netdevice, as there are scenarios which will cause
13814          * the kernel to hang, e.g., when trying to remove bnx2i while the
13815          * rootfs is mounted from SAN.
13816          */
13817         __bnx2x_remove(pdev, dev, bp, false);
13818 }
13819
13820 static struct pci_driver bnx2x_pci_driver = {
13821         .name        = DRV_MODULE_NAME,
13822         .id_table    = bnx2x_pci_tbl,
13823         .probe       = bnx2x_init_one,
13824         .remove      = bnx2x_remove_one,
13825         .suspend     = bnx2x_suspend,
13826         .resume      = bnx2x_resume,
13827         .err_handler = &bnx2x_err_handler,
13828 #ifdef CONFIG_BNX2X_SRIOV
13829         .sriov_configure = bnx2x_sriov_configure,
13830 #endif
13831         .shutdown    = bnx2x_shutdown,
13832 };
13833
13834 static int __init bnx2x_init(void)
13835 {
13836         int ret;
13837
13838         pr_info("%s", version);
13839
13840         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13841         if (bnx2x_wq == NULL) {
13842                 pr_err("Cannot create workqueue\n");
13843                 return -ENOMEM;
13844         }
13845         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13846         if (!bnx2x_iov_wq) {
13847                 pr_err("Cannot create iov workqueue\n");
13848                 destroy_workqueue(bnx2x_wq);
13849                 return -ENOMEM;
13850         }
13851
13852         ret = pci_register_driver(&bnx2x_pci_driver);
13853         if (ret) {
13854                 pr_err("Cannot register driver\n");
13855                 destroy_workqueue(bnx2x_wq);
13856                 destroy_workqueue(bnx2x_iov_wq);
13857         }
13858         return ret;
13859 }
13860
13861 static void __exit bnx2x_cleanup(void)
13862 {
13863         struct list_head *pos, *q;
13864
13865         pci_unregister_driver(&bnx2x_pci_driver);
13866
13867         destroy_workqueue(bnx2x_wq);
13868         destroy_workqueue(bnx2x_iov_wq);
13869
13870         /* Free globally allocated resources */
13871         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13872                 struct bnx2x_prev_path_list *tmp =
13873                         list_entry(pos, struct bnx2x_prev_path_list, list);
13874                 list_del(pos);
13875                 kfree(tmp);
13876         }
13877 }
13878
13879 void bnx2x_notify_link_changed(struct bnx2x *bp)
13880 {
13881         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13882 }
13883
13884 module_init(bnx2x_init);
13885 module_exit(bnx2x_cleanup);
13886
13887 /**
13888  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13889  *
13890  * @bp:         driver handle
13891  * @set:        set or clear the CAM entry
13892  *
13893  * This function will wait until the ramrod completion returns.
13894  * Return 0 if success, -ENODEV if ramrod doesn't return.
13895  */
13896 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13897 {
13898         unsigned long ramrod_flags = 0;
13899
13900         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13901         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13902                                  &bp->iscsi_l2_mac_obj, true,
13903                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13904 }
13905
13906 /* count denotes the number of new completions we have seen */
13907 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13908 {
13909         struct eth_spe *spe;
13910         int cxt_index, cxt_offset;
13911
13912 #ifdef BNX2X_STOP_ON_ERROR
13913         if (unlikely(bp->panic))
13914                 return;
13915 #endif
13916
13917         spin_lock_bh(&bp->spq_lock);
13918         BUG_ON(bp->cnic_spq_pending < count);
13919         bp->cnic_spq_pending -= count;
13920
13921         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13922                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13923                                 & SPE_HDR_CONN_TYPE) >>
13924                                 SPE_HDR_CONN_TYPE_SHIFT;
13925                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13926                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13927
13928                 /* Set validation for iSCSI L2 client before sending SETUP
13929                  *  ramrod
13930                  */
13931                 if (type == ETH_CONNECTION_TYPE) {
13932                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13933                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13934                                         ILT_PAGE_CIDS;
13935                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13936                                         (cxt_index * ILT_PAGE_CIDS);
13937                                 bnx2x_set_ctx_validation(bp,
13938                                         &bp->context[cxt_index].
13939                                                          vcxt[cxt_offset].eth,
13940                                         BNX2X_ISCSI_ETH_CID(bp));
13941                         }
13942                 }
13943
13944                 /*
13945                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13946                  * and in the air. We also check that number of outstanding
13947                  * COMMON ramrods is not more than the EQ and SPQ can
13948                  * accommodate.
13949                  */
13950                 if (type == ETH_CONNECTION_TYPE) {
13951                         if (!atomic_read(&bp->cq_spq_left))
13952                                 break;
13953                         else
13954                                 atomic_dec(&bp->cq_spq_left);
13955                 } else if (type == NONE_CONNECTION_TYPE) {
13956                         if (!atomic_read(&bp->eq_spq_left))
13957                                 break;
13958                         else
13959                                 atomic_dec(&bp->eq_spq_left);
13960                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13961                            (type == FCOE_CONNECTION_TYPE)) {
13962                         if (bp->cnic_spq_pending >=
13963                             bp->cnic_eth_dev.max_kwqe_pending)
13964                                 break;
13965                         else
13966                                 bp->cnic_spq_pending++;
13967                 } else {
13968                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13969                         bnx2x_panic();
13970                         break;
13971                 }
13972
13973                 spe = bnx2x_sp_get_next(bp);
13974                 *spe = *bp->cnic_kwq_cons;
13975
13976                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13977                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13978
13979                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13980                         bp->cnic_kwq_cons = bp->cnic_kwq;
13981                 else
13982                         bp->cnic_kwq_cons++;
13983         }
13984         bnx2x_sp_prod_update(bp);
13985         spin_unlock_bh(&bp->spq_lock);
13986 }
13987
13988 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13989                                struct kwqe_16 *kwqes[], u32 count)
13990 {
13991         struct bnx2x *bp = netdev_priv(dev);
13992         int i;
13993
13994 #ifdef BNX2X_STOP_ON_ERROR
13995         if (unlikely(bp->panic)) {
13996                 BNX2X_ERR("Can't post to SP queue while panic\n");
13997                 return -EIO;
13998         }
13999 #endif
14000
14001         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14002             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14003                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14004                 return -EAGAIN;
14005         }
14006
14007         spin_lock_bh(&bp->spq_lock);
14008
14009         for (i = 0; i < count; i++) {
14010                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14011
14012                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14013                         break;
14014
14015                 *bp->cnic_kwq_prod = *spe;
14016
14017                 bp->cnic_kwq_pending++;
14018
14019                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14020                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14021                    spe->data.update_data_addr.hi,
14022                    spe->data.update_data_addr.lo,
14023                    bp->cnic_kwq_pending);
14024
14025                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14026                         bp->cnic_kwq_prod = bp->cnic_kwq;
14027                 else
14028                         bp->cnic_kwq_prod++;
14029         }
14030
14031         spin_unlock_bh(&bp->spq_lock);
14032
14033         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14034                 bnx2x_cnic_sp_post(bp, 0);
14035
14036         return i;
14037 }
14038
14039 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14040 {
14041         struct cnic_ops *c_ops;
14042         int rc = 0;
14043
14044         mutex_lock(&bp->cnic_mutex);
14045         c_ops = rcu_dereference_protected(bp->cnic_ops,
14046                                           lockdep_is_held(&bp->cnic_mutex));
14047         if (c_ops)
14048                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14049         mutex_unlock(&bp->cnic_mutex);
14050
14051         return rc;
14052 }
14053
14054 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14055 {
14056         struct cnic_ops *c_ops;
14057         int rc = 0;
14058
14059         rcu_read_lock();
14060         c_ops = rcu_dereference(bp->cnic_ops);
14061         if (c_ops)
14062                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14063         rcu_read_unlock();
14064
14065         return rc;
14066 }
14067
14068 /*
14069  * for commands that have no data
14070  */
14071 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14072 {
14073         struct cnic_ctl_info ctl = {0};
14074
14075         ctl.cmd = cmd;
14076
14077         return bnx2x_cnic_ctl_send(bp, &ctl);
14078 }
14079
14080 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14081 {
14082         struct cnic_ctl_info ctl = {0};
14083
14084         /* first we tell CNIC and only then we count this as a completion */
14085         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14086         ctl.data.comp.cid = cid;
14087         ctl.data.comp.error = err;
14088
14089         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14090         bnx2x_cnic_sp_post(bp, 0);
14091 }
14092
14093 /* Called with netif_addr_lock_bh() taken.
14094  * Sets an rx_mode config for an iSCSI ETH client.
14095  * Doesn't block.
14096  * Completion should be checked outside.
14097  */
14098 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14099 {
14100         unsigned long accept_flags = 0, ramrod_flags = 0;
14101         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14102         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14103
14104         if (start) {
14105                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14106                  * because it's the only way for UIO Queue to accept
14107                  * multicasts (in non-promiscuous mode only one Queue per
14108                  * function will receive multicast packets (leading in our
14109                  * case).
14110                  */
14111                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14112                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14113                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14114                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14115
14116                 /* Clear STOP_PENDING bit if START is requested */
14117                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14118
14119                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14120         } else
14121                 /* Clear START_PENDING bit if STOP is requested */
14122                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14123
14124         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14125                 set_bit(sched_state, &bp->sp_state);
14126         else {
14127                 __set_bit(RAMROD_RX, &ramrod_flags);
14128                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14129                                     ramrod_flags);
14130         }
14131 }
14132
14133 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14134 {
14135         struct bnx2x *bp = netdev_priv(dev);
14136         int rc = 0;
14137
14138         switch (ctl->cmd) {
14139         case DRV_CTL_CTXTBL_WR_CMD: {
14140                 u32 index = ctl->data.io.offset;
14141                 dma_addr_t addr = ctl->data.io.dma_addr;
14142
14143                 bnx2x_ilt_wr(bp, index, addr);
14144                 break;
14145         }
14146
14147         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14148                 int count = ctl->data.credit.credit_count;
14149
14150                 bnx2x_cnic_sp_post(bp, count);
14151                 break;
14152         }
14153
14154         /* rtnl_lock is held.  */
14155         case DRV_CTL_START_L2_CMD: {
14156                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14157                 unsigned long sp_bits = 0;
14158
14159                 /* Configure the iSCSI classification object */
14160                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14161                                    cp->iscsi_l2_client_id,
14162                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14163                                    bnx2x_sp(bp, mac_rdata),
14164                                    bnx2x_sp_mapping(bp, mac_rdata),
14165                                    BNX2X_FILTER_MAC_PENDING,
14166                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14167                                    &bp->macs_pool);
14168
14169                 /* Set iSCSI MAC address */
14170                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14171                 if (rc)
14172                         break;
14173
14174                 mmiowb();
14175                 barrier();
14176
14177                 /* Start accepting on iSCSI L2 ring */
14178
14179                 netif_addr_lock_bh(dev);
14180                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14181                 netif_addr_unlock_bh(dev);
14182
14183                 /* bits to wait on */
14184                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14185                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14186
14187                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14188                         BNX2X_ERR("rx_mode completion timed out!\n");
14189
14190                 break;
14191         }
14192
14193         /* rtnl_lock is held.  */
14194         case DRV_CTL_STOP_L2_CMD: {
14195                 unsigned long sp_bits = 0;
14196
14197                 /* Stop accepting on iSCSI L2 ring */
14198                 netif_addr_lock_bh(dev);
14199                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14200                 netif_addr_unlock_bh(dev);
14201
14202                 /* bits to wait on */
14203                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14204                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14205
14206                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14207                         BNX2X_ERR("rx_mode completion timed out!\n");
14208
14209                 mmiowb();
14210                 barrier();
14211
14212                 /* Unset iSCSI L2 MAC */
14213                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14214                                         BNX2X_ISCSI_ETH_MAC, true);
14215                 break;
14216         }
14217         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14218                 int count = ctl->data.credit.credit_count;
14219
14220                 smp_mb__before_atomic();
14221                 atomic_add(count, &bp->cq_spq_left);
14222                 smp_mb__after_atomic();
14223                 break;
14224         }
14225         case DRV_CTL_ULP_REGISTER_CMD: {
14226                 int ulp_type = ctl->data.register_data.ulp_type;
14227
14228                 if (CHIP_IS_E3(bp)) {
14229                         int idx = BP_FW_MB_IDX(bp);
14230                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14231                         int path = BP_PATH(bp);
14232                         int port = BP_PORT(bp);
14233                         int i;
14234                         u32 scratch_offset;
14235                         u32 *host_addr;
14236
14237                         /* first write capability to shmem2 */
14238                         if (ulp_type == CNIC_ULP_ISCSI)
14239                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14240                         else if (ulp_type == CNIC_ULP_FCOE)
14241                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14242                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14243
14244                         if ((ulp_type != CNIC_ULP_FCOE) ||
14245                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14246                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14247                                 break;
14248
14249                         /* if reached here - should write fcoe capabilities */
14250                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14251                         if (!scratch_offset)
14252                                 break;
14253                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14254                                                    fcoe_features[path][port]);
14255                         host_addr = (u32 *) &(ctl->data.register_data.
14256                                               fcoe_features);
14257                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14258                              i += 4)
14259                                 REG_WR(bp, scratch_offset + i,
14260                                        *(host_addr + i/4));
14261                 }
14262                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14263                 break;
14264         }
14265
14266         case DRV_CTL_ULP_UNREGISTER_CMD: {
14267                 int ulp_type = ctl->data.ulp_type;
14268
14269                 if (CHIP_IS_E3(bp)) {
14270                         int idx = BP_FW_MB_IDX(bp);
14271                         u32 cap;
14272
14273                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14274                         if (ulp_type == CNIC_ULP_ISCSI)
14275                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14276                         else if (ulp_type == CNIC_ULP_FCOE)
14277                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14278                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14279                 }
14280                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14281                 break;
14282         }
14283
14284         default:
14285                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14286                 rc = -EINVAL;
14287         }
14288
14289         return rc;
14290 }
14291
14292 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14293 {
14294         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14295
14296         if (bp->flags & USING_MSIX_FLAG) {
14297                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14298                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14299                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14300         } else {
14301                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14302                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14303         }
14304         if (!CHIP_IS_E1x(bp))
14305                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14306         else
14307                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14308
14309         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14310         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14311         cp->irq_arr[1].status_blk = bp->def_status_blk;
14312         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14313         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14314
14315         cp->num_irq = 2;
14316 }
14317
14318 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14319 {
14320         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14321
14322         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14323                              bnx2x_cid_ilt_lines(bp);
14324         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14325         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14326         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14327
14328         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14329            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14330            cp->iscsi_l2_cid);
14331
14332         if (NO_ISCSI_OOO(bp))
14333                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14334 }
14335
14336 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14337                                void *data)
14338 {
14339         struct bnx2x *bp = netdev_priv(dev);
14340         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14341         int rc;
14342
14343         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14344
14345         if (ops == NULL) {
14346                 BNX2X_ERR("NULL ops received\n");
14347                 return -EINVAL;
14348         }
14349
14350         if (!CNIC_SUPPORT(bp)) {
14351                 BNX2X_ERR("Can't register CNIC when not supported\n");
14352                 return -EOPNOTSUPP;
14353         }
14354
14355         if (!CNIC_LOADED(bp)) {
14356                 rc = bnx2x_load_cnic(bp);
14357                 if (rc) {
14358                         BNX2X_ERR("CNIC-related load failed\n");
14359                         return rc;
14360                 }
14361         }
14362
14363         bp->cnic_enabled = true;
14364
14365         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14366         if (!bp->cnic_kwq)
14367                 return -ENOMEM;
14368
14369         bp->cnic_kwq_cons = bp->cnic_kwq;
14370         bp->cnic_kwq_prod = bp->cnic_kwq;
14371         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14372
14373         bp->cnic_spq_pending = 0;
14374         bp->cnic_kwq_pending = 0;
14375
14376         bp->cnic_data = data;
14377
14378         cp->num_irq = 0;
14379         cp->drv_state |= CNIC_DRV_STATE_REGD;
14380         cp->iro_arr = bp->iro_arr;
14381
14382         bnx2x_setup_cnic_irq_info(bp);
14383
14384         rcu_assign_pointer(bp->cnic_ops, ops);
14385
14386         /* Schedule driver to read CNIC driver versions */
14387         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14388
14389         return 0;
14390 }
14391
14392 static int bnx2x_unregister_cnic(struct net_device *dev)
14393 {
14394         struct bnx2x *bp = netdev_priv(dev);
14395         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14396
14397         mutex_lock(&bp->cnic_mutex);
14398         cp->drv_state = 0;
14399         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14400         mutex_unlock(&bp->cnic_mutex);
14401         synchronize_rcu();
14402         bp->cnic_enabled = false;
14403         kfree(bp->cnic_kwq);
14404         bp->cnic_kwq = NULL;
14405
14406         return 0;
14407 }
14408
14409 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14410 {
14411         struct bnx2x *bp = netdev_priv(dev);
14412         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14413
14414         /* If both iSCSI and FCoE are disabled - return NULL in
14415          * order to indicate CNIC that it should not try to work
14416          * with this device.
14417          */
14418         if (NO_ISCSI(bp) && NO_FCOE(bp))
14419                 return NULL;
14420
14421         cp->drv_owner = THIS_MODULE;
14422         cp->chip_id = CHIP_ID(bp);
14423         cp->pdev = bp->pdev;
14424         cp->io_base = bp->regview;
14425         cp->io_base2 = bp->doorbells;
14426         cp->max_kwqe_pending = 8;
14427         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14428         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14429                              bnx2x_cid_ilt_lines(bp);
14430         cp->ctx_tbl_len = CNIC_ILT_LINES;
14431         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14432         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14433         cp->drv_ctl = bnx2x_drv_ctl;
14434         cp->drv_register_cnic = bnx2x_register_cnic;
14435         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14436         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14437         cp->iscsi_l2_client_id =
14438                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14439         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14440
14441         if (NO_ISCSI_OOO(bp))
14442                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14443
14444         if (NO_ISCSI(bp))
14445                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14446
14447         if (NO_FCOE(bp))
14448                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14449
14450         BNX2X_DEV_INFO(
14451                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14452            cp->ctx_blk_size,
14453            cp->ctx_tbl_offset,
14454            cp->ctx_tbl_len,
14455            cp->starting_cid);
14456         return cp;
14457 }
14458
14459 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14460 {
14461         struct bnx2x *bp = fp->bp;
14462         u32 offset = BAR_USTRORM_INTMEM;
14463
14464         if (IS_VF(bp))
14465                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14466         else if (!CHIP_IS_E1x(bp))
14467                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14468         else
14469                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14470
14471         return offset;
14472 }
14473
14474 /* called only on E1H or E2.
14475  * When pretending to be PF, the pretend value is the function number 0...7
14476  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14477  * combination
14478  */
14479 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14480 {
14481         u32 pretend_reg;
14482
14483         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14484                 return -1;
14485
14486         /* get my own pretend register */
14487         pretend_reg = bnx2x_get_pretend_reg(bp);
14488         REG_WR(bp, pretend_reg, pretend_func_val);
14489         REG_RD(bp, pretend_reg);
14490         return 0;
14491 }
14492
14493 static void bnx2x_ptp_task(struct work_struct *work)
14494 {
14495         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14496         int port = BP_PORT(bp);
14497         u32 val_seq;
14498         u64 timestamp, ns;
14499         struct skb_shared_hwtstamps shhwtstamps;
14500
14501         /* Read Tx timestamp registers */
14502         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14503                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14504         if (val_seq & 0x10000) {
14505                 /* There is a valid timestamp value */
14506                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14507                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14508                 timestamp <<= 32;
14509                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14510                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14511                 /* Reset timestamp register to allow new timestamp */
14512                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14513                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14514                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14515
14516                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14517                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14518                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14519                 dev_kfree_skb_any(bp->ptp_tx_skb);
14520                 bp->ptp_tx_skb = NULL;
14521
14522                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14523                    timestamp, ns);
14524         } else {
14525                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14526                 /* Reschedule to keep checking for a valid timestamp value */
14527                 schedule_work(&bp->ptp_task);
14528         }
14529 }
14530
14531 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14532 {
14533         int port = BP_PORT(bp);
14534         u64 timestamp, ns;
14535
14536         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14537                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14538         timestamp <<= 32;
14539         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14540                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14541
14542         /* Reset timestamp register to allow new timestamp */
14543         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14544                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14545
14546         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14547
14548         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14549
14550         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14551            timestamp, ns);
14552 }
14553
14554 /* Read the PHC */
14555 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14556 {
14557         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14558         int port = BP_PORT(bp);
14559         u32 wb_data[2];
14560         u64 phc_cycles;
14561
14562         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14563                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14564         phc_cycles = wb_data[1];
14565         phc_cycles = (phc_cycles << 32) + wb_data[0];
14566
14567         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14568
14569         return phc_cycles;
14570 }
14571
14572 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14573 {
14574         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14575         bp->cyclecounter.read = bnx2x_cyclecounter_read;
14576         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
14577         bp->cyclecounter.shift = 1;
14578         bp->cyclecounter.mult = 1;
14579 }
14580
14581 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14582 {
14583         struct bnx2x_func_state_params func_params = {NULL};
14584         struct bnx2x_func_set_timesync_params *set_timesync_params =
14585                 &func_params.params.set_timesync;
14586
14587         /* Prepare parameters for function state transitions */
14588         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14589         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14590
14591         func_params.f_obj = &bp->func_obj;
14592         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14593
14594         /* Function parameters */
14595         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14596         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14597
14598         return bnx2x_func_state_change(bp, &func_params);
14599 }
14600
14601 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14602 {
14603         struct bnx2x_queue_state_params q_params;
14604         int rc, i;
14605
14606         /* send queue update ramrod to enable PTP packets */
14607         memset(&q_params, 0, sizeof(q_params));
14608         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14609         q_params.cmd = BNX2X_Q_CMD_UPDATE;
14610         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14611                   &q_params.params.update.update_flags);
14612         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14613                   &q_params.params.update.update_flags);
14614
14615         /* send the ramrod on all the queues of the PF */
14616         for_each_eth_queue(bp, i) {
14617                 struct bnx2x_fastpath *fp = &bp->fp[i];
14618
14619                 /* Set the appropriate Queue object */
14620                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14621
14622                 /* Update the Queue state */
14623                 rc = bnx2x_queue_state_change(bp, &q_params);
14624                 if (rc) {
14625                         BNX2X_ERR("Failed to enable PTP packets\n");
14626                         return rc;
14627                 }
14628         }
14629
14630         return 0;
14631 }
14632
14633 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14634 {
14635         int port = BP_PORT(bp);
14636         int rc;
14637
14638         if (!bp->hwtstamp_ioctl_called)
14639                 return 0;
14640
14641         switch (bp->tx_type) {
14642         case HWTSTAMP_TX_ON:
14643                 bp->flags |= TX_TIMESTAMPING_EN;
14644                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14645                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14646                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14647                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14648                 break;
14649         case HWTSTAMP_TX_ONESTEP_SYNC:
14650                 BNX2X_ERR("One-step timestamping is not supported\n");
14651                 return -ERANGE;
14652         }
14653
14654         switch (bp->rx_filter) {
14655         case HWTSTAMP_FILTER_NONE:
14656                 break;
14657         case HWTSTAMP_FILTER_ALL:
14658         case HWTSTAMP_FILTER_SOME:
14659                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14660                 break;
14661         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14662         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14663         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14664                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14665                 /* Initialize PTP detection for UDP/IPv4 events */
14666                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14667                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14668                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14669                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14670                 break;
14671         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14672         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14673         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14674                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14675                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14676                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14677                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14678                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14679                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14680                 break;
14681         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14682         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14683         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14684                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14685                 /* Initialize PTP detection L2 events */
14686                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14687                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14688                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14689                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14690
14691                 break;
14692         case HWTSTAMP_FILTER_PTP_V2_EVENT:
14693         case HWTSTAMP_FILTER_PTP_V2_SYNC:
14694         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14695                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14696                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14697                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14698                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14699                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14700                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14701                 break;
14702         }
14703
14704         /* Indicate to FW that this PF expects recorded PTP packets */
14705         rc = bnx2x_enable_ptp_packets(bp);
14706         if (rc)
14707                 return rc;
14708
14709         /* Enable sending PTP packets to host */
14710         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14711                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14712
14713         return 0;
14714 }
14715
14716 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14717 {
14718         struct hwtstamp_config config;
14719         int rc;
14720
14721         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14722
14723         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14724                 return -EFAULT;
14725
14726         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14727            config.tx_type, config.rx_filter);
14728
14729         if (config.flags) {
14730                 BNX2X_ERR("config.flags is reserved for future use\n");
14731                 return -EINVAL;
14732         }
14733
14734         bp->hwtstamp_ioctl_called = 1;
14735         bp->tx_type = config.tx_type;
14736         bp->rx_filter = config.rx_filter;
14737
14738         rc = bnx2x_configure_ptp_filters(bp);
14739         if (rc)
14740                 return rc;
14741
14742         config.rx_filter = bp->rx_filter;
14743
14744         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14745                 -EFAULT : 0;
14746 }
14747
14748 /* Configures HW for PTP */
14749 static int bnx2x_configure_ptp(struct bnx2x *bp)
14750 {
14751         int rc, port = BP_PORT(bp);
14752         u32 wb_data[2];
14753
14754         /* Reset PTP event detection rules - will be configured in the IOCTL */
14755         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14756                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14757         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14758                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14759         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14760                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14761         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14762                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14763
14764         /* Disable PTP packets to host - will be configured in the IOCTL*/
14765         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14766                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14767
14768         /* Enable the PTP feature */
14769         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14770                NIG_REG_P0_PTP_EN, 0x3F);
14771
14772         /* Enable the free-running counter */
14773         wb_data[0] = 0;
14774         wb_data[1] = 0;
14775         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14776
14777         /* Reset drift register (offset register is not reset) */
14778         rc = bnx2x_send_reset_timesync_ramrod(bp);
14779         if (rc) {
14780                 BNX2X_ERR("Failed to reset PHC drift register\n");
14781                 return -EFAULT;
14782         }
14783
14784         /* Reset possibly old timestamps */
14785         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14786                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14787         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14788                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14789
14790         return 0;
14791 }
14792
14793 /* Called during load, to initialize PTP-related stuff */
14794 void bnx2x_init_ptp(struct bnx2x *bp)
14795 {
14796         int rc;
14797
14798         /* Configure PTP in HW */
14799         rc = bnx2x_configure_ptp(bp);
14800         if (rc) {
14801                 BNX2X_ERR("Stopping PTP initialization\n");
14802                 return;
14803         }
14804
14805         /* Init work queue for Tx timestamping */
14806         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14807
14808         /* Init cyclecounter and timecounter. This is done only in the first
14809          * load. If done in every load, PTP application will fail when doing
14810          * unload / load (e.g. MTU change) while it is running.
14811          */
14812         if (!bp->timecounter_init_done) {
14813                 bnx2x_init_cyclecounter(bp);
14814                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14815                                  ktime_to_ns(ktime_get_real()));
14816                 bp->timecounter_init_done = 1;
14817         }
14818
14819         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14820 }