drivers/net/ethernet/amazon/ena/ena_com.c

   1 /*
   2  * Copyright 2015 Amazon.com, Inc. or its affiliates.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include "ena_com.h"
  34
  35 /*****************************************************************************/
  36 /*****************************************************************************/
  37
  38 /* Timeout in micro-sec */
  39 #define ADMIN_CMD_TIMEOUT_US (3000000)
  40
  41 #define ENA_ASYNC_QUEUE_DEPTH 16
  42 #define ENA_ADMIN_QUEUE_DEPTH 32
  43
  44 #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \
  45                 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \
  46                 | (ENA_COMMON_SPEC_VERSION_MINOR))
  47
  48 #define ENA_CTRL_MAJOR          0
  49 #define ENA_CTRL_MINOR          0
  50 #define ENA_CTRL_SUB_MINOR      1
  51
  52 #define MIN_ENA_CTRL_VER \
  53         (((ENA_CTRL_MAJOR) << \
  54         (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  55         ((ENA_CTRL_MINOR) << \
  56         (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  57         (ENA_CTRL_SUB_MINOR))
  58
  59 #define ENA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  60 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  61
  62 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
  63
  64 #define ENA_REGS_ADMIN_INTR_MASK 1
  65
  66 /*****************************************************************************/
  67 /*****************************************************************************/
  68 /*****************************************************************************/
  69
  70 enum ena_cmd_status {
  71         ENA_CMD_SUBMITTED,
  72         ENA_CMD_COMPLETED,
  73         /* Abort - canceled by the driver */
  74         ENA_CMD_ABORTED,
  75 };
  76
  77 struct ena_comp_ctx {
  78         struct completion wait_event;
  79         struct ena_admin_acq_entry *user_cqe;
  80         u32 comp_size;
  81         enum ena_cmd_status status;
  82         /* status from the device */
  83         u8 comp_status;
  84         u8 cmd_opcode;
  85         bool occupied;
  86 };
  87
  88 struct ena_com_stats_ctx {
  89         struct ena_admin_aq_get_stats_cmd get_cmd;
  90         struct ena_admin_acq_get_stats_resp get_resp;
  91 };
  92
  93 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
  94                                        struct ena_common_mem_addr *ena_addr,
  95                                        dma_addr_t addr)
  96 {
  97         if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
  98                 pr_err("dma address has more bits that the device supports\n");
  99                 return -EINVAL;
 100         }
 101
 102         ena_addr->mem_addr_low = (u32)addr;
 103         ena_addr->mem_addr_high = (u64)addr >> 32;
 104
 105         return 0;
 106 }
 107
 108 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
 109 {
 110         struct ena_com_admin_sq *sq = &queue->sq;
 111         u16 size = ADMIN_SQ_SIZE(queue->q_depth);
 112
 113         sq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &sq->dma_addr,
 114                                           GFP_KERNEL);
 115
 116         if (!sq->entries) {
 117                 pr_err("memory allocation failed");
 118                 return -ENOMEM;
 119         }
 120
 121         sq->head = 0;
 122         sq->tail = 0;
 123         sq->phase = 1;
 124
 125         sq->db_addr = NULL;
 126
 127         return 0;
 128 }
 129
 130 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
 131 {
 132         struct ena_com_admin_cq *cq = &queue->cq;
 133         u16 size = ADMIN_CQ_SIZE(queue->q_depth);
 134
 135         cq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &cq->dma_addr,
 136                                           GFP_KERNEL);
 137
 138         if (!cq->entries) {
 139                 pr_err("memory allocation failed");
 140                 return -ENOMEM;
 141         }
 142
 143         cq->head = 0;
 144         cq->phase = 1;
 145
 146         return 0;
 147 }
 148
 149 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
 150                                    struct ena_aenq_handlers *aenq_handlers)
 151 {
 152         struct ena_com_aenq *aenq = &dev->aenq;
 153         u32 addr_low, addr_high, aenq_caps;
 154         u16 size;
 155
 156         dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
 157         size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
 158         aenq->entries = dma_zalloc_coherent(dev->dmadev, size, &aenq->dma_addr,
 159                                             GFP_KERNEL);
 160
 161         if (!aenq->entries) {
 162                 pr_err("memory allocation failed");
 163                 return -ENOMEM;
 164         }
 165
 166         aenq->head = aenq->q_depth;
 167         aenq->phase = 1;
 168
 169         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 170         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 171
 172         writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
 173         writel(addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
 174
 175         aenq_caps = 0;
 176         aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 177         aenq_caps |= (sizeof(struct ena_admin_aenq_entry)
 178                       << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 179                      ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 180         writel(aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
 181
 182         if (unlikely(!aenq_handlers)) {
 183                 pr_err("aenq handlers pointer is NULL\n");
 184                 return -EINVAL;
 185         }
 186
 187         aenq->aenq_handlers = aenq_handlers;
 188
 189         return 0;
 190 }
 191
 192 static inline void comp_ctxt_release(struct ena_com_admin_queue *queue,
 193                                      struct ena_comp_ctx *comp_ctx)
 194 {
 195         comp_ctx->occupied = false;
 196         atomic_dec(&queue->outstanding_cmds);
 197 }
 198
 199 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
 200                                           u16 command_id, bool capture)
 201 {
 202         if (unlikely(command_id >= queue->q_depth)) {
 203                 pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
 204                        command_id, queue->q_depth);
 205                 return NULL;
 206         }
 207
 208         if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
 209                 pr_err("Completion context is occupied\n");
 210                 return NULL;
 211         }
 212
 213         if (capture) {
 214                 atomic_inc(&queue->outstanding_cmds);
 215                 queue->comp_ctx[command_id].occupied = true;
 216         }
 217
 218         return &queue->comp_ctx[command_id];
 219 }
 220
 221 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 222                                                        struct ena_admin_aq_entry *cmd,
 223                                                        size_t cmd_size_in_bytes,
 224                                                        struct ena_admin_acq_entry *comp,
 225                                                        size_t comp_size_in_bytes)
 226 {
 227         struct ena_comp_ctx *comp_ctx;
 228         u16 tail_masked, cmd_id;
 229         u16 queue_size_mask;
 230         u16 cnt;
 231
 232         queue_size_mask = admin_queue->q_depth - 1;
 233
 234         tail_masked = admin_queue->sq.tail & queue_size_mask;
 235
 236         /* In case of queue FULL */
 237         cnt = atomic_read(&admin_queue->outstanding_cmds);
 238         if (cnt >= admin_queue->q_depth) {
 239                 pr_debug("admin queue is full.\n");
 240                 admin_queue->stats.out_of_space++;
 241                 return ERR_PTR(-ENOSPC);
 242         }
 243
 244         cmd_id = admin_queue->curr_cmd_id;
 245
 246         cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
 247                 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 248
 249         cmd->aq_common_descriptor.command_id |= cmd_id &
 250                 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 251
 252         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
 253         if (unlikely(!comp_ctx))
 254                 return ERR_PTR(-EINVAL);
 255
 256         comp_ctx->status = ENA_CMD_SUBMITTED;
 257         comp_ctx->comp_size = (u32)comp_size_in_bytes;
 258         comp_ctx->user_cqe = comp;
 259         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 260
 261         reinit_completion(&comp_ctx->wait_event);
 262
 263         memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
 264
 265         admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
 266                 queue_size_mask;
 267
 268         admin_queue->sq.tail++;
 269         admin_queue->stats.submitted_cmd++;
 270
 271         if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
 272                 admin_queue->sq.phase = !admin_queue->sq.phase;
 273
 274         writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
 275
 276         return comp_ctx;
 277 }
 278
 279 static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
 280 {
 281         size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
 282         struct ena_comp_ctx *comp_ctx;
 283         u16 i;
 284
 285         queue->comp_ctx = devm_kzalloc(queue->q_dmadev, size, GFP_KERNEL);
 286         if (unlikely(!queue->comp_ctx)) {
 287                 pr_err("memory allocation failed");
 288                 return -ENOMEM;
 289         }
 290
 291         for (i = 0; i < queue->q_depth; i++) {
 292                 comp_ctx = get_comp_ctxt(queue, i, false);
 293                 if (comp_ctx)
 294                         init_completion(&comp_ctx->wait_event);
 295         }
 296
 297         return 0;
 298 }
 299
 300 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 301                                                      struct ena_admin_aq_entry *cmd,
 302                                                      size_t cmd_size_in_bytes,
 303                                                      struct ena_admin_acq_entry *comp,
 304                                                      size_t comp_size_in_bytes)
 305 {
 306         unsigned long flags;
 307         struct ena_comp_ctx *comp_ctx;
 308
 309         spin_lock_irqsave(&admin_queue->q_lock, flags);
 310         if (unlikely(!admin_queue->running_state)) {
 311                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 312                 return ERR_PTR(-ENODEV);
 313         }
 314         comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
 315                                               cmd_size_in_bytes,
 316                                               comp,
 317                                               comp_size_in_bytes);
 318         if (unlikely(IS_ERR(comp_ctx)))
 319                 admin_queue->running_state = false;
 320         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 321
 322         return comp_ctx;
 323 }
 324
 325 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
 326                               struct ena_com_create_io_ctx *ctx,
 327                               struct ena_com_io_sq *io_sq)
 328 {
 329         size_t size;
 330         int dev_node = 0;
 331
 332         memset(&io_sq->desc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));
 333
 334         io_sq->dma_addr_bits = ena_dev->dma_addr_bits;
 335         io_sq->desc_entry_size =
 336                 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 337                 sizeof(struct ena_eth_io_tx_desc) :
 338                 sizeof(struct ena_eth_io_rx_desc);
 339
 340         size = io_sq->desc_entry_size * io_sq->q_depth;
 341
 342         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 343                 dev_node = dev_to_node(ena_dev->dmadev);
 344                 set_dev_node(ena_dev->dmadev, ctx->numa_node);
 345                 io_sq->desc_addr.virt_addr =
 346                         dma_zalloc_coherent(ena_dev->dmadev, size,
 347                                             &io_sq->desc_addr.phys_addr,
 348                                             GFP_KERNEL);
 349                 set_dev_node(ena_dev->dmadev, dev_node);
 350                 if (!io_sq->desc_addr.virt_addr) {
 351                         io_sq->desc_addr.virt_addr =
 352                                 dma_zalloc_coherent(ena_dev->dmadev, size,
 353                                                     &io_sq->desc_addr.phys_addr,
 354                                                     GFP_KERNEL);
 355                 }
 356         } else {
 357                 dev_node = dev_to_node(ena_dev->dmadev);
 358                 set_dev_node(ena_dev->dmadev, ctx->numa_node);
 359                 io_sq->desc_addr.virt_addr =
 360                         devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
 361                 set_dev_node(ena_dev->dmadev, dev_node);
 362                 if (!io_sq->desc_addr.virt_addr) {
 363                         io_sq->desc_addr.virt_addr =
 364                                 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
 365                 }
 366         }
 367
 368         if (!io_sq->desc_addr.virt_addr) {
 369                 pr_err("memory allocation failed");
 370                 return -ENOMEM;
 371         }
 372
 373         io_sq->tail = 0;
 374         io_sq->next_to_comp = 0;
 375         io_sq->phase = 1;
 376
 377         return 0;
 378 }
 379
 380 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 381                               struct ena_com_create_io_ctx *ctx,
 382                               struct ena_com_io_cq *io_cq)
 383 {
 384         size_t size;
 385         int prev_node = 0;
 386
 387         memset(&io_cq->cdesc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));
 388
 389         /* Use the basic completion descriptor for Rx */
 390         io_cq->cdesc_entry_size_in_bytes =
 391                 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 392                 sizeof(struct ena_eth_io_tx_cdesc) :
 393                 sizeof(struct ena_eth_io_rx_cdesc_base);
 394
 395         size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 396
 397         prev_node = dev_to_node(ena_dev->dmadev);
 398         set_dev_node(ena_dev->dmadev, ctx->numa_node);
 399         io_cq->cdesc_addr.virt_addr =
 400                 dma_zalloc_coherent(ena_dev->dmadev, size,
 401                                     &io_cq->cdesc_addr.phys_addr, GFP_KERNEL);
 402         set_dev_node(ena_dev->dmadev, prev_node);
 403         if (!io_cq->cdesc_addr.virt_addr) {
 404                 io_cq->cdesc_addr.virt_addr =
 405                         dma_zalloc_coherent(ena_dev->dmadev, size,
 406                                             &io_cq->cdesc_addr.phys_addr,
 407                                             GFP_KERNEL);
 408         }
 409
 410         if (!io_cq->cdesc_addr.virt_addr) {
 411                 pr_err("memory allocation failed");
 412                 return -ENOMEM;
 413         }
 414
 415         io_cq->phase = 1;
 416         io_cq->head = 0;
 417
 418         return 0;
 419 }
 420
 421 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
 422                                                    struct ena_admin_acq_entry *cqe)
 423 {
 424         struct ena_comp_ctx *comp_ctx;
 425         u16 cmd_id;
 426
 427         cmd_id = cqe->acq_common_descriptor.command &
 428                 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 429
 430         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
 431         if (unlikely(!comp_ctx)) {
 432                 pr_err("comp_ctx is NULL. Changing the admin queue running state\n");
 433                 admin_queue->running_state = false;
 434                 return;
 435         }
 436
 437         comp_ctx->status = ENA_CMD_COMPLETED;
 438         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 439
 440         if (comp_ctx->user_cqe)
 441                 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
 442
 443         if (!admin_queue->polling)
 444                 complete(&comp_ctx->wait_event);
 445 }
 446
 447 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
 448 {
 449         struct ena_admin_acq_entry *cqe = NULL;
 450         u16 comp_num = 0;
 451         u16 head_masked;
 452         u8 phase;
 453
 454         head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
 455         phase = admin_queue->cq.phase;
 456
 457         cqe = &admin_queue->cq.entries[head_masked];
 458
 459         /* Go over all the completions */
 460         while ((cqe->acq_common_descriptor.flags &
 461                         ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 462                 /* Do not read the rest of the completion entry before the
 463                  * phase bit was validated
 464                  */
 465                 rmb();
 466                 ena_com_handle_single_admin_completion(admin_queue, cqe);
 467
 468                 head_masked++;
 469                 comp_num++;
 470                 if (unlikely(head_masked == admin_queue->q_depth)) {
 471                         head_masked = 0;
 472                         phase = !phase;
 473                 }
 474
 475                 cqe = &admin_queue->cq.entries[head_masked];
 476         }
 477
 478         admin_queue->cq.head += comp_num;
 479         admin_queue->cq.phase = phase;
 480         admin_queue->sq.head += comp_num;
 481         admin_queue->stats.completed_cmd += comp_num;
 482 }
 483
 484 static int ena_com_comp_status_to_errno(u8 comp_status)
 485 {
 486         if (unlikely(comp_status != 0))
 487                 pr_err("admin command failed[%u]\n", comp_status);
 488
 489         if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR))
 490                 return -EINVAL;
 491
 492         switch (comp_status) {
 493         case ENA_ADMIN_SUCCESS:
 494                 return 0;
 495         case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 496                 return -ENOMEM;
 497         case ENA_ADMIN_UNSUPPORTED_OPCODE:
 498                 return -EPERM;
 499         case ENA_ADMIN_BAD_OPCODE:
 500         case ENA_ADMIN_MALFORMED_REQUEST:
 501         case ENA_ADMIN_ILLEGAL_PARAMETER:
 502         case ENA_ADMIN_UNKNOWN_ERROR:
 503                 return -EINVAL;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 510                                                      struct ena_com_admin_queue *admin_queue)
 511 {
 512         unsigned long flags, timeout;
 513         int ret;
 514
 515         timeout = jiffies + ADMIN_CMD_TIMEOUT_US;
 516
 517         while (1) {
 518                 spin_lock_irqsave(&admin_queue->q_lock, flags);
 519                 ena_com_handle_admin_completion(admin_queue);
 520                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 521
 522                 if (comp_ctx->status != ENA_CMD_SUBMITTED)
 523                         break;
 524
 525                 if (time_is_before_jiffies(timeout)) {
 526                         pr_err("Wait for completion (polling) timeout\n");
 527                         /* ENA didn't have any completion */
 528                         spin_lock_irqsave(&admin_queue->q_lock, flags);
 529                         admin_queue->stats.no_completion++;
 530                         admin_queue->running_state = false;
 531                         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 532
 533                         ret = -ETIME;
 534                         goto err;
 535                 }
 536
 537                 msleep(100);
 538         }
 539
 540         if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 541                 pr_err("Command was aborted\n");
 542                 spin_lock_irqsave(&admin_queue->q_lock, flags);
 543                 admin_queue->stats.aborted_cmd++;
 544                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 545                 ret = -ENODEV;
 546                 goto err;
 547         }
 548
 549         WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n",
 550              comp_ctx->status);
 551
 552         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 553 err:
 554         comp_ctxt_release(admin_queue, comp_ctx);
 555         return ret;
 556 }
 557
 558 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
 559                                                         struct ena_com_admin_queue *admin_queue)
 560 {
 561         unsigned long flags;
 562         int ret;
 563
 564         wait_for_completion_timeout(&comp_ctx->wait_event,
 565                                     usecs_to_jiffies(ADMIN_CMD_TIMEOUT_US));
 566
 567         /* In case the command wasn't completed find out the root cause.
 568          * There might be 2 kinds of errors
 569          * 1) No completion (timeout reached)
 570          * 2) There is completion but the device didn't get any msi-x interrupt.
 571          */
 572         if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
 573                 spin_lock_irqsave(&admin_queue->q_lock, flags);
 574                 ena_com_handle_admin_completion(admin_queue);
 575                 admin_queue->stats.no_completion++;
 576                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 577
 578                 if (comp_ctx->status == ENA_CMD_COMPLETED)
 579                         pr_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n",
 580                                comp_ctx->cmd_opcode);
 581                 else
 582                         pr_err("The ena device doesn't send any completion for the admin cmd %d status %d\n",
 583                                comp_ctx->cmd_opcode, comp_ctx->status);
 584
 585                 admin_queue->running_state = false;
 586                 ret = -ETIME;
 587                 goto err;
 588         }
 589
 590         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 591 err:
 592         comp_ctxt_release(admin_queue, comp_ctx);
 593         return ret;
 594 }
 595
 596 /* This method read the hardware device register through posting writes
 597  * and waiting for response
 598  * On timeout the function will return ENA_MMIO_READ_TIMEOUT
 599  */
 600 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
 601 {
 602         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
 603         volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
 604                 mmio_read->read_resp;
 605         u32 mmio_read_reg, ret;
 606         unsigned long flags;
 607         int i;
 608
 609         might_sleep();
 610
 611         /* If readless is disabled, perform regular read */
 612         if (!mmio_read->readless_supported)
 613                 return readl(ena_dev->reg_bar + offset);
 614
 615         spin_lock_irqsave(&mmio_read->lock, flags);
 616         mmio_read->seq_num++;
 617
 618         read_resp->req_id = mmio_read->seq_num + 0xDEAD;
 619         mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
 620                         ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
 621         mmio_read_reg |= mmio_read->seq_num &
 622                         ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 623
 624         /* make sure read_resp->req_id get updated before the hw can write
 625          * there
 626          */
 627         wmb();
 628
 629         writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 630
 631         for (i = 0; i < ENA_REG_READ_TIMEOUT; i++) {
 632                 if (read_resp->req_id == mmio_read->seq_num)
 633                         break;
 634
 635                 udelay(1);
 636         }
 637
 638         if (unlikely(i == ENA_REG_READ_TIMEOUT)) {
 639                 pr_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
 640                        mmio_read->seq_num, offset, read_resp->req_id,
 641                        read_resp->reg_off);
 642                 ret = ENA_MMIO_READ_TIMEOUT;
 643                 goto err;
 644         }
 645
 646         if (read_resp->reg_off != offset) {
 647                 pr_err("Read failure: wrong offset provided");
 648                 ret = ENA_MMIO_READ_TIMEOUT;
 649         } else {
 650                 ret = read_resp->reg_val;
 651         }
 652 err:
 653         spin_unlock_irqrestore(&mmio_read->lock, flags);
 654
 655         return ret;
 656 }
 657
 658 /* There are two types to wait for completion.
 659  * Polling mode - wait until the completion is available.
 660  * Async mode - wait on wait queue until the completion is ready
 661  * (or the timeout expired).
 662  * It is expected that the IRQ called ena_com_handle_admin_completion
 663  * to mark the completions.
 664  */
 665 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
 666                                              struct ena_com_admin_queue *admin_queue)
 667 {
 668         if (admin_queue->polling)
 669                 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
 670                                                                  admin_queue);
 671
 672         return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
 673                                                             admin_queue);
 674 }
 675
 676 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
 677                                  struct ena_com_io_sq *io_sq)
 678 {
 679         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 680         struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
 681         struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
 682         u8 direction;
 683         int ret;
 684
 685         memset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd));
 686
 687         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 688                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 689         else
 690                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 691
 692         destroy_cmd.sq.sq_identity |= (direction <<
 693                 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
 694                 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
 695
 696         destroy_cmd.sq.sq_idx = io_sq->idx;
 697         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
 698
 699         ret = ena_com_execute_admin_command(admin_queue,
 700                                             (struct ena_admin_aq_entry *)&destroy_cmd,
 701                                             sizeof(destroy_cmd),
 702                                             (struct ena_admin_acq_entry *)&destroy_resp,
 703                                             sizeof(destroy_resp));
 704
 705         if (unlikely(ret && (ret != -ENODEV)))
 706                 pr_err("failed to destroy io sq error: %d\n", ret);
 707
 708         return ret;
 709 }
 710
 711 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
 712                                   struct ena_com_io_sq *io_sq,
 713                                   struct ena_com_io_cq *io_cq)
 714 {
 715         size_t size;
 716
 717         if (io_cq->cdesc_addr.virt_addr) {
 718                 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 719
 720                 dma_free_coherent(ena_dev->dmadev, size,
 721                                   io_cq->cdesc_addr.virt_addr,
 722                                   io_cq->cdesc_addr.phys_addr);
 723
 724                 io_cq->cdesc_addr.virt_addr = NULL;
 725         }
 726
 727         if (io_sq->desc_addr.virt_addr) {
 728                 size = io_sq->desc_entry_size * io_sq->q_depth;
 729
 730                 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
 731                         dma_free_coherent(ena_dev->dmadev, size,
 732                                           io_sq->desc_addr.virt_addr,
 733                                           io_sq->desc_addr.phys_addr);
 734                 else
 735                         devm_kfree(ena_dev->dmadev, io_sq->desc_addr.virt_addr);
 736
 737                 io_sq->desc_addr.virt_addr = NULL;
 738         }
 739 }
 740
 741 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
 742                                 u16 exp_state)
 743 {
 744         u32 val, i;
 745
 746         for (i = 0; i < timeout; i++) {
 747                 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 748
 749                 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
 750                         pr_err("Reg read timeout occurred\n");
 751                         return -ETIME;
 752                 }
 753
 754                 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
 755                         exp_state)
 756                         return 0;
 757
 758                 /* The resolution of the timeout is 100ms */
 759                 msleep(100);
 760         }
 761
 762         return -ETIME;
 763 }
 764
 765 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
 766                                                enum ena_admin_aq_feature_id feature_id)
 767 {
 768         u32 feature_mask = 1 << feature_id;
 769
 770         /* Device attributes is always supported */
 771         if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
 772             !(ena_dev->supported_features & feature_mask))
 773                 return false;
 774
 775         return true;
 776 }
 777
 778 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
 779                                   struct ena_admin_get_feat_resp *get_resp,
 780                                   enum ena_admin_aq_feature_id feature_id,
 781                                   dma_addr_t control_buf_dma_addr,
 782                                   u32 control_buff_size)
 783 {
 784         struct ena_com_admin_queue *admin_queue;
 785         struct ena_admin_get_feat_cmd get_cmd;
 786         int ret;
 787
 788         if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
 789                 pr_info("Feature %d isn't supported\n", feature_id);
 790                 return -EPERM;
 791         }
 792
 793         memset(&get_cmd, 0x0, sizeof(get_cmd));
 794         admin_queue = &ena_dev->admin_queue;
 795
 796         get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
 797
 798         if (control_buff_size)
 799                 get_cmd.aq_common_descriptor.flags =
 800                         ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
 801         else
 802                 get_cmd.aq_common_descriptor.flags = 0;
 803
 804         ret = ena_com_mem_addr_set(ena_dev,
 805                                    &get_cmd.control_buffer.address,
 806                                    control_buf_dma_addr);
 807         if (unlikely(ret)) {
 808                 pr_err("memory address set failed\n");
 809                 return ret;
 810         }
 811
 812         get_cmd.control_buffer.length = control_buff_size;
 813
 814         get_cmd.feat_common.feature_id = feature_id;
 815
 816         ret = ena_com_execute_admin_command(admin_queue,
 817                                             (struct ena_admin_aq_entry *)
 818                                             &get_cmd,
 819                                             sizeof(get_cmd),
 820                                             (struct ena_admin_acq_entry *)
 821                                             get_resp,
 822                                             sizeof(*get_resp));
 823
 824         if (unlikely(ret))
 825                 pr_err("Failed to submit get_feature command %d error: %d\n",
 826                        feature_id, ret);
 827
 828         return ret;
 829 }
 830
 831 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
 832                                struct ena_admin_get_feat_resp *get_resp,
 833                                enum ena_admin_aq_feature_id feature_id)
 834 {
 835         return ena_com_get_feature_ex(ena_dev,
 836                                       get_resp,
 837                                       feature_id,
 838                                       0,
 839                                       0);
 840 }
 841
 842 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
 843 {
 844         struct ena_rss *rss = &ena_dev->rss;
 845
 846         rss->hash_key =
 847                 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
 848                                     &rss->hash_key_dma_addr, GFP_KERNEL);
 849
 850         if (unlikely(!rss->hash_key))
 851                 return -ENOMEM;
 852
 853         return 0;
 854 }
 855
 856 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
 857 {
 858         struct ena_rss *rss = &ena_dev->rss;
 859
 860         if (rss->hash_key)
 861                 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
 862                                   rss->hash_key, rss->hash_key_dma_addr);
 863         rss->hash_key = NULL;
 864 }
 865
 866 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
 867 {
 868         struct ena_rss *rss = &ena_dev->rss;
 869
 870         rss->hash_ctrl =
 871                 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
 872                                     &rss->hash_ctrl_dma_addr, GFP_KERNEL);
 873
 874         if (unlikely(!rss->hash_ctrl))
 875                 return -ENOMEM;
 876
 877         return 0;
 878 }
 879
 880 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
 881 {
 882         struct ena_rss *rss = &ena_dev->rss;
 883
 884         if (rss->hash_ctrl)
 885                 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
 886                                   rss->hash_ctrl, rss->hash_ctrl_dma_addr);
 887         rss->hash_ctrl = NULL;
 888 }
 889
 890 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
 891                                            u16 log_size)
 892 {
 893         struct ena_rss *rss = &ena_dev->rss;
 894         struct ena_admin_get_feat_resp get_resp;
 895         size_t tbl_size;
 896         int ret;
 897
 898         ret = ena_com_get_feature(ena_dev, &get_resp,
 899                                   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
 900         if (unlikely(ret))
 901                 return ret;
 902
 903         if ((get_resp.u.ind_table.min_size > log_size) ||
 904             (get_resp.u.ind_table.max_size < log_size)) {
 905                 pr_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
 906                        1 << log_size, 1 << get_resp.u.ind_table.min_size,
 907                        1 << get_resp.u.ind_table.max_size);
 908                 return -EINVAL;
 909         }
 910
 911         tbl_size = (1ULL << log_size) *
 912                 sizeof(struct ena_admin_rss_ind_table_entry);
 913
 914         rss->rss_ind_tbl =
 915                 dma_zalloc_coherent(ena_dev->dmadev, tbl_size,
 916                                     &rss->rss_ind_tbl_dma_addr, GFP_KERNEL);
 917         if (unlikely(!rss->rss_ind_tbl))
 918                 goto mem_err1;
 919
 920         tbl_size = (1ULL << log_size) * sizeof(u16);
 921         rss->host_rss_ind_tbl =
 922                 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL);
 923         if (unlikely(!rss->host_rss_ind_tbl))
 924                 goto mem_err2;
 925
 926         rss->tbl_log_size = log_size;
 927
 928         return 0;
 929
 930 mem_err2:
 931         tbl_size = (1ULL << log_size) *
 932                 sizeof(struct ena_admin_rss_ind_table_entry);
 933
 934         dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
 935                           rss->rss_ind_tbl_dma_addr);
 936         rss->rss_ind_tbl = NULL;
 937 mem_err1:
 938         rss->tbl_log_size = 0;
 939         return -ENOMEM;
 940 }
 941
 942 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
 943 {
 944         struct ena_rss *rss = &ena_dev->rss;
 945         size_t tbl_size = (1ULL << rss->tbl_log_size) *
 946                 sizeof(struct ena_admin_rss_ind_table_entry);
 947
 948         if (rss->rss_ind_tbl)
 949                 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
 950                                   rss->rss_ind_tbl_dma_addr);
 951         rss->rss_ind_tbl = NULL;
 952
 953         if (rss->host_rss_ind_tbl)
 954                 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl);
 955         rss->host_rss_ind_tbl = NULL;
 956 }
 957
 958 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
 959                                 struct ena_com_io_sq *io_sq, u16 cq_idx)
 960 {
 961         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 962         struct ena_admin_aq_create_sq_cmd create_cmd;
 963         struct ena_admin_acq_create_sq_resp_desc cmd_completion;
 964         u8 direction;
 965         int ret;
 966
 967         memset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_sq_cmd));
 968
 969         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
 970
 971         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 972                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 973         else
 974                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 975
 976         create_cmd.sq_identity |= (direction <<
 977                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
 978                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
 979
 980         create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
 981                 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
 982
 983         create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
 984                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
 985                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
 986
 987         create_cmd.sq_caps_3 |=
 988                 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
 989
 990         create_cmd.cq_idx = cq_idx;
 991         create_cmd.sq_depth = io_sq->q_depth;
 992
 993         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 994                 ret = ena_com_mem_addr_set(ena_dev,
 995                                            &create_cmd.sq_ba,
 996                                            io_sq->desc_addr.phys_addr);
 997                 if (unlikely(ret)) {
 998                         pr_err("memory address set failed\n");
 999                         return ret;
1000                 }
1001         }
1002
1003         ret = ena_com_execute_admin_command(admin_queue,
1004                                             (struct ena_admin_aq_entry *)&create_cmd,
1005                                             sizeof(create_cmd),
1006                                             (struct ena_admin_acq_entry *)&cmd_completion,
1007                                             sizeof(cmd_completion));
1008         if (unlikely(ret)) {
1009                 pr_err("Failed to create IO SQ. error: %d\n", ret);
1010                 return ret;
1011         }
1012
1013         io_sq->idx = cmd_completion.sq_idx;
1014
1015         io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1016                 (uintptr_t)cmd_completion.sq_doorbell_offset);
1017
1018         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1019                 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1020                                 + cmd_completion.llq_headers_offset);
1021
1022                 io_sq->desc_addr.pbuf_dev_addr =
1023                         (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1024                         cmd_completion.llq_descriptors_offset);
1025         }
1026
1027         pr_debug("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1028
1029         return ret;
1030 }
1031
1032 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1033 {
1034         struct ena_rss *rss = &ena_dev->rss;
1035         struct ena_com_io_sq *io_sq;
1036         u16 qid;
1037         int i;
1038
1039         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1040                 qid = rss->host_rss_ind_tbl[i];
1041                 if (qid >= ENA_TOTAL_NUM_QUEUES)
1042                         return -EINVAL;
1043
1044                 io_sq = &ena_dev->io_sq_queues[qid];
1045
1046                 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1047                         return -EINVAL;
1048
1049                 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1050         }
1051
1052         return 0;
1053 }
1054
1055 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev)
1056 {
1057         u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 };
1058         struct ena_rss *rss = &ena_dev->rss;
1059         u8 idx;
1060         u16 i;
1061
1062         for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++)
1063                 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i;
1064
1065         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1066                 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES)
1067                         return -EINVAL;
1068                 idx = (u8)rss->rss_ind_tbl[i].cq_idx;
1069
1070                 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES)
1071                         return -EINVAL;
1072
1073                 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx];
1074         }
1075
1076         return 0;
1077 }
1078
1079 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)
1080 {
1081         size_t size;
1082
1083         size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS;
1084
1085         ena_dev->intr_moder_tbl =
1086                 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
1087         if (!ena_dev->intr_moder_tbl)
1088                 return -ENOMEM;
1089
1090         ena_com_config_default_interrupt_moderation_table(ena_dev);
1091
1092         return 0;
1093 }
1094
1095 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1096                                                  u16 intr_delay_resolution)
1097 {
1098         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
1099         unsigned int i;
1100
1101         if (!intr_delay_resolution) {
1102                 pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1103                 intr_delay_resolution = 1;
1104         }
1105         ena_dev->intr_delay_resolution = intr_delay_resolution;
1106
1107         /* update Rx */
1108         for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++)
1109                 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution;
1110
1111         /* update Tx */
1112         ena_dev->intr_moder_tx_interval /= intr_delay_resolution;
1113 }
1114
1115 /*****************************************************************************/
1116 /*******************************      API       ******************************/
1117 /*****************************************************************************/
1118
1119 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1120                                   struct ena_admin_aq_entry *cmd,
1121                                   size_t cmd_size,
1122                                   struct ena_admin_acq_entry *comp,
1123                                   size_t comp_size)
1124 {
1125         struct ena_comp_ctx *comp_ctx;
1126         int ret;
1127
1128         comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1129                                             comp, comp_size);
1130         if (unlikely(IS_ERR(comp_ctx))) {
1131                 pr_err("Failed to submit command [%ld]\n", PTR_ERR(comp_ctx));
1132                 return PTR_ERR(comp_ctx);
1133         }
1134
1135         ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1136         if (unlikely(ret)) {
1137                 if (admin_queue->running_state)
1138                         pr_err("Failed to process command. ret = %d\n", ret);
1139                 else
1140                         pr_debug("Failed to process command. ret = %d\n", ret);
1141         }
1142         return ret;
1143 }
1144
1145 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1146                          struct ena_com_io_cq *io_cq)
1147 {
1148         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1149         struct ena_admin_aq_create_cq_cmd create_cmd;
1150         struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1151         int ret;
1152
1153         memset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_cq_cmd));
1154
1155         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1156
1157         create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1158                 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1159         create_cmd.cq_caps_1 |=
1160                 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1161
1162         create_cmd.msix_vector = io_cq->msix_vector;
1163         create_cmd.cq_depth = io_cq->q_depth;
1164
1165         ret = ena_com_mem_addr_set(ena_dev,
1166                                    &create_cmd.cq_ba,
1167                                    io_cq->cdesc_addr.phys_addr);
1168         if (unlikely(ret)) {
1169                 pr_err("memory address set failed\n");
1170                 return ret;
1171         }
1172
1173         ret = ena_com_execute_admin_command(admin_queue,
1174                                             (struct ena_admin_aq_entry *)&create_cmd,
1175                                             sizeof(create_cmd),
1176                                             (struct ena_admin_acq_entry *)&cmd_completion,
1177                                             sizeof(cmd_completion));
1178         if (unlikely(ret)) {
1179                 pr_err("Failed to create IO CQ. error: %d\n", ret);
1180                 return ret;
1181         }
1182
1183         io_cq->idx = cmd_completion.cq_idx;
1184
1185         io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1186                 cmd_completion.cq_interrupt_unmask_register_offset);
1187
1188         if (cmd_completion.cq_head_db_register_offset)
1189                 io_cq->cq_head_db_reg =
1190                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1191                         cmd_completion.cq_head_db_register_offset);
1192
1193         if (cmd_completion.numa_node_register_offset)
1194                 io_cq->numa_node_cfg_reg =
1195                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1196                         cmd_completion.numa_node_register_offset);
1197
1198         pr_debug("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1199
1200         return ret;
1201 }
1202
1203 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1204                             struct ena_com_io_sq **io_sq,
1205                             struct ena_com_io_cq **io_cq)
1206 {
1207         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1208                 pr_err("Invalid queue number %d but the max is %d\n", qid,
1209                        ENA_TOTAL_NUM_QUEUES);
1210                 return -EINVAL;
1211         }
1212
1213         *io_sq = &ena_dev->io_sq_queues[qid];
1214         *io_cq = &ena_dev->io_cq_queues[qid];
1215
1216         return 0;
1217 }
1218
1219 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1220 {
1221         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1222         struct ena_comp_ctx *comp_ctx;
1223         u16 i;
1224
1225         if (!admin_queue->comp_ctx)
1226                 return;
1227
1228         for (i = 0; i < admin_queue->q_depth; i++) {
1229                 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1230                 if (unlikely(!comp_ctx))
1231                         break;
1232
1233                 comp_ctx->status = ENA_CMD_ABORTED;
1234
1235                 complete(&comp_ctx->wait_event);
1236         }
1237 }
1238
1239 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1240 {
1241         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1242         unsigned long flags;
1243
1244         spin_lock_irqsave(&admin_queue->q_lock, flags);
1245         while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
1246                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1247                 msleep(20);
1248                 spin_lock_irqsave(&admin_queue->q_lock, flags);
1249         }
1250         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1251 }
1252
1253 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1254                           struct ena_com_io_cq *io_cq)
1255 {
1256         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1257         struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1258         struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1259         int ret;
1260
1261         memset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd));
1262
1263         destroy_cmd.cq_idx = io_cq->idx;
1264         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1265
1266         ret = ena_com_execute_admin_command(admin_queue,
1267                                             (struct ena_admin_aq_entry *)&destroy_cmd,
1268                                             sizeof(destroy_cmd),
1269                                             (struct ena_admin_acq_entry *)&destroy_resp,
1270                                             sizeof(destroy_resp));
1271
1272         if (unlikely(ret && (ret != -ENODEV)))
1273                 pr_err("Failed to destroy IO CQ. error: %d\n", ret);
1274
1275         return ret;
1276 }
1277
1278 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1279 {
1280         return ena_dev->admin_queue.running_state;
1281 }
1282
1283 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1284 {
1285         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1286         unsigned long flags;
1287
1288         spin_lock_irqsave(&admin_queue->q_lock, flags);
1289         ena_dev->admin_queue.running_state = state;
1290         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1291 }
1292
1293 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1294 {
1295         u16 depth = ena_dev->aenq.q_depth;
1296
1297         WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1298
1299         /* Init head_db to mark that all entries in the queue
1300          * are initially available
1301          */
1302         writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1303 }
1304
1305 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1306 {
1307         struct ena_com_admin_queue *admin_queue;
1308         struct ena_admin_set_feat_cmd cmd;
1309         struct ena_admin_set_feat_resp resp;
1310         struct ena_admin_get_feat_resp get_resp;
1311         int ret;
1312
1313         ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG);
1314         if (ret) {
1315                 pr_info("Can't get aenq configuration\n");
1316                 return ret;
1317         }
1318
1319         if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1320                 pr_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n",
1321                         get_resp.u.aenq.supported_groups, groups_flag);
1322                 return -EPERM;
1323         }
1324
1325         memset(&cmd, 0x0, sizeof(cmd));
1326         admin_queue = &ena_dev->admin_queue;
1327
1328         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1329         cmd.aq_common_descriptor.flags = 0;
1330         cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1331         cmd.u.aenq.enabled_groups = groups_flag;
1332
1333         ret = ena_com_execute_admin_command(admin_queue,
1334                                             (struct ena_admin_aq_entry *)&cmd,
1335                                             sizeof(cmd),
1336                                             (struct ena_admin_acq_entry *)&resp,
1337                                             sizeof(resp));
1338
1339         if (unlikely(ret))
1340                 pr_err("Failed to config AENQ ret: %d\n", ret);
1341
1342         return ret;
1343 }
1344
1345 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1346 {
1347         u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1348         int width;
1349
1350         if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1351                 pr_err("Reg read timeout occurred\n");
1352                 return -ETIME;
1353         }
1354
1355         width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1356                 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1357
1358         pr_debug("ENA dma width: %d\n", width);
1359
1360         if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1361                 pr_err("DMA width illegal value: %d\n", width);
1362                 return -EINVAL;
1363         }
1364
1365         ena_dev->dma_addr_bits = width;
1366
1367         return width;
1368 }
1369
1370 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1371 {
1372         u32 ver;
1373         u32 ctrl_ver;
1374         u32 ctrl_ver_masked;
1375
1376         /* Make sure the ENA version and the controller version are at least
1377          * as the driver expects
1378          */
1379         ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1380         ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1381                                           ENA_REGS_CONTROLLER_VERSION_OFF);
1382
1383         if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1384                      (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1385                 pr_err("Reg read timeout occurred\n");
1386                 return -ETIME;
1387         }
1388
1389         pr_info("ena device version: %d.%d\n",
1390                 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1391                         ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1392                 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1393
1394         if (ver < MIN_ENA_VER) {
1395                 pr_err("ENA version is lower than the minimal version the driver supports\n");
1396                 return -1;
1397         }
1398
1399         pr_info("ena controller version: %d.%d.%d implementation version %d\n",
1400                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1401                         ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1402                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1403                         ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1404                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1405                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1406                         ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1407
1408         ctrl_ver_masked =
1409                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1410                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1411                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1412
1413         /* Validate the ctrl version without the implementation ID */
1414         if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1415                 pr_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1416                 return -1;
1417         }
1418
1419         return 0;
1420 }
1421
1422 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1423 {
1424         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1425         struct ena_com_admin_cq *cq = &admin_queue->cq;
1426         struct ena_com_admin_sq *sq = &admin_queue->sq;
1427         struct ena_com_aenq *aenq = &ena_dev->aenq;
1428         u16 size;
1429
1430         if (admin_queue->comp_ctx)
1431                 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx);
1432         admin_queue->comp_ctx = NULL;
1433         size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1434         if (sq->entries)
1435                 dma_free_coherent(ena_dev->dmadev, size, sq->entries,
1436                                   sq->dma_addr);
1437         sq->entries = NULL;
1438
1439         size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1440         if (cq->entries)
1441                 dma_free_coherent(ena_dev->dmadev, size, cq->entries,
1442                                   cq->dma_addr);
1443         cq->entries = NULL;
1444
1445         size = ADMIN_AENQ_SIZE(aenq->q_depth);
1446         if (ena_dev->aenq.entries)
1447                 dma_free_coherent(ena_dev->dmadev, size, aenq->entries,
1448                                   aenq->dma_addr);
1449         aenq->entries = NULL;
1450 }
1451
1452 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1453 {
1454         u32 mask_value = 0;
1455
1456         if (polling)
1457                 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1458
1459         writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1460         ena_dev->admin_queue.polling = polling;
1461 }
1462
1463 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1464 {
1465         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1466
1467         spin_lock_init(&mmio_read->lock);
1468         mmio_read->read_resp =
1469                 dma_zalloc_coherent(ena_dev->dmadev,
1470                                     sizeof(*mmio_read->read_resp),
1471                                     &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1472         if (unlikely(!mmio_read->read_resp))
1473                 return -ENOMEM;
1474
1475         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1476
1477         mmio_read->read_resp->req_id = 0x0;
1478         mmio_read->seq_num = 0x0;
1479         mmio_read->readless_supported = true;
1480
1481         return 0;
1482 }
1483
1484 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1485 {
1486         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1487
1488         mmio_read->readless_supported = readless_supported;
1489 }
1490
1491 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1492 {
1493         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1494
1495         writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1496         writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1497
1498         dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1499                           mmio_read->read_resp, mmio_read->read_resp_dma_addr);
1500
1501         mmio_read->read_resp = NULL;
1502 }
1503
1504 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1505 {
1506         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1507         u32 addr_low, addr_high;
1508
1509         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1510         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1511
1512         writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1513         writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1514 }
1515
1516 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1517                        struct ena_aenq_handlers *aenq_handlers,
1518                        bool init_spinlock)
1519 {
1520         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1521         u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1522         int ret;
1523
1524         dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1525
1526         if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1527                 pr_err("Reg read timeout occurred\n");
1528                 return -ETIME;
1529         }
1530
1531         if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1532                 pr_err("Device isn't ready, abort com init\n");
1533                 return -ENODEV;
1534         }
1535
1536         admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1537
1538         admin_queue->q_dmadev = ena_dev->dmadev;
1539         admin_queue->polling = false;
1540         admin_queue->curr_cmd_id = 0;
1541
1542         atomic_set(&admin_queue->outstanding_cmds, 0);
1543
1544         if (init_spinlock)
1545                 spin_lock_init(&admin_queue->q_lock);
1546
1547         ret = ena_com_init_comp_ctxt(admin_queue);
1548         if (ret)
1549                 goto error;
1550
1551         ret = ena_com_admin_init_sq(admin_queue);
1552         if (ret)
1553                 goto error;
1554
1555         ret = ena_com_admin_init_cq(admin_queue);
1556         if (ret)
1557                 goto error;
1558
1559         admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1560                 ENA_REGS_AQ_DB_OFF);
1561
1562         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1563         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1564
1565         writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1566         writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1567
1568         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1569         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1570
1571         writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1572         writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1573
1574         aq_caps = 0;
1575         aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1576         aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1577                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1578                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1579
1580         acq_caps = 0;
1581         acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1582         acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1583                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1584                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1585
1586         writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1587         writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1588         ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1589         if (ret)
1590                 goto error;
1591
1592         admin_queue->running_state = true;
1593
1594         return 0;
1595 error:
1596         ena_com_admin_destroy(ena_dev);
1597
1598         return ret;
1599 }
1600
1601 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1602                             struct ena_com_create_io_ctx *ctx)
1603 {
1604         struct ena_com_io_sq *io_sq;
1605         struct ena_com_io_cq *io_cq;
1606         int ret;
1607
1608         if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1609                 pr_err("Qid (%d) is bigger than max num of queues (%d)\n",
1610                        ctx->qid, ENA_TOTAL_NUM_QUEUES);
1611                 return -EINVAL;
1612         }
1613
1614         io_sq = &ena_dev->io_sq_queues[ctx->qid];
1615         io_cq = &ena_dev->io_cq_queues[ctx->qid];
1616
1617         memset(io_sq, 0x0, sizeof(struct ena_com_io_sq));
1618         memset(io_cq, 0x0, sizeof(struct ena_com_io_cq));
1619
1620         /* Init CQ */
1621         io_cq->q_depth = ctx->queue_size;
1622         io_cq->direction = ctx->direction;
1623         io_cq->qid = ctx->qid;
1624
1625         io_cq->msix_vector = ctx->msix_vector;
1626
1627         io_sq->q_depth = ctx->queue_size;
1628         io_sq->direction = ctx->direction;
1629         io_sq->qid = ctx->qid;
1630
1631         io_sq->mem_queue_type = ctx->mem_queue_type;
1632
1633         if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1634                 /* header length is limited to 8 bits */
1635                 io_sq->tx_max_header_size =
1636                         min_t(u32, ena_dev->tx_max_header_size, SZ_256);
1637
1638         ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1639         if (ret)
1640                 goto error;
1641         ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1642         if (ret)
1643                 goto error;
1644
1645         ret = ena_com_create_io_cq(ena_dev, io_cq);
1646         if (ret)
1647                 goto error;
1648
1649         ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1650         if (ret)
1651                 goto destroy_io_cq;
1652
1653         return 0;
1654
1655 destroy_io_cq:
1656         ena_com_destroy_io_cq(ena_dev, io_cq);
1657 error:
1658         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1659         return ret;
1660 }
1661
1662 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1663 {
1664         struct ena_com_io_sq *io_sq;
1665         struct ena_com_io_cq *io_cq;
1666
1667         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1668                 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", qid,
1669                        ENA_TOTAL_NUM_QUEUES);
1670                 return;
1671         }
1672
1673         io_sq = &ena_dev->io_sq_queues[qid];
1674         io_cq = &ena_dev->io_cq_queues[qid];
1675
1676         ena_com_destroy_io_sq(ena_dev, io_sq);
1677         ena_com_destroy_io_cq(ena_dev, io_cq);
1678
1679         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1680 }
1681
1682 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1683                             struct ena_admin_get_feat_resp *resp)
1684 {
1685         return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG);
1686 }
1687
1688 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1689                               struct ena_com_dev_get_features_ctx *get_feat_ctx)
1690 {
1691         struct ena_admin_get_feat_resp get_resp;
1692         int rc;
1693
1694         rc = ena_com_get_feature(ena_dev, &get_resp,
1695                                  ENA_ADMIN_DEVICE_ATTRIBUTES);
1696         if (rc)
1697                 return rc;
1698
1699         memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1700                sizeof(get_resp.u.dev_attr));
1701         ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1702
1703         rc = ena_com_get_feature(ena_dev, &get_resp,
1704                                  ENA_ADMIN_MAX_QUEUES_NUM);
1705         if (rc)
1706                 return rc;
1707
1708         memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1709                sizeof(get_resp.u.max_queue));
1710         ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size;
1711
1712         rc = ena_com_get_feature(ena_dev, &get_resp,
1713                                  ENA_ADMIN_AENQ_CONFIG);
1714         if (rc)
1715                 return rc;
1716
1717         memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1718                sizeof(get_resp.u.aenq));
1719
1720         rc = ena_com_get_feature(ena_dev, &get_resp,
1721                                  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1722         if (rc)
1723                 return rc;
1724
1725         memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1726                sizeof(get_resp.u.offload));
1727
1728         return 0;
1729 }
1730
1731 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
1732 {
1733         ena_com_handle_admin_completion(&ena_dev->admin_queue);
1734 }
1735
1736 /* ena_handle_specific_aenq_event:
1737  * return the handler that is relevant to the specific event group
1738  */
1739 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
1740                                                      u16 group)
1741 {
1742         struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
1743
1744         if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
1745                 return aenq_handlers->handlers[group];
1746
1747         return aenq_handlers->unimplemented_handler;
1748 }
1749
1750 /* ena_aenq_intr_handler:
1751  * handles the aenq incoming events.
1752  * pop events from the queue and apply the specific handler
1753  */
1754 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
1755 {
1756         struct ena_admin_aenq_entry *aenq_e;
1757         struct ena_admin_aenq_common_desc *aenq_common;
1758         struct ena_com_aenq *aenq  = &dev->aenq;
1759         ena_aenq_handler handler_cb;
1760         u16 masked_head, processed = 0;
1761         u8 phase;
1762
1763         masked_head = aenq->head & (aenq->q_depth - 1);
1764         phase = aenq->phase;
1765         aenq_e = &aenq->entries[masked_head]; /* Get first entry */
1766         aenq_common = &aenq_e->aenq_common_desc;
1767
1768         /* Go over all the events */
1769         while ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) ==
1770                phase) {
1771                 pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
1772                          aenq_common->group, aenq_common->syndrom,
1773                          (u64)aenq_common->timestamp_low +
1774                                  ((u64)aenq_common->timestamp_high << 32));
1775
1776                 /* Handle specific event*/
1777                 handler_cb = ena_com_get_specific_aenq_cb(dev,
1778                                                           aenq_common->group);
1779                 handler_cb(data, aenq_e); /* call the actual event handler*/
1780
1781                 /* Get next event entry */
1782                 masked_head++;
1783                 processed++;
1784
1785                 if (unlikely(masked_head == aenq->q_depth)) {
1786                         masked_head = 0;
1787                         phase = !phase;
1788                 }
1789                 aenq_e = &aenq->entries[masked_head];
1790                 aenq_common = &aenq_e->aenq_common_desc;
1791         }
1792
1793         aenq->head += processed;
1794         aenq->phase = phase;
1795
1796         /* Don't update aenq doorbell if there weren't any processed events */
1797         if (!processed)
1798                 return;
1799
1800         /* write the aenq doorbell after all AENQ descriptors were read */
1801         mb();
1802         writel((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1803 }
1804
1805 int ena_com_dev_reset(struct ena_com_dev *ena_dev)
1806 {
1807         u32 stat, timeout, cap, reset_val;
1808         int rc;
1809
1810         stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1811         cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1812
1813         if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
1814                      (cap == ENA_MMIO_READ_TIMEOUT))) {
1815                 pr_err("Reg read32 timeout occurred\n");
1816                 return -ETIME;
1817         }
1818
1819         if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
1820                 pr_err("Device isn't ready, can't reset device\n");
1821                 return -EINVAL;
1822         }
1823
1824         timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
1825                         ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
1826         if (timeout == 0) {
1827                 pr_err("Invalid timeout value\n");
1828                 return -EINVAL;
1829         }
1830
1831         /* start reset */
1832         reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
1833         writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
1834
1835         /* Write again the MMIO read request address */
1836         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1837
1838         rc = wait_for_reset_state(ena_dev, timeout,
1839                                   ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
1840         if (rc != 0) {
1841                 pr_err("Reset indication didn't turn on\n");
1842                 return rc;
1843         }
1844
1845         /* reset done */
1846         writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
1847         rc = wait_for_reset_state(ena_dev, timeout, 0);
1848         if (rc != 0) {
1849                 pr_err("Reset indication didn't turn off\n");
1850                 return rc;
1851         }
1852
1853         return 0;
1854 }
1855
1856 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
1857                              struct ena_com_stats_ctx *ctx,
1858                              enum ena_admin_get_stats_type type)
1859 {
1860         struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
1861         struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
1862         struct ena_com_admin_queue *admin_queue;
1863         int ret;
1864
1865         admin_queue = &ena_dev->admin_queue;
1866
1867         get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
1868         get_cmd->aq_common_descriptor.flags = 0;
1869         get_cmd->type = type;
1870
1871         ret =  ena_com_execute_admin_command(admin_queue,
1872                                              (struct ena_admin_aq_entry *)get_cmd,
1873                                              sizeof(*get_cmd),
1874                                              (struct ena_admin_acq_entry *)get_resp,
1875                                              sizeof(*get_resp));
1876
1877         if (unlikely(ret))
1878                 pr_err("Failed to get stats. error: %d\n", ret);
1879
1880         return ret;
1881 }
1882
1883 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
1884                                 struct ena_admin_basic_stats *stats)
1885 {
1886         struct ena_com_stats_ctx ctx;
1887         int ret;
1888
1889         memset(&ctx, 0x0, sizeof(ctx));
1890         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
1891         if (likely(ret == 0))
1892                 memcpy(stats, &ctx.get_resp.basic_stats,
1893                        sizeof(ctx.get_resp.basic_stats));
1894
1895         return ret;
1896 }
1897
1898 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
1899 {
1900         struct ena_com_admin_queue *admin_queue;
1901         struct ena_admin_set_feat_cmd cmd;
1902         struct ena_admin_set_feat_resp resp;
1903         int ret;
1904
1905         if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
1906                 pr_info("Feature %d isn't supported\n", ENA_ADMIN_MTU);
1907                 return -EPERM;
1908         }
1909
1910         memset(&cmd, 0x0, sizeof(cmd));
1911         admin_queue = &ena_dev->admin_queue;
1912
1913         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1914         cmd.aq_common_descriptor.flags = 0;
1915         cmd.feat_common.feature_id = ENA_ADMIN_MTU;
1916         cmd.u.mtu.mtu = mtu;
1917
1918         ret = ena_com_execute_admin_command(admin_queue,
1919                                             (struct ena_admin_aq_entry *)&cmd,
1920                                             sizeof(cmd),
1921                                             (struct ena_admin_acq_entry *)&resp,
1922                                             sizeof(resp));
1923
1924         if (unlikely(ret))
1925                 pr_err("Failed to set mtu %d. error: %d\n", mtu, ret);
1926
1927         return ret;
1928 }
1929
1930 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
1931                                  struct ena_admin_feature_offload_desc *offload)
1932 {
1933         int ret;
1934         struct ena_admin_get_feat_resp resp;
1935
1936         ret = ena_com_get_feature(ena_dev, &resp,
1937                                   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1938         if (unlikely(ret)) {
1939                 pr_err("Failed to get offload capabilities %d\n", ret);
1940                 return ret;
1941         }
1942
1943         memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
1944
1945         return 0;
1946 }
1947
1948 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
1949 {
1950         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1951         struct ena_rss *rss = &ena_dev->rss;
1952         struct ena_admin_set_feat_cmd cmd;
1953         struct ena_admin_set_feat_resp resp;
1954         struct ena_admin_get_feat_resp get_resp;
1955         int ret;
1956
1957         if (!ena_com_check_supported_feature_id(ena_dev,
1958                                                 ENA_ADMIN_RSS_HASH_FUNCTION)) {
1959                 pr_info("Feature %d isn't supported\n",
1960                         ENA_ADMIN_RSS_HASH_FUNCTION);
1961                 return -EPERM;
1962         }
1963
1964         /* Validate hash function is supported */
1965         ret = ena_com_get_feature(ena_dev, &get_resp,
1966                                   ENA_ADMIN_RSS_HASH_FUNCTION);
1967         if (unlikely(ret))
1968                 return ret;
1969
1970         if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) {
1971                 pr_err("Func hash %d isn't supported by device, abort\n",
1972                        rss->hash_func);
1973                 return -EPERM;
1974         }
1975
1976         memset(&cmd, 0x0, sizeof(cmd));
1977
1978         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1979         cmd.aq_common_descriptor.flags =
1980                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1981         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
1982         cmd.u.flow_hash_func.init_val = rss->hash_init_val;
1983         cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
1984
1985         ret = ena_com_mem_addr_set(ena_dev,
1986                                    &cmd.control_buffer.address,
1987                                    rss->hash_key_dma_addr);
1988         if (unlikely(ret)) {
1989                 pr_err("memory address set failed\n");
1990                 return ret;
1991         }
1992
1993         cmd.control_buffer.length = sizeof(*rss->hash_key);
1994
1995         ret = ena_com_execute_admin_command(admin_queue,
1996                                             (struct ena_admin_aq_entry *)&cmd,
1997                                             sizeof(cmd),
1998                                             (struct ena_admin_acq_entry *)&resp,
1999                                             sizeof(resp));
2000         if (unlikely(ret)) {
2001                 pr_err("Failed to set hash function %d. error: %d\n",
2002                        rss->hash_func, ret);
2003                 return -EINVAL;
2004         }
2005
2006         return 0;
2007 }
2008
2009 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2010                                enum ena_admin_hash_functions func,
2011                                const u8 *key, u16 key_len, u32 init_val)
2012 {
2013         struct ena_rss *rss = &ena_dev->rss;
2014         struct ena_admin_get_feat_resp get_resp;
2015         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2016                 rss->hash_key;
2017         int rc;
2018
2019         /* Make sure size is a mult of DWs */
2020         if (unlikely(key_len & 0x3))
2021                 return -EINVAL;
2022
2023         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2024                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2025                                     rss->hash_key_dma_addr,
2026                                     sizeof(*rss->hash_key));
2027         if (unlikely(rc))
2028                 return rc;
2029
2030         if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
2031                 pr_err("Flow hash function %d isn't supported\n", func);
2032                 return -EPERM;
2033         }
2034
2035         switch (func) {
2036         case ENA_ADMIN_TOEPLITZ:
2037                 if (key_len > sizeof(hash_key->key)) {
2038                         pr_err("key len (%hu) is bigger than the max supported (%zu)\n",
2039                                key_len, sizeof(hash_key->key));
2040                         return -EINVAL;
2041                 }
2042
2043                 memcpy(hash_key->key, key, key_len);
2044                 rss->hash_init_val = init_val;
2045                 hash_key->keys_num = key_len >> 2;
2046                 break;
2047         case ENA_ADMIN_CRC32:
2048                 rss->hash_init_val = init_val;
2049                 break;
2050         default:
2051                 pr_err("Invalid hash function (%d)\n", func);
2052                 return -EINVAL;
2053         }
2054
2055         rc = ena_com_set_hash_function(ena_dev);
2056
2057         /* Restore the old function */
2058         if (unlikely(rc))
2059                 ena_com_get_hash_function(ena_dev, NULL, NULL);
2060
2061         return rc;
2062 }
2063
2064 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2065                               enum ena_admin_hash_functions *func,
2066                               u8 *key)
2067 {
2068         struct ena_rss *rss = &ena_dev->rss;
2069         struct ena_admin_get_feat_resp get_resp;
2070         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2071                 rss->hash_key;
2072         int rc;
2073
2074         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2075                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2076                                     rss->hash_key_dma_addr,
2077                                     sizeof(*rss->hash_key));
2078         if (unlikely(rc))
2079                 return rc;
2080
2081         rss->hash_func = get_resp.u.flow_hash_func.selected_func;
2082         if (func)
2083                 *func = rss->hash_func;
2084
2085         if (key)
2086                 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2087
2088         return 0;
2089 }
2090
2091 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2092                           enum ena_admin_flow_hash_proto proto,
2093                           u16 *fields)
2094 {
2095         struct ena_rss *rss = &ena_dev->rss;
2096         struct ena_admin_get_feat_resp get_resp;
2097         int rc;
2098
2099         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2100                                     ENA_ADMIN_RSS_HASH_INPUT,
2101                                     rss->hash_ctrl_dma_addr,
2102                                     sizeof(*rss->hash_ctrl));
2103         if (unlikely(rc))
2104                 return rc;
2105
2106         if (fields)
2107                 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2108
2109         return 0;
2110 }
2111
2112 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2113 {
2114         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2115         struct ena_rss *rss = &ena_dev->rss;
2116         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2117         struct ena_admin_set_feat_cmd cmd;
2118         struct ena_admin_set_feat_resp resp;
2119         int ret;
2120
2121         if (!ena_com_check_supported_feature_id(ena_dev,
2122                                                 ENA_ADMIN_RSS_HASH_INPUT)) {
2123                 pr_info("Feature %d isn't supported\n", ENA_ADMIN_RSS_HASH_INPUT);
2124                 return -EPERM;
2125         }
2126
2127         memset(&cmd, 0x0, sizeof(cmd));
2128
2129         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2130         cmd.aq_common_descriptor.flags =
2131                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2132         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2133         cmd.u.flow_hash_input.enabled_input_sort =
2134                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2135                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2136
2137         ret = ena_com_mem_addr_set(ena_dev,
2138                                    &cmd.control_buffer.address,
2139                                    rss->hash_ctrl_dma_addr);
2140         if (unlikely(ret)) {
2141                 pr_err("memory address set failed\n");
2142                 return ret;
2143         }
2144         cmd.control_buffer.length = sizeof(*hash_ctrl);
2145
2146         ret = ena_com_execute_admin_command(admin_queue,
2147                                             (struct ena_admin_aq_entry *)&cmd,
2148                                             sizeof(cmd),
2149                                             (struct ena_admin_acq_entry *)&resp,
2150                                             sizeof(resp));
2151         if (unlikely(ret))
2152                 pr_err("Failed to set hash input. error: %d\n", ret);
2153
2154         return ret;
2155 }
2156
2157 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2158 {
2159         struct ena_rss *rss = &ena_dev->rss;
2160         struct ena_admin_feature_rss_hash_control *hash_ctrl =
2161                 rss->hash_ctrl;
2162         u16 available_fields = 0;
2163         int rc, i;
2164
2165         /* Get the supported hash input */
2166         rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2167         if (unlikely(rc))
2168                 return rc;
2169
2170         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2171                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2172                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2173
2174         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2175                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2176                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2177
2178         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2179                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2180                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2181
2182         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2183                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2184                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2185
2186         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2187                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2188
2189         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2190                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2191
2192         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2193                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2194
2195         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2196                 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2197
2198         for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2199                 available_fields = hash_ctrl->selected_fields[i].fields &
2200                                 hash_ctrl->supported_fields[i].fields;
2201                 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2202                         pr_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2203                                i, hash_ctrl->supported_fields[i].fields,
2204                                hash_ctrl->selected_fields[i].fields);
2205                         return -EPERM;
2206                 }
2207         }
2208
2209         rc = ena_com_set_hash_ctrl(ena_dev);
2210
2211         /* In case of failure, restore the old hash ctrl */
2212         if (unlikely(rc))
2213                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2214
2215         return rc;
2216 }
2217
2218 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2219                            enum ena_admin_flow_hash_proto proto,
2220                            u16 hash_fields)
2221 {
2222         struct ena_rss *rss = &ena_dev->rss;
2223         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2224         u16 supported_fields;
2225         int rc;
2226
2227         if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2228                 pr_err("Invalid proto num (%u)\n", proto);
2229                 return -EINVAL;
2230         }
2231
2232         /* Get the ctrl table */
2233         rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2234         if (unlikely(rc))
2235                 return rc;
2236
2237         /* Make sure all the fields are supported */
2238         supported_fields = hash_ctrl->supported_fields[proto].fields;
2239         if ((hash_fields & supported_fields) != hash_fields) {
2240                 pr_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2241                        proto, hash_fields, supported_fields);
2242         }
2243
2244         hash_ctrl->selected_fields[proto].fields = hash_fields;
2245
2246         rc = ena_com_set_hash_ctrl(ena_dev);
2247
2248         /* In case of failure, restore the old hash ctrl */
2249         if (unlikely(rc))
2250                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2251
2252         return 0;
2253 }
2254
2255 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2256                                       u16 entry_idx, u16 entry_value)
2257 {
2258         struct ena_rss *rss = &ena_dev->rss;
2259
2260         if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2261                 return -EINVAL;
2262
2263         if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2264                 return -EINVAL;
2265
2266         rss->host_rss_ind_tbl[entry_idx] = entry_value;
2267
2268         return 0;
2269 }
2270
2271 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2272 {
2273         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2274         struct ena_rss *rss = &ena_dev->rss;
2275         struct ena_admin_set_feat_cmd cmd;
2276         struct ena_admin_set_feat_resp resp;
2277         int ret;
2278
2279         if (!ena_com_check_supported_feature_id(
2280                     ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2281                 pr_info("Feature %d isn't supported\n",
2282                         ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2283                 return -EPERM;
2284         }
2285
2286         ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2287         if (ret) {
2288                 pr_err("Failed to convert host indirection table to device table\n");
2289                 return ret;
2290         }
2291
2292         memset(&cmd, 0x0, sizeof(cmd));
2293
2294         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2295         cmd.aq_common_descriptor.flags =
2296                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2297         cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2298         cmd.u.ind_table.size = rss->tbl_log_size;
2299         cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2300
2301         ret = ena_com_mem_addr_set(ena_dev,
2302                                    &cmd.control_buffer.address,
2303                                    rss->rss_ind_tbl_dma_addr);
2304         if (unlikely(ret)) {
2305                 pr_err("memory address set failed\n");
2306                 return ret;
2307         }
2308
2309         cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2310                 sizeof(struct ena_admin_rss_ind_table_entry);
2311
2312         ret = ena_com_execute_admin_command(admin_queue,
2313                                             (struct ena_admin_aq_entry *)&cmd,
2314                                             sizeof(cmd),
2315                                             (struct ena_admin_acq_entry *)&resp,
2316                                             sizeof(resp));
2317
2318         if (unlikely(ret))
2319                 pr_err("Failed to set indirect table. error: %d\n", ret);
2320
2321         return ret;
2322 }
2323
2324 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2325 {
2326         struct ena_rss *rss = &ena_dev->rss;
2327         struct ena_admin_get_feat_resp get_resp;
2328         u32 tbl_size;
2329         int i, rc;
2330
2331         tbl_size = (1ULL << rss->tbl_log_size) *
2332                 sizeof(struct ena_admin_rss_ind_table_entry);
2333
2334         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2335                                     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2336                                     rss->rss_ind_tbl_dma_addr,
2337                                     tbl_size);
2338         if (unlikely(rc))
2339                 return rc;
2340
2341         if (!ind_tbl)
2342                 return 0;
2343
2344         rc = ena_com_ind_tbl_convert_from_device(ena_dev);
2345         if (unlikely(rc))
2346                 return rc;
2347
2348         for (i = 0; i < (1 << rss->tbl_log_size); i++)
2349                 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2350
2351         return 0;
2352 }
2353
2354 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2355 {
2356         int rc;
2357
2358         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2359
2360         rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2361         if (unlikely(rc))
2362                 goto err_indr_tbl;
2363
2364         rc = ena_com_hash_key_allocate(ena_dev);
2365         if (unlikely(rc))
2366                 goto err_hash_key;
2367
2368         rc = ena_com_hash_ctrl_init(ena_dev);
2369         if (unlikely(rc))
2370                 goto err_hash_ctrl;
2371
2372         return 0;
2373
2374 err_hash_ctrl:
2375         ena_com_hash_key_destroy(ena_dev);
2376 err_hash_key:
2377         ena_com_indirect_table_destroy(ena_dev);
2378 err_indr_tbl:
2379
2380         return rc;
2381 }
2382
2383 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2384 {
2385         ena_com_indirect_table_destroy(ena_dev);
2386         ena_com_hash_key_destroy(ena_dev);
2387         ena_com_hash_ctrl_destroy(ena_dev);
2388
2389         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2390 }
2391
2392 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2393 {
2394         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2395
2396         host_attr->host_info =
2397                 dma_zalloc_coherent(ena_dev->dmadev, SZ_4K,
2398                                     &host_attr->host_info_dma_addr, GFP_KERNEL);
2399         if (unlikely(!host_attr->host_info))
2400                 return -ENOMEM;
2401
2402         return 0;
2403 }
2404
2405 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2406                                 u32 debug_area_size)
2407 {
2408         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2409
2410         host_attr->debug_area_virt_addr =
2411                 dma_zalloc_coherent(ena_dev->dmadev, debug_area_size,
2412                                     &host_attr->debug_area_dma_addr, GFP_KERNEL);
2413         if (unlikely(!host_attr->debug_area_virt_addr)) {
2414                 host_attr->debug_area_size = 0;
2415                 return -ENOMEM;
2416         }
2417
2418         host_attr->debug_area_size = debug_area_size;
2419
2420         return 0;
2421 }
2422
2423 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2424 {
2425         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2426
2427         if (host_attr->host_info) {
2428                 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,
2429                                   host_attr->host_info_dma_addr);
2430                 host_attr->host_info = NULL;
2431         }
2432 }
2433
2434 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2435 {
2436         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2437
2438         if (host_attr->debug_area_virt_addr) {
2439                 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size,
2440                                   host_attr->debug_area_virt_addr,
2441                                   host_attr->debug_area_dma_addr);
2442                 host_attr->debug_area_virt_addr = NULL;
2443         }
2444 }
2445
2446 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2447 {
2448         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2449         struct ena_com_admin_queue *admin_queue;
2450         struct ena_admin_set_feat_cmd cmd;
2451         struct ena_admin_set_feat_resp resp;
2452
2453         int ret;
2454
2455         if (!ena_com_check_supported_feature_id(ena_dev,
2456                                                 ENA_ADMIN_HOST_ATTR_CONFIG)) {
2457                 pr_warn("Set host attribute isn't supported\n");
2458                 return -EPERM;
2459         }
2460
2461         memset(&cmd, 0x0, sizeof(cmd));
2462         admin_queue = &ena_dev->admin_queue;
2463
2464         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2465         cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2466
2467         ret = ena_com_mem_addr_set(ena_dev,
2468                                    &cmd.u.host_attr.debug_ba,
2469                                    host_attr->debug_area_dma_addr);
2470         if (unlikely(ret)) {
2471                 pr_err("memory address set failed\n");
2472                 return ret;
2473         }
2474
2475         ret = ena_com_mem_addr_set(ena_dev,
2476                                    &cmd.u.host_attr.os_info_ba,
2477                                    host_attr->host_info_dma_addr);
2478         if (unlikely(ret)) {
2479                 pr_err("memory address set failed\n");
2480                 return ret;
2481         }
2482
2483         cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2484
2485         ret = ena_com_execute_admin_command(admin_queue,
2486                                             (struct ena_admin_aq_entry *)&cmd,
2487                                             sizeof(cmd),
2488                                             (struct ena_admin_acq_entry *)&resp,
2489                                             sizeof(resp));
2490
2491         if (unlikely(ret))
2492                 pr_err("Failed to set host attributes: %d\n", ret);
2493
2494         return ret;
2495 }
2496
2497 /* Interrupt moderation */
2498 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2499 {
2500         return ena_com_check_supported_feature_id(ena_dev,
2501                                                   ENA_ADMIN_INTERRUPT_MODERATION);
2502 }
2503
2504 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2505                                                       u32 tx_coalesce_usecs)
2506 {
2507         if (!ena_dev->intr_delay_resolution) {
2508                 pr_err("Illegal interrupt delay granularity value\n");
2509                 return -EFAULT;
2510         }
2511
2512         ena_dev->intr_moder_tx_interval = tx_coalesce_usecs /
2513                 ena_dev->intr_delay_resolution;
2514
2515         return 0;
2516 }
2517
2518 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2519                                                       u32 rx_coalesce_usecs)
2520 {
2521         if (!ena_dev->intr_delay_resolution) {
2522                 pr_err("Illegal interrupt delay granularity value\n");
2523                 return -EFAULT;
2524         }
2525
2526         /* We use LOWEST entry of moderation table for storing
2527          * nonadaptive interrupt coalescing values
2528          */
2529         ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2530                 rx_coalesce_usecs / ena_dev->intr_delay_resolution;
2531
2532         return 0;
2533 }
2534
2535 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev)
2536 {
2537         if (ena_dev->intr_moder_tbl)
2538                 devm_kfree(ena_dev->dmadev, ena_dev->intr_moder_tbl);
2539         ena_dev->intr_moder_tbl = NULL;
2540 }
2541
2542 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2543 {
2544         struct ena_admin_get_feat_resp get_resp;
2545         u16 delay_resolution;
2546         int rc;
2547
2548         rc = ena_com_get_feature(ena_dev, &get_resp,
2549                                  ENA_ADMIN_INTERRUPT_MODERATION);
2550
2551         if (rc) {
2552                 if (rc == -EPERM) {
2553                         pr_info("Feature %d isn't supported\n",
2554                                 ENA_ADMIN_INTERRUPT_MODERATION);
2555                         rc = 0;
2556                 } else {
2557                         pr_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2558                                rc);
2559                 }
2560
2561                 /* no moderation supported, disable adaptive support */
2562                 ena_com_disable_adaptive_moderation(ena_dev);
2563                 return rc;
2564         }
2565
2566         rc = ena_com_init_interrupt_moderation_table(ena_dev);
2567         if (rc)
2568                 goto err;
2569
2570         /* if moderation is supported by device we set adaptive moderation */
2571         delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2572         ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2573         ena_com_enable_adaptive_moderation(ena_dev);
2574
2575         return 0;
2576 err:
2577         ena_com_destroy_interrupt_moderation(ena_dev);
2578         return rc;
2579 }
2580
2581 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)
2582 {
2583         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2584
2585         if (!intr_moder_tbl)
2586                 return;
2587
2588         intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2589                 ENA_INTR_LOWEST_USECS;
2590         intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval =
2591                 ENA_INTR_LOWEST_PKTS;
2592         intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval =
2593                 ENA_INTR_LOWEST_BYTES;
2594
2595         intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval =
2596                 ENA_INTR_LOW_USECS;
2597         intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval =
2598                 ENA_INTR_LOW_PKTS;
2599         intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval =
2600                 ENA_INTR_LOW_BYTES;
2601
2602         intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval =
2603                 ENA_INTR_MID_USECS;
2604         intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval =
2605                 ENA_INTR_MID_PKTS;
2606         intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval =
2607                 ENA_INTR_MID_BYTES;
2608
2609         intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval =
2610                 ENA_INTR_HIGH_USECS;
2611         intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval =
2612                 ENA_INTR_HIGH_PKTS;
2613         intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval =
2614                 ENA_INTR_HIGH_BYTES;
2615
2616         intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval =
2617                 ENA_INTR_HIGHEST_USECS;
2618         intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval =
2619                 ENA_INTR_HIGHEST_PKTS;
2620         intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval =
2621                 ENA_INTR_HIGHEST_BYTES;
2622 }
2623
2624 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2625 {
2626         return ena_dev->intr_moder_tx_interval;
2627 }
2628
2629 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2630 {
2631         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2632
2633         if (intr_moder_tbl)
2634                 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval;
2635
2636         return 0;
2637 }
2638
2639 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
2640                                         enum ena_intr_moder_level level,
2641                                         struct ena_intr_moder_entry *entry)
2642 {
2643         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2644
2645         if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2646                 return;
2647
2648         intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval;
2649         if (ena_dev->intr_delay_resolution)
2650                 intr_moder_tbl[level].intr_moder_interval /=
2651                         ena_dev->intr_delay_resolution;
2652         intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval;
2653
2654         /* use hardcoded value until ethtool supports bytecount parameter */
2655         if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED)
2656                 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;
2657 }
2658
2659 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
2660                                        enum ena_intr_moder_level level,
2661                                        struct ena_intr_moder_entry *entry)
2662 {
2663         struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2664
2665         if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2666                 return;
2667
2668         entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval;
2669         if (ena_dev->intr_delay_resolution)
2670                 entry->intr_moder_interval *= ena_dev->intr_delay_resolution;
2671         entry->pkts_per_interval =
2672         intr_moder_tbl[level].pkts_per_interval;
2673         entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval;
2674 }