1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright (c) 2016-2018, NXP Semiconductors
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
5 #include <linux/packing.h>
8 #define SJA1105_SIZE_CGU_CMD 4
10 struct sja1105_cfg_pad_mii_tx {
22 struct sja1105_cfg_pad_mii_id {
34 * IDIV_0_C to IDIV_4_C control registers
35 * (addr. 10000Bh to 10000Fh)
37 struct sja1105_cgu_idiv {
44 /* PLL_1_C control register
46 * SJA1105 E/T: UM10944 Table 81 (address 10000Ah)
47 * SJA1105 P/Q/R/S: UM11040 Table 116 (address 10000Ah)
49 struct sja1105_cgu_pll_ctrl {
61 CLKSRC_MII0_TX_CLK = 0x00,
62 CLKSRC_MII0_RX_CLK = 0x01,
63 CLKSRC_MII1_TX_CLK = 0x02,
64 CLKSRC_MII1_RX_CLK = 0x03,
65 CLKSRC_MII2_TX_CLK = 0x04,
66 CLKSRC_MII2_RX_CLK = 0x05,
67 CLKSRC_MII3_TX_CLK = 0x06,
68 CLKSRC_MII3_RX_CLK = 0x07,
69 CLKSRC_MII4_TX_CLK = 0x08,
70 CLKSRC_MII4_RX_CLK = 0x09,
81 * MIIx clock control registers 1 to 30
82 * (addresses 100013h to 100035h)
84 struct sja1105_cgu_mii_ctrl {
90 static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv,
95 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op);
96 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op);
97 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op);
98 sja1105_packing(buf, &idiv->pd, 0, 0, size, op);
101 static int sja1105_cgu_idiv_config(struct sja1105_private *priv, int port,
102 bool enabled, int factor)
104 const struct sja1105_regs *regs = priv->info->regs;
105 struct device *dev = priv->ds->dev;
106 struct sja1105_cgu_idiv idiv;
107 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
109 if (enabled && factor != 1 && factor != 10) {
110 dev_err(dev, "idiv factor must be 1 or 10\n");
114 /* Payload for packed_buf */
115 idiv.clksrc = 0x0A; /* 25MHz */
116 idiv.autoblock = 1; /* Block clk automatically */
117 idiv.idiv = factor - 1; /* Divide by 1 or 10 */
118 idiv.pd = enabled ? 0 : 1; /* Power down? */
119 sja1105_cgu_idiv_packing(packed_buf, &idiv, PACK);
121 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
122 regs->cgu_idiv[port], packed_buf,
123 SJA1105_SIZE_CGU_CMD);
127 sja1105_cgu_mii_control_packing(void *buf, struct sja1105_cgu_mii_ctrl *cmd,
132 sja1105_packing(buf, &cmd->clksrc, 28, 24, size, op);
133 sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
134 sja1105_packing(buf, &cmd->pd, 0, 0, size, op);
137 static int sja1105_cgu_mii_tx_clk_config(struct sja1105_private *priv,
138 int port, sja1105_mii_role_t role)
140 const struct sja1105_regs *regs = priv->info->regs;
141 struct sja1105_cgu_mii_ctrl mii_tx_clk;
142 const int mac_clk_sources[] = {
149 const int phy_clk_sources[] = {
156 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
159 if (role == XMII_MAC)
160 clksrc = mac_clk_sources[port];
162 clksrc = phy_clk_sources[port];
164 /* Payload for packed_buf */
165 mii_tx_clk.clksrc = clksrc;
166 mii_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
167 mii_tx_clk.pd = 0; /* Power Down off => enabled */
168 sja1105_cgu_mii_control_packing(packed_buf, &mii_tx_clk, PACK);
170 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
171 regs->mii_tx_clk[port], packed_buf,
172 SJA1105_SIZE_CGU_CMD);
176 sja1105_cgu_mii_rx_clk_config(struct sja1105_private *priv, int port)
178 const struct sja1105_regs *regs = priv->info->regs;
179 struct sja1105_cgu_mii_ctrl mii_rx_clk;
180 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
181 const int clk_sources[] = {
189 /* Payload for packed_buf */
190 mii_rx_clk.clksrc = clk_sources[port];
191 mii_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
192 mii_rx_clk.pd = 0; /* Power Down off => enabled */
193 sja1105_cgu_mii_control_packing(packed_buf, &mii_rx_clk, PACK);
195 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
196 regs->mii_rx_clk[port], packed_buf,
197 SJA1105_SIZE_CGU_CMD);
201 sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private *priv, int port)
203 const struct sja1105_regs *regs = priv->info->regs;
204 struct sja1105_cgu_mii_ctrl mii_ext_tx_clk;
205 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
206 const int clk_sources[] = {
214 /* Payload for packed_buf */
215 mii_ext_tx_clk.clksrc = clk_sources[port];
216 mii_ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
217 mii_ext_tx_clk.pd = 0; /* Power Down off => enabled */
218 sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_tx_clk, PACK);
220 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
221 regs->mii_ext_tx_clk[port],
222 packed_buf, SJA1105_SIZE_CGU_CMD);
226 sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private *priv, int port)
228 const struct sja1105_regs *regs = priv->info->regs;
229 struct sja1105_cgu_mii_ctrl mii_ext_rx_clk;
230 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
231 const int clk_sources[] = {
239 /* Payload for packed_buf */
240 mii_ext_rx_clk.clksrc = clk_sources[port];
241 mii_ext_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
242 mii_ext_rx_clk.pd = 0; /* Power Down off => enabled */
243 sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_rx_clk, PACK);
245 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
246 regs->mii_ext_rx_clk[port],
247 packed_buf, SJA1105_SIZE_CGU_CMD);
250 static int sja1105_mii_clocking_setup(struct sja1105_private *priv, int port,
251 sja1105_mii_role_t role)
253 struct device *dev = priv->ds->dev;
256 dev_dbg(dev, "Configuring MII-%s clocking\n",
257 (role == XMII_MAC) ? "MAC" : "PHY");
258 /* If role is MAC, disable IDIV
259 * If role is PHY, enable IDIV and configure for 1/1 divider
261 rc = sja1105_cgu_idiv_config(priv, port, (role == XMII_PHY), 1);
265 /* Configure CLKSRC of MII_TX_CLK_n
266 * * If role is MAC, select TX_CLK_n
267 * * If role is PHY, select IDIV_n
269 rc = sja1105_cgu_mii_tx_clk_config(priv, port, role);
273 /* Configure CLKSRC of MII_RX_CLK_n
276 rc = sja1105_cgu_mii_rx_clk_config(priv, port);
280 if (role == XMII_PHY) {
281 /* Per MII spec, the PHY (which is us) drives the TX_CLK pin */
283 /* Configure CLKSRC of EXT_TX_CLK_n
286 rc = sja1105_cgu_mii_ext_tx_clk_config(priv, port);
290 /* Configure CLKSRC of EXT_RX_CLK_n
293 rc = sja1105_cgu_mii_ext_rx_clk_config(priv, port);
301 sja1105_cgu_pll_control_packing(void *buf, struct sja1105_cgu_pll_ctrl *cmd,
306 sja1105_packing(buf, &cmd->pllclksrc, 28, 24, size, op);
307 sja1105_packing(buf, &cmd->msel, 23, 16, size, op);
308 sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
309 sja1105_packing(buf, &cmd->psel, 9, 8, size, op);
310 sja1105_packing(buf, &cmd->direct, 7, 7, size, op);
311 sja1105_packing(buf, &cmd->fbsel, 6, 6, size, op);
312 sja1105_packing(buf, &cmd->bypass, 1, 1, size, op);
313 sja1105_packing(buf, &cmd->pd, 0, 0, size, op);
316 static int sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private *priv,
317 int port, sja1105_speed_t speed)
319 const struct sja1105_regs *regs = priv->info->regs;
320 struct sja1105_cgu_mii_ctrl txc;
321 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
324 if (speed == SJA1105_SPEED_1000MBPS) {
325 clksrc = CLKSRC_PLL0;
327 int clk_sources[] = {CLKSRC_IDIV0, CLKSRC_IDIV1, CLKSRC_IDIV2,
328 CLKSRC_IDIV3, CLKSRC_IDIV4};
329 clksrc = clk_sources[port];
332 /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */
334 /* Autoblock clk while changing clksrc */
336 /* Power Down off => enabled */
338 sja1105_cgu_mii_control_packing(packed_buf, &txc, PACK);
340 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
341 regs->rgmii_tx_clk[port],
342 packed_buf, SJA1105_SIZE_CGU_CMD);
347 sja1105_cfg_pad_mii_tx_packing(void *buf, struct sja1105_cfg_pad_mii_tx *cmd,
352 sja1105_packing(buf, &cmd->d32_os, 28, 27, size, op);
353 sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op);
354 sja1105_packing(buf, &cmd->d10_os, 20, 19, size, op);
355 sja1105_packing(buf, &cmd->d10_ipud, 17, 16, size, op);
356 sja1105_packing(buf, &cmd->ctrl_os, 12, 11, size, op);
357 sja1105_packing(buf, &cmd->ctrl_ipud, 9, 8, size, op);
358 sja1105_packing(buf, &cmd->clk_os, 4, 3, size, op);
359 sja1105_packing(buf, &cmd->clk_ih, 2, 2, size, op);
360 sja1105_packing(buf, &cmd->clk_ipud, 1, 0, size, op);
363 static int sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private *priv,
366 const struct sja1105_regs *regs = priv->info->regs;
367 struct sja1105_cfg_pad_mii_tx pad_mii_tx;
368 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
371 pad_mii_tx.d32_os = 3; /* TXD[3:2] output stage: */
372 /* high noise/high speed */
373 pad_mii_tx.d10_os = 3; /* TXD[1:0] output stage: */
374 /* high noise/high speed */
375 pad_mii_tx.d32_ipud = 2; /* TXD[3:2] input stage: */
376 /* plain input (default) */
377 pad_mii_tx.d10_ipud = 2; /* TXD[1:0] input stage: */
378 /* plain input (default) */
379 pad_mii_tx.ctrl_os = 3; /* TX_CTL / TX_ER output stage */
380 pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */
381 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */
382 pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */
383 pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */
384 sja1105_cfg_pad_mii_tx_packing(packed_buf, &pad_mii_tx, PACK);
386 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
387 regs->pad_mii_tx[port],
388 packed_buf, SJA1105_SIZE_CGU_CMD);
392 sja1105_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
395 const int size = SJA1105_SIZE_CGU_CMD;
397 sja1105_packing(buf, &cmd->rxc_stable_ovr, 15, 15, size, op);
398 sja1105_packing(buf, &cmd->rxc_delay, 14, 10, size, op);
399 sja1105_packing(buf, &cmd->rxc_bypass, 9, 9, size, op);
400 sja1105_packing(buf, &cmd->rxc_pd, 8, 8, size, op);
401 sja1105_packing(buf, &cmd->txc_stable_ovr, 7, 7, size, op);
402 sja1105_packing(buf, &cmd->txc_delay, 6, 2, size, op);
403 sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op);
404 sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op);
407 /* Valid range in degrees is an integer between 73.8 and 101.7 */
408 static inline u64 sja1105_rgmii_delay(u64 phase)
410 /* UM11040.pdf: The delay in degree phase is 73.8 + delay_tune * 0.9.
411 * To avoid floating point operations we'll multiply by 10
412 * and get 1 decimal point precision.
415 return (phase - 738) / 9;
418 /* The RGMII delay setup procedure is 2-step and gets called upon each
419 * .phylink_mac_config. Both are strategic.
420 * The reason is that the RX Tunable Delay Line of the SJA1105 MAC has issues
421 * with recovering from a frequency change of the link partner's RGMII clock.
422 * The easiest way to recover from this is to temporarily power down the TDL,
423 * as it will re-lock at the new frequency afterwards.
425 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port)
427 const struct sja1105_private *priv = ctx;
428 const struct sja1105_regs *regs = priv->info->regs;
429 struct sja1105_cfg_pad_mii_id pad_mii_id = {0};
430 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
433 if (priv->rgmii_rx_delay[port])
434 pad_mii_id.rxc_delay = sja1105_rgmii_delay(90);
435 if (priv->rgmii_tx_delay[port])
436 pad_mii_id.txc_delay = sja1105_rgmii_delay(90);
438 /* Stage 1: Turn the RGMII delay lines off. */
439 pad_mii_id.rxc_bypass = 1;
440 pad_mii_id.rxc_pd = 1;
441 pad_mii_id.txc_bypass = 1;
442 pad_mii_id.txc_pd = 1;
443 sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
445 rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE,
446 regs->pad_mii_id[port],
447 packed_buf, SJA1105_SIZE_CGU_CMD);
451 /* Stage 2: Turn the RGMII delay lines on. */
452 if (priv->rgmii_rx_delay[port]) {
453 pad_mii_id.rxc_bypass = 0;
454 pad_mii_id.rxc_pd = 0;
456 if (priv->rgmii_tx_delay[port]) {
457 pad_mii_id.txc_bypass = 0;
458 pad_mii_id.txc_pd = 0;
460 sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
462 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
463 regs->pad_mii_id[port],
464 packed_buf, SJA1105_SIZE_CGU_CMD);
467 static int sja1105_rgmii_clocking_setup(struct sja1105_private *priv, int port,
468 sja1105_mii_role_t role)
470 struct device *dev = priv->ds->dev;
471 struct sja1105_mac_config_entry *mac;
472 sja1105_speed_t speed;
475 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
476 speed = mac[port].speed;
478 dev_dbg(dev, "Configuring port %d RGMII at speed %dMbps\n",
482 case SJA1105_SPEED_1000MBPS:
483 /* 1000Mbps, IDIV disabled (125 MHz) */
484 rc = sja1105_cgu_idiv_config(priv, port, false, 1);
486 case SJA1105_SPEED_100MBPS:
487 /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */
488 rc = sja1105_cgu_idiv_config(priv, port, true, 1);
490 case SJA1105_SPEED_10MBPS:
491 /* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */
492 rc = sja1105_cgu_idiv_config(priv, port, true, 10);
494 case SJA1105_SPEED_AUTO:
495 /* Skip CGU configuration if there is no speed available
496 * (e.g. link is not established yet)
498 dev_dbg(dev, "Speed not available, skipping CGU config\n");
505 dev_err(dev, "Failed to configure idiv\n");
508 rc = sja1105_cgu_rgmii_tx_clk_config(priv, port, speed);
510 dev_err(dev, "Failed to configure RGMII Tx clock\n");
513 rc = sja1105_rgmii_cfg_pad_tx_config(priv, port);
515 dev_err(dev, "Failed to configure Tx pad registers\n");
518 if (!priv->info->setup_rgmii_delay)
520 /* The role has no hardware effect for RGMII. However we use it as
521 * a proxy for this interface being a MAC-to-MAC connection, with
522 * the RGMII internal delays needing to be applied by us.
524 if (role == XMII_MAC)
527 return priv->info->setup_rgmii_delay(priv, port);
530 static int sja1105_cgu_rmii_ref_clk_config(struct sja1105_private *priv,
533 const struct sja1105_regs *regs = priv->info->regs;
534 struct sja1105_cgu_mii_ctrl ref_clk;
535 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
536 const int clk_sources[] = {
544 /* Payload for packed_buf */
545 ref_clk.clksrc = clk_sources[port];
546 ref_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
547 ref_clk.pd = 0; /* Power Down off => enabled */
548 sja1105_cgu_mii_control_packing(packed_buf, &ref_clk, PACK);
550 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
551 regs->rmii_ref_clk[port],
552 packed_buf, SJA1105_SIZE_CGU_CMD);
556 sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private *priv, int port)
558 const struct sja1105_regs *regs = priv->info->regs;
559 struct sja1105_cgu_mii_ctrl ext_tx_clk;
560 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
562 /* Payload for packed_buf */
563 ext_tx_clk.clksrc = CLKSRC_PLL1;
564 ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
565 ext_tx_clk.pd = 0; /* Power Down off => enabled */
566 sja1105_cgu_mii_control_packing(packed_buf, &ext_tx_clk, PACK);
568 return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
569 regs->rmii_ext_tx_clk[port],
570 packed_buf, SJA1105_SIZE_CGU_CMD);
573 static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv)
575 const struct sja1105_regs *regs = priv->info->regs;
576 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
577 struct sja1105_cgu_pll_ctrl pll = {0};
578 struct device *dev = priv->ds->dev;
581 /* PLL1 must be enabled and output 50 Mhz.
582 * This is done by writing first 0x0A010941 to
583 * the PLL_1_C register and then deasserting
584 * power down (PD) 0x0A010940.
587 /* Step 1: PLL1 setup for 50Mhz */
597 sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
598 rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rmii_pll1,
599 packed_buf, SJA1105_SIZE_CGU_CMD);
601 dev_err(dev, "failed to configure PLL1 for 50MHz\n");
605 /* Step 2: Enable PLL1 */
608 sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
609 rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rmii_pll1,
610 packed_buf, SJA1105_SIZE_CGU_CMD);
612 dev_err(dev, "failed to enable PLL1\n");
618 static int sja1105_rmii_clocking_setup(struct sja1105_private *priv, int port,
619 sja1105_mii_role_t role)
621 struct device *dev = priv->ds->dev;
624 dev_dbg(dev, "Configuring RMII-%s clocking\n",
625 (role == XMII_MAC) ? "MAC" : "PHY");
626 /* AH1601.pdf chapter 2.5.1. Sources */
627 if (role == XMII_MAC) {
628 /* Configure and enable PLL1 for 50Mhz output */
629 rc = sja1105_cgu_rmii_pll_config(priv);
633 /* Disable IDIV for this port */
634 rc = sja1105_cgu_idiv_config(priv, port, false, 1);
637 /* Source to sink mappings */
638 rc = sja1105_cgu_rmii_ref_clk_config(priv, port);
641 if (role == XMII_MAC) {
642 rc = sja1105_cgu_rmii_ext_tx_clk_config(priv, port);
649 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port)
651 struct sja1105_xmii_params_entry *mii;
652 struct device *dev = priv->ds->dev;
653 sja1105_phy_interface_t phy_mode;
654 sja1105_mii_role_t role;
657 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
660 phy_mode = mii->xmii_mode[port];
661 /* MAC or PHY, for applicable types (not RGMII) */
662 role = mii->phy_mac[port];
666 rc = sja1105_mii_clocking_setup(priv, port, role);
669 rc = sja1105_rmii_clocking_setup(priv, port, role);
671 case XMII_MODE_RGMII:
672 rc = sja1105_rgmii_clocking_setup(priv, port, role);
675 dev_err(dev, "Invalid interface mode specified: %d\n",
680 dev_err(dev, "Clocking setup for port %d failed: %d\n",
685 int sja1105_clocking_setup(struct sja1105_private *priv)
689 for (port = 0; port < SJA1105_NUM_PORTS; port++) {
690 rc = sja1105_clocking_setup_port(priv, port);