1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Xilinx CAN device driver
4 * Copyright (C) 2012 - 2014 Xilinx, Inc.
5 * Copyright (C) 2009 PetaLogix. All rights reserved.
6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy
9 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/netdevice.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/string.h>
26 #include <linux/types.h>
27 #include <linux/can/dev.h>
28 #include <linux/can/error.h>
29 #include <linux/can/led.h>
30 #include <linux/pm_runtime.h>
32 #define DRIVER_NAME "xilinx_can"
34 /* CAN registers set */
36 XCAN_SRR_OFFSET = 0x00, /* Software reset */
37 XCAN_MSR_OFFSET = 0x04, /* Mode select */
38 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */
39 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */
40 XCAN_ECR_OFFSET = 0x10, /* Error counter */
41 XCAN_ESR_OFFSET = 0x14, /* Error status */
42 XCAN_SR_OFFSET = 0x18, /* Status */
43 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */
44 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */
45 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */
47 /* not on CAN FD cores */
48 XCAN_TXFIFO_OFFSET = 0x30, /* TX FIFO base */
49 XCAN_RXFIFO_OFFSET = 0x50, /* RX FIFO base */
50 XCAN_AFR_OFFSET = 0x60, /* Acceptance Filter */
52 /* only on CAN FD cores */
53 XCAN_F_BRPR_OFFSET = 0x088, /* Data Phase Baud Rate
56 XCAN_F_BTR_OFFSET = 0x08C, /* Data Phase Bit Timing */
57 XCAN_TRR_OFFSET = 0x0090, /* TX Buffer Ready Request */
58 XCAN_AFR_EXT_OFFSET = 0x00E0, /* Acceptance Filter */
59 XCAN_FSR_OFFSET = 0x00E8, /* RX FIFO Status */
60 XCAN_TXMSG_BASE_OFFSET = 0x0100, /* TX Message Space */
61 XCAN_RXMSG_BASE_OFFSET = 0x1100, /* RX Message Space */
62 XCAN_RXMSG_2_BASE_OFFSET = 0x2100, /* RX Message Space */
63 XCAN_AFR_2_MASK_OFFSET = 0x0A00, /* Acceptance Filter MASK */
64 XCAN_AFR_2_ID_OFFSET = 0x0A04, /* Acceptance Filter ID */
67 #define XCAN_FRAME_ID_OFFSET(frame_base) ((frame_base) + 0x00)
68 #define XCAN_FRAME_DLC_OFFSET(frame_base) ((frame_base) + 0x04)
69 #define XCAN_FRAME_DW1_OFFSET(frame_base) ((frame_base) + 0x08)
70 #define XCAN_FRAME_DW2_OFFSET(frame_base) ((frame_base) + 0x0C)
71 #define XCANFD_FRAME_DW_OFFSET(frame_base) ((frame_base) + 0x08)
73 #define XCAN_CANFD_FRAME_SIZE 0x48
74 #define XCAN_TXMSG_FRAME_OFFSET(n) (XCAN_TXMSG_BASE_OFFSET + \
75 XCAN_CANFD_FRAME_SIZE * (n))
76 #define XCAN_RXMSG_FRAME_OFFSET(n) (XCAN_RXMSG_BASE_OFFSET + \
77 XCAN_CANFD_FRAME_SIZE * (n))
78 #define XCAN_RXMSG_2_FRAME_OFFSET(n) (XCAN_RXMSG_2_BASE_OFFSET + \
79 XCAN_CANFD_FRAME_SIZE * (n))
81 /* the single TX mailbox used by this driver on CAN FD HW */
82 #define XCAN_TX_MAILBOX_IDX 0
84 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
85 #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */
86 #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
87 #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */
88 #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */
89 #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */
90 #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */
91 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
92 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
93 #define XCAN_BTR_SJW_MASK_CANFD 0x000F0000 /* Synchronous jump width */
94 #define XCAN_BTR_TS2_MASK_CANFD 0x00000F00 /* Time segment 2 */
95 #define XCAN_BTR_TS1_MASK_CANFD 0x0000003F /* Time segment 1 */
96 #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */
97 #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */
98 #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */
99 #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */
100 #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */
101 #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */
102 #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */
103 #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */
104 #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */
105 #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */
106 #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */
107 #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */
108 #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */
109 #define XCAN_IXR_RXMNF_MASK 0x00020000 /* RX match not finished */
110 #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */
111 #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */
112 #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */
113 #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */
114 #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */
115 #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */
116 #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */
117 #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */
118 #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */
119 #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */
120 #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */
121 #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
122 #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
123 #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
124 #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
125 #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */
126 #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */
127 #define XCAN_FSR_FL_MASK 0x00003F00 /* RX Fill Level */
128 #define XCAN_2_FSR_FL_MASK 0x00007F00 /* RX Fill Level */
129 #define XCAN_FSR_IRI_MASK 0x00000080 /* RX Increment Read Index */
130 #define XCAN_FSR_RI_MASK 0x0000001F /* RX Read Index */
131 #define XCAN_2_FSR_RI_MASK 0x0000003F /* RX Read Index */
132 #define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */
133 #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */
135 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
136 #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
137 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
138 #define XCAN_BTR_SJW_SHIFT_CANFD 16 /* Synchronous jump width */
139 #define XCAN_BTR_TS2_SHIFT_CANFD 8 /* Time segment 2 */
140 #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
141 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
142 #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */
143 #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */
145 /* CAN frame length constants */
146 #define XCAN_FRAME_MAX_DATA_LEN 8
147 #define XCANFD_DW_BYTES 4
148 #define XCAN_TIMEOUT (1 * HZ)
150 /* TX-FIFO-empty interrupt available */
151 #define XCAN_FLAG_TXFEMP 0x0001
152 /* RX Match Not Finished interrupt available */
153 #define XCAN_FLAG_RXMNF 0x0002
154 /* Extended acceptance filters with control at 0xE0 */
155 #define XCAN_FLAG_EXT_FILTERS 0x0004
156 /* TX mailboxes instead of TX FIFO */
157 #define XCAN_FLAG_TX_MAILBOXES 0x0008
158 /* RX FIFO with each buffer in separate registers at 0x1100
159 * instead of the regular FIFO at 0x50
161 #define XCAN_FLAG_RX_FIFO_MULTI 0x0010
162 #define XCAN_FLAG_CANFD_2 0x0020
171 struct xcan_devtype_data {
172 enum xcan_ip_type cantype;
174 const struct can_bittiming_const *bittiming_const;
175 const char *bus_clk_name;
176 unsigned int btr_ts2_shift;
177 unsigned int btr_sjw_shift;
181 * struct xcan_priv - This definition define CAN driver instance
182 * @can: CAN private data structure.
183 * @tx_lock: Lock for synchronizing TX interrupt handling
184 * @tx_head: Tx CAN packets ready to send on the queue
185 * @tx_tail: Tx CAN packets successfully sended on the queue
186 * @tx_max: Maximum number packets the driver can send
187 * @napi: NAPI structure
188 * @read_reg: For reading data from CAN registers
189 * @write_reg: For writing data to CAN registers
190 * @dev: Network device data structure
191 * @reg_base: Ioremapped address to registers
192 * @irq_flags: For request_irq()
193 * @bus_clk: Pointer to struct clk
194 * @can_clk: Pointer to struct clk
195 * @devtype: Device type specific constants
200 unsigned int tx_head;
201 unsigned int tx_tail;
203 struct napi_struct napi;
204 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
205 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
208 void __iomem *reg_base;
209 unsigned long irq_flags;
212 struct xcan_devtype_data devtype;
215 /* CAN Bittiming constants as per Xilinx CAN specs */
216 static const struct can_bittiming_const xcan_bittiming_const = {
228 /* AXI CANFD Arbitration Bittiming constants as per AXI CANFD 1.0 spec */
229 static const struct can_bittiming_const xcan_bittiming_const_canfd = {
241 /* AXI CANFD Data Bittiming constants as per AXI CANFD 1.0 specs */
242 static struct can_bittiming_const xcan_data_bittiming_const_canfd = {
254 /* AXI CANFD 2.0 Arbitration Bittiming constants as per AXI CANFD 2.0 spec */
255 static const struct can_bittiming_const xcan_bittiming_const_canfd2 = {
267 /* AXI CANFD 2.0 Data Bittiming constants as per AXI CANFD 2.0 spec */
268 static struct can_bittiming_const xcan_data_bittiming_const_canfd2 = {
281 * xcan_write_reg_le - Write a value to the device register little endian
282 * @priv: Driver private data structure
283 * @reg: Register offset
284 * @val: Value to write at the Register offset
286 * Write data to the paricular CAN register
288 static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
291 iowrite32(val, priv->reg_base + reg);
295 * xcan_read_reg_le - Read a value from the device register little endian
296 * @priv: Driver private data structure
297 * @reg: Register offset
299 * Read data from the particular CAN register
300 * Return: value read from the CAN register
302 static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg)
304 return ioread32(priv->reg_base + reg);
308 * xcan_write_reg_be - Write a value to the device register big endian
309 * @priv: Driver private data structure
310 * @reg: Register offset
311 * @val: Value to write at the Register offset
313 * Write data to the paricular CAN register
315 static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
318 iowrite32be(val, priv->reg_base + reg);
322 * xcan_read_reg_be - Read a value from the device register big endian
323 * @priv: Driver private data structure
324 * @reg: Register offset
326 * Read data from the particular CAN register
327 * Return: value read from the CAN register
329 static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg)
331 return ioread32be(priv->reg_base + reg);
335 * xcan_rx_int_mask - Get the mask for the receive interrupt
336 * @priv: Driver private data structure
338 * Return: The receive interrupt mask used by the driver on this HW
340 static u32 xcan_rx_int_mask(const struct xcan_priv *priv)
342 /* RXNEMP is better suited for our use case as it cannot be cleared
343 * while the FIFO is non-empty, but CAN FD HW does not have it
345 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI)
346 return XCAN_IXR_RXOK_MASK;
348 return XCAN_IXR_RXNEMP_MASK;
352 * set_reset_mode - Resets the CAN device mode
353 * @ndev: Pointer to net_device structure
355 * This is the driver reset mode routine.The driver
356 * enters into configuration mode.
358 * Return: 0 on success and failure value on error
360 static int set_reset_mode(struct net_device *ndev)
362 struct xcan_priv *priv = netdev_priv(ndev);
363 unsigned long timeout;
365 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
367 timeout = jiffies + XCAN_TIMEOUT;
368 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
369 if (time_after(jiffies, timeout)) {
370 netdev_warn(ndev, "timed out for config mode\n");
373 usleep_range(500, 10000);
376 /* reset clears FIFOs */
384 * xcan_set_bittiming - CAN set bit timing routine
385 * @ndev: Pointer to net_device structure
387 * This is the driver set bittiming routine.
388 * Return: 0 on success and failure value on error
390 static int xcan_set_bittiming(struct net_device *ndev)
392 struct xcan_priv *priv = netdev_priv(ndev);
393 struct can_bittiming *bt = &priv->can.bittiming;
394 struct can_bittiming *dbt = &priv->can.data_bittiming;
398 /* Check whether Xilinx CAN is in configuration mode.
399 * It cannot set bit timing if Xilinx CAN is not in configuration mode.
401 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
403 if (!is_config_mode) {
405 "BUG! Cannot set bittiming - CAN is not in config mode\n");
409 /* Setting Baud Rate prescalar value in BRPR Register */
410 btr0 = (bt->brp - 1);
412 /* Setting Time Segment 1 in BTR Register */
413 btr1 = (bt->prop_seg + bt->phase_seg1 - 1);
415 /* Setting Time Segment 2 in BTR Register */
416 btr1 |= (bt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift;
418 /* Setting Synchronous jump width in BTR Register */
419 btr1 |= (bt->sjw - 1) << priv->devtype.btr_sjw_shift;
421 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
422 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
424 if (priv->devtype.cantype == XAXI_CANFD ||
425 priv->devtype.cantype == XAXI_CANFD_2_0) {
426 /* Setting Baud Rate prescalar value in F_BRPR Register */
429 /* Setting Time Segment 1 in BTR Register */
430 btr1 = dbt->prop_seg + dbt->phase_seg1 - 1;
432 /* Setting Time Segment 2 in BTR Register */
433 btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift;
435 /* Setting Synchronous jump width in BTR Register */
436 btr1 |= (dbt->sjw - 1) << priv->devtype.btr_sjw_shift;
438 priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0);
439 priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1);
442 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
443 priv->read_reg(priv, XCAN_BRPR_OFFSET),
444 priv->read_reg(priv, XCAN_BTR_OFFSET));
450 * xcan_chip_start - This the drivers start routine
451 * @ndev: Pointer to net_device structure
453 * This is the drivers start routine.
454 * Based on the State of the CAN device it puts
455 * the CAN device into a proper mode.
457 * Return: 0 on success and failure value on error
459 static int xcan_chip_start(struct net_device *ndev)
461 struct xcan_priv *priv = netdev_priv(ndev);
466 /* Check if it is in reset mode */
467 err = set_reset_mode(ndev);
471 err = xcan_set_bittiming(ndev);
475 /* Enable interrupts */
476 ier = XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |
477 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK |
478 XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
479 XCAN_IXR_ARBLST_MASK | xcan_rx_int_mask(priv);
481 if (priv->devtype.flags & XCAN_FLAG_RXMNF)
482 ier |= XCAN_IXR_RXMNF_MASK;
484 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
486 /* Check whether it is loopback mode or normal mode */
487 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
488 reg_msr = XCAN_MSR_LBACK_MASK;
493 /* enable the first extended filter, if any, as cores with extended
494 * filtering default to non-receipt if all filters are disabled
496 if (priv->devtype.flags & XCAN_FLAG_EXT_FILTERS)
497 priv->write_reg(priv, XCAN_AFR_EXT_OFFSET, 0x00000001);
499 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
500 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
502 netdev_dbg(ndev, "status:#x%08x\n",
503 priv->read_reg(priv, XCAN_SR_OFFSET));
505 priv->can.state = CAN_STATE_ERROR_ACTIVE;
510 * xcan_do_set_mode - This sets the mode of the driver
511 * @ndev: Pointer to net_device structure
512 * @mode: Tells the mode of the driver
514 * This check the drivers state and calls the
515 * the corresponding modes to set.
517 * Return: 0 on success and failure value on error
519 static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode)
525 ret = xcan_chip_start(ndev);
527 netdev_err(ndev, "xcan_chip_start failed!\n");
530 netif_wake_queue(ndev);
541 * xcan_write_frame - Write a frame to HW
542 * @priv: Driver private data structure
543 * @skb: sk_buff pointer that contains data to be Txed
544 * @frame_offset: Register offset to write the frame to
546 static void xcan_write_frame(struct xcan_priv *priv, struct sk_buff *skb,
549 u32 id, dlc, data[2] = {0, 0};
550 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
551 u32 ramoff, dwindex = 0, i;
553 /* Watch carefully on the bit sequence */
554 if (cf->can_id & CAN_EFF_FLAG) {
555 /* Extended CAN ID format */
556 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
558 id |= (((cf->can_id & CAN_EFF_MASK) >>
559 (CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)) <<
560 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
562 /* The substibute remote TX request bit should be "1"
563 * for extended frames as in the Xilinx CAN datasheet
565 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK;
567 if (cf->can_id & CAN_RTR_FLAG)
568 /* Extended frames remote TX request */
569 id |= XCAN_IDR_RTR_MASK;
571 /* Standard CAN ID format */
572 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) &
575 if (cf->can_id & CAN_RTR_FLAG)
576 /* Standard frames remote TX request */
577 id |= XCAN_IDR_SRR_MASK;
580 dlc = can_len2dlc(cf->len) << XCAN_DLCR_DLC_SHIFT;
581 if (can_is_canfd_skb(skb)) {
582 if (cf->flags & CANFD_BRS)
583 dlc |= XCAN_DLCR_BRS_MASK;
584 dlc |= XCAN_DLCR_EDL_MASK;
587 priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id);
588 /* If the CAN frame is RTR frame this write triggers transmission
591 priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc);
592 if (priv->devtype.cantype == XAXI_CANFD ||
593 priv->devtype.cantype == XAXI_CANFD_2_0) {
594 for (i = 0; i < cf->len; i += 4) {
595 ramoff = XCANFD_FRAME_DW_OFFSET(frame_offset) +
596 (dwindex * XCANFD_DW_BYTES);
597 priv->write_reg(priv, ramoff,
598 be32_to_cpup((__be32 *)(cf->data + i)));
603 data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
605 data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
607 if (!(cf->can_id & CAN_RTR_FLAG)) {
608 priv->write_reg(priv,
609 XCAN_FRAME_DW1_OFFSET(frame_offset),
611 /* If the CAN frame is Standard/Extended frame this
612 * write triggers transmission (not on CAN FD)
614 priv->write_reg(priv,
615 XCAN_FRAME_DW2_OFFSET(frame_offset),
622 * xcan_start_xmit_fifo - Starts the transmission (FIFO mode)
623 * @skb: sk_buff pointer that contains data to be Txed
624 * @ndev: Pointer to net_device structure
626 * Return: 0 on success, -ENOSPC if FIFO is full.
628 static int xcan_start_xmit_fifo(struct sk_buff *skb, struct net_device *ndev)
630 struct xcan_priv *priv = netdev_priv(ndev);
633 /* Check if the TX buffer is full */
634 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
638 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
640 spin_lock_irqsave(&priv->tx_lock, flags);
644 xcan_write_frame(priv, skb, XCAN_TXFIFO_OFFSET);
646 /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */
647 if (priv->tx_max > 1)
648 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK);
650 /* Check if the TX buffer is full */
651 if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
652 netif_stop_queue(ndev);
654 spin_unlock_irqrestore(&priv->tx_lock, flags);
660 * xcan_start_xmit_mailbox - Starts the transmission (mailbox mode)
661 * @skb: sk_buff pointer that contains data to be Txed
662 * @ndev: Pointer to net_device structure
664 * Return: 0 on success, -ENOSPC if there is no space
666 static int xcan_start_xmit_mailbox(struct sk_buff *skb, struct net_device *ndev)
668 struct xcan_priv *priv = netdev_priv(ndev);
671 if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) &
672 BIT(XCAN_TX_MAILBOX_IDX)))
675 can_put_echo_skb(skb, ndev, 0);
677 spin_lock_irqsave(&priv->tx_lock, flags);
681 xcan_write_frame(priv, skb,
682 XCAN_TXMSG_FRAME_OFFSET(XCAN_TX_MAILBOX_IDX));
684 /* Mark buffer as ready for transmit */
685 priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX));
687 netif_stop_queue(ndev);
689 spin_unlock_irqrestore(&priv->tx_lock, flags);
695 * xcan_start_xmit - Starts the transmission
696 * @skb: sk_buff pointer that contains data to be Txed
697 * @ndev: Pointer to net_device structure
699 * This function is invoked from upper layers to initiate transmission.
701 * Return: NETDEV_TX_OK on success and NETDEV_TX_BUSY when the tx queue is full
703 static netdev_tx_t xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
705 struct xcan_priv *priv = netdev_priv(ndev);
708 if (can_dropped_invalid_skb(ndev, skb))
711 if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES)
712 ret = xcan_start_xmit_mailbox(skb, ndev);
714 ret = xcan_start_xmit_fifo(skb, ndev);
717 netdev_err(ndev, "BUG!, TX full when queue awake!\n");
718 netif_stop_queue(ndev);
719 return NETDEV_TX_BUSY;
726 * xcan_rx - Is called from CAN isr to complete the received
728 * @ndev: Pointer to net_device structure
729 * @frame_base: Register offset to the frame to be read
731 * This function is invoked from the CAN isr(poll) to process the Rx frames. It
732 * does minimal processing and invokes "netif_receive_skb" to complete further
734 * Return: 1 on success and 0 on failure.
736 static int xcan_rx(struct net_device *ndev, int frame_base)
738 struct xcan_priv *priv = netdev_priv(ndev);
739 struct net_device_stats *stats = &ndev->stats;
740 struct can_frame *cf;
742 u32 id_xcan, dlc, data[2] = {0, 0};
744 skb = alloc_can_skb(ndev, &cf);
745 if (unlikely(!skb)) {
750 /* Read a frame from Xilinx zynq CANPS */
751 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base));
752 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >>
755 /* Change Xilinx CAN data length format to socketCAN data format */
756 cf->can_dlc = get_can_dlc(dlc);
758 /* Change Xilinx CAN ID format to socketCAN ID format */
759 if (id_xcan & XCAN_IDR_IDE_MASK) {
760 /* The received frame is an Extended format frame */
761 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
762 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
764 cf->can_id |= CAN_EFF_FLAG;
765 if (id_xcan & XCAN_IDR_RTR_MASK)
766 cf->can_id |= CAN_RTR_FLAG;
768 /* The received frame is a standard format frame */
769 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
771 if (id_xcan & XCAN_IDR_SRR_MASK)
772 cf->can_id |= CAN_RTR_FLAG;
775 /* DW1/DW2 must always be read to remove message from RXFIFO */
776 data[0] = priv->read_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_base));
777 data[1] = priv->read_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_base));
779 if (!(cf->can_id & CAN_RTR_FLAG)) {
780 /* Change Xilinx CAN data format to socketCAN data format */
782 *(__be32 *)(cf->data) = cpu_to_be32(data[0]);
784 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]);
787 stats->rx_bytes += cf->can_dlc;
789 netif_receive_skb(skb);
795 * xcanfd_rx - Is called from CAN isr to complete the received
797 * @ndev: Pointer to net_device structure
798 * @frame_base: Register offset to the frame to be read
800 * This function is invoked from the CAN isr(poll) to process the Rx frames. It
801 * does minimal processing and invokes "netif_receive_skb" to complete further
803 * Return: 1 on success and 0 on failure.
805 static int xcanfd_rx(struct net_device *ndev, int frame_base)
807 struct xcan_priv *priv = netdev_priv(ndev);
808 struct net_device_stats *stats = &ndev->stats;
809 struct canfd_frame *cf;
811 u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, dw_offset;
813 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base));
814 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base));
815 if (dlc & XCAN_DLCR_EDL_MASK)
816 skb = alloc_canfd_skb(ndev, &cf);
818 skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
820 if (unlikely(!skb)) {
825 /* Change Xilinx CANFD data length format to socketCAN data
828 if (dlc & XCAN_DLCR_EDL_MASK)
829 cf->len = can_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >>
830 XCAN_DLCR_DLC_SHIFT);
832 cf->len = get_can_dlc((dlc & XCAN_DLCR_DLC_MASK) >>
833 XCAN_DLCR_DLC_SHIFT);
835 /* Change Xilinx CAN ID format to socketCAN ID format */
836 if (id_xcan & XCAN_IDR_IDE_MASK) {
837 /* The received frame is an Extended format frame */
838 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
839 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
841 cf->can_id |= CAN_EFF_FLAG;
842 if (id_xcan & XCAN_IDR_RTR_MASK)
843 cf->can_id |= CAN_RTR_FLAG;
845 /* The received frame is a standard format frame */
846 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
848 if (!(dlc & XCAN_DLCR_EDL_MASK) && (id_xcan &
850 cf->can_id |= CAN_RTR_FLAG;
853 /* Check the frame received is FD or not*/
854 if (dlc & XCAN_DLCR_EDL_MASK) {
855 for (i = 0; i < cf->len; i += 4) {
856 dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base) +
857 (dwindex * XCANFD_DW_BYTES);
858 data[0] = priv->read_reg(priv, dw_offset);
859 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);
863 for (i = 0; i < cf->len; i += 4) {
864 dw_offset = XCANFD_FRAME_DW_OFFSET(frame_base);
865 data[0] = priv->read_reg(priv, dw_offset + i);
866 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]);
869 stats->rx_bytes += cf->len;
871 netif_receive_skb(skb);
877 * xcan_current_error_state - Get current error state from HW
878 * @ndev: Pointer to net_device structure
880 * Checks the current CAN error state from the HW. Note that this
881 * only checks for ERROR_PASSIVE and ERROR_WARNING.
884 * ERROR_PASSIVE or ERROR_WARNING if either is active, ERROR_ACTIVE
887 static enum can_state xcan_current_error_state(struct net_device *ndev)
889 struct xcan_priv *priv = netdev_priv(ndev);
890 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET);
892 if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK)
893 return CAN_STATE_ERROR_PASSIVE;
894 else if (status & XCAN_SR_ERRWRN_MASK)
895 return CAN_STATE_ERROR_WARNING;
897 return CAN_STATE_ERROR_ACTIVE;
901 * xcan_set_error_state - Set new CAN error state
902 * @ndev: Pointer to net_device structure
903 * @new_state: The new CAN state to be set
904 * @cf: Error frame to be populated or NULL
906 * Set new CAN error state for the device, updating statistics and
907 * populating the error frame if given.
909 static void xcan_set_error_state(struct net_device *ndev,
910 enum can_state new_state,
911 struct can_frame *cf)
913 struct xcan_priv *priv = netdev_priv(ndev);
914 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET);
915 u32 txerr = ecr & XCAN_ECR_TEC_MASK;
916 u32 rxerr = (ecr & XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT;
917 enum can_state tx_state = txerr >= rxerr ? new_state : 0;
918 enum can_state rx_state = txerr <= rxerr ? new_state : 0;
920 /* non-ERROR states are handled elsewhere */
921 if (WARN_ON(new_state > CAN_STATE_ERROR_PASSIVE))
924 can_change_state(ndev, cf, tx_state, rx_state);
933 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX
934 * @ndev: Pointer to net_device structure
936 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if
937 * the performed RX/TX has caused it to drop to a lesser state and set
938 * the interface state accordingly.
940 static void xcan_update_error_state_after_rxtx(struct net_device *ndev)
942 struct xcan_priv *priv = netdev_priv(ndev);
943 enum can_state old_state = priv->can.state;
944 enum can_state new_state;
946 /* changing error state due to successful frame RX/TX can only
947 * occur from these states
949 if (old_state != CAN_STATE_ERROR_WARNING &&
950 old_state != CAN_STATE_ERROR_PASSIVE)
953 new_state = xcan_current_error_state(ndev);
955 if (new_state != old_state) {
957 struct can_frame *cf;
959 skb = alloc_can_err_skb(ndev, &cf);
961 xcan_set_error_state(ndev, new_state, skb ? cf : NULL);
964 struct net_device_stats *stats = &ndev->stats;
967 stats->rx_bytes += cf->can_dlc;
974 * xcan_err_interrupt - error frame Isr
975 * @ndev: net_device pointer
976 * @isr: interrupt status register value
978 * This is the CAN error interrupt and it will
979 * check the the type of error and forward the error
980 * frame to upper layers.
982 static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
984 struct xcan_priv *priv = netdev_priv(ndev);
985 struct net_device_stats *stats = &ndev->stats;
986 struct can_frame *cf;
990 skb = alloc_can_err_skb(ndev, &cf);
992 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
993 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
995 if (isr & XCAN_IXR_BSOFF_MASK) {
996 priv->can.state = CAN_STATE_BUS_OFF;
997 priv->can.can_stats.bus_off++;
998 /* Leave device in Config Mode in bus-off state */
999 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
1002 cf->can_id |= CAN_ERR_BUSOFF;
1004 enum can_state new_state = xcan_current_error_state(ndev);
1006 if (new_state != priv->can.state)
1007 xcan_set_error_state(ndev, new_state, skb ? cf : NULL);
1010 /* Check for Arbitration lost interrupt */
1011 if (isr & XCAN_IXR_ARBLST_MASK) {
1012 priv->can.can_stats.arbitration_lost++;
1014 cf->can_id |= CAN_ERR_LOSTARB;
1015 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
1019 /* Check for RX FIFO Overflow interrupt */
1020 if (isr & XCAN_IXR_RXOFLW_MASK) {
1021 stats->rx_over_errors++;
1024 cf->can_id |= CAN_ERR_CRTL;
1025 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
1029 /* Check for RX Match Not Finished interrupt */
1030 if (isr & XCAN_IXR_RXMNF_MASK) {
1031 stats->rx_dropped++;
1033 netdev_err(ndev, "RX match not finished, frame discarded\n");
1035 cf->can_id |= CAN_ERR_CRTL;
1036 cf->data[1] |= CAN_ERR_CRTL_UNSPEC;
1040 /* Check for error interrupt */
1041 if (isr & XCAN_IXR_ERROR_MASK) {
1043 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1045 /* Check for Ack error interrupt */
1046 if (err_status & XCAN_ESR_ACKER_MASK) {
1049 cf->can_id |= CAN_ERR_ACK;
1050 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
1054 /* Check for Bit error interrupt */
1055 if (err_status & XCAN_ESR_BERR_MASK) {
1058 cf->can_id |= CAN_ERR_PROT;
1059 cf->data[2] = CAN_ERR_PROT_BIT;
1063 /* Check for Stuff error interrupt */
1064 if (err_status & XCAN_ESR_STER_MASK) {
1067 cf->can_id |= CAN_ERR_PROT;
1068 cf->data[2] = CAN_ERR_PROT_STUFF;
1072 /* Check for Form error interrupt */
1073 if (err_status & XCAN_ESR_FMER_MASK) {
1076 cf->can_id |= CAN_ERR_PROT;
1077 cf->data[2] = CAN_ERR_PROT_FORM;
1081 /* Check for CRC error interrupt */
1082 if (err_status & XCAN_ESR_CRCER_MASK) {
1085 cf->can_id |= CAN_ERR_PROT;
1086 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
1089 priv->can.can_stats.bus_error++;
1093 stats->rx_packets++;
1094 stats->rx_bytes += cf->can_dlc;
1098 netdev_dbg(ndev, "%s: error status register:0x%x\n",
1099 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
1103 * xcan_state_interrupt - It will check the state of the CAN device
1104 * @ndev: net_device pointer
1105 * @isr: interrupt status register value
1107 * This will checks the state of the CAN device
1108 * and puts the device into appropriate state.
1110 static void xcan_state_interrupt(struct net_device *ndev, u32 isr)
1112 struct xcan_priv *priv = netdev_priv(ndev);
1114 /* Check for Sleep interrupt if set put CAN device in sleep state */
1115 if (isr & XCAN_IXR_SLP_MASK)
1116 priv->can.state = CAN_STATE_SLEEPING;
1118 /* Check for Wake up interrupt if set put CAN device in Active state */
1119 if (isr & XCAN_IXR_WKUP_MASK)
1120 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1124 * xcan_rx_fifo_get_next_frame - Get register offset of next RX frame
1125 * @priv: Driver private data structure
1127 * Return: Register offset of the next frame in RX FIFO.
1129 static int xcan_rx_fifo_get_next_frame(struct xcan_priv *priv)
1133 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) {
1136 /* clear RXOK before the is-empty check so that any newly
1137 * received frame will reassert it without a race
1139 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOK_MASK);
1141 fsr = priv->read_reg(priv, XCAN_FSR_OFFSET);
1143 /* check if RX FIFO is empty */
1144 if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
1145 mask = XCAN_2_FSR_FL_MASK;
1147 mask = XCAN_FSR_FL_MASK;
1152 if (priv->devtype.flags & XCAN_FLAG_CANFD_2)
1154 XCAN_RXMSG_2_FRAME_OFFSET(fsr & XCAN_2_FSR_RI_MASK);
1157 XCAN_RXMSG_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK);
1160 /* check if RX FIFO is empty */
1161 if (!(priv->read_reg(priv, XCAN_ISR_OFFSET) &
1162 XCAN_IXR_RXNEMP_MASK))
1165 /* frames are read from a static offset */
1166 offset = XCAN_RXFIFO_OFFSET;
1173 * xcan_rx_poll - Poll routine for rx packets (NAPI)
1174 * @napi: napi structure pointer
1175 * @quota: Max number of rx packets to be processed.
1177 * This is the poll routine for rx part.
1178 * It will process the packets maximux quota value.
1180 * Return: number of packets received
1182 static int xcan_rx_poll(struct napi_struct *napi, int quota)
1184 struct net_device *ndev = napi->dev;
1185 struct xcan_priv *priv = netdev_priv(ndev);
1190 while ((frame_offset = xcan_rx_fifo_get_next_frame(priv)) >= 0 &&
1191 (work_done < quota)) {
1192 if (xcan_rx_int_mask(priv) & XCAN_IXR_RXOK_MASK)
1193 work_done += xcanfd_rx(ndev, frame_offset);
1195 work_done += xcan_rx(ndev, frame_offset);
1197 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI)
1198 /* increment read index */
1199 priv->write_reg(priv, XCAN_FSR_OFFSET,
1202 /* clear rx-not-empty (will actually clear only if
1205 priv->write_reg(priv, XCAN_ICR_OFFSET,
1206 XCAN_IXR_RXNEMP_MASK);
1210 can_led_event(ndev, CAN_LED_EVENT_RX);
1211 xcan_update_error_state_after_rxtx(ndev);
1214 if (work_done < quota) {
1215 napi_complete_done(napi, work_done);
1216 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
1217 ier |= xcan_rx_int_mask(priv);
1218 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
1224 * xcan_tx_interrupt - Tx Done Isr
1225 * @ndev: net_device pointer
1226 * @isr: Interrupt status register value
1228 static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
1230 struct xcan_priv *priv = netdev_priv(ndev);
1231 struct net_device_stats *stats = &ndev->stats;
1232 unsigned int frames_in_fifo;
1233 int frames_sent = 1; /* TXOK => at least 1 frame was sent */
1234 unsigned long flags;
1237 /* Synchronize with xmit as we need to know the exact number
1238 * of frames in the FIFO to stay in sync due to the TXFEMP
1240 * This also prevents a race between netif_wake_queue() and
1241 * netif_stop_queue().
1243 spin_lock_irqsave(&priv->tx_lock, flags);
1245 frames_in_fifo = priv->tx_head - priv->tx_tail;
1247 if (WARN_ON_ONCE(frames_in_fifo == 0)) {
1248 /* clear TXOK anyway to avoid getting back here */
1249 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
1250 spin_unlock_irqrestore(&priv->tx_lock, flags);
1254 /* Check if 2 frames were sent (TXOK only means that at least 1
1257 if (frames_in_fifo > 1) {
1258 WARN_ON(frames_in_fifo > priv->tx_max);
1260 /* Synchronize TXOK and isr so that after the loop:
1261 * (1) isr variable is up-to-date at least up to TXOK clear
1262 * time. This avoids us clearing a TXOK of a second frame
1263 * but not noticing that the FIFO is now empty and thus
1264 * marking only a single frame as sent.
1265 * (2) No TXOK is left. Having one could mean leaving a
1266 * stray TXOK as we might process the associated frame
1267 * via TXFEMP handling as we read TXFEMP *after* TXOK
1268 * clear to satisfy (1).
1270 while ((isr & XCAN_IXR_TXOK_MASK) &&
1271 !WARN_ON(++retries == 100)) {
1272 priv->write_reg(priv, XCAN_ICR_OFFSET,
1273 XCAN_IXR_TXOK_MASK);
1274 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
1277 if (isr & XCAN_IXR_TXFEMP_MASK) {
1278 /* nothing in FIFO anymore */
1279 frames_sent = frames_in_fifo;
1282 /* single frame in fifo, just clear TXOK */
1283 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
1286 while (frames_sent--) {
1287 stats->tx_bytes += can_get_echo_skb(ndev, priv->tx_tail %
1290 stats->tx_packets++;
1293 netif_wake_queue(ndev);
1295 spin_unlock_irqrestore(&priv->tx_lock, flags);
1297 can_led_event(ndev, CAN_LED_EVENT_TX);
1298 xcan_update_error_state_after_rxtx(ndev);
1302 * xcan_interrupt - CAN Isr
1304 * @dev_id: device id poniter
1306 * This is the xilinx CAN Isr. It checks for the type of interrupt
1307 * and invokes the corresponding ISR.
1310 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
1312 static irqreturn_t xcan_interrupt(int irq, void *dev_id)
1314 struct net_device *ndev = (struct net_device *)dev_id;
1315 struct xcan_priv *priv = netdev_priv(ndev);
1318 u32 rx_int_mask = xcan_rx_int_mask(priv);
1320 /* Get the interrupt status from Xilinx CAN */
1321 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
1325 /* Check for the type of interrupt and Processing it */
1326 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
1327 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
1328 XCAN_IXR_WKUP_MASK));
1329 xcan_state_interrupt(ndev, isr);
1332 /* Check for Tx interrupt and Processing it */
1333 if (isr & XCAN_IXR_TXOK_MASK)
1334 xcan_tx_interrupt(ndev, isr);
1336 /* Check for the type of error interrupt and Processing it */
1337 isr_errors = isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
1338 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK |
1339 XCAN_IXR_RXMNF_MASK);
1341 priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors);
1342 xcan_err_interrupt(ndev, isr);
1345 /* Check for the type of receive interrupt and Processing it */
1346 if (isr & rx_int_mask) {
1347 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
1348 ier &= ~rx_int_mask;
1349 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
1350 napi_schedule(&priv->napi);
1356 * xcan_chip_stop - Driver stop routine
1357 * @ndev: Pointer to net_device structure
1359 * This is the drivers stop routine. It will disable the
1360 * interrupts and put the device into configuration mode.
1362 static void xcan_chip_stop(struct net_device *ndev)
1364 struct xcan_priv *priv = netdev_priv(ndev);
1366 /* Disable interrupts and leave the can in configuration mode */
1367 set_reset_mode(ndev);
1368 priv->can.state = CAN_STATE_STOPPED;
1372 * xcan_open - Driver open routine
1373 * @ndev: Pointer to net_device structure
1375 * This is the driver open routine.
1376 * Return: 0 on success and failure value on error
1378 static int xcan_open(struct net_device *ndev)
1380 struct xcan_priv *priv = netdev_priv(ndev);
1383 ret = pm_runtime_get_sync(priv->dev);
1385 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
1390 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
1393 netdev_err(ndev, "irq allocation for CAN failed\n");
1397 /* Set chip into reset mode */
1398 ret = set_reset_mode(ndev);
1400 netdev_err(ndev, "mode resetting failed!\n");
1405 ret = open_candev(ndev);
1409 ret = xcan_chip_start(ndev);
1411 netdev_err(ndev, "xcan_chip_start failed!\n");
1415 can_led_event(ndev, CAN_LED_EVENT_OPEN);
1416 napi_enable(&priv->napi);
1417 netif_start_queue(ndev);
1424 free_irq(ndev->irq, ndev);
1426 pm_runtime_put(priv->dev);
1432 * xcan_close - Driver close routine
1433 * @ndev: Pointer to net_device structure
1437 static int xcan_close(struct net_device *ndev)
1439 struct xcan_priv *priv = netdev_priv(ndev);
1441 netif_stop_queue(ndev);
1442 napi_disable(&priv->napi);
1443 xcan_chip_stop(ndev);
1444 free_irq(ndev->irq, ndev);
1447 can_led_event(ndev, CAN_LED_EVENT_STOP);
1448 pm_runtime_put(priv->dev);
1454 * xcan_get_berr_counter - error counter routine
1455 * @ndev: Pointer to net_device structure
1456 * @bec: Pointer to can_berr_counter structure
1458 * This is the driver error counter routine.
1459 * Return: 0 on success and failure value on error
1461 static int xcan_get_berr_counter(const struct net_device *ndev,
1462 struct can_berr_counter *bec)
1464 struct xcan_priv *priv = netdev_priv(ndev);
1467 ret = pm_runtime_get_sync(priv->dev);
1469 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
1474 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
1475 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
1476 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
1478 pm_runtime_put(priv->dev);
1483 static const struct net_device_ops xcan_netdev_ops = {
1484 .ndo_open = xcan_open,
1485 .ndo_stop = xcan_close,
1486 .ndo_start_xmit = xcan_start_xmit,
1487 .ndo_change_mtu = can_change_mtu,
1491 * xcan_suspend - Suspend method for the driver
1492 * @dev: Address of the device structure
1494 * Put the driver into low power mode.
1495 * Return: 0 on success and failure value on error
1497 static int __maybe_unused xcan_suspend(struct device *dev)
1499 struct net_device *ndev = dev_get_drvdata(dev);
1501 if (netif_running(ndev)) {
1502 netif_stop_queue(ndev);
1503 netif_device_detach(ndev);
1504 xcan_chip_stop(ndev);
1507 return pm_runtime_force_suspend(dev);
1511 * xcan_resume - Resume from suspend
1512 * @dev: Address of the device structure
1514 * Resume operation after suspend.
1515 * Return: 0 on success and failure value on error
1517 static int __maybe_unused xcan_resume(struct device *dev)
1519 struct net_device *ndev = dev_get_drvdata(dev);
1522 ret = pm_runtime_force_resume(dev);
1524 dev_err(dev, "pm_runtime_force_resume failed on resume\n");
1528 if (netif_running(ndev)) {
1529 ret = xcan_chip_start(ndev);
1531 dev_err(dev, "xcan_chip_start failed on resume\n");
1535 netif_device_attach(ndev);
1536 netif_start_queue(ndev);
1543 * xcan_runtime_suspend - Runtime suspend method for the driver
1544 * @dev: Address of the device structure
1546 * Put the driver into low power mode.
1549 static int __maybe_unused xcan_runtime_suspend(struct device *dev)
1551 struct net_device *ndev = dev_get_drvdata(dev);
1552 struct xcan_priv *priv = netdev_priv(ndev);
1554 clk_disable_unprepare(priv->bus_clk);
1555 clk_disable_unprepare(priv->can_clk);
1561 * xcan_runtime_resume - Runtime resume from suspend
1562 * @dev: Address of the device structure
1564 * Resume operation after suspend.
1565 * Return: 0 on success and failure value on error
1567 static int __maybe_unused xcan_runtime_resume(struct device *dev)
1569 struct net_device *ndev = dev_get_drvdata(dev);
1570 struct xcan_priv *priv = netdev_priv(ndev);
1573 ret = clk_prepare_enable(priv->bus_clk);
1575 dev_err(dev, "Cannot enable clock.\n");
1578 ret = clk_prepare_enable(priv->can_clk);
1580 dev_err(dev, "Cannot enable clock.\n");
1581 clk_disable_unprepare(priv->bus_clk);
1588 static const struct dev_pm_ops xcan_dev_pm_ops = {
1589 SET_SYSTEM_SLEEP_PM_OPS(xcan_suspend, xcan_resume)
1590 SET_RUNTIME_PM_OPS(xcan_runtime_suspend, xcan_runtime_resume, NULL)
1593 static const struct xcan_devtype_data xcan_zynq_data = {
1594 .cantype = XZYNQ_CANPS,
1595 .flags = XCAN_FLAG_TXFEMP,
1596 .bittiming_const = &xcan_bittiming_const,
1597 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT,
1598 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT,
1599 .bus_clk_name = "pclk",
1602 static const struct xcan_devtype_data xcan_axi_data = {
1603 .cantype = XAXI_CAN,
1604 .bittiming_const = &xcan_bittiming_const,
1605 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT,
1606 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT,
1607 .bus_clk_name = "s_axi_aclk",
1610 static const struct xcan_devtype_data xcan_canfd_data = {
1611 .cantype = XAXI_CANFD,
1612 .flags = XCAN_FLAG_EXT_FILTERS |
1614 XCAN_FLAG_TX_MAILBOXES |
1615 XCAN_FLAG_RX_FIFO_MULTI,
1616 .bittiming_const = &xcan_bittiming_const_canfd,
1617 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT_CANFD,
1618 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT_CANFD,
1619 .bus_clk_name = "s_axi_aclk",
1622 static const struct xcan_devtype_data xcan_canfd2_data = {
1623 .cantype = XAXI_CANFD_2_0,
1624 .flags = XCAN_FLAG_EXT_FILTERS |
1626 XCAN_FLAG_TX_MAILBOXES |
1628 XCAN_FLAG_RX_FIFO_MULTI,
1629 .bittiming_const = &xcan_bittiming_const_canfd2,
1630 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT_CANFD,
1631 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT_CANFD,
1632 .bus_clk_name = "s_axi_aclk",
1635 /* Match table for OF platform binding */
1636 static const struct of_device_id xcan_of_match[] = {
1637 { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data },
1638 { .compatible = "xlnx,axi-can-1.00.a", .data = &xcan_axi_data },
1639 { .compatible = "xlnx,canfd-1.0", .data = &xcan_canfd_data },
1640 { .compatible = "xlnx,canfd-2.0", .data = &xcan_canfd2_data },
1641 { /* end of list */ },
1643 MODULE_DEVICE_TABLE(of, xcan_of_match);
1646 * xcan_probe - Platform registration call
1647 * @pdev: Handle to the platform device structure
1649 * This function does all the memory allocation and registration for the CAN
1652 * Return: 0 on success and failure value on error
1654 static int xcan_probe(struct platform_device *pdev)
1656 struct resource *res; /* IO mem resources */
1657 struct net_device *ndev;
1658 struct xcan_priv *priv;
1659 const struct of_device_id *of_id;
1660 const struct xcan_devtype_data *devtype = &xcan_axi_data;
1664 int hw_tx_max, hw_rx_max;
1665 const char *hw_tx_max_property;
1667 /* Get the virtual base address for the device */
1668 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1669 addr = devm_ioremap_resource(&pdev->dev, res);
1671 ret = PTR_ERR(addr);
1675 of_id = of_match_device(xcan_of_match, &pdev->dev);
1676 if (of_id && of_id->data)
1677 devtype = of_id->data;
1679 hw_tx_max_property = devtype->flags & XCAN_FLAG_TX_MAILBOXES ?
1680 "tx-mailbox-count" : "tx-fifo-depth";
1682 ret = of_property_read_u32(pdev->dev.of_node, hw_tx_max_property,
1685 dev_err(&pdev->dev, "missing %s property\n",
1686 hw_tx_max_property);
1690 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1694 "missing rx-fifo-depth property (mailbox mode is not supported)\n");
1700 * There is no way to directly figure out how many frames have been
1701 * sent when the TXOK interrupt is processed. If TXFEMP
1702 * is supported, we can have 2 frames in the FIFO and use TXFEMP
1703 * to determine if 1 or 2 frames have been sent.
1704 * Theoretically we should be able to use TXFWMEMP to determine up
1705 * to 3 frames, but it seems that after putting a second frame in the
1706 * FIFO, with watermark at 2 frames, it can happen that TXFWMEMP (less
1707 * than 2 frames in FIFO) is set anyway with no TXOK (a frame was
1708 * sent), which is not a sensible state - possibly TXFWMEMP is not
1709 * completely synchronized with the rest of the bits?
1711 * With TX mailboxes:
1713 * HW sends frames in CAN ID priority order. To preserve FIFO ordering
1714 * we submit frames one at a time.
1716 if (!(devtype->flags & XCAN_FLAG_TX_MAILBOXES) &&
1717 (devtype->flags & XCAN_FLAG_TXFEMP))
1718 tx_max = min(hw_tx_max, 2);
1724 /* Create a CAN device instance */
1725 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
1729 priv = netdev_priv(ndev);
1730 priv->dev = &pdev->dev;
1731 priv->can.bittiming_const = devtype->bittiming_const;
1732 priv->can.do_set_mode = xcan_do_set_mode;
1733 priv->can.do_get_berr_counter = xcan_get_berr_counter;
1734 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1735 CAN_CTRLMODE_BERR_REPORTING;
1737 if (devtype->cantype == XAXI_CANFD)
1738 priv->can.data_bittiming_const =
1739 &xcan_data_bittiming_const_canfd;
1741 if (devtype->cantype == XAXI_CANFD_2_0)
1742 priv->can.data_bittiming_const =
1743 &xcan_data_bittiming_const_canfd2;
1745 if (devtype->cantype == XAXI_CANFD ||
1746 devtype->cantype == XAXI_CANFD_2_0)
1747 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD;
1749 priv->reg_base = addr;
1750 priv->tx_max = tx_max;
1751 priv->devtype = *devtype;
1752 spin_lock_init(&priv->tx_lock);
1754 /* Get IRQ for the device */
1755 ndev->irq = platform_get_irq(pdev, 0);
1756 ndev->flags |= IFF_ECHO; /* We support local echo */
1758 platform_set_drvdata(pdev, ndev);
1759 SET_NETDEV_DEV(ndev, &pdev->dev);
1760 ndev->netdev_ops = &xcan_netdev_ops;
1762 /* Getting the CAN can_clk info */
1763 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1764 if (IS_ERR(priv->can_clk)) {
1765 if (PTR_ERR(priv->can_clk) != -EPROBE_DEFER)
1766 dev_err(&pdev->dev, "Device clock not found.\n");
1767 ret = PTR_ERR(priv->can_clk);
1771 priv->bus_clk = devm_clk_get(&pdev->dev, devtype->bus_clk_name);
1772 if (IS_ERR(priv->bus_clk)) {
1773 dev_err(&pdev->dev, "bus clock not found\n");
1774 ret = PTR_ERR(priv->bus_clk);
1778 priv->write_reg = xcan_write_reg_le;
1779 priv->read_reg = xcan_read_reg_le;
1781 pm_runtime_enable(&pdev->dev);
1782 ret = pm_runtime_get_sync(&pdev->dev);
1784 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
1789 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
1790 priv->write_reg = xcan_write_reg_be;
1791 priv->read_reg = xcan_read_reg_be;
1794 priv->can.clock.freq = clk_get_rate(priv->can_clk);
1796 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max);
1798 ret = register_candev(ndev);
1800 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret);
1801 goto err_disableclks;
1804 devm_can_led_init(ndev);
1806 pm_runtime_put(&pdev->dev);
1808 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) {
1809 priv->write_reg(priv, XCAN_AFR_2_ID_OFFSET, 0x00000000);
1810 priv->write_reg(priv, XCAN_AFR_2_MASK_OFFSET, 0x00000000);
1813 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx buffers: actual %d, using %d\n",
1814 priv->reg_base, ndev->irq, priv->can.clock.freq,
1815 hw_tx_max, priv->tx_max);
1820 pm_runtime_put(priv->dev);
1822 pm_runtime_disable(&pdev->dev);
1830 * xcan_remove - Unregister the device after releasing the resources
1831 * @pdev: Handle to the platform device structure
1833 * This function frees all the resources allocated to the device.
1836 static int xcan_remove(struct platform_device *pdev)
1838 struct net_device *ndev = platform_get_drvdata(pdev);
1839 struct xcan_priv *priv = netdev_priv(ndev);
1841 unregister_candev(ndev);
1842 pm_runtime_disable(&pdev->dev);
1843 netif_napi_del(&priv->napi);
1849 static struct platform_driver xcan_driver = {
1850 .probe = xcan_probe,
1851 .remove = xcan_remove,
1853 .name = DRIVER_NAME,
1854 .pm = &xcan_dev_pm_ops,
1855 .of_match_table = xcan_of_match,
1859 module_platform_driver(xcan_driver);
1861 MODULE_LICENSE("GPL");
1862 MODULE_AUTHOR("Xilinx Inc");
1863 MODULE_DESCRIPTION("Xilinx CAN interface");