1 // SPDX-License-Identifier: GPL-2.0
2 // CAN bus driver for Bosch M_CAN controller
3 // Copyright (C) 2014 Freescale Semiconductor, Inc.
4 // Dong Aisheng <b29396@freescale.com>
5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
7 /* Bosch M_CAN user manual can be obtained from:
8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9 * mcan_users_manual_v302.pdf
12 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/iopoll.h>
22 #include <linux/can/dev.h>
23 #include <linux/pinctrl/consumer.h>
27 /* registers definition */
43 /* TDCR Register only available for version >=3.1.x */
80 #define M_CAN_NAPI_WEIGHT 64
82 /* message ram configuration data length */
83 #define MRAM_CFG_LEN 8
85 /* Core Release Register (CREL) */
86 #define CREL_REL_SHIFT 28
87 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT)
88 #define CREL_STEP_SHIFT 24
89 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT)
90 #define CREL_SUBSTEP_SHIFT 20
91 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT)
93 /* Data Bit Timing & Prescaler Register (DBTP) */
94 #define DBTP_TDC BIT(23)
95 #define DBTP_DBRP_SHIFT 16
96 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT)
97 #define DBTP_DTSEG1_SHIFT 8
98 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
99 #define DBTP_DTSEG2_SHIFT 4
100 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
101 #define DBTP_DSJW_SHIFT 0
102 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
104 /* Transmitter Delay Compensation Register (TDCR) */
105 #define TDCR_TDCO_SHIFT 8
106 #define TDCR_TDCO_MASK (0x7F << TDCR_TDCO_SHIFT)
107 #define TDCR_TDCF_SHIFT 0
108 #define TDCR_TDCF_MASK (0x7F << TDCR_TDCF_SHIFT)
110 /* Test Register (TEST) */
111 #define TEST_LBCK BIT(4)
113 /* CC Control Register(CCCR) */
114 #define CCCR_CMR_MASK 0x3
115 #define CCCR_CMR_SHIFT 10
116 #define CCCR_CMR_CANFD 0x1
117 #define CCCR_CMR_CANFD_BRS 0x2
118 #define CCCR_CMR_CAN 0x3
119 #define CCCR_CME_MASK 0x3
120 #define CCCR_CME_SHIFT 8
121 #define CCCR_CME_CAN 0
122 #define CCCR_CME_CANFD 0x1
123 #define CCCR_CME_CANFD_BRS 0x2
124 #define CCCR_TXP BIT(14)
125 #define CCCR_TEST BIT(7)
126 #define CCCR_MON BIT(5)
127 #define CCCR_CSR BIT(4)
128 #define CCCR_CSA BIT(3)
129 #define CCCR_ASM BIT(2)
130 #define CCCR_CCE BIT(1)
131 #define CCCR_INIT BIT(0)
132 #define CCCR_CANFD 0x10
133 /* for version >=3.1.x */
134 #define CCCR_EFBI BIT(13)
135 #define CCCR_PXHD BIT(12)
136 #define CCCR_BRSE BIT(9)
137 #define CCCR_FDOE BIT(8)
138 /* only for version >=3.2.x */
139 #define CCCR_NISO BIT(15)
141 /* Nominal Bit Timing & Prescaler Register (NBTP) */
142 #define NBTP_NSJW_SHIFT 25
143 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
144 #define NBTP_NBRP_SHIFT 16
145 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT)
146 #define NBTP_NTSEG1_SHIFT 8
147 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT)
148 #define NBTP_NTSEG2_SHIFT 0
149 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
151 /* Error Counter Register(ECR) */
152 #define ECR_RP BIT(15)
153 #define ECR_REC_SHIFT 8
154 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
155 #define ECR_TEC_SHIFT 0
156 #define ECR_TEC_MASK 0xff
158 /* Protocol Status Register(PSR) */
159 #define PSR_BO BIT(7)
160 #define PSR_EW BIT(6)
161 #define PSR_EP BIT(5)
162 #define PSR_LEC_MASK 0x7
164 /* Interrupt Register(IR) */
165 #define IR_ALL_INT 0xffffffff
167 /* Renamed bits for versions > 3.1.x */
168 #define IR_ARA BIT(29)
169 #define IR_PED BIT(28)
170 #define IR_PEA BIT(27)
172 /* Bits for version 3.0.x */
173 #define IR_STE BIT(31)
174 #define IR_FOE BIT(30)
175 #define IR_ACKE BIT(29)
176 #define IR_BE BIT(28)
177 #define IR_CRCE BIT(27)
178 #define IR_WDI BIT(26)
179 #define IR_BO BIT(25)
180 #define IR_EW BIT(24)
181 #define IR_EP BIT(23)
182 #define IR_ELO BIT(22)
183 #define IR_BEU BIT(21)
184 #define IR_BEC BIT(20)
185 #define IR_DRX BIT(19)
186 #define IR_TOO BIT(18)
187 #define IR_MRAF BIT(17)
188 #define IR_TSW BIT(16)
189 #define IR_TEFL BIT(15)
190 #define IR_TEFF BIT(14)
191 #define IR_TEFW BIT(13)
192 #define IR_TEFN BIT(12)
193 #define IR_TFE BIT(11)
194 #define IR_TCF BIT(10)
196 #define IR_HPM BIT(8)
197 #define IR_RF1L BIT(7)
198 #define IR_RF1F BIT(6)
199 #define IR_RF1W BIT(5)
200 #define IR_RF1N BIT(4)
201 #define IR_RF0L BIT(3)
202 #define IR_RF0F BIT(2)
203 #define IR_RF0W BIT(1)
204 #define IR_RF0N BIT(0)
205 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
207 /* Interrupts for version 3.0.x */
208 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
209 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \
210 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
212 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
213 /* Interrupts for version >= 3.1.x */
214 #define IR_ERR_LEC_31X (IR_PED | IR_PEA)
215 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
216 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
218 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
220 /* Interrupt Line Select (ILS) */
221 #define ILS_ALL_INT0 0x0
222 #define ILS_ALL_INT1 0xFFFFFFFF
224 /* Interrupt Line Enable (ILE) */
225 #define ILE_EINT1 BIT(1)
226 #define ILE_EINT0 BIT(0)
228 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
229 #define RXFC_FWM_SHIFT 24
230 #define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT)
231 #define RXFC_FS_SHIFT 16
232 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT)
234 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
235 #define RXFS_RFL BIT(25)
236 #define RXFS_FF BIT(24)
237 #define RXFS_FPI_SHIFT 16
238 #define RXFS_FPI_MASK 0x3f0000
239 #define RXFS_FGI_SHIFT 8
240 #define RXFS_FGI_MASK 0x3f00
241 #define RXFS_FFL_MASK 0x7f
243 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
244 #define M_CAN_RXESC_8BYTES 0x0
245 #define M_CAN_RXESC_64BYTES 0x777
247 /* Tx Buffer Configuration(TXBC) */
248 #define TXBC_NDTB_SHIFT 16
249 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT)
250 #define TXBC_TFQS_SHIFT 24
251 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT)
253 /* Tx FIFO/Queue Status (TXFQS) */
254 #define TXFQS_TFQF BIT(21)
255 #define TXFQS_TFQPI_SHIFT 16
256 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT)
257 #define TXFQS_TFGI_SHIFT 8
258 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT)
259 #define TXFQS_TFFL_SHIFT 0
260 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT)
262 /* Tx Buffer Element Size Configuration(TXESC) */
263 #define TXESC_TBDS_8BYTES 0x0
264 #define TXESC_TBDS_64BYTES 0x7
266 /* Tx Event FIFO Configuration (TXEFC) */
267 #define TXEFC_EFS_SHIFT 16
268 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT)
270 /* Tx Event FIFO Status (TXEFS) */
271 #define TXEFS_TEFL BIT(25)
272 #define TXEFS_EFF BIT(24)
273 #define TXEFS_EFGI_SHIFT 8
274 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT)
275 #define TXEFS_EFFL_SHIFT 0
276 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT)
278 /* Tx Event FIFO Acknowledge (TXEFA) */
279 #define TXEFA_EFAI_SHIFT 0
280 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT)
282 /* Message RAM Configuration (in bytes) */
283 #define SIDF_ELEMENT_SIZE 4
284 #define XIDF_ELEMENT_SIZE 8
285 #define RXF0_ELEMENT_SIZE 72
286 #define RXF1_ELEMENT_SIZE 72
287 #define RXB_ELEMENT_SIZE 72
288 #define TXE_ELEMENT_SIZE 8
289 #define TXB_ELEMENT_SIZE 72
291 /* Message RAM Elements */
292 #define M_CAN_FIFO_ID 0x0
293 #define M_CAN_FIFO_DLC 0x4
294 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2))
296 /* Rx Buffer Element */
298 #define RX_BUF_ESI BIT(31)
299 #define RX_BUF_XTD BIT(30)
300 #define RX_BUF_RTR BIT(29)
302 #define RX_BUF_ANMF BIT(31)
303 #define RX_BUF_FDF BIT(21)
304 #define RX_BUF_BRS BIT(20)
306 /* Tx Buffer Element */
308 #define TX_BUF_ESI BIT(31)
309 #define TX_BUF_XTD BIT(30)
310 #define TX_BUF_RTR BIT(29)
312 #define TX_BUF_EFC BIT(23)
313 #define TX_BUF_FDF BIT(21)
314 #define TX_BUF_BRS BIT(20)
315 #define TX_BUF_MM_SHIFT 24
316 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
318 /* Tx event FIFO Element */
320 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
321 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
323 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)
325 return cdev->ops->read_reg(cdev, reg);
328 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,
331 cdev->ops->write_reg(cdev, reg, val);
334 static u32 m_can_fifo_read(struct m_can_classdev *cdev,
335 u32 fgi, unsigned int offset)
337 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
340 return cdev->ops->read_fifo(cdev, addr_offset);
343 static void m_can_fifo_write(struct m_can_classdev *cdev,
344 u32 fpi, unsigned int offset, u32 val)
346 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
349 cdev->ops->write_fifo(cdev, addr_offset, val);
352 static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev,
355 cdev->ops->write_fifo(cdev, fpi, val);
358 static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset)
360 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
363 return cdev->ops->read_fifo(cdev, addr_offset);
366 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev)
368 return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF);
371 void m_can_config_endisable(struct m_can_classdev *cdev, bool enable)
373 u32 cccr = m_can_read(cdev, M_CAN_CCCR);
377 /* Clear the Clock stop request if it was set */
382 /* Clear the Clock stop request if it was set */
386 /* enable m_can configuration */
387 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT);
389 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
390 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
392 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
395 /* there's a delay for module initialization */
397 val = CCCR_INIT | CCCR_CCE;
399 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
401 netdev_warn(cdev->net, "Failed to init module\n");
409 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev)
411 /* Only interrupt line 0 is used in this driver */
412 m_can_write(cdev, M_CAN_ILE, ILE_EINT0);
415 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev)
417 m_can_write(cdev, M_CAN_ILE, 0x0);
420 static void m_can_clean(struct net_device *net)
422 struct m_can_classdev *cdev = netdev_priv(net);
427 net->stats.tx_errors++;
428 if (cdev->version > 30)
429 putidx = ((m_can_read(cdev, M_CAN_TXFQS) &
430 TXFQS_TFQPI_MASK) >> TXFQS_TFQPI_SHIFT);
432 can_free_echo_skb(cdev->net, putidx);
437 static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
439 struct net_device_stats *stats = &dev->stats;
440 struct m_can_classdev *cdev = netdev_priv(dev);
441 struct canfd_frame *cf;
446 /* calculate the fifo get index for where to read data */
447 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
448 dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC);
449 if (dlc & RX_BUF_FDF)
450 skb = alloc_canfd_skb(dev, &cf);
452 skb = alloc_can_skb(dev, (struct can_frame **)&cf);
458 if (dlc & RX_BUF_FDF)
459 cf->len = can_dlc2len((dlc >> 16) & 0x0F);
461 cf->len = get_can_dlc((dlc >> 16) & 0x0F);
463 id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID);
465 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
467 cf->can_id = (id >> 18) & CAN_SFF_MASK;
469 if (id & RX_BUF_ESI) {
470 cf->flags |= CANFD_ESI;
471 netdev_dbg(dev, "ESI Error\n");
474 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) {
475 cf->can_id |= CAN_RTR_FLAG;
477 if (dlc & RX_BUF_BRS)
478 cf->flags |= CANFD_BRS;
480 for (i = 0; i < cf->len; i += 4)
481 *(u32 *)(cf->data + i) =
482 m_can_fifo_read(cdev, fgi,
483 M_CAN_FIFO_DATA(i / 4));
486 /* acknowledge rx fifo 0 */
487 m_can_write(cdev, M_CAN_RXF0A, fgi);
490 stats->rx_bytes += cf->len;
492 netif_receive_skb(skb);
495 static int m_can_do_rx_poll(struct net_device *dev, int quota)
497 struct m_can_classdev *cdev = netdev_priv(dev);
501 rxfs = m_can_read(cdev, M_CAN_RXF0S);
502 if (!(rxfs & RXFS_FFL_MASK)) {
503 netdev_dbg(dev, "no messages in fifo0\n");
507 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
509 netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
511 m_can_read_fifo(dev, rxfs);
515 rxfs = m_can_read(cdev, M_CAN_RXF0S);
519 can_led_event(dev, CAN_LED_EVENT_RX);
524 static int m_can_handle_lost_msg(struct net_device *dev)
526 struct net_device_stats *stats = &dev->stats;
528 struct can_frame *frame;
530 netdev_err(dev, "msg lost in rxf0\n");
533 stats->rx_over_errors++;
535 skb = alloc_can_err_skb(dev, &frame);
539 frame->can_id |= CAN_ERR_CRTL;
540 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
542 netif_receive_skb(skb);
547 static int m_can_handle_lec_err(struct net_device *dev,
548 enum m_can_lec_type lec_type)
550 struct m_can_classdev *cdev = netdev_priv(dev);
551 struct net_device_stats *stats = &dev->stats;
552 struct can_frame *cf;
555 cdev->can.can_stats.bus_error++;
558 /* propagate the error condition to the CAN stack */
559 skb = alloc_can_err_skb(dev, &cf);
563 /* check for 'last error code' which tells us the
564 * type of the last error to occur on the CAN bus
566 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
569 case LEC_STUFF_ERROR:
570 netdev_dbg(dev, "stuff error\n");
571 cf->data[2] |= CAN_ERR_PROT_STUFF;
574 netdev_dbg(dev, "form error\n");
575 cf->data[2] |= CAN_ERR_PROT_FORM;
578 netdev_dbg(dev, "ack error\n");
579 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
582 netdev_dbg(dev, "bit1 error\n");
583 cf->data[2] |= CAN_ERR_PROT_BIT1;
586 netdev_dbg(dev, "bit0 error\n");
587 cf->data[2] |= CAN_ERR_PROT_BIT0;
590 netdev_dbg(dev, "CRC error\n");
591 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
598 stats->rx_bytes += cf->can_dlc;
599 netif_receive_skb(skb);
604 static int __m_can_get_berr_counter(const struct net_device *dev,
605 struct can_berr_counter *bec)
607 struct m_can_classdev *cdev = netdev_priv(dev);
610 ecr = m_can_read(cdev, M_CAN_ECR);
611 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
612 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
617 static int m_can_clk_start(struct m_can_classdev *cdev)
621 if (cdev->pm_clock_support == 0)
624 err = pm_runtime_get_sync(cdev->dev);
626 pm_runtime_put_noidle(cdev->dev);
633 static void m_can_clk_stop(struct m_can_classdev *cdev)
635 if (cdev->pm_clock_support)
636 pm_runtime_put_sync(cdev->dev);
639 static int m_can_get_berr_counter(const struct net_device *dev,
640 struct can_berr_counter *bec)
642 struct m_can_classdev *cdev = netdev_priv(dev);
645 err = m_can_clk_start(cdev);
649 __m_can_get_berr_counter(dev, bec);
651 m_can_clk_stop(cdev);
656 static int m_can_handle_state_change(struct net_device *dev,
657 enum can_state new_state)
659 struct m_can_classdev *cdev = netdev_priv(dev);
660 struct net_device_stats *stats = &dev->stats;
661 struct can_frame *cf;
663 struct can_berr_counter bec;
667 case CAN_STATE_ERROR_ACTIVE:
668 /* error warning state */
669 cdev->can.can_stats.error_warning++;
670 cdev->can.state = CAN_STATE_ERROR_WARNING;
672 case CAN_STATE_ERROR_PASSIVE:
673 /* error passive state */
674 cdev->can.can_stats.error_passive++;
675 cdev->can.state = CAN_STATE_ERROR_PASSIVE;
677 case CAN_STATE_BUS_OFF:
679 cdev->can.state = CAN_STATE_BUS_OFF;
680 m_can_disable_all_interrupts(cdev);
681 cdev->can.can_stats.bus_off++;
688 /* propagate the error condition to the CAN stack */
689 skb = alloc_can_err_skb(dev, &cf);
693 __m_can_get_berr_counter(dev, &bec);
696 case CAN_STATE_ERROR_ACTIVE:
697 /* error warning state */
698 cf->can_id |= CAN_ERR_CRTL;
699 cf->data[1] = (bec.txerr > bec.rxerr) ?
700 CAN_ERR_CRTL_TX_WARNING :
701 CAN_ERR_CRTL_RX_WARNING;
702 cf->data[6] = bec.txerr;
703 cf->data[7] = bec.rxerr;
705 case CAN_STATE_ERROR_PASSIVE:
706 /* error passive state */
707 cf->can_id |= CAN_ERR_CRTL;
708 ecr = m_can_read(cdev, M_CAN_ECR);
710 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
712 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
713 cf->data[6] = bec.txerr;
714 cf->data[7] = bec.rxerr;
716 case CAN_STATE_BUS_OFF:
718 cf->can_id |= CAN_ERR_BUSOFF;
725 stats->rx_bytes += cf->can_dlc;
726 netif_receive_skb(skb);
731 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
733 struct m_can_classdev *cdev = netdev_priv(dev);
736 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) {
737 netdev_dbg(dev, "entered error warning state\n");
738 work_done += m_can_handle_state_change(dev,
739 CAN_STATE_ERROR_WARNING);
742 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) {
743 netdev_dbg(dev, "entered error passive state\n");
744 work_done += m_can_handle_state_change(dev,
745 CAN_STATE_ERROR_PASSIVE);
748 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) {
749 netdev_dbg(dev, "entered error bus off state\n");
750 work_done += m_can_handle_state_change(dev,
757 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
759 if (irqstatus & IR_WDI)
760 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
761 if (irqstatus & IR_ELO)
762 netdev_err(dev, "Error Logging Overflow\n");
763 if (irqstatus & IR_BEU)
764 netdev_err(dev, "Bit Error Uncorrected\n");
765 if (irqstatus & IR_BEC)
766 netdev_err(dev, "Bit Error Corrected\n");
767 if (irqstatus & IR_TOO)
768 netdev_err(dev, "Timeout reached\n");
769 if (irqstatus & IR_MRAF)
770 netdev_err(dev, "Message RAM access failure occurred\n");
773 static inline bool is_lec_err(u32 psr)
777 return psr && (psr != LEC_UNUSED);
780 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
783 struct m_can_classdev *cdev = netdev_priv(dev);
786 if (irqstatus & IR_RF0L)
787 work_done += m_can_handle_lost_msg(dev);
789 /* handle lec errors on the bus */
790 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
792 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
794 /* other unproccessed error interrupts */
795 m_can_handle_other_err(dev, irqstatus);
800 static int m_can_rx_handler(struct net_device *dev, int quota)
802 struct m_can_classdev *cdev = netdev_priv(dev);
806 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR);
810 /* Errata workaround for issue "Needless activation of MRAF irq"
811 * During frame reception while the MCAN is in Error Passive state
812 * and the Receive Error Counter has the value MCAN_ECR.REC = 127,
813 * it may happen that MCAN_IR.MRAF is set although there was no
814 * Message RAM access failure.
815 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated
816 * The Message RAM Access Failure interrupt routine needs to check
817 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
818 * In this case, reset MCAN_IR.MRAF. No further action is required.
820 if (cdev->version <= 31 && irqstatus & IR_MRAF &&
821 m_can_read(cdev, M_CAN_ECR) & ECR_RP) {
822 struct can_berr_counter bec;
824 __m_can_get_berr_counter(dev, &bec);
825 if (bec.rxerr == 127) {
826 m_can_write(cdev, M_CAN_IR, IR_MRAF);
827 irqstatus &= ~IR_MRAF;
831 psr = m_can_read(cdev, M_CAN_PSR);
833 if (irqstatus & IR_ERR_STATE)
834 work_done += m_can_handle_state_errors(dev, psr);
836 if (irqstatus & IR_ERR_BUS_30X)
837 work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
839 if (irqstatus & IR_RF0N)
840 work_done += m_can_do_rx_poll(dev, (quota - work_done));
845 static int m_can_rx_peripheral(struct net_device *dev)
847 struct m_can_classdev *cdev = netdev_priv(dev);
849 m_can_rx_handler(dev, 1);
851 m_can_enable_all_interrupts(cdev);
856 static int m_can_poll(struct napi_struct *napi, int quota)
858 struct net_device *dev = napi->dev;
859 struct m_can_classdev *cdev = netdev_priv(dev);
862 work_done = m_can_rx_handler(dev, quota);
863 if (work_done < quota) {
864 napi_complete_done(napi, work_done);
865 m_can_enable_all_interrupts(cdev);
871 static void m_can_echo_tx_event(struct net_device *dev)
877 unsigned int msg_mark;
879 struct m_can_classdev *cdev = netdev_priv(dev);
880 struct net_device_stats *stats = &dev->stats;
882 /* read tx event fifo status */
883 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);
885 /* Get Tx Event fifo element count */
886 txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
889 /* Get and process all sent elements */
890 for (i = 0; i < txe_count; i++) {
891 /* retrieve get index */
892 fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
895 /* get message marker */
896 msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) &
897 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
899 /* ack txe element */
900 m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
901 (fgi << TXEFA_EFAI_SHIFT)));
904 stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
909 static irqreturn_t m_can_isr(int irq, void *dev_id)
911 struct net_device *dev = (struct net_device *)dev_id;
912 struct m_can_classdev *cdev = netdev_priv(dev);
913 struct net_device_stats *stats = &dev->stats;
916 ir = m_can_read(cdev, M_CAN_IR);
922 m_can_write(cdev, M_CAN_IR, ir);
924 if (cdev->ops->clear_interrupts)
925 cdev->ops->clear_interrupts(cdev);
927 /* schedule NAPI in case of
930 * - bus error IRQ and bus error reporting
932 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
933 cdev->irqstatus = ir;
934 m_can_disable_all_interrupts(cdev);
935 if (!cdev->is_peripheral)
936 napi_schedule(&cdev->napi);
938 m_can_rx_peripheral(dev);
941 if (cdev->version == 30) {
943 /* Transmission Complete Interrupt*/
944 stats->tx_bytes += can_get_echo_skb(dev, 0);
946 can_led_event(dev, CAN_LED_EVENT_TX);
947 netif_wake_queue(dev);
951 /* New TX FIFO Element arrived */
952 m_can_echo_tx_event(dev);
953 can_led_event(dev, CAN_LED_EVENT_TX);
954 if (netif_queue_stopped(dev) &&
955 !m_can_tx_fifo_full(cdev))
956 netif_wake_queue(dev);
963 static const struct can_bittiming_const m_can_bittiming_const_30X = {
964 .name = KBUILD_MODNAME,
965 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
967 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
975 static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
976 .name = KBUILD_MODNAME,
977 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
979 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
987 static const struct can_bittiming_const m_can_bittiming_const_31X = {
988 .name = KBUILD_MODNAME,
989 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
991 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
999 static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
1000 .name = KBUILD_MODNAME,
1001 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
1003 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1011 static int m_can_set_bittiming(struct net_device *dev)
1013 struct m_can_classdev *cdev = netdev_priv(dev);
1014 const struct can_bittiming *bt = &cdev->can.bittiming;
1015 const struct can_bittiming *dbt = &cdev->can.data_bittiming;
1016 u16 brp, sjw, tseg1, tseg2;
1021 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1022 tseg2 = bt->phase_seg2 - 1;
1023 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
1024 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT);
1025 m_can_write(cdev, M_CAN_NBTP, reg_btp);
1027 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1031 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1032 tseg2 = dbt->phase_seg2 - 1;
1034 /* TDC is only needed for bitrates beyond 2.5 MBit/s.
1035 * This is mentioned in the "Bit Time Requirements for CAN FD"
1036 * paper presented at the International CAN Conference 2013
1038 if (dbt->bitrate > 2500000) {
1041 /* Use the same value of secondary sampling point
1042 * as the data sampling point
1044 ssp = dbt->sample_point;
1046 /* Equation based on Bosch's M_CAN User Manual's
1047 * Transmitter Delay Compensation Section
1049 tdco = (cdev->can.clock.freq / 1000) *
1052 /* Max valid TDCO value is 127 */
1054 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n",
1059 reg_btp |= DBTP_TDC;
1060 m_can_write(cdev, M_CAN_TDCR,
1061 tdco << TDCR_TDCO_SHIFT);
1064 reg_btp |= (brp << DBTP_DBRP_SHIFT) |
1065 (sjw << DBTP_DSJW_SHIFT) |
1066 (tseg1 << DBTP_DTSEG1_SHIFT) |
1067 (tseg2 << DBTP_DTSEG2_SHIFT);
1069 m_can_write(cdev, M_CAN_DBTP, reg_btp);
1075 /* Configure M_CAN chip:
1076 * - set rx buffer/fifo element size
1077 * - configure rx fifo
1078 * - accept non-matching frame into fifo 0
1079 * - configure tx buffer
1080 * - >= v3.1.x: TX FIFO is used
1084 static void m_can_chip_config(struct net_device *dev)
1086 struct m_can_classdev *cdev = netdev_priv(dev);
1089 m_can_config_endisable(cdev, true);
1091 /* RX Buffer/FIFO Element Size 64 bytes data field */
1092 m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
1094 /* Accept Non-matching Frames Into FIFO 0 */
1095 m_can_write(cdev, M_CAN_GFC, 0x0);
1097 if (cdev->version == 30) {
1098 /* only support one Tx Buffer currently */
1099 m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
1100 cdev->mcfg[MRAM_TXB].off);
1102 /* TX FIFO is used for newer IP Core versions */
1103 m_can_write(cdev, M_CAN_TXBC,
1104 (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) |
1105 (cdev->mcfg[MRAM_TXB].off));
1108 /* support 64 bytes payload */
1109 m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES);
1112 if (cdev->version == 30) {
1113 m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
1114 cdev->mcfg[MRAM_TXE].off);
1116 /* Full TX Event FIFO is used */
1117 m_can_write(cdev, M_CAN_TXEFC,
1118 ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
1120 cdev->mcfg[MRAM_TXE].off);
1123 /* rx fifo configuration, blocking mode, fifo size 1 */
1124 m_can_write(cdev, M_CAN_RXF0C,
1125 (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
1126 cdev->mcfg[MRAM_RXF0].off);
1128 m_can_write(cdev, M_CAN_RXF1C,
1129 (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
1130 cdev->mcfg[MRAM_RXF1].off);
1132 cccr = m_can_read(cdev, M_CAN_CCCR);
1133 test = m_can_read(cdev, M_CAN_TEST);
1135 if (cdev->version == 30) {
1138 cccr &= ~(CCCR_TEST | CCCR_MON |
1139 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
1140 (CCCR_CME_MASK << CCCR_CME_SHIFT));
1142 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1143 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
1146 /* Version 3.1.x or 3.2.x */
1147 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
1150 /* Only 3.2.x has NISO Bit implemented */
1151 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1154 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1155 cccr |= (CCCR_BRSE | CCCR_FDOE);
1159 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1160 cccr |= CCCR_TEST | CCCR_MON;
1164 /* Enable Monitoring (all versions) */
1165 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1169 m_can_write(cdev, M_CAN_CCCR, cccr);
1170 m_can_write(cdev, M_CAN_TEST, test);
1172 /* Enable interrupts */
1173 m_can_write(cdev, M_CAN_IR, IR_ALL_INT);
1174 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1175 if (cdev->version == 30)
1176 m_can_write(cdev, M_CAN_IE, IR_ALL_INT &
1179 m_can_write(cdev, M_CAN_IE, IR_ALL_INT &
1182 m_can_write(cdev, M_CAN_IE, IR_ALL_INT);
1184 /* route all interrupts to INT0 */
1185 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);
1187 /* set bittiming params */
1188 m_can_set_bittiming(dev);
1190 m_can_config_endisable(cdev, false);
1192 if (cdev->ops->init)
1193 cdev->ops->init(cdev);
1196 static void m_can_start(struct net_device *dev)
1198 struct m_can_classdev *cdev = netdev_priv(dev);
1200 /* basic m_can configuration */
1201 m_can_chip_config(dev);
1203 cdev->can.state = CAN_STATE_ERROR_ACTIVE;
1205 m_can_enable_all_interrupts(cdev);
1208 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1211 case CAN_MODE_START:
1214 netif_wake_queue(dev);
1223 /* Checks core release number of M_CAN
1224 * returns 0 if an unsupported device is detected
1225 * else it returns the release and step coded as:
1226 * return value = 10 * <release> + 1 * <step>
1228 static int m_can_check_core_release(struct m_can_classdev *cdev)
1235 /* Read Core Release Version and split into version number
1236 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1238 crel_reg = m_can_read(cdev, M_CAN_CREL);
1239 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
1240 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
1243 /* M_CAN v3.x.y: create return value */
1246 /* Unsupported M_CAN version */
1253 /* Selectable Non ISO support only in version 3.2.x
1254 * This function checks if the bit is writable.
1256 static bool m_can_niso_supported(struct m_can_classdev *cdev)
1258 u32 cccr_reg, cccr_poll = 0;
1259 int niso_timeout = -ETIMEDOUT;
1262 m_can_config_endisable(cdev, true);
1263 cccr_reg = m_can_read(cdev, M_CAN_CCCR);
1264 cccr_reg |= CCCR_NISO;
1265 m_can_write(cdev, M_CAN_CCCR, cccr_reg);
1267 for (i = 0; i <= 10; i++) {
1268 cccr_poll = m_can_read(cdev, M_CAN_CCCR);
1269 if (cccr_poll == cccr_reg) {
1278 cccr_reg &= ~(CCCR_NISO);
1279 m_can_write(cdev, M_CAN_CCCR, cccr_reg);
1281 m_can_config_endisable(cdev, false);
1283 /* return false if time out (-ETIMEDOUT), else return true */
1284 return !niso_timeout;
1287 static int m_can_dev_setup(struct m_can_classdev *m_can_dev)
1289 struct net_device *dev = m_can_dev->net;
1292 m_can_version = m_can_check_core_release(m_can_dev);
1293 /* return if unsupported version */
1294 if (!m_can_version) {
1295 dev_err(m_can_dev->dev, "Unsupported version number: %2d",
1300 if (!m_can_dev->is_peripheral)
1301 netif_napi_add(dev, &m_can_dev->napi,
1302 m_can_poll, M_CAN_NAPI_WEIGHT);
1304 /* Shared properties of all M_CAN versions */
1305 m_can_dev->version = m_can_version;
1306 m_can_dev->can.do_set_mode = m_can_set_mode;
1307 m_can_dev->can.do_get_berr_counter = m_can_get_berr_counter;
1309 /* Set M_CAN supported operations */
1310 m_can_dev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1311 CAN_CTRLMODE_LISTENONLY |
1312 CAN_CTRLMODE_BERR_REPORTING |
1315 /* Set properties depending on M_CAN version */
1316 switch (m_can_dev->version) {
1318 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1319 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1320 m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
1321 m_can_dev->bit_timing : &m_can_bittiming_const_30X;
1323 m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
1324 m_can_dev->data_timing :
1325 &m_can_data_bittiming_const_30X;
1328 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1329 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1330 m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
1331 m_can_dev->bit_timing : &m_can_bittiming_const_31X;
1333 m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
1334 m_can_dev->data_timing :
1335 &m_can_data_bittiming_const_31X;
1338 m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
1339 m_can_dev->bit_timing : &m_can_bittiming_const_31X;
1341 m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
1342 m_can_dev->data_timing :
1343 &m_can_data_bittiming_const_31X;
1345 m_can_dev->can.ctrlmode_supported |=
1346 (m_can_niso_supported(m_can_dev)
1347 ? CAN_CTRLMODE_FD_NON_ISO
1351 dev_err(m_can_dev->dev, "Unsupported version number: %2d",
1352 m_can_dev->version);
1356 if (m_can_dev->ops->init)
1357 m_can_dev->ops->init(m_can_dev);
1362 static void m_can_stop(struct net_device *dev)
1364 struct m_can_classdev *cdev = netdev_priv(dev);
1366 /* disable all interrupts */
1367 m_can_disable_all_interrupts(cdev);
1369 /* set the state as STOPPED */
1370 cdev->can.state = CAN_STATE_STOPPED;
1373 static int m_can_close(struct net_device *dev)
1375 struct m_can_classdev *cdev = netdev_priv(dev);
1377 netif_stop_queue(dev);
1379 if (!cdev->is_peripheral)
1380 napi_disable(&cdev->napi);
1383 m_can_clk_stop(cdev);
1384 free_irq(dev->irq, dev);
1386 if (cdev->is_peripheral) {
1387 cdev->tx_skb = NULL;
1388 destroy_workqueue(cdev->tx_wq);
1393 can_led_event(dev, CAN_LED_EVENT_STOP);
1398 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
1400 struct m_can_classdev *cdev = netdev_priv(dev);
1401 /*get wrap around for loopback skb index */
1402 unsigned int wrap = cdev->can.echo_skb_max;
1405 /* calculate next index */
1406 next_idx = (++putidx >= wrap ? 0 : putidx);
1408 /* check if occupied */
1409 return !!cdev->can.echo_skb[next_idx];
1412 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
1414 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data;
1415 struct net_device *dev = cdev->net;
1416 struct sk_buff *skb = cdev->tx_skb;
1417 u32 id, cccr, fdflags;
1421 /* Generate ID field for TX buffer Element */
1422 /* Common to all supported M_CAN versions */
1423 if (cf->can_id & CAN_EFF_FLAG) {
1424 id = cf->can_id & CAN_EFF_MASK;
1427 id = ((cf->can_id & CAN_SFF_MASK) << 18);
1430 if (cf->can_id & CAN_RTR_FLAG)
1433 if (cdev->version == 30) {
1434 netif_stop_queue(dev);
1436 /* message ram configuration */
1437 m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, id);
1438 m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC,
1439 can_len2dlc(cf->len) << 16);
1441 for (i = 0; i < cf->len; i += 4)
1442 m_can_fifo_write(cdev, 0,
1443 M_CAN_FIFO_DATA(i / 4),
1444 *(u32 *)(cf->data + i));
1446 can_put_echo_skb(skb, dev, 0);
1448 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1449 cccr = m_can_read(cdev, M_CAN_CCCR);
1450 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
1451 if (can_is_canfd_skb(skb)) {
1452 if (cf->flags & CANFD_BRS)
1453 cccr |= CCCR_CMR_CANFD_BRS <<
1456 cccr |= CCCR_CMR_CANFD <<
1459 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
1461 m_can_write(cdev, M_CAN_CCCR, cccr);
1463 m_can_write(cdev, M_CAN_TXBTIE, 0x1);
1464 m_can_write(cdev, M_CAN_TXBAR, 0x1);
1465 /* End of xmit function for version 3.0.x */
1467 /* Transmit routine for version >= v3.1.x */
1469 /* Check if FIFO full */
1470 if (m_can_tx_fifo_full(cdev)) {
1471 /* This shouldn't happen */
1472 netif_stop_queue(dev);
1474 "TX queue active although FIFO is full.");
1476 if (cdev->is_peripheral) {
1478 dev->stats.tx_dropped++;
1479 return NETDEV_TX_OK;
1481 return NETDEV_TX_BUSY;
1485 /* get put index for frame */
1486 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
1487 >> TXFQS_TFQPI_SHIFT);
1488 /* Write ID Field to FIFO Element */
1489 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id);
1491 /* get CAN FD configuration of frame */
1493 if (can_is_canfd_skb(skb)) {
1494 fdflags |= TX_BUF_FDF;
1495 if (cf->flags & CANFD_BRS)
1496 fdflags |= TX_BUF_BRS;
1499 /* Construct DLC Field. Also contains CAN-FD configuration
1500 * use put index of fifo as message marker
1501 * it is used in TX interrupt for
1502 * sending the correct echo frame
1504 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC,
1505 ((putidx << TX_BUF_MM_SHIFT) &
1507 (can_len2dlc(cf->len) << 16) |
1508 fdflags | TX_BUF_EFC);
1510 for (i = 0; i < cf->len; i += 4)
1511 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4),
1512 *(u32 *)(cf->data + i));
1514 /* Push loopback echo.
1515 * Will be looped back on TX interrupt based on message marker
1517 can_put_echo_skb(skb, dev, putidx);
1519 /* Enable TX FIFO element to start transfer */
1520 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx));
1522 /* stop network queue if fifo full */
1523 if (m_can_tx_fifo_full(cdev) ||
1524 m_can_next_echo_skb_occupied(dev, putidx))
1525 netif_stop_queue(dev);
1528 return NETDEV_TX_OK;
1531 static void m_can_tx_work_queue(struct work_struct *ws)
1533 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev,
1536 m_can_tx_handler(cdev);
1537 cdev->tx_skb = NULL;
1540 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1541 struct net_device *dev)
1543 struct m_can_classdev *cdev = netdev_priv(dev);
1545 if (can_dropped_invalid_skb(dev, skb))
1546 return NETDEV_TX_OK;
1548 if (cdev->is_peripheral) {
1550 netdev_err(dev, "hard_xmit called while tx busy\n");
1551 return NETDEV_TX_BUSY;
1554 if (cdev->can.state == CAN_STATE_BUS_OFF) {
1557 /* Need to stop the queue to avoid numerous requests
1558 * from being sent. Suggested improvement is to create
1559 * a queueing mechanism that will queue the skbs and
1560 * process them in order.
1563 netif_stop_queue(cdev->net);
1564 queue_work(cdev->tx_wq, &cdev->tx_work);
1568 return m_can_tx_handler(cdev);
1571 return NETDEV_TX_OK;
1574 static int m_can_open(struct net_device *dev)
1576 struct m_can_classdev *cdev = netdev_priv(dev);
1579 err = m_can_clk_start(cdev);
1583 /* open the can device */
1584 err = open_candev(dev);
1586 netdev_err(dev, "failed to open can device\n");
1587 goto exit_disable_clks;
1590 /* register interrupt handler */
1591 if (cdev->is_peripheral) {
1592 cdev->tx_skb = NULL;
1593 cdev->tx_wq = alloc_workqueue("mcan_wq",
1594 WQ_FREEZABLE | WQ_MEM_RECLAIM, 0);
1600 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue);
1602 err = request_threaded_irq(dev->irq, NULL, m_can_isr,
1603 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1606 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
1611 netdev_err(dev, "failed to request interrupt\n");
1615 /* start the m_can controller */
1618 can_led_event(dev, CAN_LED_EVENT_OPEN);
1620 if (!cdev->is_peripheral)
1621 napi_enable(&cdev->napi);
1623 netif_start_queue(dev);
1628 if (cdev->is_peripheral)
1629 destroy_workqueue(cdev->tx_wq);
1633 m_can_clk_stop(cdev);
1637 static const struct net_device_ops m_can_netdev_ops = {
1638 .ndo_open = m_can_open,
1639 .ndo_stop = m_can_close,
1640 .ndo_start_xmit = m_can_start_xmit,
1641 .ndo_change_mtu = can_change_mtu,
1644 static int register_m_can_dev(struct net_device *dev)
1646 dev->flags |= IFF_ECHO; /* we support local echo */
1647 dev->netdev_ops = &m_can_netdev_ops;
1649 return register_candev(dev);
1652 static void m_can_of_parse_mram(struct m_can_classdev *cdev,
1653 const u32 *mram_config_vals)
1655 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];
1656 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];
1657 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +
1658 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1659 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];
1660 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
1661 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1662 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
1663 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1664 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
1665 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1666 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
1667 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1668 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
1669 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1670 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
1671 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +
1672 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1673 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];
1674 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
1675 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1676 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
1677 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
1680 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1681 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num,
1682 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num,
1683 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num,
1684 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num,
1685 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num,
1686 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num,
1687 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);
1690 void m_can_init_ram(struct m_can_classdev *cdev)
1694 /* initialize the entire Message RAM in use to avoid possible
1695 * ECC/parity checksum errors when reading an uninitialized buffer
1697 start = cdev->mcfg[MRAM_SIDF].off;
1698 end = cdev->mcfg[MRAM_TXB].off +
1699 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1701 for (i = start; i < end; i += 4)
1702 m_can_fifo_write_no_off(cdev, i, 0x0);
1704 EXPORT_SYMBOL_GPL(m_can_init_ram);
1706 int m_can_class_get_clocks(struct m_can_classdev *m_can_dev)
1710 m_can_dev->hclk = devm_clk_get(m_can_dev->dev, "hclk");
1711 m_can_dev->cclk = devm_clk_get(m_can_dev->dev, "cclk");
1713 if (IS_ERR(m_can_dev->cclk)) {
1714 dev_err(m_can_dev->dev, "no clock found\n");
1720 EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
1722 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev)
1724 struct m_can_classdev *class_dev = NULL;
1725 u32 mram_config_vals[MRAM_CFG_LEN];
1726 struct net_device *net_dev;
1730 ret = fwnode_property_read_u32_array(dev_fwnode(dev),
1733 sizeof(mram_config_vals) / 4);
1735 dev_err(dev, "Could not get Message RAM configuration.");
1740 * Defines the total amount of echo buffers for loopback
1742 tx_fifo_size = mram_config_vals[7];
1744 /* allocate the m_can device */
1745 net_dev = alloc_candev(sizeof(*class_dev), tx_fifo_size);
1747 dev_err(dev, "Failed to allocate CAN device");
1751 class_dev = netdev_priv(net_dev);
1753 dev_err(dev, "Failed to init netdev cdevate");
1757 class_dev->net = net_dev;
1758 class_dev->dev = dev;
1759 SET_NETDEV_DEV(net_dev, dev);
1761 m_can_of_parse_mram(class_dev, mram_config_vals);
1765 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev);
1767 int m_can_class_register(struct m_can_classdev *m_can_dev)
1771 if (m_can_dev->pm_clock_support) {
1772 pm_runtime_enable(m_can_dev->dev);
1773 ret = m_can_clk_start(m_can_dev);
1775 goto pm_runtime_fail;
1778 ret = m_can_dev_setup(m_can_dev);
1782 ret = register_m_can_dev(m_can_dev->net);
1784 dev_err(m_can_dev->dev, "registering %s failed (err=%d)\n",
1785 m_can_dev->net->name, ret);
1789 devm_can_led_init(m_can_dev->net);
1791 of_can_transceiver(m_can_dev->net);
1793 dev_info(m_can_dev->dev, "%s device registered (irq=%d, version=%d)\n",
1794 KBUILD_MODNAME, m_can_dev->net->irq, m_can_dev->version);
1797 * Stop clocks. They will be reactivated once the M_CAN device is opened
1800 m_can_clk_stop(m_can_dev);
1803 if (m_can_dev->pm_clock_support)
1804 pm_runtime_disable(m_can_dev->dev);
1805 free_candev(m_can_dev->net);
1810 EXPORT_SYMBOL_GPL(m_can_class_register);
1812 int m_can_class_suspend(struct device *dev)
1814 struct net_device *ndev = dev_get_drvdata(dev);
1815 struct m_can_classdev *cdev = netdev_priv(ndev);
1817 if (netif_running(ndev)) {
1818 netif_stop_queue(ndev);
1819 netif_device_detach(ndev);
1821 m_can_clk_stop(cdev);
1824 pinctrl_pm_select_sleep_state(dev);
1826 cdev->can.state = CAN_STATE_SLEEPING;
1830 EXPORT_SYMBOL_GPL(m_can_class_suspend);
1832 int m_can_class_resume(struct device *dev)
1834 struct net_device *ndev = dev_get_drvdata(dev);
1835 struct m_can_classdev *cdev = netdev_priv(ndev);
1837 pinctrl_pm_select_default_state(dev);
1839 cdev->can.state = CAN_STATE_ERROR_ACTIVE;
1841 if (netif_running(ndev)) {
1844 ret = m_can_clk_start(cdev);
1848 m_can_init_ram(cdev);
1850 netif_device_attach(ndev);
1851 netif_start_queue(ndev);
1856 EXPORT_SYMBOL_GPL(m_can_class_resume);
1858 void m_can_class_unregister(struct m_can_classdev *m_can_dev)
1860 unregister_candev(m_can_dev->net);
1862 m_can_clk_stop(m_can_dev);
1864 free_candev(m_can_dev->net);
1866 EXPORT_SYMBOL_GPL(m_can_class_unregister);
1868 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
1869 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
1870 MODULE_LICENSE("GPL v2");
1871 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");