drivers/mtd/nand/raw/jz4780_nand.c

   1 /*
   2  * JZ4780 NAND driver
   3  *
   4  * Copyright (c) 2015 Imagination Technologies
   5  * Author: Alex Smith <alex.smith@imgtec.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/list.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/gpio/consumer.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/mtd/mtd.h>
  23 #include <linux/mtd/rawnand.h>
  24 #include <linux/mtd/partitions.h>
  25
  26 #include <linux/jz4780-nemc.h>
  27
  28 #include "jz4780_bch.h"
  29
  30 #define DRV_NAME        "jz4780-nand"
  31
  32 #define OFFSET_DATA     0x00000000
  33 #define OFFSET_CMD      0x00400000
  34 #define OFFSET_ADDR     0x00800000
  35
  36 /* Command delay when there is no R/B pin. */
  37 #define RB_DELAY_US     100
  38
  39 struct jz4780_nand_cs {
  40         unsigned int bank;
  41         void __iomem *base;
  42 };
  43
  44 struct jz4780_nand_controller {
  45         struct device *dev;
  46         struct jz4780_bch *bch;
  47         struct nand_controller controller;
  48         unsigned int num_banks;
  49         struct list_head chips;
  50         int selected;
  51         struct jz4780_nand_cs cs[];
  52 };
  53
  54 struct jz4780_nand_chip {
  55         struct nand_chip chip;
  56         struct list_head chip_list;
  57
  58         struct gpio_desc *busy_gpio;
  59         struct gpio_desc *wp_gpio;
  60         unsigned int reading: 1;
  61 };
  62
  63 static inline struct jz4780_nand_chip *to_jz4780_nand_chip(struct mtd_info *mtd)
  64 {
  65         return container_of(mtd_to_nand(mtd), struct jz4780_nand_chip, chip);
  66 }
  67
  68 static inline struct jz4780_nand_controller
  69 *to_jz4780_nand_controller(struct nand_controller *ctrl)
  70 {
  71         return container_of(ctrl, struct jz4780_nand_controller, controller);
  72 }
  73
  74 static void jz4780_nand_select_chip(struct mtd_info *mtd, int chipnr)
  75 {
  76         struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
  77         struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
  78         struct jz4780_nand_cs *cs;
  79
  80         /* Ensure the currently selected chip is deasserted. */
  81         if (chipnr == -1 && nfc->selected >= 0) {
  82                 cs = &nfc->cs[nfc->selected];
  83                 jz4780_nemc_assert(nfc->dev, cs->bank, false);
  84         }
  85
  86         nfc->selected = chipnr;
  87 }
  88
  89 static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
  90                                  unsigned int ctrl)
  91 {
  92         struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
  93         struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
  94         struct jz4780_nand_cs *cs;
  95
  96         if (WARN_ON(nfc->selected < 0))
  97                 return;
  98
  99         cs = &nfc->cs[nfc->selected];
 100
 101         jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
 102
 103         if (cmd == NAND_CMD_NONE)
 104                 return;
 105
 106         if (ctrl & NAND_ALE)
 107                 writeb(cmd, cs->base + OFFSET_ADDR);
 108         else if (ctrl & NAND_CLE)
 109                 writeb(cmd, cs->base + OFFSET_CMD);
 110 }
 111
 112 static int jz4780_nand_dev_ready(struct mtd_info *mtd)
 113 {
 114         struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
 115
 116         return !gpiod_get_value_cansleep(nand->busy_gpio);
 117 }
 118
 119 static void jz4780_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
 120 {
 121         struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
 122
 123         nand->reading = (mode == NAND_ECC_READ);
 124 }
 125
 126 static int jz4780_nand_ecc_calculate(struct mtd_info *mtd, const u8 *dat,
 127                                      u8 *ecc_code)
 128 {
 129         struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
 130         struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
 131         struct jz4780_bch_params params;
 132
 133         /*
 134          * Don't need to generate the ECC when reading, BCH does it for us as
 135          * part of decoding/correction.
 136          */
 137         if (nand->reading)
 138                 return 0;
 139
 140         params.size = nand->chip.ecc.size;
 141         params.bytes = nand->chip.ecc.bytes;
 142         params.strength = nand->chip.ecc.strength;
 143
 144         return jz4780_bch_calculate(nfc->bch, &params, dat, ecc_code);
 145 }
 146
 147 static int jz4780_nand_ecc_correct(struct mtd_info *mtd, u8 *dat,
 148                                    u8 *read_ecc, u8 *calc_ecc)
 149 {
 150         struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
 151         struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
 152         struct jz4780_bch_params params;
 153
 154         params.size = nand->chip.ecc.size;
 155         params.bytes = nand->chip.ecc.bytes;
 156         params.strength = nand->chip.ecc.strength;
 157
 158         return jz4780_bch_correct(nfc->bch, &params, dat, read_ecc);
 159 }
 160
 161 static int jz4780_nand_attach_chip(struct nand_chip *chip)
 162 {
 163         struct mtd_info *mtd = nand_to_mtd(chip);
 164         struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(chip->controller);
 165         int eccbytes;
 166
 167         chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) *
 168                                 (chip->ecc.strength / 8);
 169
 170         switch (chip->ecc.mode) {
 171         case NAND_ECC_HW:
 172                 if (!nfc->bch) {
 173                         dev_err(nfc->dev,
 174                                 "HW BCH selected, but BCH controller not found\n");
 175                         return -ENODEV;
 176                 }
 177
 178                 chip->ecc.hwctl = jz4780_nand_ecc_hwctl;
 179                 chip->ecc.calculate = jz4780_nand_ecc_calculate;
 180                 chip->ecc.correct = jz4780_nand_ecc_correct;
 181                 /* fall through */
 182         case NAND_ECC_SOFT:
 183                 dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
 184                          (nfc->bch) ? "hardware BCH" : "software ECC",
 185                          chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
 186                 break;
 187         case NAND_ECC_NONE:
 188                 dev_info(nfc->dev, "not using ECC\n");
 189                 break;
 190         default:
 191                 dev_err(nfc->dev, "ECC mode %d not supported\n",
 192                         chip->ecc.mode);
 193                 return -EINVAL;
 194         }
 195
 196         /* The NAND core will generate the ECC layout for SW ECC */
 197         if (chip->ecc.mode != NAND_ECC_HW)
 198                 return 0;
 199
 200         /* Generate ECC layout. ECC codes are right aligned in the OOB area. */
 201         eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
 202
 203         if (eccbytes > mtd->oobsize - 2) {
 204                 dev_err(nfc->dev,
 205                         "invalid ECC config: required %d ECC bytes, but only %d are available",
 206                         eccbytes, mtd->oobsize - 2);
 207                 return -EINVAL;
 208         }
 209
 210         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
 211
 212         return 0;
 213 }
 214
 215 static const struct nand_controller_ops jz4780_nand_controller_ops = {
 216         .attach_chip = jz4780_nand_attach_chip,
 217 };
 218
 219 static int jz4780_nand_init_chip(struct platform_device *pdev,
 220                                 struct jz4780_nand_controller *nfc,
 221                                 struct device_node *np,
 222                                 unsigned int chipnr)
 223 {
 224         struct device *dev = &pdev->dev;
 225         struct jz4780_nand_chip *nand;
 226         struct jz4780_nand_cs *cs;
 227         struct resource *res;
 228         struct nand_chip *chip;
 229         struct mtd_info *mtd;
 230         const __be32 *reg;
 231         int ret = 0;
 232
 233         cs = &nfc->cs[chipnr];
 234
 235         reg = of_get_property(np, "reg", NULL);
 236         if (!reg)
 237                 return -EINVAL;
 238
 239         cs->bank = be32_to_cpu(*reg);
 240
 241         jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
 242
 243         res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr);
 244         cs->base = devm_ioremap_resource(dev, res);
 245         if (IS_ERR(cs->base))
 246                 return PTR_ERR(cs->base);
 247
 248         nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
 249         if (!nand)
 250                 return -ENOMEM;
 251
 252         nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
 253
 254         if (IS_ERR(nand->busy_gpio)) {
 255                 ret = PTR_ERR(nand->busy_gpio);
 256                 dev_err(dev, "failed to request busy GPIO: %d\n", ret);
 257                 return ret;
 258         } else if (nand->busy_gpio) {
 259                 nand->chip.dev_ready = jz4780_nand_dev_ready;
 260         }
 261
 262         nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
 263
 264         if (IS_ERR(nand->wp_gpio)) {
 265                 ret = PTR_ERR(nand->wp_gpio);
 266                 dev_err(dev, "failed to request WP GPIO: %d\n", ret);
 267                 return ret;
 268         }
 269
 270         chip = &nand->chip;
 271         mtd = nand_to_mtd(chip);
 272         mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
 273                                    cs->bank);
 274         if (!mtd->name)
 275                 return -ENOMEM;
 276         mtd->dev.parent = dev;
 277
 278         chip->IO_ADDR_R = cs->base + OFFSET_DATA;
 279         chip->IO_ADDR_W = cs->base + OFFSET_DATA;
 280         chip->chip_delay = RB_DELAY_US;
 281         chip->options = NAND_NO_SUBPAGE_WRITE;
 282         chip->select_chip = jz4780_nand_select_chip;
 283         chip->cmd_ctrl = jz4780_nand_cmd_ctrl;
 284         chip->ecc.mode = NAND_ECC_HW;
 285         chip->controller = &nfc->controller;
 286         nand_set_flash_node(chip, np);
 287
 288         chip->controller->ops = &jz4780_nand_controller_ops;
 289         ret = nand_scan(mtd, 1);
 290         if (ret)
 291                 return ret;
 292
 293         ret = mtd_device_register(mtd, NULL, 0);
 294         if (ret) {
 295                 nand_release(mtd);
 296                 return ret;
 297         }
 298
 299         list_add_tail(&nand->chip_list, &nfc->chips);
 300
 301         return 0;
 302 }
 303
 304 static void jz4780_nand_cleanup_chips(struct jz4780_nand_controller *nfc)
 305 {
 306         struct jz4780_nand_chip *chip;
 307
 308         while (!list_empty(&nfc->chips)) {
 309                 chip = list_first_entry(&nfc->chips, struct jz4780_nand_chip, chip_list);
 310                 nand_release(nand_to_mtd(&chip->chip));
 311                 list_del(&chip->chip_list);
 312         }
 313 }
 314
 315 static int jz4780_nand_init_chips(struct jz4780_nand_controller *nfc,
 316                                   struct platform_device *pdev)
 317 {
 318         struct device *dev = &pdev->dev;
 319         struct device_node *np;
 320         int i = 0;
 321         int ret;
 322         int num_chips = of_get_child_count(dev->of_node);
 323
 324         if (num_chips > nfc->num_banks) {
 325                 dev_err(dev, "found %d chips but only %d banks\n", num_chips, nfc->num_banks);
 326                 return -EINVAL;
 327         }
 328
 329         for_each_child_of_node(dev->of_node, np) {
 330                 ret = jz4780_nand_init_chip(pdev, nfc, np, i);
 331                 if (ret) {
 332                         jz4780_nand_cleanup_chips(nfc);
 333                         return ret;
 334                 }
 335
 336                 i++;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int jz4780_nand_probe(struct platform_device *pdev)
 343 {
 344         struct device *dev = &pdev->dev;
 345         unsigned int num_banks;
 346         struct jz4780_nand_controller *nfc;
 347         int ret;
 348
 349         num_banks = jz4780_nemc_num_banks(dev);
 350         if (num_banks == 0) {
 351                 dev_err(dev, "no banks found\n");
 352                 return -ENODEV;
 353         }
 354
 355         nfc = devm_kzalloc(dev, sizeof(*nfc) + (sizeof(nfc->cs[0]) * num_banks), GFP_KERNEL);
 356         if (!nfc)
 357                 return -ENOMEM;
 358
 359         /*
 360          * Check for BCH HW before we call nand_scan_ident, to prevent us from
 361          * having to call it again if the BCH driver returns -EPROBE_DEFER.
 362          */
 363         nfc->bch = of_jz4780_bch_get(dev->of_node);
 364         if (IS_ERR(nfc->bch))
 365                 return PTR_ERR(nfc->bch);
 366
 367         nfc->dev = dev;
 368         nfc->num_banks = num_banks;
 369
 370         nand_controller_init(&nfc->controller);
 371         INIT_LIST_HEAD(&nfc->chips);
 372
 373         ret = jz4780_nand_init_chips(nfc, pdev);
 374         if (ret) {
 375                 if (nfc->bch)
 376                         jz4780_bch_release(nfc->bch);
 377                 return ret;
 378         }
 379
 380         platform_set_drvdata(pdev, nfc);
 381         return 0;
 382 }
 383
 384 static int jz4780_nand_remove(struct platform_device *pdev)
 385 {
 386         struct jz4780_nand_controller *nfc = platform_get_drvdata(pdev);
 387
 388         if (nfc->bch)
 389                 jz4780_bch_release(nfc->bch);
 390
 391         jz4780_nand_cleanup_chips(nfc);
 392
 393         return 0;
 394 }
 395
 396 static const struct of_device_id jz4780_nand_dt_match[] = {
 397         { .compatible = "ingenic,jz4780-nand" },
 398         {},
 399 };
 400 MODULE_DEVICE_TABLE(of, jz4780_nand_dt_match);
 401
 402 static struct platform_driver jz4780_nand_driver = {
 403         .probe          = jz4780_nand_probe,
 404         .remove         = jz4780_nand_remove,
 405         .driver = {
 406                 .name   = DRV_NAME,
 407                 .of_match_table = of_match_ptr(jz4780_nand_dt_match),
 408         },
 409 };
 410 module_platform_driver(jz4780_nand_driver);
 411
 412 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
 413 MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
 414 MODULE_DESCRIPTION("Ingenic JZ4780 NAND driver");
 415 MODULE_LICENSE("GPL v2");