2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
28 #include <asm/byteorder.h>
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
62 size_t *, struct otp_info *);
63 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
64 size_t *, struct otp_info *);
65 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
66 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
68 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
70 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
72 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
74 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
75 size_t *retlen, const u_char *buf);
77 static void cfi_amdstd_destroy(struct mtd_info *);
79 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
80 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
82 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
83 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
86 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
87 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
89 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
90 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
91 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
93 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
94 .probe = NULL, /* Not usable directly */
95 .destroy = cfi_amdstd_destroy,
96 .name = "cfi_cmdset_0002",
101 /* #define DEBUG_CFI_FEATURES */
104 #ifdef DEBUG_CFI_FEATURES
105 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
107 const char* erase_suspend[3] = {
108 "Not supported", "Read only", "Read/write"
110 const char* top_bottom[6] = {
111 "No WP", "8x8KiB sectors at top & bottom, no WP",
112 "Bottom boot", "Top boot",
113 "Uniform, Bottom WP", "Uniform, Top WP"
116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
117 printk(" Address sensitive unlock: %s\n",
118 (extp->SiliconRevision & 1) ? "Not required" : "Required");
120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
125 if (extp->BlkProt == 0)
126 printk(" Block protection: Not supported\n");
128 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
131 printk(" Temporary block unprotect: %s\n",
132 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
135 printk(" Burst mode: %s\n",
136 extp->BurstMode ? "Supported" : "Not supported");
137 if (extp->PageMode == 0)
138 printk(" Page mode: Not supported\n");
140 printk(" Page mode: %d word page\n", extp->PageMode << 2);
142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
143 extp->VppMin >> 4, extp->VppMin & 0xf);
144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
145 extp->VppMax >> 4, extp->VppMax & 0xf);
147 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
154 #ifdef AMD_BOOTLOC_BUG
155 /* Wheee. Bring me the head of someone at AMD. */
156 static void fixup_amd_bootblock(struct mtd_info *mtd)
158 struct map_info *map = mtd->priv;
159 struct cfi_private *cfi = map->fldrv_priv;
160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
161 __u8 major = extp->MajorVersion;
162 __u8 minor = extp->MinorVersion;
164 if (((major << 8) | minor) < 0x3131) {
165 /* CFI version 1.0 => don't trust bootloc */
167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
168 map->name, cfi->mfr, cfi->id);
170 /* AFAICS all 29LV400 with a bottom boot block have a device ID
171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
172 * These were badly detected as they have the 0x80 bit set
173 * so treat them as a special case.
175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
177 /* Macronix added CFI to their 2nd generation
178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
179 * Fujitsu, Spansion, EON, ESI and older Macronix)
182 * Therefore also check the manufacturer.
183 * This reduces the risk of false detection due to
184 * the 8-bit device ID.
186 (cfi->mfr == CFI_MFR_MACRONIX)) {
187 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
188 " detected\n", map->name);
189 extp->TopBottom = 2; /* bottom boot */
191 if (cfi->id & 0x80) {
192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
193 extp->TopBottom = 3; /* top boot */
195 extp->TopBottom = 2; /* bottom boot */
198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
199 " deduced %s from Device ID\n", map->name, major, minor,
200 extp->TopBottom == 2 ? "bottom" : "top");
205 static void fixup_use_write_buffers(struct mtd_info *mtd)
207 struct map_info *map = mtd->priv;
208 struct cfi_private *cfi = map->fldrv_priv;
209 if (cfi->cfiq->BufWriteTimeoutTyp) {
210 pr_debug("Using buffer write method\n" );
211 mtd->_write = cfi_amdstd_write_buffers;
215 /* Atmel chips don't use the same PRI format as AMD chips */
216 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
218 struct map_info *map = mtd->priv;
219 struct cfi_private *cfi = map->fldrv_priv;
220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
221 struct cfi_pri_atmel atmel_pri;
223 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
224 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
226 if (atmel_pri.Features & 0x02)
227 extp->EraseSuspend = 2;
229 /* Some chips got it backwards... */
230 if (cfi->id == AT49BV6416) {
231 if (atmel_pri.BottomBoot)
236 if (atmel_pri.BottomBoot)
242 /* burst write mode not supported */
243 cfi->cfiq->BufWriteTimeoutTyp = 0;
244 cfi->cfiq->BufWriteTimeoutMax = 0;
247 static void fixup_use_secsi(struct mtd_info *mtd)
249 /* Setup for chips with a secsi area */
250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
254 static void fixup_use_erase_chip(struct mtd_info *mtd)
256 struct map_info *map = mtd->priv;
257 struct cfi_private *cfi = map->fldrv_priv;
258 if ((cfi->cfiq->NumEraseRegions == 1) &&
259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
260 mtd->_erase = cfi_amdstd_erase_chip;
266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
269 static void fixup_use_atmel_lock(struct mtd_info *mtd)
271 mtd->_lock = cfi_atmel_lock;
272 mtd->_unlock = cfi_atmel_unlock;
273 mtd->flags |= MTD_POWERUP_LOCK;
276 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
278 struct map_info *map = mtd->priv;
279 struct cfi_private *cfi = map->fldrv_priv;
282 * These flashes report two separate eraseblock regions based on the
283 * sector_erase-size and block_erase-size, although they both operate on the
284 * same memory. This is not allowed according to CFI, so we just pick the
287 cfi->cfiq->NumEraseRegions = 1;
290 static void fixup_sst39vf(struct mtd_info *mtd)
292 struct map_info *map = mtd->priv;
293 struct cfi_private *cfi = map->fldrv_priv;
295 fixup_old_sst_eraseregion(mtd);
297 cfi->addr_unlock1 = 0x5555;
298 cfi->addr_unlock2 = 0x2AAA;
301 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
303 struct map_info *map = mtd->priv;
304 struct cfi_private *cfi = map->fldrv_priv;
306 fixup_old_sst_eraseregion(mtd);
308 cfi->addr_unlock1 = 0x555;
309 cfi->addr_unlock2 = 0x2AA;
311 cfi->sector_erase_cmd = CMD(0x50);
314 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
316 struct map_info *map = mtd->priv;
317 struct cfi_private *cfi = map->fldrv_priv;
319 fixup_sst39vf_rev_b(mtd);
322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
323 * it should report a size of 8KBytes (0x0020*256).
325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
326 pr_warning("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", mtd->name);
329 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
331 struct map_info *map = mtd->priv;
332 struct cfi_private *cfi = map->fldrv_priv;
334 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
335 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
336 pr_warning("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n", mtd->name);
340 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
342 struct map_info *map = mtd->priv;
343 struct cfi_private *cfi = map->fldrv_priv;
345 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
346 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
347 pr_warning("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n", mtd->name);
351 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
353 struct map_info *map = mtd->priv;
354 struct cfi_private *cfi = map->fldrv_priv;
357 * S29NS512P flash uses more than 8bits to report number of sectors,
358 * which is not permitted by CFI.
360 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
361 pr_warning("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n", mtd->name);
364 /* Used to fix CFI-Tables of chips without Extended Query Tables */
365 static struct cfi_fixup cfi_nopri_fixup_table[] = {
366 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
367 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
368 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
369 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
370 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
371 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
372 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
373 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
377 static struct cfi_fixup cfi_fixup_table[] = {
378 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
379 #ifdef AMD_BOOTLOC_BUG
380 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
381 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
382 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
384 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
385 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
386 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
387 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
388 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
389 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
390 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
391 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
392 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
393 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
394 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
395 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
396 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
397 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
398 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
399 #if !FORCE_WORD_WRITE
400 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
404 static struct cfi_fixup jedec_fixup_table[] = {
405 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
406 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
407 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
411 static struct cfi_fixup fixup_table[] = {
412 /* The CFI vendor ids and the JEDEC vendor IDs appear
413 * to be common. It is like the devices id's are as
414 * well. This table is to pick all cases where
415 * we know that is the case.
417 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
418 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
423 static void cfi_fixup_major_minor(struct cfi_private *cfi,
424 struct cfi_pri_amdstd *extp)
426 if (cfi->mfr == CFI_MFR_SAMSUNG) {
427 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
428 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
430 * Samsung K8P2815UQB and K8D6x16UxM chips
431 * report major=0 / minor=0.
432 * K8D3x16UxC chips report major=3 / minor=3.
434 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
435 " Extended Query version to 1.%c\n",
437 extp->MajorVersion = '1';
442 * SST 38VF640x chips report major=0xFF / minor=0xFF.
444 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
445 extp->MajorVersion = '1';
446 extp->MinorVersion = '0';
450 static int is_m29ew(struct cfi_private *cfi)
452 if (cfi->mfr == CFI_MFR_INTEL &&
453 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
454 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
460 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
461 * Some revisions of the M29EW suffer from erase suspend hang ups. In
462 * particular, it can occur when the sequence
463 * Erase Confirm -> Suspend -> Program -> Resume
464 * causes a lockup due to internal timing issues. The consequence is that the
465 * erase cannot be resumed without inserting a dummy command after programming
466 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
467 * that writes an F0 command code before the RESUME command.
469 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
472 struct cfi_private *cfi = map->fldrv_priv;
473 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
475 map_write(map, CMD(0xF0), adr);
479 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
481 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
482 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
483 * command is issued after an ERASE RESUME operation without waiting for a
484 * minimum delay. The result is that once the ERASE seems to be completed
485 * (no bits are toggling), the contents of the Flash memory block on which
486 * the erase was ongoing could be inconsistent with the expected values
487 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
488 * values), causing a consequent failure of the ERASE operation.
489 * The occurrence of this issue could be high, especially when file system
490 * operations on the Flash are intensive. As a result, it is recommended
491 * that a patch be applied. Intensive file system operations can cause many
492 * calls to the garbage routine to free Flash space (also by erasing physical
493 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
494 * commands can occur. The problem disappears when a delay is inserted after
495 * the RESUME command by using the udelay() function available in Linux.
496 * The DELAY value must be tuned based on the customer's platform.
497 * The maximum value that fixes the problem in all cases is 500us.
498 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
500 * We have chosen 500µs because this latency is acceptable.
502 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
505 * Resolving the Delay After Resume Issue see Micron TN-13-07
506 * Worst case delay must be 500µs but 30-50µs should be ok as well
512 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
514 struct cfi_private *cfi = map->fldrv_priv;
515 struct device_node __maybe_unused *np = map->device_node;
516 struct mtd_info *mtd;
519 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
523 mtd->type = MTD_NORFLASH;
525 /* Fill in the default mtd operations */
526 mtd->_erase = cfi_amdstd_erase_varsize;
527 mtd->_write = cfi_amdstd_write_words;
528 mtd->_read = cfi_amdstd_read;
529 mtd->_sync = cfi_amdstd_sync;
530 mtd->_suspend = cfi_amdstd_suspend;
531 mtd->_resume = cfi_amdstd_resume;
532 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
533 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
534 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
535 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
536 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
537 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
538 mtd->flags = MTD_CAP_NORFLASH;
539 mtd->name = map->name;
541 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
543 pr_debug("MTD %s(): write buffer size %d\n", __func__,
546 mtd->_panic_write = cfi_amdstd_panic_write;
547 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
549 if (cfi->cfi_mode==CFI_MODE_CFI){
550 unsigned char bootloc;
551 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
552 struct cfi_pri_amdstd *extp;
554 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
557 * It's a real CFI chip, not one for which the probe
558 * routine faked a CFI structure.
560 cfi_fixup_major_minor(cfi, extp);
563 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
564 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
565 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
566 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
567 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
569 if (extp->MajorVersion != '1' ||
570 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
571 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
572 "version %c.%c (%#02x/%#02x).\n",
573 extp->MajorVersion, extp->MinorVersion,
574 extp->MajorVersion, extp->MinorVersion);
580 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
581 extp->MajorVersion, extp->MinorVersion);
583 /* Install our own private info structure */
584 cfi->cmdset_priv = extp;
586 /* Apply cfi device specific fixups */
587 cfi_fixup(mtd, cfi_fixup_table);
589 #ifdef DEBUG_CFI_FEATURES
590 /* Tell the user about it in lots of lovely detail */
591 cfi_tell_features(extp);
595 if (np && of_property_read_bool(
596 np, "use-advanced-sector-protection")
597 && extp->BlkProtUnprot == 8) {
598 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
599 mtd->_lock = cfi_ppb_lock;
600 mtd->_unlock = cfi_ppb_unlock;
601 mtd->_is_locked = cfi_ppb_is_locked;
605 bootloc = extp->TopBottom;
606 if ((bootloc < 2) || (bootloc > 5)) {
607 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
608 "bank location (%d). Assuming bottom.\n",
613 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
614 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
616 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
617 int j = (cfi->cfiq->NumEraseRegions-1)-i;
620 swap = cfi->cfiq->EraseRegionInfo[i];
621 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
622 cfi->cfiq->EraseRegionInfo[j] = swap;
625 /* Set the default CFI lock/unlock addresses */
626 cfi->addr_unlock1 = 0x555;
627 cfi->addr_unlock2 = 0x2aa;
629 cfi_fixup(mtd, cfi_nopri_fixup_table);
631 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
637 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
638 /* Apply jedec specific fixups */
639 cfi_fixup(mtd, jedec_fixup_table);
641 /* Apply generic fixups */
642 cfi_fixup(mtd, fixup_table);
644 for (i=0; i< cfi->numchips; i++) {
645 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
646 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
647 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
649 * First calculate the timeout max according to timeout field
650 * of struct cfi_ident that probed from chip's CFI aera, if
651 * available. Specify a minimum of 2000us, in case the CFI data
654 if (cfi->cfiq->BufWriteTimeoutTyp &&
655 cfi->cfiq->BufWriteTimeoutMax)
656 cfi->chips[i].buffer_write_time_max =
657 1 << (cfi->cfiq->BufWriteTimeoutTyp +
658 cfi->cfiq->BufWriteTimeoutMax);
660 cfi->chips[i].buffer_write_time_max = 0;
662 cfi->chips[i].buffer_write_time_max =
663 max(cfi->chips[i].buffer_write_time_max, 2000);
665 cfi->chips[i].ref_point_counter = 0;
666 init_waitqueue_head(&(cfi->chips[i].wq));
669 map->fldrv = &cfi_amdstd_chipdrv;
671 return cfi_amdstd_setup(mtd);
673 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
674 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
675 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
676 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
677 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
679 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
681 struct map_info *map = mtd->priv;
682 struct cfi_private *cfi = map->fldrv_priv;
683 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
684 unsigned long offset = 0;
687 printk(KERN_NOTICE "number of %s chips: %d\n",
688 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
689 /* Select the correct geometry setup */
690 mtd->size = devsize * cfi->numchips;
692 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
693 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
694 * mtd->numeraseregions, GFP_KERNEL);
695 if (!mtd->eraseregions)
698 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
699 unsigned long ernum, ersize;
700 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
701 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
703 if (mtd->erasesize < ersize) {
704 mtd->erasesize = ersize;
706 for (j=0; j<cfi->numchips; j++) {
707 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
708 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
709 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
711 offset += (ersize * ernum);
713 if (offset != devsize) {
715 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
719 __module_get(THIS_MODULE);
720 register_reboot_notifier(&mtd->reboot_notifier);
724 kfree(mtd->eraseregions);
726 kfree(cfi->cmdset_priv);
732 * Return true if the chip is ready.
734 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
735 * non-suspended sector) and is indicated by no toggle bits toggling.
737 * Note that anything more complicated than checking if no bits are toggling
738 * (including checking DQ5 for an error status) is tricky to get working
739 * correctly and is therefore not done (particularly with interleaved chips
740 * as each chip must be checked independently of the others).
742 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
746 d = map_read(map, addr);
747 t = map_read(map, addr);
749 return map_word_equal(map, d, t);
753 * Return true if the chip is ready and has the correct value.
755 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
756 * non-suspended sector) and it is indicated by no bits toggling.
758 * Error are indicated by toggling bits or bits held with the wrong value,
759 * or with bits toggling.
761 * Note that anything more complicated than checking if no bits are toggling
762 * (including checking DQ5 for an error status) is tricky to get working
763 * correctly and is therefore not done (particularly with interleaved chips
764 * as each chip must be checked independently of the others).
767 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
771 oldd = map_read(map, addr);
772 curd = map_read(map, addr);
774 return map_word_equal(map, oldd, curd) &&
775 map_word_equal(map, curd, expected);
778 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
780 DECLARE_WAITQUEUE(wait, current);
781 struct cfi_private *cfi = map->fldrv_priv;
783 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
786 timeo = jiffies + HZ;
788 switch (chip->state) {
792 if (chip_ready(map, adr))
795 if (time_after(jiffies, timeo)) {
796 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
799 mutex_unlock(&chip->mutex);
801 mutex_lock(&chip->mutex);
802 /* Someone else might have been playing with it. */
812 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
813 !(mode == FL_READY || mode == FL_POINT ||
814 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
817 /* Do not allow suspend iff read/write to EB address */
818 if ((adr & chip->in_progress_block_mask) ==
819 chip->in_progress_block_addr)
823 /* It's harmless to issue the Erase-Suspend and Erase-Resume
824 * commands when the erase algorithm isn't in progress. */
825 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
826 chip->oldstate = FL_ERASING;
827 chip->state = FL_ERASE_SUSPENDING;
828 chip->erase_suspended = 1;
830 if (chip_ready(map, adr))
833 if (time_after(jiffies, timeo)) {
834 /* Should have suspended the erase by now.
835 * Send an Erase-Resume command as either
836 * there was an error (so leave the erase
837 * routine to recover from it) or we trying to
838 * use the erase-in-progress sector. */
839 put_chip(map, chip, adr);
840 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
844 mutex_unlock(&chip->mutex);
846 mutex_lock(&chip->mutex);
847 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
848 So we can just loop here. */
850 chip->state = FL_READY;
853 case FL_XIP_WHILE_ERASING:
854 if (mode != FL_READY && mode != FL_POINT &&
855 (!cfip || !(cfip->EraseSuspend&2)))
857 chip->oldstate = chip->state;
858 chip->state = FL_READY;
862 /* The machine is rebooting */
866 /* Only if there's no operation suspended... */
867 if (mode == FL_READY && chip->oldstate == FL_READY)
872 set_current_state(TASK_UNINTERRUPTIBLE);
873 add_wait_queue(&chip->wq, &wait);
874 mutex_unlock(&chip->mutex);
876 remove_wait_queue(&chip->wq, &wait);
877 mutex_lock(&chip->mutex);
883 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
885 struct cfi_private *cfi = map->fldrv_priv;
887 switch(chip->oldstate) {
889 cfi_fixup_m29ew_erase_suspend(map,
890 chip->in_progress_block_addr);
891 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
892 cfi_fixup_m29ew_delay_after_resume(cfi);
893 chip->oldstate = FL_READY;
894 chip->state = FL_ERASING;
897 case FL_XIP_WHILE_ERASING:
898 chip->state = chip->oldstate;
899 chip->oldstate = FL_READY;
906 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
911 #ifdef CONFIG_MTD_XIP
914 * No interrupt what so ever can be serviced while the flash isn't in array
915 * mode. This is ensured by the xip_disable() and xip_enable() functions
916 * enclosing any code path where the flash is known not to be in array mode.
917 * And within a XIP disabled code path, only functions marked with __xipram
918 * may be called and nothing else (it's a good thing to inspect generated
919 * assembly to make sure inline functions were actually inlined and that gcc
920 * didn't emit calls to its own support functions). Also configuring MTD CFI
921 * support to a single buswidth and a single interleave is also recommended.
924 static void xip_disable(struct map_info *map, struct flchip *chip,
927 /* TODO: chips with no XIP use should ignore and return */
928 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
932 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
935 struct cfi_private *cfi = map->fldrv_priv;
937 if (chip->state != FL_POINT && chip->state != FL_READY) {
938 map_write(map, CMD(0xf0), adr);
939 chip->state = FL_READY;
941 (void) map_read(map, adr);
947 * When a delay is required for the flash operation to complete, the
948 * xip_udelay() function is polling for both the given timeout and pending
949 * (but still masked) hardware interrupts. Whenever there is an interrupt
950 * pending then the flash erase operation is suspended, array mode restored
951 * and interrupts unmasked. Task scheduling might also happen at that
952 * point. The CPU eventually returns from the interrupt or the call to
953 * schedule() and the suspended flash operation is resumed for the remaining
954 * of the delay period.
956 * Warning: this function _will_ fool interrupt latency tracing tools.
959 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
960 unsigned long adr, int usec)
962 struct cfi_private *cfi = map->fldrv_priv;
963 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
964 map_word status, OK = CMD(0x80);
965 unsigned long suspended, start = xip_currtime();
970 if (xip_irqpending() && extp &&
971 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
972 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
974 * Let's suspend the erase operation when supported.
975 * Note that we currently don't try to suspend
976 * interleaved chips if there is already another
977 * operation suspended (imagine what happens
978 * when one chip was already done with the current
979 * operation while another chip suspended it, then
980 * we resume the whole thing at once). Yes, it
983 map_write(map, CMD(0xb0), adr);
984 usec -= xip_elapsed_since(start);
985 suspended = xip_currtime();
987 if (xip_elapsed_since(suspended) > 100000) {
989 * The chip doesn't want to suspend
990 * after waiting for 100 msecs.
991 * This is a critical error but there
992 * is not much we can do here.
996 status = map_read(map, adr);
997 } while (!map_word_andequal(map, status, OK, OK));
999 /* Suspend succeeded */
1000 oldstate = chip->state;
1001 if (!map_word_bitsset(map, status, CMD(0x40)))
1003 chip->state = FL_XIP_WHILE_ERASING;
1004 chip->erase_suspended = 1;
1005 map_write(map, CMD(0xf0), adr);
1006 (void) map_read(map, adr);
1009 mutex_unlock(&chip->mutex);
1014 * We're back. However someone else might have
1015 * decided to go write to the chip if we are in
1016 * a suspended erase state. If so let's wait
1019 mutex_lock(&chip->mutex);
1020 while (chip->state != FL_XIP_WHILE_ERASING) {
1021 DECLARE_WAITQUEUE(wait, current);
1022 set_current_state(TASK_UNINTERRUPTIBLE);
1023 add_wait_queue(&chip->wq, &wait);
1024 mutex_unlock(&chip->mutex);
1026 remove_wait_queue(&chip->wq, &wait);
1027 mutex_lock(&chip->mutex);
1029 /* Disallow XIP again */
1030 local_irq_disable();
1032 /* Correct Erase Suspend Hangups for M29EW */
1033 cfi_fixup_m29ew_erase_suspend(map, adr);
1034 /* Resume the write or erase operation */
1035 map_write(map, cfi->sector_erase_cmd, adr);
1036 chip->state = oldstate;
1037 start = xip_currtime();
1038 } else if (usec >= 1000000/HZ) {
1040 * Try to save on CPU power when waiting delay
1041 * is at least a system timer tick period.
1042 * No need to be extremely accurate here.
1046 status = map_read(map, adr);
1047 } while (!map_word_andequal(map, status, OK, OK)
1048 && xip_elapsed_since(start) < usec);
1051 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1054 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1055 * the flash is actively programming or erasing since we have to poll for
1056 * the operation to complete anyway. We can't do that in a generic way with
1057 * a XIP setup so do it before the actual flash operation in this case
1058 * and stub it out from INVALIDATE_CACHE_UDELAY.
1060 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1061 INVALIDATE_CACHED_RANGE(map, from, size)
1063 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1064 UDELAY(map, chip, adr, usec)
1069 * Activating this XIP support changes the way the code works a bit. For
1070 * example the code to suspend the current process when concurrent access
1071 * happens is never executed because xip_udelay() will always return with the
1072 * same chip state as it was entered with. This is why there is no care for
1073 * the presence of add_wait_queue() or schedule() calls from within a couple
1074 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1075 * The queueing and scheduling are always happening within xip_udelay().
1077 * Similarly, get_chip() and put_chip() just happen to always be executed
1078 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1079 * is in array mode, therefore never executing many cases therein and not
1080 * causing any problem with XIP.
1085 #define xip_disable(map, chip, adr)
1086 #define xip_enable(map, chip, adr)
1087 #define XIP_INVAL_CACHED_RANGE(x...)
1089 #define UDELAY(map, chip, adr, usec) \
1091 mutex_unlock(&chip->mutex); \
1093 mutex_lock(&chip->mutex); \
1096 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1098 mutex_unlock(&chip->mutex); \
1099 INVALIDATE_CACHED_RANGE(map, adr, len); \
1101 mutex_lock(&chip->mutex); \
1106 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1108 unsigned long cmd_addr;
1109 struct cfi_private *cfi = map->fldrv_priv;
1114 /* Ensure cmd read/writes are aligned. */
1115 cmd_addr = adr & ~(map_bankwidth(map)-1);
1117 mutex_lock(&chip->mutex);
1118 ret = get_chip(map, chip, cmd_addr, FL_READY);
1120 mutex_unlock(&chip->mutex);
1124 if (chip->state != FL_POINT && chip->state != FL_READY) {
1125 map_write(map, CMD(0xf0), cmd_addr);
1126 chip->state = FL_READY;
1129 map_copy_from(map, buf, adr, len);
1131 put_chip(map, chip, cmd_addr);
1133 mutex_unlock(&chip->mutex);
1138 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1140 struct map_info *map = mtd->priv;
1141 struct cfi_private *cfi = map->fldrv_priv;
1146 /* ofs: offset within the first chip that the first read should start */
1147 chipnum = (from >> cfi->chipshift);
1148 ofs = from - (chipnum << cfi->chipshift);
1151 unsigned long thislen;
1153 if (chipnum >= cfi->numchips)
1156 if ((len + ofs -1) >> cfi->chipshift)
1157 thislen = (1<<cfi->chipshift) - ofs;
1161 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1175 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1176 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1178 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1179 loff_t adr, size_t len)
1181 struct cfi_private *cfi = map->fldrv_priv;
1183 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1184 cfi->device_type, NULL);
1185 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1186 cfi->device_type, NULL);
1187 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1188 cfi->device_type, NULL);
1190 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1193 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1194 loff_t adr, size_t len)
1196 struct cfi_private *cfi = map->fldrv_priv;
1198 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1199 cfi->device_type, NULL);
1200 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1201 cfi->device_type, NULL);
1202 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1203 cfi->device_type, NULL);
1204 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1205 cfi->device_type, NULL);
1207 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1210 static inline int do_read_secsi_onechip(struct map_info *map,
1211 struct flchip *chip, loff_t adr,
1212 size_t len, u_char *buf,
1215 DECLARE_WAITQUEUE(wait, current);
1216 unsigned long timeo = jiffies + HZ;
1219 mutex_lock(&chip->mutex);
1221 if (chip->state != FL_READY){
1222 set_current_state(TASK_UNINTERRUPTIBLE);
1223 add_wait_queue(&chip->wq, &wait);
1225 mutex_unlock(&chip->mutex);
1228 remove_wait_queue(&chip->wq, &wait);
1229 timeo = jiffies + HZ;
1236 chip->state = FL_READY;
1238 otp_enter(map, chip, adr, len);
1239 map_copy_from(map, buf, adr, len);
1240 otp_exit(map, chip, adr, len);
1243 mutex_unlock(&chip->mutex);
1248 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1250 struct map_info *map = mtd->priv;
1251 struct cfi_private *cfi = map->fldrv_priv;
1256 /* ofs: offset within the first chip that the first read should start */
1257 /* 8 secsi bytes per chip */
1262 unsigned long thislen;
1264 if (chipnum >= cfi->numchips)
1267 if ((len + ofs -1) >> 3)
1268 thislen = (1<<3) - ofs;
1272 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1287 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1288 unsigned long adr, map_word datum,
1291 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1292 size_t len, u_char *buf, size_t grouplen)
1296 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1297 int gap = adr - bus_ofs;
1298 int n = min_t(int, len, map_bankwidth(map) - gap);
1299 map_word datum = map_word_ff(map);
1301 if (n != map_bankwidth(map)) {
1302 /* partial write of a word, load old contents */
1303 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1304 datum = map_read(map, bus_ofs);
1305 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1308 datum = map_word_load_partial(map, datum, buf, gap, n);
1309 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1321 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1322 size_t len, u_char *buf, size_t grouplen)
1324 struct cfi_private *cfi = map->fldrv_priv;
1326 unsigned long timeo;
1329 /* make sure area matches group boundaries */
1330 if ((adr != 0) || (len != grouplen))
1333 mutex_lock(&chip->mutex);
1334 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1336 mutex_unlock(&chip->mutex);
1339 chip->state = FL_LOCKING;
1341 /* Enter lock register command */
1342 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1343 cfi->device_type, NULL);
1344 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1345 cfi->device_type, NULL);
1346 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1347 cfi->device_type, NULL);
1349 /* read lock register */
1350 lockreg = cfi_read_query(map, 0);
1352 /* set bit 0 to protect extended memory block */
1355 /* set bit 0 to protect extended memory block */
1356 /* write lock register */
1357 map_write(map, CMD(0xA0), chip->start);
1358 map_write(map, CMD(lockreg), chip->start);
1360 /* wait for chip to become ready */
1361 timeo = jiffies + msecs_to_jiffies(2);
1363 if (chip_ready(map, adr))
1366 if (time_after(jiffies, timeo)) {
1367 pr_err("Waiting for chip to be ready timed out.\n");
1371 UDELAY(map, chip, 0, 1);
1374 /* exit protection commands */
1375 map_write(map, CMD(0x90), chip->start);
1376 map_write(map, CMD(0x00), chip->start);
1378 chip->state = FL_READY;
1379 put_chip(map, chip, chip->start);
1380 mutex_unlock(&chip->mutex);
1385 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1386 size_t *retlen, u_char *buf,
1387 otp_op_t action, int user_regs)
1389 struct map_info *map = mtd->priv;
1390 struct cfi_private *cfi = map->fldrv_priv;
1391 int ofs_factor = cfi->interleave * cfi->device_type;
1394 struct flchip *chip;
1395 uint8_t otp, lockreg;
1398 size_t user_size, factory_size, otpsize;
1399 loff_t user_offset, factory_offset, otpoffset;
1400 int user_locked = 0, otplocked;
1404 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1405 chip = &cfi->chips[chipnum];
1409 /* Micron M29EW family */
1410 if (is_m29ew(cfi)) {
1413 /* check whether secsi area is factory locked
1415 mutex_lock(&chip->mutex);
1416 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1418 mutex_unlock(&chip->mutex);
1421 cfi_qry_mode_on(base, map, cfi);
1422 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1423 cfi_qry_mode_off(base, map, cfi);
1424 put_chip(map, chip, base);
1425 mutex_unlock(&chip->mutex);
1428 /* factory locked */
1430 factory_size = 0x100;
1432 /* customer lockable */
1436 mutex_lock(&chip->mutex);
1437 ret = get_chip(map, chip, base, FL_LOCKING);
1439 mutex_unlock(&chip->mutex);
1443 /* Enter lock register command */
1444 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1445 chip->start, map, cfi,
1446 cfi->device_type, NULL);
1447 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1448 chip->start, map, cfi,
1449 cfi->device_type, NULL);
1450 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1451 chip->start, map, cfi,
1452 cfi->device_type, NULL);
1453 /* read lock register */
1454 lockreg = cfi_read_query(map, 0);
1455 /* exit protection commands */
1456 map_write(map, CMD(0x90), chip->start);
1457 map_write(map, CMD(0x00), chip->start);
1458 put_chip(map, chip, chip->start);
1459 mutex_unlock(&chip->mutex);
1461 user_locked = ((lockreg & 0x01) == 0x00);
1465 otpsize = user_regs ? user_size : factory_size;
1468 otpoffset = user_regs ? user_offset : factory_offset;
1469 otplocked = user_regs ? user_locked : 1;
1472 /* return otpinfo */
1473 struct otp_info *otpinfo;
1474 len -= sizeof(*otpinfo);
1477 otpinfo = (struct otp_info *)buf;
1478 otpinfo->start = from;
1479 otpinfo->length = otpsize;
1480 otpinfo->locked = otplocked;
1481 buf += sizeof(*otpinfo);
1482 *retlen += sizeof(*otpinfo);
1484 } else if ((from < otpsize) && (len > 0)) {
1486 size = (len < otpsize - from) ? len : otpsize - from;
1487 ret = action(map, chip, otpoffset + from, size, buf,
1503 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1504 size_t *retlen, struct otp_info *buf)
1506 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1510 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1511 size_t *retlen, struct otp_info *buf)
1513 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1517 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1518 size_t len, size_t *retlen,
1521 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1522 buf, do_read_secsi_onechip, 0);
1525 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1526 size_t len, size_t *retlen,
1529 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1530 buf, do_read_secsi_onechip, 1);
1533 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1534 size_t len, size_t *retlen,
1537 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1541 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1545 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1549 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1550 unsigned long adr, map_word datum,
1553 struct cfi_private *cfi = map->fldrv_priv;
1554 unsigned long timeo = jiffies + HZ;
1556 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1557 * have a max write time of a few hundreds usec). However, we should
1558 * use the maximum timeout value given by the chip at probe time
1559 * instead. Unfortunately, struct flchip does have a field for
1560 * maximum timeout, only for typical which can be far too short
1561 * depending of the conditions. The ' + 1' is to avoid having a
1562 * timeout of 0 jiffies if HZ is smaller than 1000.
1564 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1571 mutex_lock(&chip->mutex);
1572 ret = get_chip(map, chip, adr, mode);
1574 mutex_unlock(&chip->mutex);
1578 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1579 __func__, adr, datum.x[0] );
1581 if (mode == FL_OTP_WRITE)
1582 otp_enter(map, chip, adr, map_bankwidth(map));
1585 * Check for a NOP for the case when the datum to write is already
1586 * present - it saves time and works around buggy chips that corrupt
1587 * data at other locations when 0xff is written to a location that
1588 * already contains 0xff.
1590 oldd = map_read(map, adr);
1591 if (map_word_equal(map, oldd, datum)) {
1592 pr_debug("MTD %s(): NOP\n",
1597 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1599 xip_disable(map, chip, adr);
1602 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1603 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1604 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1605 map_write(map, datum, adr);
1608 INVALIDATE_CACHE_UDELAY(map, chip,
1609 adr, map_bankwidth(map),
1610 chip->word_write_time);
1612 /* See comment above for timeout value. */
1613 timeo = jiffies + uWriteTimeout;
1615 if (chip->state != mode) {
1616 /* Someone's suspended the write. Sleep */
1617 DECLARE_WAITQUEUE(wait, current);
1619 set_current_state(TASK_UNINTERRUPTIBLE);
1620 add_wait_queue(&chip->wq, &wait);
1621 mutex_unlock(&chip->mutex);
1623 remove_wait_queue(&chip->wq, &wait);
1624 timeo = jiffies + (HZ / 2); /* FIXME */
1625 mutex_lock(&chip->mutex);
1630 * We check "time_after" and "!chip_good" before checking
1631 * "chip_good" to avoid the failure due to scheduling.
1633 if (time_after(jiffies, timeo) && !chip_good(map, adr, datum)) {
1634 xip_enable(map, chip, adr);
1635 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1636 xip_disable(map, chip, adr);
1641 if (chip_good(map, adr, datum))
1644 /* Latency issues. Drop the lock, wait a while and retry */
1645 UDELAY(map, chip, adr, 1);
1648 /* Did we succeed? */
1650 /* reset on all failures. */
1651 map_write( map, CMD(0xF0), chip->start );
1652 /* FIXME - should have reset delay before continuing */
1654 if (++retry_cnt <= MAX_RETRIES) {
1659 xip_enable(map, chip, adr);
1661 if (mode == FL_OTP_WRITE)
1662 otp_exit(map, chip, adr, map_bankwidth(map));
1663 chip->state = FL_READY;
1665 put_chip(map, chip, adr);
1666 mutex_unlock(&chip->mutex);
1672 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1673 size_t *retlen, const u_char *buf)
1675 struct map_info *map = mtd->priv;
1676 struct cfi_private *cfi = map->fldrv_priv;
1679 unsigned long ofs, chipstart;
1680 DECLARE_WAITQUEUE(wait, current);
1682 chipnum = to >> cfi->chipshift;
1683 ofs = to - (chipnum << cfi->chipshift);
1684 chipstart = cfi->chips[chipnum].start;
1686 /* If it's not bus-aligned, do the first byte write */
1687 if (ofs & (map_bankwidth(map)-1)) {
1688 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1689 int i = ofs - bus_ofs;
1694 mutex_lock(&cfi->chips[chipnum].mutex);
1696 if (cfi->chips[chipnum].state != FL_READY) {
1697 set_current_state(TASK_UNINTERRUPTIBLE);
1698 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1700 mutex_unlock(&cfi->chips[chipnum].mutex);
1703 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1707 /* Load 'tmp_buf' with old contents of flash */
1708 tmp_buf = map_read(map, bus_ofs+chipstart);
1710 mutex_unlock(&cfi->chips[chipnum].mutex);
1712 /* Number of bytes to copy from buffer */
1713 n = min_t(int, len, map_bankwidth(map)-i);
1715 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1717 ret = do_write_oneword(map, &cfi->chips[chipnum],
1718 bus_ofs, tmp_buf, FL_WRITING);
1727 if (ofs >> cfi->chipshift) {
1730 if (chipnum == cfi->numchips)
1735 /* We are now aligned, write as much as possible */
1736 while(len >= map_bankwidth(map)) {
1739 datum = map_word_load(map, buf);
1741 ret = do_write_oneword(map, &cfi->chips[chipnum],
1742 ofs, datum, FL_WRITING);
1746 ofs += map_bankwidth(map);
1747 buf += map_bankwidth(map);
1748 (*retlen) += map_bankwidth(map);
1749 len -= map_bankwidth(map);
1751 if (ofs >> cfi->chipshift) {
1754 if (chipnum == cfi->numchips)
1756 chipstart = cfi->chips[chipnum].start;
1760 /* Write the trailing bytes if any */
1761 if (len & (map_bankwidth(map)-1)) {
1765 mutex_lock(&cfi->chips[chipnum].mutex);
1767 if (cfi->chips[chipnum].state != FL_READY) {
1768 set_current_state(TASK_UNINTERRUPTIBLE);
1769 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1771 mutex_unlock(&cfi->chips[chipnum].mutex);
1774 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1778 tmp_buf = map_read(map, ofs + chipstart);
1780 mutex_unlock(&cfi->chips[chipnum].mutex);
1782 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1784 ret = do_write_oneword(map, &cfi->chips[chipnum],
1785 ofs, tmp_buf, FL_WRITING);
1797 * FIXME: interleaved mode not tested, and probably not supported!
1799 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1800 unsigned long adr, const u_char *buf,
1803 struct cfi_private *cfi = map->fldrv_priv;
1804 unsigned long timeo = jiffies + HZ;
1806 * Timeout is calculated according to CFI data, if available.
1807 * See more comments in cfi_cmdset_0002().
1809 unsigned long uWriteTimeout =
1810 usecs_to_jiffies(chip->buffer_write_time_max);
1812 unsigned long cmd_adr;
1819 mutex_lock(&chip->mutex);
1820 ret = get_chip(map, chip, adr, FL_WRITING);
1822 mutex_unlock(&chip->mutex);
1826 datum = map_word_load(map, buf);
1828 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1829 __func__, adr, datum.x[0] );
1831 XIP_INVAL_CACHED_RANGE(map, adr, len);
1833 xip_disable(map, chip, cmd_adr);
1835 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1836 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1838 /* Write Buffer Load */
1839 map_write(map, CMD(0x25), cmd_adr);
1841 chip->state = FL_WRITING_TO_BUFFER;
1843 /* Write length of data to come */
1844 words = len / map_bankwidth(map);
1845 map_write(map, CMD(words - 1), cmd_adr);
1848 while(z < words * map_bankwidth(map)) {
1849 datum = map_word_load(map, buf);
1850 map_write(map, datum, adr + z);
1852 z += map_bankwidth(map);
1853 buf += map_bankwidth(map);
1855 z -= map_bankwidth(map);
1859 /* Write Buffer Program Confirm: GO GO GO */
1860 map_write(map, CMD(0x29), cmd_adr);
1861 chip->state = FL_WRITING;
1863 INVALIDATE_CACHE_UDELAY(map, chip,
1864 adr, map_bankwidth(map),
1865 chip->word_write_time);
1867 timeo = jiffies + uWriteTimeout;
1870 if (chip->state != FL_WRITING) {
1871 /* Someone's suspended the write. Sleep */
1872 DECLARE_WAITQUEUE(wait, current);
1874 set_current_state(TASK_UNINTERRUPTIBLE);
1875 add_wait_queue(&chip->wq, &wait);
1876 mutex_unlock(&chip->mutex);
1878 remove_wait_queue(&chip->wq, &wait);
1879 timeo = jiffies + (HZ / 2); /* FIXME */
1880 mutex_lock(&chip->mutex);
1885 * We check "time_after" and "!chip_good" before checking "chip_good" to avoid
1886 * the failure due to scheduling.
1888 if (time_after(jiffies, timeo) && !chip_good(map, adr, datum))
1891 if (chip_good(map, adr, datum)) {
1892 xip_enable(map, chip, adr);
1896 /* Latency issues. Drop the lock, wait a while and retry */
1897 UDELAY(map, chip, adr, 1);
1901 * Recovery from write-buffer programming failures requires
1902 * the write-to-buffer-reset sequence. Since the last part
1903 * of the sequence also works as a normal reset, we can run
1904 * the same commands regardless of why we are here.
1906 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
1908 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1909 cfi->device_type, NULL);
1910 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1911 cfi->device_type, NULL);
1912 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
1913 cfi->device_type, NULL);
1914 xip_enable(map, chip, adr);
1915 /* FIXME - should have reset delay before continuing */
1917 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n",
1922 chip->state = FL_READY;
1924 put_chip(map, chip, adr);
1925 mutex_unlock(&chip->mutex);
1931 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1932 size_t *retlen, const u_char *buf)
1934 struct map_info *map = mtd->priv;
1935 struct cfi_private *cfi = map->fldrv_priv;
1936 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1941 chipnum = to >> cfi->chipshift;
1942 ofs = to - (chipnum << cfi->chipshift);
1944 /* If it's not bus-aligned, do the first word write */
1945 if (ofs & (map_bankwidth(map)-1)) {
1946 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1947 if (local_len > len)
1949 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1950 local_len, retlen, buf);
1957 if (ofs >> cfi->chipshift) {
1960 if (chipnum == cfi->numchips)
1965 /* Write buffer is worth it only if more than one word to write... */
1966 while (len >= map_bankwidth(map) * 2) {
1967 /* We must not cross write block boundaries */
1968 int size = wbufsize - (ofs & (wbufsize-1));
1972 if (size % map_bankwidth(map))
1973 size -= size % map_bankwidth(map);
1975 ret = do_write_buffer(map, &cfi->chips[chipnum],
1985 if (ofs >> cfi->chipshift) {
1988 if (chipnum == cfi->numchips)
1994 size_t retlen_dregs = 0;
1996 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1997 len, &retlen_dregs, buf);
1999 *retlen += retlen_dregs;
2007 * Wait for the flash chip to become ready to write data
2009 * This is only called during the panic_write() path. When panic_write()
2010 * is called, the kernel is in the process of a panic, and will soon be
2011 * dead. Therefore we don't take any locks, and attempt to get access
2012 * to the chip as soon as possible.
2014 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2017 struct cfi_private *cfi = map->fldrv_priv;
2022 * If the driver thinks the chip is idle, and no toggle bits
2023 * are changing, then the chip is actually idle for sure.
2025 if (chip->state == FL_READY && chip_ready(map, adr))
2029 * Try several times to reset the chip and then wait for it
2030 * to become idle. The upper limit of a few milliseconds of
2031 * delay isn't a big problem: the kernel is dying anyway. It
2032 * is more important to save the messages.
2034 while (retries > 0) {
2035 const unsigned long timeo = (HZ / 1000) + 1;
2037 /* send the reset command */
2038 map_write(map, CMD(0xF0), chip->start);
2040 /* wait for the chip to become ready */
2041 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2042 if (chip_ready(map, adr))
2051 /* the chip never became ready */
2056 * Write out one word of data to a single flash chip during a kernel panic
2058 * This is only called during the panic_write() path. When panic_write()
2059 * is called, the kernel is in the process of a panic, and will soon be
2060 * dead. Therefore we don't take any locks, and attempt to get access
2061 * to the chip as soon as possible.
2063 * The implementation of this routine is intentionally similar to
2064 * do_write_oneword(), in order to ease code maintenance.
2066 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2067 unsigned long adr, map_word datum)
2069 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2070 struct cfi_private *cfi = map->fldrv_priv;
2078 ret = cfi_amdstd_panic_wait(map, chip, adr);
2082 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2083 __func__, adr, datum.x[0]);
2086 * Check for a NOP for the case when the datum to write is already
2087 * present - it saves time and works around buggy chips that corrupt
2088 * data at other locations when 0xff is written to a location that
2089 * already contains 0xff.
2091 oldd = map_read(map, adr);
2092 if (map_word_equal(map, oldd, datum)) {
2093 pr_debug("MTD %s(): NOP\n", __func__);
2100 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2101 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2102 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2103 map_write(map, datum, adr);
2105 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2106 if (chip_ready(map, adr))
2112 if (!chip_good(map, adr, datum)) {
2113 /* reset on all failures. */
2114 map_write(map, CMD(0xF0), chip->start);
2115 /* FIXME - should have reset delay before continuing */
2117 if (++retry_cnt <= MAX_RETRIES)
2129 * Write out some data during a kernel panic
2131 * This is used by the mtdoops driver to save the dying messages from a
2132 * kernel which has panic'd.
2134 * This routine ignores all of the locking used throughout the rest of the
2135 * driver, in order to ensure that the data gets written out no matter what
2136 * state this driver (and the flash chip itself) was in when the kernel crashed.
2138 * The implementation of this routine is intentionally similar to
2139 * cfi_amdstd_write_words(), in order to ease code maintenance.
2141 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2142 size_t *retlen, const u_char *buf)
2144 struct map_info *map = mtd->priv;
2145 struct cfi_private *cfi = map->fldrv_priv;
2146 unsigned long ofs, chipstart;
2150 chipnum = to >> cfi->chipshift;
2151 ofs = to - (chipnum << cfi->chipshift);
2152 chipstart = cfi->chips[chipnum].start;
2154 /* If it's not bus aligned, do the first byte write */
2155 if (ofs & (map_bankwidth(map) - 1)) {
2156 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2157 int i = ofs - bus_ofs;
2161 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2165 /* Load 'tmp_buf' with old contents of flash */
2166 tmp_buf = map_read(map, bus_ofs + chipstart);
2168 /* Number of bytes to copy from buffer */
2169 n = min_t(int, len, map_bankwidth(map) - i);
2171 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2173 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2183 if (ofs >> cfi->chipshift) {
2186 if (chipnum == cfi->numchips)
2191 /* We are now aligned, write as much as possible */
2192 while (len >= map_bankwidth(map)) {
2195 datum = map_word_load(map, buf);
2197 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2202 ofs += map_bankwidth(map);
2203 buf += map_bankwidth(map);
2204 (*retlen) += map_bankwidth(map);
2205 len -= map_bankwidth(map);
2207 if (ofs >> cfi->chipshift) {
2210 if (chipnum == cfi->numchips)
2213 chipstart = cfi->chips[chipnum].start;
2217 /* Write the trailing bytes if any */
2218 if (len & (map_bankwidth(map) - 1)) {
2221 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2225 tmp_buf = map_read(map, ofs + chipstart);
2227 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2229 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2242 * Handle devices with one erase region, that only implement
2243 * the chip erase command.
2245 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2247 struct cfi_private *cfi = map->fldrv_priv;
2248 unsigned long timeo = jiffies + HZ;
2249 unsigned long int adr;
2250 DECLARE_WAITQUEUE(wait, current);
2254 adr = cfi->addr_unlock1;
2256 mutex_lock(&chip->mutex);
2257 ret = get_chip(map, chip, adr, FL_WRITING);
2259 mutex_unlock(&chip->mutex);
2263 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2264 __func__, chip->start );
2266 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2268 xip_disable(map, chip, adr);
2271 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2272 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2273 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2274 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2275 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2276 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2278 chip->state = FL_ERASING;
2279 chip->erase_suspended = 0;
2280 chip->in_progress_block_addr = adr;
2281 chip->in_progress_block_mask = ~(map->size - 1);
2283 INVALIDATE_CACHE_UDELAY(map, chip,
2285 chip->erase_time*500);
2287 timeo = jiffies + (HZ*20);
2290 if (chip->state != FL_ERASING) {
2291 /* Someone's suspended the erase. Sleep */
2292 set_current_state(TASK_UNINTERRUPTIBLE);
2293 add_wait_queue(&chip->wq, &wait);
2294 mutex_unlock(&chip->mutex);
2296 remove_wait_queue(&chip->wq, &wait);
2297 mutex_lock(&chip->mutex);
2300 if (chip->erase_suspended) {
2301 /* This erase was suspended and resumed.
2302 Adjust the timeout */
2303 timeo = jiffies + (HZ*20); /* FIXME */
2304 chip->erase_suspended = 0;
2307 if (chip_good(map, adr, map_word_ff(map)))
2310 if (time_after(jiffies, timeo)) {
2311 printk(KERN_WARNING "MTD %s(): software timeout\n",
2317 /* Latency issues. Drop the lock, wait a while and retry */
2318 UDELAY(map, chip, adr, 1000000/HZ);
2320 /* Did we succeed? */
2322 /* reset on all failures. */
2323 map_write( map, CMD(0xF0), chip->start );
2324 /* FIXME - should have reset delay before continuing */
2326 if (++retry_cnt <= MAX_RETRIES) {
2332 chip->state = FL_READY;
2333 xip_enable(map, chip, adr);
2335 put_chip(map, chip, adr);
2336 mutex_unlock(&chip->mutex);
2342 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2344 struct cfi_private *cfi = map->fldrv_priv;
2345 unsigned long timeo = jiffies + HZ;
2346 DECLARE_WAITQUEUE(wait, current);
2352 mutex_lock(&chip->mutex);
2353 ret = get_chip(map, chip, adr, FL_ERASING);
2355 mutex_unlock(&chip->mutex);
2359 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2362 XIP_INVAL_CACHED_RANGE(map, adr, len);
2364 xip_disable(map, chip, adr);
2367 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2368 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2369 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2370 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2371 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2372 map_write(map, cfi->sector_erase_cmd, adr);
2374 chip->state = FL_ERASING;
2375 chip->erase_suspended = 0;
2376 chip->in_progress_block_addr = adr;
2377 chip->in_progress_block_mask = ~(len - 1);
2379 INVALIDATE_CACHE_UDELAY(map, chip,
2381 chip->erase_time*500);
2383 timeo = jiffies + (HZ*20);
2386 if (chip->state != FL_ERASING) {
2387 /* Someone's suspended the erase. Sleep */
2388 set_current_state(TASK_UNINTERRUPTIBLE);
2389 add_wait_queue(&chip->wq, &wait);
2390 mutex_unlock(&chip->mutex);
2392 remove_wait_queue(&chip->wq, &wait);
2393 mutex_lock(&chip->mutex);
2396 if (chip->erase_suspended) {
2397 /* This erase was suspended and resumed.
2398 Adjust the timeout */
2399 timeo = jiffies + (HZ*20); /* FIXME */
2400 chip->erase_suspended = 0;
2403 if (chip_good(map, adr, map_word_ff(map))) {
2404 xip_enable(map, chip, adr);
2408 if (time_after(jiffies, timeo)) {
2409 xip_enable(map, chip, adr);
2410 printk(KERN_WARNING "MTD %s(): software timeout\n",
2416 /* Latency issues. Drop the lock, wait a while and retry */
2417 UDELAY(map, chip, adr, 1000000/HZ);
2419 /* Did we succeed? */
2421 /* reset on all failures. */
2422 map_write( map, CMD(0xF0), chip->start );
2423 /* FIXME - should have reset delay before continuing */
2425 if (++retry_cnt <= MAX_RETRIES) {
2431 chip->state = FL_READY;
2433 put_chip(map, chip, adr);
2434 mutex_unlock(&chip->mutex);
2439 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2441 unsigned long ofs, len;
2447 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
2451 instr->state = MTD_ERASE_DONE;
2452 mtd_erase_callback(instr);
2458 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2460 struct map_info *map = mtd->priv;
2461 struct cfi_private *cfi = map->fldrv_priv;
2464 if (instr->addr != 0)
2467 if (instr->len != mtd->size)
2470 ret = do_erase_chip(map, &cfi->chips[0]);
2474 instr->state = MTD_ERASE_DONE;
2475 mtd_erase_callback(instr);
2480 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2481 unsigned long adr, int len, void *thunk)
2483 struct cfi_private *cfi = map->fldrv_priv;
2486 mutex_lock(&chip->mutex);
2487 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2490 chip->state = FL_LOCKING;
2492 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2494 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2495 cfi->device_type, NULL);
2496 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2497 cfi->device_type, NULL);
2498 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2499 cfi->device_type, NULL);
2500 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2501 cfi->device_type, NULL);
2502 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2503 cfi->device_type, NULL);
2504 map_write(map, CMD(0x40), chip->start + adr);
2506 chip->state = FL_READY;
2507 put_chip(map, chip, adr + chip->start);
2511 mutex_unlock(&chip->mutex);
2515 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2516 unsigned long adr, int len, void *thunk)
2518 struct cfi_private *cfi = map->fldrv_priv;
2521 mutex_lock(&chip->mutex);
2522 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2525 chip->state = FL_UNLOCKING;
2527 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2529 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2530 cfi->device_type, NULL);
2531 map_write(map, CMD(0x70), adr);
2533 chip->state = FL_READY;
2534 put_chip(map, chip, adr + chip->start);
2538 mutex_unlock(&chip->mutex);
2542 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2544 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2547 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2549 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2553 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2557 struct flchip *chip;
2562 #define MAX_SECTORS 512
2564 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2565 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2566 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2568 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2569 struct flchip *chip,
2570 unsigned long adr, int len, void *thunk)
2572 struct cfi_private *cfi = map->fldrv_priv;
2573 unsigned long timeo;
2577 mutex_lock(&chip->mutex);
2578 ret = get_chip(map, chip, adr, FL_LOCKING);
2580 mutex_unlock(&chip->mutex);
2584 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2586 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2587 cfi->device_type, NULL);
2588 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2589 cfi->device_type, NULL);
2590 /* PPB entry command */
2591 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2592 cfi->device_type, NULL);
2594 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2595 chip->state = FL_LOCKING;
2596 map_write(map, CMD(0xA0), adr);
2597 map_write(map, CMD(0x00), adr);
2598 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2600 * Unlocking of one specific sector is not supported, so we
2601 * have to unlock all sectors of this device instead
2603 chip->state = FL_UNLOCKING;
2604 map_write(map, CMD(0x80), chip->start);
2605 map_write(map, CMD(0x30), chip->start);
2606 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2607 chip->state = FL_JEDEC_QUERY;
2608 /* Return locked status: 0->locked, 1->unlocked */
2609 ret = !cfi_read_query(map, adr);
2614 * Wait for some time as unlocking of all sectors takes quite long
2616 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2618 if (chip_ready(map, adr))
2621 if (time_after(jiffies, timeo)) {
2622 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2627 UDELAY(map, chip, adr, 1);
2630 /* Exit BC commands */
2631 map_write(map, CMD(0x90), chip->start);
2632 map_write(map, CMD(0x00), chip->start);
2634 chip->state = FL_READY;
2635 put_chip(map, chip, adr);
2636 mutex_unlock(&chip->mutex);
2641 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2644 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2645 DO_XXLOCK_ONEBLOCK_LOCK);
2648 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2651 struct mtd_erase_region_info *regions = mtd->eraseregions;
2652 struct map_info *map = mtd->priv;
2653 struct cfi_private *cfi = map->fldrv_priv;
2654 struct ppb_lock *sect;
2664 * PPB unlocking always unlocks all sectors of the flash chip.
2665 * We need to re-lock all previously locked sectors. So lets
2666 * first check the locking status of all sectors and save
2667 * it for future use.
2669 sect = kzalloc(MAX_SECTORS * sizeof(struct ppb_lock), GFP_KERNEL);
2674 * This code to walk all sectors is a slightly modified version
2675 * of the cfi_varsize_frob() code.
2685 int size = regions[i].erasesize;
2688 * Only test sectors that shall not be unlocked. The other
2689 * sectors shall be unlocked, so lets keep their locking
2690 * status at "unlocked" (locked=0) for the final re-locking.
2692 if ((offset < ofs) || (offset >= (ofs + len))) {
2693 sect[sectors].chip = &cfi->chips[chipnum];
2694 sect[sectors].adr = adr;
2695 sect[sectors].locked = do_ppb_xxlock(
2696 map, &cfi->chips[chipnum], adr, 0,
2697 DO_XXLOCK_ONEBLOCK_GETLOCK);
2704 if (offset == regions[i].offset + size * regions[i].numblocks)
2707 if (adr >> cfi->chipshift) {
2708 if (offset >= (ofs + len))
2713 if (chipnum >= cfi->numchips)
2718 if (sectors >= MAX_SECTORS) {
2719 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2726 /* Now unlock the whole chip */
2727 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2728 DO_XXLOCK_ONEBLOCK_UNLOCK);
2735 * PPB unlocking always unlocks all sectors of the flash chip.
2736 * We need to re-lock all previously locked sectors.
2738 for (i = 0; i < sectors; i++) {
2740 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
2741 DO_XXLOCK_ONEBLOCK_LOCK);
2748 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2751 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2752 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2755 static void cfi_amdstd_sync (struct mtd_info *mtd)
2757 struct map_info *map = mtd->priv;
2758 struct cfi_private *cfi = map->fldrv_priv;
2760 struct flchip *chip;
2762 DECLARE_WAITQUEUE(wait, current);
2764 for (i=0; !ret && i<cfi->numchips; i++) {
2765 chip = &cfi->chips[i];
2768 mutex_lock(&chip->mutex);
2770 switch(chip->state) {
2774 case FL_JEDEC_QUERY:
2775 chip->oldstate = chip->state;
2776 chip->state = FL_SYNCING;
2777 /* No need to wake_up() on this state change -
2778 * as the whole point is that nobody can do anything
2779 * with the chip now anyway.
2782 mutex_unlock(&chip->mutex);
2786 /* Not an idle state */
2787 set_current_state(TASK_UNINTERRUPTIBLE);
2788 add_wait_queue(&chip->wq, &wait);
2790 mutex_unlock(&chip->mutex);
2794 remove_wait_queue(&chip->wq, &wait);
2800 /* Unlock the chips again */
2802 for (i--; i >=0; i--) {
2803 chip = &cfi->chips[i];
2805 mutex_lock(&chip->mutex);
2807 if (chip->state == FL_SYNCING) {
2808 chip->state = chip->oldstate;
2811 mutex_unlock(&chip->mutex);
2816 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2818 struct map_info *map = mtd->priv;
2819 struct cfi_private *cfi = map->fldrv_priv;
2821 struct flchip *chip;
2824 for (i=0; !ret && i<cfi->numchips; i++) {
2825 chip = &cfi->chips[i];
2827 mutex_lock(&chip->mutex);
2829 switch(chip->state) {
2833 case FL_JEDEC_QUERY:
2834 chip->oldstate = chip->state;
2835 chip->state = FL_PM_SUSPENDED;
2836 /* No need to wake_up() on this state change -
2837 * as the whole point is that nobody can do anything
2838 * with the chip now anyway.
2840 case FL_PM_SUSPENDED:
2847 mutex_unlock(&chip->mutex);
2850 /* Unlock the chips again */
2853 for (i--; i >=0; i--) {
2854 chip = &cfi->chips[i];
2856 mutex_lock(&chip->mutex);
2858 if (chip->state == FL_PM_SUSPENDED) {
2859 chip->state = chip->oldstate;
2862 mutex_unlock(&chip->mutex);
2870 static void cfi_amdstd_resume(struct mtd_info *mtd)
2872 struct map_info *map = mtd->priv;
2873 struct cfi_private *cfi = map->fldrv_priv;
2875 struct flchip *chip;
2877 for (i=0; i<cfi->numchips; i++) {
2879 chip = &cfi->chips[i];
2881 mutex_lock(&chip->mutex);
2883 if (chip->state == FL_PM_SUSPENDED) {
2884 chip->state = FL_READY;
2885 map_write(map, CMD(0xF0), chip->start);
2889 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
2891 mutex_unlock(&chip->mutex);
2897 * Ensure that the flash device is put back into read array mode before
2898 * unloading the driver or rebooting. On some systems, rebooting while
2899 * the flash is in query/program/erase mode will prevent the CPU from
2900 * fetching the bootloader code, requiring a hard reset or power cycle.
2902 static int cfi_amdstd_reset(struct mtd_info *mtd)
2904 struct map_info *map = mtd->priv;
2905 struct cfi_private *cfi = map->fldrv_priv;
2907 struct flchip *chip;
2909 for (i = 0; i < cfi->numchips; i++) {
2911 chip = &cfi->chips[i];
2913 mutex_lock(&chip->mutex);
2915 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2917 map_write(map, CMD(0xF0), chip->start);
2918 chip->state = FL_SHUTDOWN;
2919 put_chip(map, chip, chip->start);
2922 mutex_unlock(&chip->mutex);
2929 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2932 struct mtd_info *mtd;
2934 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2935 cfi_amdstd_reset(mtd);
2940 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2942 struct map_info *map = mtd->priv;
2943 struct cfi_private *cfi = map->fldrv_priv;
2945 cfi_amdstd_reset(mtd);
2946 unregister_reboot_notifier(&mtd->reboot_notifier);
2947 kfree(cfi->cmdset_priv);
2950 kfree(mtd->eraseregions);
2953 MODULE_LICENSE("GPL");
2954 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2955 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2956 MODULE_ALIAS("cfi_cmdset_0006");
2957 MODULE_ALIAS("cfi_cmdset_0701");