1 // SPDX-License-Identifier: GPL-2.0-only
3 * Host side test driver to test endpoint functionality
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
9 #include <linux/crc32.h>
10 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/miscdevice.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/random.h>
19 #include <linux/slab.h>
20 #include <linux/pci.h>
21 #include <linux/pci_ids.h>
23 #include <linux/pci_regs.h>
25 #include <uapi/linux/pcitest.h>
27 #define DRV_MODULE_NAME "pci-endpoint-test"
29 #define IRQ_TYPE_UNDEFINED -1
30 #define IRQ_TYPE_LEGACY 0
31 #define IRQ_TYPE_MSI 1
32 #define IRQ_TYPE_MSIX 2
34 #define PCI_ENDPOINT_TEST_MAGIC 0x0
36 #define PCI_ENDPOINT_TEST_COMMAND 0x4
37 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
38 #define COMMAND_RAISE_MSI_IRQ BIT(1)
39 #define COMMAND_RAISE_MSIX_IRQ BIT(2)
40 #define COMMAND_READ BIT(3)
41 #define COMMAND_WRITE BIT(4)
42 #define COMMAND_COPY BIT(5)
44 #define PCI_ENDPOINT_TEST_STATUS 0x8
45 #define STATUS_READ_SUCCESS BIT(0)
46 #define STATUS_READ_FAIL BIT(1)
47 #define STATUS_WRITE_SUCCESS BIT(2)
48 #define STATUS_WRITE_FAIL BIT(3)
49 #define STATUS_COPY_SUCCESS BIT(4)
50 #define STATUS_COPY_FAIL BIT(5)
51 #define STATUS_IRQ_RAISED BIT(6)
52 #define STATUS_SRC_ADDR_INVALID BIT(7)
53 #define STATUS_DST_ADDR_INVALID BIT(8)
55 #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
56 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
58 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
59 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
61 #define PCI_ENDPOINT_TEST_SIZE 0x1c
62 #define PCI_ENDPOINT_TEST_CHECKSUM 0x20
64 #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
65 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
67 #define PCI_DEVICE_ID_TI_AM654 0xb00c
69 #define is_am654_pci_dev(pdev) \
70 ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
72 static DEFINE_IDA(pci_endpoint_test_ida);
74 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
78 module_param(no_msi, bool, 0444);
79 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
81 static int irq_type = IRQ_TYPE_MSI;
82 module_param(irq_type, int, 0444);
83 MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
94 struct pci_endpoint_test {
98 struct completion irq_raised;
102 /* mutex to protect the ioctls */
104 struct miscdevice miscdev;
105 enum pci_barno test_reg_bar;
109 struct pci_endpoint_test_data {
110 enum pci_barno test_reg_bar;
115 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
118 return readl(test->base + offset);
121 static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
122 u32 offset, u32 value)
124 writel(value, test->base + offset);
127 static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
130 return readl(test->bar[bar] + offset);
133 static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
134 int bar, u32 offset, u32 value)
136 writel(value, test->bar[bar] + offset);
139 static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
141 struct pci_endpoint_test *test = dev_id;
144 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
145 if (reg & STATUS_IRQ_RAISED) {
146 test->last_irq = irq;
147 complete(&test->irq_raised);
148 reg &= ~STATUS_IRQ_RAISED;
150 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
156 static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
158 struct pci_dev *pdev = test->pdev;
160 pci_free_irq_vectors(pdev);
161 test->irq_type = IRQ_TYPE_UNDEFINED;
164 static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
168 struct pci_dev *pdev = test->pdev;
169 struct device *dev = &pdev->dev;
173 case IRQ_TYPE_LEGACY:
174 irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
176 dev_err(dev, "Failed to get Legacy interrupt\n");
179 irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
181 dev_err(dev, "Failed to get MSI interrupts\n");
184 irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
186 dev_err(dev, "Failed to get MSI-X interrupts\n");
189 dev_err(dev, "Invalid IRQ type selected\n");
197 test->irq_type = type;
198 test->num_irqs = irq;
203 static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
206 struct pci_dev *pdev = test->pdev;
207 struct device *dev = &pdev->dev;
209 for (i = 0; i < test->num_irqs; i++)
210 devm_free_irq(dev, pci_irq_vector(pdev, i), test);
215 static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
219 struct pci_dev *pdev = test->pdev;
220 struct device *dev = &pdev->dev;
222 for (i = 0; i < test->num_irqs; i++) {
223 err = devm_request_irq(dev, pci_irq_vector(pdev, i),
224 pci_endpoint_test_irqhandler,
225 IRQF_SHARED, DRV_MODULE_NAME, test);
234 case IRQ_TYPE_LEGACY:
235 dev_err(dev, "Failed to request IRQ %d for Legacy\n",
236 pci_irq_vector(pdev, i));
239 dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
240 pci_irq_vector(pdev, i),
244 dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
245 pci_irq_vector(pdev, i),
253 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
254 enum pci_barno barno)
259 struct pci_dev *pdev = test->pdev;
261 if (!test->bar[barno])
264 size = pci_resource_len(pdev, barno);
266 if (barno == test->test_reg_bar)
269 for (j = 0; j < size; j += 4)
270 pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
272 for (j = 0; j < size; j += 4) {
273 val = pci_endpoint_test_bar_readl(test, barno, j);
274 if (val != 0xA0A0A0A0)
281 static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
285 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
287 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
288 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
289 COMMAND_RAISE_LEGACY_IRQ);
290 val = wait_for_completion_timeout(&test->irq_raised,
291 msecs_to_jiffies(1000));
298 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
299 u16 msi_num, bool msix)
302 struct pci_dev *pdev = test->pdev;
304 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
305 msix == false ? IRQ_TYPE_MSI :
307 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
308 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
309 msix == false ? COMMAND_RAISE_MSI_IRQ :
310 COMMAND_RAISE_MSIX_IRQ);
311 val = wait_for_completion_timeout(&test->irq_raised,
312 msecs_to_jiffies(1000));
316 if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
322 static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
327 dma_addr_t src_phys_addr;
328 dma_addr_t dst_phys_addr;
329 struct pci_dev *pdev = test->pdev;
330 struct device *dev = &pdev->dev;
332 dma_addr_t orig_src_phys_addr;
334 dma_addr_t orig_dst_phys_addr;
336 size_t alignment = test->alignment;
337 int irq_type = test->irq_type;
341 if (size > SIZE_MAX - alignment)
344 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
345 dev_err(dev, "Invalid IRQ type option\n");
349 orig_src_addr = dma_alloc_coherent(dev, size + alignment,
350 &orig_src_phys_addr, GFP_KERNEL);
351 if (!orig_src_addr) {
352 dev_err(dev, "Failed to allocate source buffer\n");
357 if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
358 src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
359 offset = src_phys_addr - orig_src_phys_addr;
360 src_addr = orig_src_addr + offset;
362 src_phys_addr = orig_src_phys_addr;
363 src_addr = orig_src_addr;
366 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
367 lower_32_bits(src_phys_addr));
369 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
370 upper_32_bits(src_phys_addr));
372 get_random_bytes(src_addr, size);
373 src_crc32 = crc32_le(~0, src_addr, size);
375 orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
376 &orig_dst_phys_addr, GFP_KERNEL);
377 if (!orig_dst_addr) {
378 dev_err(dev, "Failed to allocate destination address\n");
380 goto err_orig_src_addr;
383 if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
384 dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
385 offset = dst_phys_addr - orig_dst_phys_addr;
386 dst_addr = orig_dst_addr + offset;
388 dst_phys_addr = orig_dst_phys_addr;
389 dst_addr = orig_dst_addr;
392 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
393 lower_32_bits(dst_phys_addr));
394 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
395 upper_32_bits(dst_phys_addr));
397 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
400 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
401 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
402 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
405 wait_for_completion(&test->irq_raised);
407 dst_crc32 = crc32_le(~0, dst_addr, size);
408 if (dst_crc32 == src_crc32)
411 dma_free_coherent(dev, size + alignment, orig_dst_addr,
415 dma_free_coherent(dev, size + alignment, orig_src_addr,
422 static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
427 dma_addr_t phys_addr;
428 struct pci_dev *pdev = test->pdev;
429 struct device *dev = &pdev->dev;
431 dma_addr_t orig_phys_addr;
433 size_t alignment = test->alignment;
434 int irq_type = test->irq_type;
437 if (size > SIZE_MAX - alignment)
440 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
441 dev_err(dev, "Invalid IRQ type option\n");
445 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
448 dev_err(dev, "Failed to allocate address\n");
453 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
454 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
455 offset = phys_addr - orig_phys_addr;
456 addr = orig_addr + offset;
458 phys_addr = orig_phys_addr;
462 get_random_bytes(addr, size);
464 crc32 = crc32_le(~0, addr, size);
465 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
468 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
469 lower_32_bits(phys_addr));
470 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
471 upper_32_bits(phys_addr));
473 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
475 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
476 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
477 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
480 wait_for_completion(&test->irq_raised);
482 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
483 if (reg & STATUS_READ_SUCCESS)
486 dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
492 static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
496 dma_addr_t phys_addr;
497 struct pci_dev *pdev = test->pdev;
498 struct device *dev = &pdev->dev;
500 dma_addr_t orig_phys_addr;
502 size_t alignment = test->alignment;
503 int irq_type = test->irq_type;
506 if (size > SIZE_MAX - alignment)
509 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
510 dev_err(dev, "Invalid IRQ type option\n");
514 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
517 dev_err(dev, "Failed to allocate destination address\n");
522 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
523 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
524 offset = phys_addr - orig_phys_addr;
525 addr = orig_addr + offset;
527 phys_addr = orig_phys_addr;
531 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
532 lower_32_bits(phys_addr));
533 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
534 upper_32_bits(phys_addr));
536 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
538 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
539 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
540 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
543 wait_for_completion(&test->irq_raised);
545 crc32 = crc32_le(~0, addr, size);
546 if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
549 dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
554 static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
557 struct pci_dev *pdev = test->pdev;
558 struct device *dev = &pdev->dev;
560 if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
561 dev_err(dev, "Invalid IRQ type option\n");
565 if (test->irq_type == req_irq_type)
568 pci_endpoint_test_release_irq(test);
569 pci_endpoint_test_free_irq_vectors(test);
571 if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
574 if (!pci_endpoint_test_request_irq(test))
580 pci_endpoint_test_free_irq_vectors(test);
584 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
589 struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
590 struct pci_dev *pdev = test->pdev;
592 mutex_lock(&test->mutex);
596 if (bar < 0 || bar > 5)
598 if (is_am654_pci_dev(pdev) && bar == BAR_0)
600 ret = pci_endpoint_test_bar(test, bar);
602 case PCITEST_LEGACY_IRQ:
603 ret = pci_endpoint_test_legacy_irq(test);
607 ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
610 ret = pci_endpoint_test_write(test, arg);
613 ret = pci_endpoint_test_read(test, arg);
616 ret = pci_endpoint_test_copy(test, arg);
618 case PCITEST_SET_IRQTYPE:
619 ret = pci_endpoint_test_set_irq(test, arg);
621 case PCITEST_GET_IRQTYPE:
627 mutex_unlock(&test->mutex);
631 static const struct file_operations pci_endpoint_test_fops = {
632 .owner = THIS_MODULE,
633 .unlocked_ioctl = pci_endpoint_test_ioctl,
636 static int pci_endpoint_test_probe(struct pci_dev *pdev,
637 const struct pci_device_id *ent)
644 struct device *dev = &pdev->dev;
645 struct pci_endpoint_test *test;
646 struct pci_endpoint_test_data *data;
647 enum pci_barno test_reg_bar = BAR_0;
648 struct miscdevice *misc_device;
650 if (pci_is_bridge(pdev))
653 test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
657 test->test_reg_bar = 0;
660 test->irq_type = IRQ_TYPE_UNDEFINED;
663 irq_type = IRQ_TYPE_LEGACY;
665 data = (struct pci_endpoint_test_data *)ent->driver_data;
667 test_reg_bar = data->test_reg_bar;
668 test->test_reg_bar = test_reg_bar;
669 test->alignment = data->alignment;
670 irq_type = data->irq_type;
673 init_completion(&test->irq_raised);
674 mutex_init(&test->mutex);
676 err = pci_enable_device(pdev);
678 dev_err(dev, "Cannot enable PCI device\n");
682 err = pci_request_regions(pdev, DRV_MODULE_NAME);
684 dev_err(dev, "Cannot obtain PCI resources\n");
685 goto err_disable_pdev;
688 pci_set_master(pdev);
690 if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type))
691 goto err_disable_irq;
693 if (!pci_endpoint_test_request_irq(test))
694 goto err_disable_irq;
696 for (bar = BAR_0; bar <= BAR_5; bar++) {
697 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
698 base = pci_ioremap_bar(pdev, bar);
700 dev_err(dev, "Failed to read BAR%d\n", bar);
701 WARN_ON(bar == test_reg_bar);
703 test->bar[bar] = base;
707 test->base = test->bar[test_reg_bar];
710 dev_err(dev, "Cannot perform PCI test without BAR%d\n",
715 pci_set_drvdata(pdev, test);
717 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
720 dev_err(dev, "Unable to get id\n");
724 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
725 misc_device = &test->miscdev;
726 misc_device->minor = MISC_DYNAMIC_MINOR;
727 misc_device->name = kstrdup(name, GFP_KERNEL);
728 if (!misc_device->name) {
732 misc_device->fops = &pci_endpoint_test_fops,
734 err = misc_register(misc_device);
736 dev_err(dev, "Failed to register device\n");
743 kfree(misc_device->name);
746 ida_simple_remove(&pci_endpoint_test_ida, id);
749 for (bar = BAR_0; bar <= BAR_5; bar++) {
751 pci_iounmap(pdev, test->bar[bar]);
753 pci_endpoint_test_release_irq(test);
756 pci_endpoint_test_free_irq_vectors(test);
757 pci_release_regions(pdev);
760 pci_disable_device(pdev);
765 static void pci_endpoint_test_remove(struct pci_dev *pdev)
769 struct pci_endpoint_test *test = pci_get_drvdata(pdev);
770 struct miscdevice *misc_device = &test->miscdev;
772 if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
777 misc_deregister(&test->miscdev);
778 kfree(misc_device->name);
779 ida_simple_remove(&pci_endpoint_test_ida, id);
780 for (bar = BAR_0; bar <= BAR_5; bar++) {
782 pci_iounmap(pdev, test->bar[bar]);
785 pci_endpoint_test_release_irq(test);
786 pci_endpoint_test_free_irq_vectors(test);
788 pci_release_regions(pdev);
789 pci_disable_device(pdev);
792 static const struct pci_endpoint_test_data am654_data = {
793 .test_reg_bar = BAR_2,
795 .irq_type = IRQ_TYPE_MSI,
798 static const struct pci_device_id pci_endpoint_test_tbl[] = {
799 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
800 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
801 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
802 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
803 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
804 .driver_data = (kernel_ulong_t)&am654_data
808 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
810 static struct pci_driver pci_endpoint_test_driver = {
811 .name = DRV_MODULE_NAME,
812 .id_table = pci_endpoint_test_tbl,
813 .probe = pci_endpoint_test_probe,
814 .remove = pci_endpoint_test_remove,
816 module_pci_driver(pci_endpoint_test_driver);
818 MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
819 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
820 MODULE_LICENSE("GPL v2");