1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2018 HabanaLabs, Ltd.
8 /************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
13 #ifndef ASIC_REG_PSOC_PCI_PLL_REGS_H_
14 #define ASIC_REG_PSOC_PCI_PLL_REGS_H_
17 *****************************************
18 * PSOC_PCI_PLL (Prototype: PLL)
19 *****************************************
22 #define mmPSOC_PCI_PLL_NR 0xC72100
24 #define mmPSOC_PCI_PLL_NF 0xC72104
26 #define mmPSOC_PCI_PLL_OD 0xC72108
28 #define mmPSOC_PCI_PLL_NB 0xC7210C
30 #define mmPSOC_PCI_PLL_CFG 0xC72110
32 #define mmPSOC_PCI_PLL_LOSE_MASK 0xC72120
34 #define mmPSOC_PCI_PLL_LOCK_INTR 0xC72128
36 #define mmPSOC_PCI_PLL_LOCK_BYPASS 0xC7212C
38 #define mmPSOC_PCI_PLL_DATA_CHNG 0xC72130
40 #define mmPSOC_PCI_PLL_RST 0xC72134
42 #define mmPSOC_PCI_PLL_SLIP_WD_CNTR 0xC72150
44 #define mmPSOC_PCI_PLL_DIV_FACTOR_0 0xC72200
46 #define mmPSOC_PCI_PLL_DIV_FACTOR_1 0xC72204
48 #define mmPSOC_PCI_PLL_DIV_FACTOR_2 0xC72208
50 #define mmPSOC_PCI_PLL_DIV_FACTOR_3 0xC7220C
52 #define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_0 0xC72220
54 #define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_1 0xC72224
56 #define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_2 0xC72228
58 #define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_3 0xC7222C
60 #define mmPSOC_PCI_PLL_DIV_SEL_0 0xC72280
62 #define mmPSOC_PCI_PLL_DIV_SEL_1 0xC72284
64 #define mmPSOC_PCI_PLL_DIV_SEL_2 0xC72288
66 #define mmPSOC_PCI_PLL_DIV_SEL_3 0xC7228C
68 #define mmPSOC_PCI_PLL_DIV_EN_0 0xC722A0
70 #define mmPSOC_PCI_PLL_DIV_EN_1 0xC722A4
72 #define mmPSOC_PCI_PLL_DIV_EN_2 0xC722A8
74 #define mmPSOC_PCI_PLL_DIV_EN_3 0xC722AC
76 #define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_0 0xC722C0
78 #define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_1 0xC722C4
80 #define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_2 0xC722C8
82 #define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_3 0xC722CC
84 #define mmPSOC_PCI_PLL_CLK_GATER 0xC72300
86 #define mmPSOC_PCI_PLL_CLK_RLX_0 0xC72310
88 #define mmPSOC_PCI_PLL_CLK_RLX_1 0xC72314
90 #define mmPSOC_PCI_PLL_CLK_RLX_2 0xC72318
92 #define mmPSOC_PCI_PLL_CLK_RLX_3 0xC7231C
94 #define mmPSOC_PCI_PLL_REF_CNTR_PERIOD 0xC72400
96 #define mmPSOC_PCI_PLL_REF_LOW_THRESHOLD 0xC72410
98 #define mmPSOC_PCI_PLL_REF_HIGH_THRESHOLD 0xC72420
100 #define mmPSOC_PCI_PLL_PLL_NOT_STABLE 0xC72430
102 #define mmPSOC_PCI_PLL_FREQ_CALC_EN 0xC72440
104 #endif /* ASIC_REG_PSOC_PCI_PLL_REGS_H_ */