drivers/misc/habanalabs/include/goya/asic_reg/mme_qm_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 /************************************
   9  ** This is an auto-generated file **
  10  **       DO NOT EDIT BELOW        **
  11  ************************************/
  12
  13 #ifndef ASIC_REG_MME_QM_REGS_H_
  14 #define ASIC_REG_MME_QM_REGS_H_
  15
  16 /*
  17  *****************************************
  18  *   MME_QM (Prototype: QMAN)
  19  *****************************************
  20  */
  21
  22 #define mmMME_QM_GLBL_CFG0                                           0xD8000
  23
  24 #define mmMME_QM_GLBL_CFG1                                           0xD8004
  25
  26 #define mmMME_QM_GLBL_PROT                                           0xD8008
  27
  28 #define mmMME_QM_GLBL_ERR_CFG                                        0xD800C
  29
  30 #define mmMME_QM_GLBL_ERR_ADDR_LO                                    0xD8010
  31
  32 #define mmMME_QM_GLBL_ERR_ADDR_HI                                    0xD8014
  33
  34 #define mmMME_QM_GLBL_ERR_WDATA                                      0xD8018
  35
  36 #define mmMME_QM_GLBL_SECURE_PROPS                                   0xD801C
  37
  38 #define mmMME_QM_GLBL_NON_SECURE_PROPS                               0xD8020
  39
  40 #define mmMME_QM_GLBL_STS0                                           0xD8024
  41
  42 #define mmMME_QM_GLBL_STS1                                           0xD8028
  43
  44 #define mmMME_QM_PQ_BASE_LO                                          0xD8060
  45
  46 #define mmMME_QM_PQ_BASE_HI                                          0xD8064
  47
  48 #define mmMME_QM_PQ_SIZE                                             0xD8068
  49
  50 #define mmMME_QM_PQ_PI                                               0xD806C
  51
  52 #define mmMME_QM_PQ_CI                                               0xD8070
  53
  54 #define mmMME_QM_PQ_CFG0                                             0xD8074
  55
  56 #define mmMME_QM_PQ_CFG1                                             0xD8078
  57
  58 #define mmMME_QM_PQ_ARUSER                                           0xD807C
  59
  60 #define mmMME_QM_PQ_PUSH0                                            0xD8080
  61
  62 #define mmMME_QM_PQ_PUSH1                                            0xD8084
  63
  64 #define mmMME_QM_PQ_PUSH2                                            0xD8088
  65
  66 #define mmMME_QM_PQ_PUSH3                                            0xD808C
  67
  68 #define mmMME_QM_PQ_STS0                                             0xD8090
  69
  70 #define mmMME_QM_PQ_STS1                                             0xD8094
  71
  72 #define mmMME_QM_PQ_RD_RATE_LIM_EN                                   0xD80A0
  73
  74 #define mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN                            0xD80A4
  75
  76 #define mmMME_QM_PQ_RD_RATE_LIM_SAT                                  0xD80A8
  77
  78 #define mmMME_QM_PQ_RD_RATE_LIM_TOUT                                 0xD80AC
  79
  80 #define mmMME_QM_CQ_CFG0                                             0xD80B0
  81
  82 #define mmMME_QM_CQ_CFG1                                             0xD80B4
  83
  84 #define mmMME_QM_CQ_ARUSER                                           0xD80B8
  85
  86 #define mmMME_QM_CQ_PTR_LO                                           0xD80C0
  87
  88 #define mmMME_QM_CQ_PTR_HI                                           0xD80C4
  89
  90 #define mmMME_QM_CQ_TSIZE                                            0xD80C8
  91
  92 #define mmMME_QM_CQ_CTL                                              0xD80CC
  93
  94 #define mmMME_QM_CQ_PTR_LO_STS                                       0xD80D4
  95
  96 #define mmMME_QM_CQ_PTR_HI_STS                                       0xD80D8
  97
  98 #define mmMME_QM_CQ_TSIZE_STS                                        0xD80DC
  99
 100 #define mmMME_QM_CQ_CTL_STS                                          0xD80E0
 101
 102 #define mmMME_QM_CQ_STS0                                             0xD80E4
 103
 104 #define mmMME_QM_CQ_STS1                                             0xD80E8
 105
 106 #define mmMME_QM_CQ_RD_RATE_LIM_EN                                   0xD80F0
 107
 108 #define mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN                            0xD80F4
 109
 110 #define mmMME_QM_CQ_RD_RATE_LIM_SAT                                  0xD80F8
 111
 112 #define mmMME_QM_CQ_RD_RATE_LIM_TOUT                                 0xD80FC
 113
 114 #define mmMME_QM_CQ_IFIFO_CNT                                        0xD8108
 115
 116 #define mmMME_QM_CP_MSG_BASE0_ADDR_LO                                0xD8120
 117
 118 #define mmMME_QM_CP_MSG_BASE0_ADDR_HI                                0xD8124
 119
 120 #define mmMME_QM_CP_MSG_BASE1_ADDR_LO                                0xD8128
 121
 122 #define mmMME_QM_CP_MSG_BASE1_ADDR_HI                                0xD812C
 123
 124 #define mmMME_QM_CP_MSG_BASE2_ADDR_LO                                0xD8130
 125
 126 #define mmMME_QM_CP_MSG_BASE2_ADDR_HI                                0xD8134
 127
 128 #define mmMME_QM_CP_MSG_BASE3_ADDR_LO                                0xD8138
 129
 130 #define mmMME_QM_CP_MSG_BASE3_ADDR_HI                                0xD813C
 131
 132 #define mmMME_QM_CP_LDMA_TSIZE_OFFSET                                0xD8140
 133
 134 #define mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET                          0xD8144
 135
 136 #define mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET                          0xD8148
 137
 138 #define mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET                          0xD814C
 139
 140 #define mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET                          0xD8150
 141
 142 #define mmMME_QM_CP_LDMA_COMMIT_OFFSET                               0xD8154
 143
 144 #define mmMME_QM_CP_FENCE0_RDATA                                     0xD8158
 145
 146 #define mmMME_QM_CP_FENCE1_RDATA                                     0xD815C
 147
 148 #define mmMME_QM_CP_FENCE2_RDATA                                     0xD8160
 149
 150 #define mmMME_QM_CP_FENCE3_RDATA                                     0xD8164
 151
 152 #define mmMME_QM_CP_FENCE0_CNT                                       0xD8168
 153
 154 #define mmMME_QM_CP_FENCE1_CNT                                       0xD816C
 155
 156 #define mmMME_QM_CP_FENCE2_CNT                                       0xD8170
 157
 158 #define mmMME_QM_CP_FENCE3_CNT                                       0xD8174
 159
 160 #define mmMME_QM_CP_STS                                              0xD8178
 161
 162 #define mmMME_QM_CP_CURRENT_INST_LO                                  0xD817C
 163
 164 #define mmMME_QM_CP_CURRENT_INST_HI                                  0xD8180
 165
 166 #define mmMME_QM_CP_BARRIER_CFG                                      0xD8184
 167
 168 #define mmMME_QM_CP_DBG_0                                            0xD8188
 169
 170 #define mmMME_QM_PQ_BUF_ADDR                                         0xD8300
 171
 172 #define mmMME_QM_PQ_BUF_RDATA                                        0xD8304
 173
 174 #define mmMME_QM_CQ_BUF_ADDR                                         0xD8308
 175
 176 #define mmMME_QM_CQ_BUF_RDATA                                        0xD830C
 177
 178 #endif /* ASIC_REG_MME_QM_REGS_H_ */