1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2018 HabanaLabs, Ltd.
8 /************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
13 #ifndef ASIC_REG_DMA_CH_2_REGS_H_
14 #define ASIC_REG_DMA_CH_2_REGS_H_
17 *****************************************
18 * DMA_CH_2 (Prototype: DMA_CH)
19 *****************************************
22 #define mmDMA_CH_2_CFG0 0x411000
24 #define mmDMA_CH_2_CFG1 0x411004
26 #define mmDMA_CH_2_ERRMSG_ADDR_LO 0x411008
28 #define mmDMA_CH_2_ERRMSG_ADDR_HI 0x41100C
30 #define mmDMA_CH_2_ERRMSG_WDATA 0x411010
32 #define mmDMA_CH_2_RD_COMP_ADDR_LO 0x411014
34 #define mmDMA_CH_2_RD_COMP_ADDR_HI 0x411018
36 #define mmDMA_CH_2_RD_COMP_WDATA 0x41101C
38 #define mmDMA_CH_2_WR_COMP_ADDR_LO 0x411020
40 #define mmDMA_CH_2_WR_COMP_ADDR_HI 0x411024
42 #define mmDMA_CH_2_WR_COMP_WDATA 0x411028
44 #define mmDMA_CH_2_LDMA_SRC_ADDR_LO 0x41102C
46 #define mmDMA_CH_2_LDMA_SRC_ADDR_HI 0x411030
48 #define mmDMA_CH_2_LDMA_DST_ADDR_LO 0x411034
50 #define mmDMA_CH_2_LDMA_DST_ADDR_HI 0x411038
52 #define mmDMA_CH_2_LDMA_TSIZE 0x41103C
54 #define mmDMA_CH_2_COMIT_TRANSFER 0x411040
56 #define mmDMA_CH_2_STS0 0x411044
58 #define mmDMA_CH_2_STS1 0x411048
60 #define mmDMA_CH_2_STS2 0x41104C
62 #define mmDMA_CH_2_STS3 0x411050
64 #define mmDMA_CH_2_STS4 0x411054
66 #define mmDMA_CH_2_SRC_ADDR_LO_STS 0x411058
68 #define mmDMA_CH_2_SRC_ADDR_HI_STS 0x41105C
70 #define mmDMA_CH_2_SRC_TSIZE_STS 0x411060
72 #define mmDMA_CH_2_DST_ADDR_LO_STS 0x411064
74 #define mmDMA_CH_2_DST_ADDR_HI_STS 0x411068
76 #define mmDMA_CH_2_DST_TSIZE_STS 0x41106C
78 #define mmDMA_CH_2_RD_RATE_LIM_EN 0x411070
80 #define mmDMA_CH_2_RD_RATE_LIM_RST_TOKEN 0x411074
82 #define mmDMA_CH_2_RD_RATE_LIM_SAT 0x411078
84 #define mmDMA_CH_2_RD_RATE_LIM_TOUT 0x41107C
86 #define mmDMA_CH_2_WR_RATE_LIM_EN 0x411080
88 #define mmDMA_CH_2_WR_RATE_LIM_RST_TOKEN 0x411084
90 #define mmDMA_CH_2_WR_RATE_LIM_SAT 0x411088
92 #define mmDMA_CH_2_WR_RATE_LIM_TOUT 0x41108C
94 #define mmDMA_CH_2_CFG2 0x411090
96 #define mmDMA_CH_2_TDMA_CTL 0x411100
98 #define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_LO 0x411104
100 #define mmDMA_CH_2_TDMA_SRC_BASE_ADDR_HI 0x411108
102 #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_0 0x41110C
104 #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_0 0x411110
106 #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_0 0x411114
108 #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_0 0x411118
110 #define mmDMA_CH_2_TDMA_SRC_STRIDE_0 0x41111C
112 #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_1 0x411120
114 #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_1 0x411124
116 #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_1 0x411128
118 #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_1 0x41112C
120 #define mmDMA_CH_2_TDMA_SRC_STRIDE_1 0x411130
122 #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_2 0x411134
124 #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_2 0x411138
126 #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_2 0x41113C
128 #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_2 0x411140
130 #define mmDMA_CH_2_TDMA_SRC_STRIDE_2 0x411144
132 #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_3 0x411148
134 #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_3 0x41114C
136 #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_3 0x411150
138 #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_3 0x411154
140 #define mmDMA_CH_2_TDMA_SRC_STRIDE_3 0x411158
142 #define mmDMA_CH_2_TDMA_SRC_ROI_BASE_4 0x41115C
144 #define mmDMA_CH_2_TDMA_SRC_ROI_SIZE_4 0x411160
146 #define mmDMA_CH_2_TDMA_SRC_VALID_ELEMENTS_4 0x411164
148 #define mmDMA_CH_2_TDMA_SRC_START_OFFSET_4 0x411168
150 #define mmDMA_CH_2_TDMA_SRC_STRIDE_4 0x41116C
152 #define mmDMA_CH_2_TDMA_DST_BASE_ADDR_LO 0x411170
154 #define mmDMA_CH_2_TDMA_DST_BASE_ADDR_HI 0x411174
156 #define mmDMA_CH_2_TDMA_DST_ROI_BASE_0 0x411178
158 #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_0 0x41117C
160 #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_0 0x411180
162 #define mmDMA_CH_2_TDMA_DST_START_OFFSET_0 0x411184
164 #define mmDMA_CH_2_TDMA_DST_STRIDE_0 0x411188
166 #define mmDMA_CH_2_TDMA_DST_ROI_BASE_1 0x41118C
168 #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_1 0x411190
170 #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_1 0x411194
172 #define mmDMA_CH_2_TDMA_DST_START_OFFSET_1 0x411198
174 #define mmDMA_CH_2_TDMA_DST_STRIDE_1 0x41119C
176 #define mmDMA_CH_2_TDMA_DST_ROI_BASE_2 0x4111A0
178 #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_2 0x4111A4
180 #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_2 0x4111A8
182 #define mmDMA_CH_2_TDMA_DST_START_OFFSET_2 0x4111AC
184 #define mmDMA_CH_2_TDMA_DST_STRIDE_2 0x4111B0
186 #define mmDMA_CH_2_TDMA_DST_ROI_BASE_3 0x4111B4
188 #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_3 0x4111B8
190 #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_3 0x4111BC
192 #define mmDMA_CH_2_TDMA_DST_START_OFFSET_3 0x4111C0
194 #define mmDMA_CH_2_TDMA_DST_STRIDE_3 0x4111C4
196 #define mmDMA_CH_2_TDMA_DST_ROI_BASE_4 0x4111C8
198 #define mmDMA_CH_2_TDMA_DST_ROI_SIZE_4 0x4111CC
200 #define mmDMA_CH_2_TDMA_DST_VALID_ELEMENTS_4 0x4111D0
202 #define mmDMA_CH_2_TDMA_DST_START_OFFSET_4 0x4111D4
204 #define mmDMA_CH_2_TDMA_DST_STRIDE_4 0x4111D8
206 #define mmDMA_CH_2_MEM_INIT_BUSY 0x4111FC
208 #endif /* ASIC_REG_DMA_CH_2_REGS_H_ */