2 * Copyright 2014 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
14 static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
16 if (dma_mask < DMA_BIT_MASK(64)) {
17 pr_info("%s only 64bit DMA supported on CXL", __func__);
21 *(pdev->dev.dma_mask) = dma_mask;
25 static int cxl_pci_probe_mode(struct pci_bus *bus)
27 return PCI_PROBE_NORMAL;
30 static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
35 static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
38 * MSI should never be set but need still need to provide this call
43 static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
45 struct pci_controller *phb;
47 struct cxl_context *ctx;
49 phb = pci_bus_to_host(dev->bus);
50 afu = (struct cxl_afu *)phb->private_data;
52 if (!cxl_ops->link_ok(afu->adapter, afu)) {
53 dev_warn(&dev->dev, "%s: Device link is down, refusing to enable AFU\n", __func__);
57 set_dma_ops(&dev->dev, &dma_nommu_ops);
58 set_dma_offset(&dev->dev, PAGE_OFFSET);
61 * Allocate a context to do cxl things too. If we eventually do real
62 * DMA ops, we'll need a default context to attach them to
64 ctx = cxl_dev_context_init(dev);
67 dev->dev.archdata.cxl_ctx = ctx;
69 return (cxl_ops->afu_check_and_enable(afu) == 0);
72 static void cxl_pci_disable_device(struct pci_dev *dev)
74 struct cxl_context *ctx = cxl_get_context(dev);
77 if (ctx->status == STARTED) {
78 dev_err(&dev->dev, "Default context started\n");
81 dev->dev.archdata.cxl_ctx = NULL;
82 cxl_release_context(ctx);
86 static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
92 static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
94 /* Should we do an AFU reset here ? */
97 static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
99 return (bus << 8) + devfn;
102 static inline struct cxl_afu *pci_bus_to_afu(struct pci_bus *bus)
104 struct pci_controller *phb = bus ? pci_bus_to_host(bus) : NULL;
106 return phb ? phb->private_data : NULL;
109 static void cxl_afu_configured_put(struct cxl_afu *afu)
111 atomic_dec_if_positive(&afu->configured_state);
114 static bool cxl_afu_configured_get(struct cxl_afu *afu)
116 return atomic_inc_unless_negative(&afu->configured_state);
119 static inline int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
120 struct cxl_afu *afu, int *_record)
124 record = cxl_pcie_cfg_record(bus->number, devfn);
125 if (record > afu->crs_num)
126 return PCIBIOS_DEVICE_NOT_FOUND;
132 static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
133 int offset, int len, u32 *val)
141 afu = pci_bus_to_afu(bus);
142 /* Grab a reader lock on afu. */
143 if (afu == NULL || !cxl_afu_configured_get(afu))
144 return PCIBIOS_DEVICE_NOT_FOUND;
146 rc = cxl_pcie_config_info(bus, devfn, afu, &record);
152 rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8);
156 rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16);
160 rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32);
168 cxl_afu_configured_put(afu);
169 return rc ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
172 static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
173 int offset, int len, u32 val)
178 afu = pci_bus_to_afu(bus);
179 /* Grab a reader lock on afu. */
180 if (afu == NULL || !cxl_afu_configured_get(afu))
181 return PCIBIOS_DEVICE_NOT_FOUND;
183 rc = cxl_pcie_config_info(bus, devfn, afu, &record);
189 rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff);
192 rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff);
195 rc = cxl_ops->afu_cr_write32(afu, record, offset, val);
202 cxl_afu_configured_put(afu);
203 return rc ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
206 static struct pci_ops cxl_pcie_pci_ops =
208 .read = cxl_pcie_read_config,
209 .write = cxl_pcie_write_config,
213 static struct pci_controller_ops cxl_pci_controller_ops =
215 .probe_mode = cxl_pci_probe_mode,
216 .enable_device_hook = cxl_pci_enable_device_hook,
217 .disable_device = cxl_pci_disable_device,
218 .release_device = cxl_pci_disable_device,
219 .window_alignment = cxl_pci_window_alignment,
220 .reset_secondary_bus = cxl_pci_reset_secondary_bus,
221 .setup_msi_irqs = cxl_setup_msi_irqs,
222 .teardown_msi_irqs = cxl_teardown_msi_irqs,
223 .dma_set_mask = cxl_dma_set_mask,
226 int cxl_pci_vphb_add(struct cxl_afu *afu)
228 struct pci_controller *phb;
229 struct device_node *vphb_dn;
230 struct device *parent;
233 * If there are no AFU configuration records we won't have anything to
234 * expose under the vPHB, so skip creating one, returning success since
235 * this is still a valid case. This will also opt us out of EEH
236 * handling since we won't have anything special to do if there are no
237 * kernel drivers attached to the vPHB, and EEH handling is not yet
238 * supported in the peer model.
243 /* The parent device is the adapter. Reuse the device node of
245 * We don't seem to care what device node is used for the vPHB,
246 * but tools such as lsvpd walk up the device parents looking
247 * for a valid location code, so we might as well show devices
248 * attached to the adapter as being located on that adapter.
250 parent = afu->adapter->dev.parent;
251 vphb_dn = parent->of_node;
253 /* Alloc and setup PHB data structure */
254 phb = pcibios_alloc_controller(vphb_dn);
258 /* Setup parent in sysfs */
259 phb->parent = parent;
261 /* Setup the PHB using arch provided callback */
262 phb->ops = &cxl_pcie_pci_ops;
263 phb->cfg_addr = NULL;
264 phb->cfg_data = NULL;
265 phb->private_data = afu;
266 phb->controller_ops = cxl_pci_controller_ops;
269 pcibios_scan_phb(phb);
270 if (phb->bus == NULL)
273 /* Set release hook on root bus */
274 pci_set_host_bridge_release(to_pci_host_bridge(phb->bus->bridge),
275 pcibios_free_controller_deferred,
278 /* Claim resources. This might need some rework as well depending
279 * whether we are doing probe-only or not, like assigning unassigned
282 pcibios_claim_one_bus(phb->bus);
284 /* Add probed PCI devices to the device model */
285 pci_bus_add_devices(phb->bus);
292 void cxl_pci_vphb_remove(struct cxl_afu *afu)
294 struct pci_controller *phb;
296 /* If there is no configuration record we won't have one of these */
297 if (!afu || !afu->phb)
303 pci_remove_root_bus(phb->bus);
305 * We don't free phb here - that's handled by
306 * pcibios_free_controller_deferred()
310 bool cxl_pci_is_vphb_device(struct pci_dev *dev)
312 struct pci_controller *phb;
314 phb = pci_bus_to_host(dev->bus);
316 return (phb->ops == &cxl_pcie_pci_ops);
319 struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
321 struct pci_controller *phb;
323 phb = pci_bus_to_host(dev->bus);
325 return (struct cxl_afu *)phb->private_data;
327 EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
329 unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
331 return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
333 EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);