drivers/media/usb/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/string.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <linux/firmware.h>
  22 #include <linux/videodev2.h>
  23 #include <media/v4l2-common.h>
  24 #include <media/tuner.h>
  25 #include "pvrusb2.h"
  26 #include "pvrusb2-std.h"
  27 #include "pvrusb2-util.h"
  28 #include "pvrusb2-hdw.h"
  29 #include "pvrusb2-i2c-core.h"
  30 #include "pvrusb2-eeprom.h"
  31 #include "pvrusb2-hdw-internal.h"
  32 #include "pvrusb2-encoder.h"
  33 #include "pvrusb2-debug.h"
  34 #include "pvrusb2-fx2-cmd.h"
  35 #include "pvrusb2-wm8775.h"
  36 #include "pvrusb2-video-v4l.h"
  37 #include "pvrusb2-cx2584x-v4l.h"
  38 #include "pvrusb2-cs53l32a.h"
  39 #include "pvrusb2-audio.h"
  40
  41 #define TV_MIN_FREQ     55250000L
  42 #define TV_MAX_FREQ    850000000L
  43
  44 /* This defines a minimum interval that the decoder must remain quiet
  45    before we are allowed to start it running. */
  46 #define TIME_MSEC_DECODER_WAIT 50
  47
  48 /* This defines a minimum interval that the decoder must be allowed to run
  49    before we can safely begin using its streaming output. */
  50 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  51
  52 /* This defines a minimum interval that the encoder must remain quiet
  53    before we are allowed to configure it. */
  54 #define TIME_MSEC_ENCODER_WAIT 50
  55
  56 /* This defines the minimum interval that the encoder must successfully run
  57    before we consider that the encoder has run at least once since its
  58    firmware has been loaded.  This measurement is in important for cases
  59    where we can't do something until we know that the encoder has been run
  60    at least once. */
  61 #define TIME_MSEC_ENCODER_OK 250
  62
  63 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  64 static DEFINE_MUTEX(pvr2_unit_mtx);
  65
  66 static int ctlchg;
  67 static int procreload;
  68 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  69 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  70 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  71 static int init_pause_msec;
  72
  73 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  74 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  75 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  76 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  77 module_param(procreload, int, S_IRUGO|S_IWUSR);
  78 MODULE_PARM_DESC(procreload,
  79                  "Attempt init failure recovery with firmware reload");
  80 module_param_array(tuner,    int, NULL, 0444);
  81 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  82 module_param_array(video_std,    int, NULL, 0444);
  83 MODULE_PARM_DESC(video_std,"specify initial video standard");
  84 module_param_array(tolerance,    int, NULL, 0444);
  85 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  86
  87 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
  88 static int default_tv_freq    = 61250000L;
  89 /* 104.3 MHz, a usable FM station for my area */
  90 static int default_radio_freq = 104300000L;
  91
  92 module_param_named(tv_freq, default_tv_freq, int, 0444);
  93 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  94 module_param_named(radio_freq, default_radio_freq, int, 0444);
  95 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  96
  97 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  98 #define PVR2_CTL_READ_ENDPOINT   0x81
  99
 100 #define PVR2_GPIO_IN 0x9008
 101 #define PVR2_GPIO_OUT 0x900c
 102 #define PVR2_GPIO_DIR 0x9020
 103
 104 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 105
 106 #define PVR2_FIRMWARE_ENDPOINT   0x02
 107
 108 /* size of a firmware chunk */
 109 #define FIRMWARE_CHUNK_SIZE 0x2000
 110
 111 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 112                                         struct v4l2_subdev *);
 113
 114 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 115         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 116         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 117         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 118         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 119         [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 120 };
 121
 122 static const char *module_names[] = {
 123         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 124         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 125         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 126         [PVR2_CLIENT_ID_TUNER] = "tuner",
 127         [PVR2_CLIENT_ID_DEMOD] = "tuner",
 128         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 129         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 130 };
 131
 132
 133 static const unsigned char *module_i2c_addresses[] = {
 134         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 135         [PVR2_CLIENT_ID_DEMOD] = "\x43",
 136         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 137         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 138         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 139         [PVR2_CLIENT_ID_CX25840] = "\x44",
 140         [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 141 };
 142
 143
 144 static const char *ir_scheme_names[] = {
 145         [PVR2_IR_SCHEME_NONE] = "none",
 146         [PVR2_IR_SCHEME_29XXX] = "29xxx",
 147         [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 148         [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 149         [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 150 };
 151
 152
 153 /* Define the list of additional controls we'll dynamically construct based
 154    on query of the cx2341x module. */
 155 struct pvr2_mpeg_ids {
 156         const char *strid;
 157         int id;
 158 };
 159 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 160         {
 161                 .strid = "audio_layer",
 162                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 163         },{
 164                 .strid = "audio_bitrate",
 165                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 166         },{
 167                 /* Already using audio_mode elsewhere :-( */
 168                 .strid = "mpeg_audio_mode",
 169                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 170         },{
 171                 .strid = "mpeg_audio_mode_extension",
 172                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 173         },{
 174                 .strid = "audio_emphasis",
 175                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 176         },{
 177                 .strid = "audio_crc",
 178                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 179         },{
 180                 .strid = "video_aspect",
 181                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 182         },{
 183                 .strid = "video_b_frames",
 184                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 185         },{
 186                 .strid = "video_gop_size",
 187                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 188         },{
 189                 .strid = "video_gop_closure",
 190                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 191         },{
 192                 .strid = "video_bitrate_mode",
 193                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 194         },{
 195                 .strid = "video_bitrate",
 196                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 197         },{
 198                 .strid = "video_bitrate_peak",
 199                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 200         },{
 201                 .strid = "video_temporal_decimation",
 202                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 203         },{
 204                 .strid = "stream_type",
 205                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 206         },{
 207                 .strid = "video_spatial_filter_mode",
 208                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 209         },{
 210                 .strid = "video_spatial_filter",
 211                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 212         },{
 213                 .strid = "video_luma_spatial_filter_type",
 214                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 215         },{
 216                 .strid = "video_chroma_spatial_filter_type",
 217                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 218         },{
 219                 .strid = "video_temporal_filter_mode",
 220                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 221         },{
 222                 .strid = "video_temporal_filter",
 223                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 224         },{
 225                 .strid = "video_median_filter_type",
 226                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 227         },{
 228                 .strid = "video_luma_median_filter_top",
 229                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 230         },{
 231                 .strid = "video_luma_median_filter_bottom",
 232                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 233         },{
 234                 .strid = "video_chroma_median_filter_top",
 235                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 236         },{
 237                 .strid = "video_chroma_median_filter_bottom",
 238                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 239         }
 240 };
 241 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 242
 243
 244 static const char *control_values_srate[] = {
 245         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 246         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 247         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 248 };
 249
 250
 251
 252 static const char *control_values_input[] = {
 253         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 254         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 255         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 256         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 257         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 258 };
 259
 260
 261 static const char *control_values_audiomode[] = {
 262         [V4L2_TUNER_MODE_MONO]   = "Mono",
 263         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 264         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 265         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 266         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 267 };
 268
 269
 270 static const char *control_values_hsm[] = {
 271         [PVR2_CVAL_HSM_FAIL] = "Fail",
 272         [PVR2_CVAL_HSM_HIGH] = "High",
 273         [PVR2_CVAL_HSM_FULL] = "Full",
 274 };
 275
 276
 277 static const char *pvr2_state_names[] = {
 278         [PVR2_STATE_NONE] =    "none",
 279         [PVR2_STATE_DEAD] =    "dead",
 280         [PVR2_STATE_COLD] =    "cold",
 281         [PVR2_STATE_WARM] =    "warm",
 282         [PVR2_STATE_ERROR] =   "error",
 283         [PVR2_STATE_READY] =   "ready",
 284         [PVR2_STATE_RUN] =     "run",
 285 };
 286
 287
 288 struct pvr2_fx2cmd_descdef {
 289         unsigned char id;
 290         unsigned char *desc;
 291 };
 292
 293 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 294         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 295         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 296         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 297         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 298         {FX2CMD_REG_WRITE, "write encoder register"},
 299         {FX2CMD_REG_READ, "read encoder register"},
 300         {FX2CMD_MEMSEL, "encoder memsel"},
 301         {FX2CMD_I2C_WRITE, "i2c write"},
 302         {FX2CMD_I2C_READ, "i2c read"},
 303         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 304         {FX2CMD_STREAMING_ON, "stream on"},
 305         {FX2CMD_STREAMING_OFF, "stream off"},
 306         {FX2CMD_FWPOST1, "fwpost1"},
 307         {FX2CMD_POWER_OFF, "power off"},
 308         {FX2CMD_POWER_ON, "power on"},
 309         {FX2CMD_DEEP_RESET, "deep reset"},
 310         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 311         {FX2CMD_GET_IR_CODE, "get IR code"},
 312         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 313         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 314         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 315         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 316         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 317         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 318         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 319 };
 320
 321
 322 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 323 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 324 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 325 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 326 static void pvr2_hdw_worker_poll(struct work_struct *work);
 327 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 328 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 329 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 330 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 331 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 332 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 333 static void pvr2_hdw_quiescent_timeout(unsigned long);
 334 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
 335 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 336 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 337 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 338 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 339                                 unsigned int timeout,int probe_fl,
 340                                 void *write_data,unsigned int write_len,
 341                                 void *read_data,unsigned int read_len);
 342 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 343 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
 344
 345 static void trace_stbit(const char *name,int val)
 346 {
 347         pvr2_trace(PVR2_TRACE_STBITS,
 348                    "State bit %s <-- %s",
 349                    name,(val ? "true" : "false"));
 350 }
 351
 352 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 353 {
 354         struct pvr2_hdw *hdw = cptr->hdw;
 355         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 356                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 357         } else {
 358                 *vp = 0;
 359         }
 360         return 0;
 361 }
 362
 363 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 364 {
 365         struct pvr2_hdw *hdw = cptr->hdw;
 366         unsigned int slotId = hdw->freqProgSlot;
 367         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 368                 hdw->freqTable[slotId-1] = v;
 369                 /* Handle side effects correctly - if we're tuned to this
 370                    slot, then forgot the slot id relation since the stored
 371                    frequency has been changed. */
 372                 if (hdw->freqSelector) {
 373                         if (hdw->freqSlotRadio == slotId) {
 374                                 hdw->freqSlotRadio = 0;
 375                         }
 376                 } else {
 377                         if (hdw->freqSlotTelevision == slotId) {
 378                                 hdw->freqSlotTelevision = 0;
 379                         }
 380                 }
 381         }
 382         return 0;
 383 }
 384
 385 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 386 {
 387         *vp = cptr->hdw->freqProgSlot;
 388         return 0;
 389 }
 390
 391 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 392 {
 393         struct pvr2_hdw *hdw = cptr->hdw;
 394         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 395                 hdw->freqProgSlot = v;
 396         }
 397         return 0;
 398 }
 399
 400 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 401 {
 402         struct pvr2_hdw *hdw = cptr->hdw;
 403         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 404         return 0;
 405 }
 406
 407 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 408 {
 409         unsigned freq = 0;
 410         struct pvr2_hdw *hdw = cptr->hdw;
 411         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 412         if (slotId > 0) {
 413                 freq = hdw->freqTable[slotId-1];
 414                 if (!freq) return 0;
 415                 pvr2_hdw_set_cur_freq(hdw,freq);
 416         }
 417         if (hdw->freqSelector) {
 418                 hdw->freqSlotRadio = slotId;
 419         } else {
 420                 hdw->freqSlotTelevision = slotId;
 421         }
 422         return 0;
 423 }
 424
 425 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 426 {
 427         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 428         return 0;
 429 }
 430
 431 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 432 {
 433         return cptr->hdw->freqDirty != 0;
 434 }
 435
 436 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 437 {
 438         cptr->hdw->freqDirty = 0;
 439 }
 440
 441 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 442 {
 443         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 444         return 0;
 445 }
 446
 447 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 448 {
 449         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 450         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 451         if (stat != 0) {
 452                 return stat;
 453         }
 454         *left = cap->bounds.left;
 455         return 0;
 456 }
 457
 458 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 459 {
 460         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 461         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 462         if (stat != 0) {
 463                 return stat;
 464         }
 465         *left = cap->bounds.left;
 466         if (cap->bounds.width > cptr->hdw->cropw_val) {
 467                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 468         }
 469         return 0;
 470 }
 471
 472 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 473 {
 474         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 475         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 476         if (stat != 0) {
 477                 return stat;
 478         }
 479         *top = cap->bounds.top;
 480         return 0;
 481 }
 482
 483 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 484 {
 485         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 486         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 487         if (stat != 0) {
 488                 return stat;
 489         }
 490         *top = cap->bounds.top;
 491         if (cap->bounds.height > cptr->hdw->croph_val) {
 492                 *top += cap->bounds.height - cptr->hdw->croph_val;
 493         }
 494         return 0;
 495 }
 496
 497 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
 498 {
 499         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 500         int stat, bleftend, cleft;
 501
 502         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 503         if (stat != 0) {
 504                 return stat;
 505         }
 506         bleftend = cap->bounds.left+cap->bounds.width;
 507         cleft = cptr->hdw->cropl_val;
 508
 509         *width = cleft < bleftend ? bleftend-cleft : 0;
 510         return 0;
 511 }
 512
 513 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
 514 {
 515         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 516         int stat, btopend, ctop;
 517
 518         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 519         if (stat != 0) {
 520                 return stat;
 521         }
 522         btopend = cap->bounds.top+cap->bounds.height;
 523         ctop = cptr->hdw->cropt_val;
 524
 525         *height = ctop < btopend ? btopend-ctop : 0;
 526         return 0;
 527 }
 528
 529 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 530 {
 531         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 532         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 533         if (stat != 0) {
 534                 return stat;
 535         }
 536         *val = cap->bounds.left;
 537         return 0;
 538 }
 539
 540 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 541 {
 542         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 543         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 544         if (stat != 0) {
 545                 return stat;
 546         }
 547         *val = cap->bounds.top;
 548         return 0;
 549 }
 550
 551 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 552 {
 553         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 554         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 555         if (stat != 0) {
 556                 return stat;
 557         }
 558         *val = cap->bounds.width;
 559         return 0;
 560 }
 561
 562 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 563 {
 564         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 565         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 566         if (stat != 0) {
 567                 return stat;
 568         }
 569         *val = cap->bounds.height;
 570         return 0;
 571 }
 572
 573 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 574 {
 575         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 576         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 577         if (stat != 0) {
 578                 return stat;
 579         }
 580         *val = cap->defrect.left;
 581         return 0;
 582 }
 583
 584 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 585 {
 586         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 587         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 588         if (stat != 0) {
 589                 return stat;
 590         }
 591         *val = cap->defrect.top;
 592         return 0;
 593 }
 594
 595 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 596 {
 597         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 598         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 599         if (stat != 0) {
 600                 return stat;
 601         }
 602         *val = cap->defrect.width;
 603         return 0;
 604 }
 605
 606 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 607 {
 608         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 609         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 610         if (stat != 0) {
 611                 return stat;
 612         }
 613         *val = cap->defrect.height;
 614         return 0;
 615 }
 616
 617 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 618 {
 619         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 620         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 621         if (stat != 0) {
 622                 return stat;
 623         }
 624         *val = cap->pixelaspect.numerator;
 625         return 0;
 626 }
 627
 628 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 629 {
 630         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 631         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 632         if (stat != 0) {
 633                 return stat;
 634         }
 635         *val = cap->pixelaspect.denominator;
 636         return 0;
 637 }
 638
 639 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 640 {
 641         /* Actual maximum depends on the video standard in effect. */
 642         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 643                 *vp = 480;
 644         } else {
 645                 *vp = 576;
 646         }
 647         return 0;
 648 }
 649
 650 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 651 {
 652         /* Actual minimum depends on device digitizer type. */
 653         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 654                 *vp = 75;
 655         } else {
 656                 *vp = 17;
 657         }
 658         return 0;
 659 }
 660
 661 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 662 {
 663         *vp = cptr->hdw->input_val;
 664         return 0;
 665 }
 666
 667 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 668 {
 669         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 670 }
 671
 672 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 673 {
 674         return pvr2_hdw_set_input(cptr->hdw,v);
 675 }
 676
 677 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 678 {
 679         return cptr->hdw->input_dirty != 0;
 680 }
 681
 682 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 683 {
 684         cptr->hdw->input_dirty = 0;
 685 }
 686
 687
 688 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 689 {
 690         unsigned long fv;
 691         struct pvr2_hdw *hdw = cptr->hdw;
 692         if (hdw->tuner_signal_stale) {
 693                 pvr2_hdw_status_poll(hdw);
 694         }
 695         fv = hdw->tuner_signal_info.rangehigh;
 696         if (!fv) {
 697                 /* Safety fallback */
 698                 *vp = TV_MAX_FREQ;
 699                 return 0;
 700         }
 701         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 702                 fv = (fv * 125) / 2;
 703         } else {
 704                 fv = fv * 62500;
 705         }
 706         *vp = fv;
 707         return 0;
 708 }
 709
 710 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 711 {
 712         unsigned long fv;
 713         struct pvr2_hdw *hdw = cptr->hdw;
 714         if (hdw->tuner_signal_stale) {
 715                 pvr2_hdw_status_poll(hdw);
 716         }
 717         fv = hdw->tuner_signal_info.rangelow;
 718         if (!fv) {
 719                 /* Safety fallback */
 720                 *vp = TV_MIN_FREQ;
 721                 return 0;
 722         }
 723         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 724                 fv = (fv * 125) / 2;
 725         } else {
 726                 fv = fv * 62500;
 727         }
 728         *vp = fv;
 729         return 0;
 730 }
 731
 732 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 733 {
 734         return cptr->hdw->enc_stale != 0;
 735 }
 736
 737 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 738 {
 739         cptr->hdw->enc_stale = 0;
 740         cptr->hdw->enc_unsafe_stale = 0;
 741 }
 742
 743 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 744 {
 745         int ret;
 746         struct v4l2_ext_controls cs;
 747         struct v4l2_ext_control c1;
 748         memset(&cs,0,sizeof(cs));
 749         memset(&c1,0,sizeof(c1));
 750         cs.controls = &c1;
 751         cs.count = 1;
 752         c1.id = cptr->info->v4l_id;
 753         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 754                                 VIDIOC_G_EXT_CTRLS);
 755         if (ret) return ret;
 756         *vp = c1.value;
 757         return 0;
 758 }
 759
 760 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 761 {
 762         int ret;
 763         struct pvr2_hdw *hdw = cptr->hdw;
 764         struct v4l2_ext_controls cs;
 765         struct v4l2_ext_control c1;
 766         memset(&cs,0,sizeof(cs));
 767         memset(&c1,0,sizeof(c1));
 768         cs.controls = &c1;
 769         cs.count = 1;
 770         c1.id = cptr->info->v4l_id;
 771         c1.value = v;
 772         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 773                                 hdw->state_encoder_run, &cs,
 774                                 VIDIOC_S_EXT_CTRLS);
 775         if (ret == -EBUSY) {
 776                 /* Oops.  cx2341x is telling us it's not safe to change
 777                    this control while we're capturing.  Make a note of this
 778                    fact so that the pipeline will be stopped the next time
 779                    controls are committed.  Then go on ahead and store this
 780                    change anyway. */
 781                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 782                                         0, &cs,
 783                                         VIDIOC_S_EXT_CTRLS);
 784                 if (!ret) hdw->enc_unsafe_stale = !0;
 785         }
 786         if (ret) return ret;
 787         hdw->enc_stale = !0;
 788         return 0;
 789 }
 790
 791 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 792 {
 793         struct v4l2_queryctrl qctrl;
 794         struct pvr2_ctl_info *info;
 795         qctrl.id = cptr->info->v4l_id;
 796         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 797         /* Strip out the const so we can adjust a function pointer.  It's
 798            OK to do this here because we know this is a dynamically created
 799            control, so the underlying storage for the info pointer is (a)
 800            private to us, and (b) not in read-only storage.  Either we do
 801            this or we significantly complicate the underlying control
 802            implementation. */
 803         info = (struct pvr2_ctl_info *)(cptr->info);
 804         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 805                 if (info->set_value) {
 806                         info->set_value = NULL;
 807                 }
 808         } else {
 809                 if (!(info->set_value)) {
 810                         info->set_value = ctrl_cx2341x_set;
 811                 }
 812         }
 813         return qctrl.flags;
 814 }
 815
 816 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 817 {
 818         *vp = cptr->hdw->state_pipeline_req;
 819         return 0;
 820 }
 821
 822 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 823 {
 824         *vp = cptr->hdw->master_state;
 825         return 0;
 826 }
 827
 828 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 829 {
 830         int result = pvr2_hdw_is_hsm(cptr->hdw);
 831         *vp = PVR2_CVAL_HSM_FULL;
 832         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 833         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 834         return 0;
 835 }
 836
 837 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
 838 {
 839         *vp = pvr2_hdw_get_detected_std(cptr->hdw);
 840         return 0;
 841 }
 842
 843 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 844 {
 845         *vp = cptr->hdw->std_mask_avail;
 846         return 0;
 847 }
 848
 849 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 850 {
 851         struct pvr2_hdw *hdw = cptr->hdw;
 852         v4l2_std_id ns;
 853         ns = hdw->std_mask_avail;
 854         ns = (ns & ~m) | (v & m);
 855         if (ns == hdw->std_mask_avail) return 0;
 856         hdw->std_mask_avail = ns;
 857         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
 858         return 0;
 859 }
 860
 861 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 862                                char *bufPtr,unsigned int bufSize,
 863                                unsigned int *len)
 864 {
 865         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 866         return 0;
 867 }
 868
 869 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 870                                const char *bufPtr,unsigned int bufSize,
 871                                int *mskp,int *valp)
 872 {
 873         int ret;
 874         v4l2_std_id id;
 875         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 876         if (ret < 0) return ret;
 877         if (mskp) *mskp = id;
 878         if (valp) *valp = id;
 879         return 0;
 880 }
 881
 882 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 883 {
 884         *vp = cptr->hdw->std_mask_cur;
 885         return 0;
 886 }
 887
 888 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 889 {
 890         struct pvr2_hdw *hdw = cptr->hdw;
 891         v4l2_std_id ns;
 892         ns = hdw->std_mask_cur;
 893         ns = (ns & ~m) | (v & m);
 894         if (ns == hdw->std_mask_cur) return 0;
 895         hdw->std_mask_cur = ns;
 896         hdw->std_dirty = !0;
 897         return 0;
 898 }
 899
 900 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 901 {
 902         return cptr->hdw->std_dirty != 0;
 903 }
 904
 905 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 906 {
 907         cptr->hdw->std_dirty = 0;
 908 }
 909
 910 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 911 {
 912         struct pvr2_hdw *hdw = cptr->hdw;
 913         pvr2_hdw_status_poll(hdw);
 914         *vp = hdw->tuner_signal_info.signal;
 915         return 0;
 916 }
 917
 918 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 919 {
 920         int val = 0;
 921         unsigned int subchan;
 922         struct pvr2_hdw *hdw = cptr->hdw;
 923         pvr2_hdw_status_poll(hdw);
 924         subchan = hdw->tuner_signal_info.rxsubchans;
 925         if (subchan & V4L2_TUNER_SUB_MONO) {
 926                 val |= (1 << V4L2_TUNER_MODE_MONO);
 927         }
 928         if (subchan & V4L2_TUNER_SUB_STEREO) {
 929                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 930         }
 931         if (subchan & V4L2_TUNER_SUB_LANG1) {
 932                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 933         }
 934         if (subchan & V4L2_TUNER_SUB_LANG2) {
 935                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 936         }
 937         *vp = val;
 938         return 0;
 939 }
 940
 941
 942 #define DEFINT(vmin,vmax) \
 943         .type = pvr2_ctl_int, \
 944         .def.type_int.min_value = vmin, \
 945         .def.type_int.max_value = vmax
 946
 947 #define DEFENUM(tab) \
 948         .type = pvr2_ctl_enum, \
 949         .def.type_enum.count = ARRAY_SIZE(tab), \
 950         .def.type_enum.value_names = tab
 951
 952 #define DEFBOOL \
 953         .type = pvr2_ctl_bool
 954
 955 #define DEFMASK(msk,tab) \
 956         .type = pvr2_ctl_bitmask, \
 957         .def.type_bitmask.valid_bits = msk, \
 958         .def.type_bitmask.bit_names = tab
 959
 960 #define DEFREF(vname) \
 961         .set_value = ctrl_set_##vname, \
 962         .get_value = ctrl_get_##vname, \
 963         .is_dirty = ctrl_isdirty_##vname, \
 964         .clear_dirty = ctrl_cleardirty_##vname
 965
 966
 967 #define VCREATE_FUNCS(vname) \
 968 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 969 {*vp = cptr->hdw->vname##_val; return 0;} \
 970 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 971 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 972 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 973 {return cptr->hdw->vname##_dirty != 0;} \
 974 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 975 {cptr->hdw->vname##_dirty = 0;}
 976
 977 VCREATE_FUNCS(brightness)
 978 VCREATE_FUNCS(contrast)
 979 VCREATE_FUNCS(saturation)
 980 VCREATE_FUNCS(hue)
 981 VCREATE_FUNCS(volume)
 982 VCREATE_FUNCS(balance)
 983 VCREATE_FUNCS(bass)
 984 VCREATE_FUNCS(treble)
 985 VCREATE_FUNCS(mute)
 986 VCREATE_FUNCS(cropl)
 987 VCREATE_FUNCS(cropt)
 988 VCREATE_FUNCS(cropw)
 989 VCREATE_FUNCS(croph)
 990 VCREATE_FUNCS(audiomode)
 991 VCREATE_FUNCS(res_hor)
 992 VCREATE_FUNCS(res_ver)
 993 VCREATE_FUNCS(srate)
 994
 995 /* Table definition of all controls which can be manipulated */
 996 static const struct pvr2_ctl_info control_defs[] = {
 997         {
 998                 .v4l_id = V4L2_CID_BRIGHTNESS,
 999                 .desc = "Brightness",
1000                 .name = "brightness",
1001                 .default_value = 128,
1002                 DEFREF(brightness),
1003                 DEFINT(0,255),
1004         },{
1005                 .v4l_id = V4L2_CID_CONTRAST,
1006                 .desc = "Contrast",
1007                 .name = "contrast",
1008                 .default_value = 68,
1009                 DEFREF(contrast),
1010                 DEFINT(0,127),
1011         },{
1012                 .v4l_id = V4L2_CID_SATURATION,
1013                 .desc = "Saturation",
1014                 .name = "saturation",
1015                 .default_value = 64,
1016                 DEFREF(saturation),
1017                 DEFINT(0,127),
1018         },{
1019                 .v4l_id = V4L2_CID_HUE,
1020                 .desc = "Hue",
1021                 .name = "hue",
1022                 .default_value = 0,
1023                 DEFREF(hue),
1024                 DEFINT(-128,127),
1025         },{
1026                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1027                 .desc = "Volume",
1028                 .name = "volume",
1029                 .default_value = 62000,
1030                 DEFREF(volume),
1031                 DEFINT(0,65535),
1032         },{
1033                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1034                 .desc = "Balance",
1035                 .name = "balance",
1036                 .default_value = 0,
1037                 DEFREF(balance),
1038                 DEFINT(-32768,32767),
1039         },{
1040                 .v4l_id = V4L2_CID_AUDIO_BASS,
1041                 .desc = "Bass",
1042                 .name = "bass",
1043                 .default_value = 0,
1044                 DEFREF(bass),
1045                 DEFINT(-32768,32767),
1046         },{
1047                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1048                 .desc = "Treble",
1049                 .name = "treble",
1050                 .default_value = 0,
1051                 DEFREF(treble),
1052                 DEFINT(-32768,32767),
1053         },{
1054                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1055                 .desc = "Mute",
1056                 .name = "mute",
1057                 .default_value = 0,
1058                 DEFREF(mute),
1059                 DEFBOOL,
1060         }, {
1061                 .desc = "Capture crop left margin",
1062                 .name = "crop_left",
1063                 .internal_id = PVR2_CID_CROPL,
1064                 .default_value = 0,
1065                 DEFREF(cropl),
1066                 DEFINT(-129, 340),
1067                 .get_min_value = ctrl_cropl_min_get,
1068                 .get_max_value = ctrl_cropl_max_get,
1069                 .get_def_value = ctrl_get_cropcapdl,
1070         }, {
1071                 .desc = "Capture crop top margin",
1072                 .name = "crop_top",
1073                 .internal_id = PVR2_CID_CROPT,
1074                 .default_value = 0,
1075                 DEFREF(cropt),
1076                 DEFINT(-35, 544),
1077                 .get_min_value = ctrl_cropt_min_get,
1078                 .get_max_value = ctrl_cropt_max_get,
1079                 .get_def_value = ctrl_get_cropcapdt,
1080         }, {
1081                 .desc = "Capture crop width",
1082                 .name = "crop_width",
1083                 .internal_id = PVR2_CID_CROPW,
1084                 .default_value = 720,
1085                 DEFREF(cropw),
1086                 DEFINT(0, 864),
1087                 .get_max_value = ctrl_cropw_max_get,
1088                 .get_def_value = ctrl_get_cropcapdw,
1089         }, {
1090                 .desc = "Capture crop height",
1091                 .name = "crop_height",
1092                 .internal_id = PVR2_CID_CROPH,
1093                 .default_value = 480,
1094                 DEFREF(croph),
1095                 DEFINT(0, 576),
1096                 .get_max_value = ctrl_croph_max_get,
1097                 .get_def_value = ctrl_get_cropcapdh,
1098         }, {
1099                 .desc = "Capture capability pixel aspect numerator",
1100                 .name = "cropcap_pixel_numerator",
1101                 .internal_id = PVR2_CID_CROPCAPPAN,
1102                 .get_value = ctrl_get_cropcappan,
1103         }, {
1104                 .desc = "Capture capability pixel aspect denominator",
1105                 .name = "cropcap_pixel_denominator",
1106                 .internal_id = PVR2_CID_CROPCAPPAD,
1107                 .get_value = ctrl_get_cropcappad,
1108         }, {
1109                 .desc = "Capture capability bounds top",
1110                 .name = "cropcap_bounds_top",
1111                 .internal_id = PVR2_CID_CROPCAPBT,
1112                 .get_value = ctrl_get_cropcapbt,
1113         }, {
1114                 .desc = "Capture capability bounds left",
1115                 .name = "cropcap_bounds_left",
1116                 .internal_id = PVR2_CID_CROPCAPBL,
1117                 .get_value = ctrl_get_cropcapbl,
1118         }, {
1119                 .desc = "Capture capability bounds width",
1120                 .name = "cropcap_bounds_width",
1121                 .internal_id = PVR2_CID_CROPCAPBW,
1122                 .get_value = ctrl_get_cropcapbw,
1123         }, {
1124                 .desc = "Capture capability bounds height",
1125                 .name = "cropcap_bounds_height",
1126                 .internal_id = PVR2_CID_CROPCAPBH,
1127                 .get_value = ctrl_get_cropcapbh,
1128         },{
1129                 .desc = "Video Source",
1130                 .name = "input",
1131                 .internal_id = PVR2_CID_INPUT,
1132                 .default_value = PVR2_CVAL_INPUT_TV,
1133                 .check_value = ctrl_check_input,
1134                 DEFREF(input),
1135                 DEFENUM(control_values_input),
1136         },{
1137                 .desc = "Audio Mode",
1138                 .name = "audio_mode",
1139                 .internal_id = PVR2_CID_AUDIOMODE,
1140                 .default_value = V4L2_TUNER_MODE_STEREO,
1141                 DEFREF(audiomode),
1142                 DEFENUM(control_values_audiomode),
1143         },{
1144                 .desc = "Horizontal capture resolution",
1145                 .name = "resolution_hor",
1146                 .internal_id = PVR2_CID_HRES,
1147                 .default_value = 720,
1148                 DEFREF(res_hor),
1149                 DEFINT(19,720),
1150         },{
1151                 .desc = "Vertical capture resolution",
1152                 .name = "resolution_ver",
1153                 .internal_id = PVR2_CID_VRES,
1154                 .default_value = 480,
1155                 DEFREF(res_ver),
1156                 DEFINT(17,576),
1157                 /* Hook in check for video standard and adjust maximum
1158                    depending on the standard. */
1159                 .get_max_value = ctrl_vres_max_get,
1160                 .get_min_value = ctrl_vres_min_get,
1161         },{
1162                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1163                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1164                 .desc = "Audio Sampling Frequency",
1165                 .name = "srate",
1166                 DEFREF(srate),
1167                 DEFENUM(control_values_srate),
1168         },{
1169                 .desc = "Tuner Frequency (Hz)",
1170                 .name = "frequency",
1171                 .internal_id = PVR2_CID_FREQUENCY,
1172                 .default_value = 0,
1173                 .set_value = ctrl_freq_set,
1174                 .get_value = ctrl_freq_get,
1175                 .is_dirty = ctrl_freq_is_dirty,
1176                 .clear_dirty = ctrl_freq_clear_dirty,
1177                 DEFINT(0,0),
1178                 /* Hook in check for input value (tv/radio) and adjust
1179                    max/min values accordingly */
1180                 .get_max_value = ctrl_freq_max_get,
1181                 .get_min_value = ctrl_freq_min_get,
1182         },{
1183                 .desc = "Channel",
1184                 .name = "channel",
1185                 .set_value = ctrl_channel_set,
1186                 .get_value = ctrl_channel_get,
1187                 DEFINT(0,FREQTABLE_SIZE),
1188         },{
1189                 .desc = "Channel Program Frequency",
1190                 .name = "freq_table_value",
1191                 .set_value = ctrl_channelfreq_set,
1192                 .get_value = ctrl_channelfreq_get,
1193                 DEFINT(0,0),
1194                 /* Hook in check for input value (tv/radio) and adjust
1195                    max/min values accordingly */
1196                 .get_max_value = ctrl_freq_max_get,
1197                 .get_min_value = ctrl_freq_min_get,
1198         },{
1199                 .desc = "Channel Program ID",
1200                 .name = "freq_table_channel",
1201                 .set_value = ctrl_channelprog_set,
1202                 .get_value = ctrl_channelprog_get,
1203                 DEFINT(0,FREQTABLE_SIZE),
1204         },{
1205                 .desc = "Streaming Enabled",
1206                 .name = "streaming_enabled",
1207                 .get_value = ctrl_streamingenabled_get,
1208                 DEFBOOL,
1209         },{
1210                 .desc = "USB Speed",
1211                 .name = "usb_speed",
1212                 .get_value = ctrl_hsm_get,
1213                 DEFENUM(control_values_hsm),
1214         },{
1215                 .desc = "Master State",
1216                 .name = "master_state",
1217                 .get_value = ctrl_masterstate_get,
1218                 DEFENUM(pvr2_state_names),
1219         },{
1220                 .desc = "Signal Present",
1221                 .name = "signal_present",
1222                 .get_value = ctrl_signal_get,
1223                 DEFINT(0,65535),
1224         },{
1225                 .desc = "Audio Modes Present",
1226                 .name = "audio_modes_present",
1227                 .get_value = ctrl_audio_modes_present_get,
1228                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1229                    v4l.  Nothing outside of this module cares about this,
1230                    but I reuse it in order to also reuse the
1231                    control_values_audiomode string table. */
1232                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1233                          (1 << V4L2_TUNER_MODE_STEREO)|
1234                          (1 << V4L2_TUNER_MODE_LANG1)|
1235                          (1 << V4L2_TUNER_MODE_LANG2)),
1236                         control_values_audiomode),
1237         },{
1238                 .desc = "Video Standards Available Mask",
1239                 .name = "video_standard_mask_available",
1240                 .internal_id = PVR2_CID_STDAVAIL,
1241                 .skip_init = !0,
1242                 .get_value = ctrl_stdavail_get,
1243                 .set_value = ctrl_stdavail_set,
1244                 .val_to_sym = ctrl_std_val_to_sym,
1245                 .sym_to_val = ctrl_std_sym_to_val,
1246                 .type = pvr2_ctl_bitmask,
1247         },{
1248                 .desc = "Video Standards In Use Mask",
1249                 .name = "video_standard_mask_active",
1250                 .internal_id = PVR2_CID_STDCUR,
1251                 .skip_init = !0,
1252                 .get_value = ctrl_stdcur_get,
1253                 .set_value = ctrl_stdcur_set,
1254                 .is_dirty = ctrl_stdcur_is_dirty,
1255                 .clear_dirty = ctrl_stdcur_clear_dirty,
1256                 .val_to_sym = ctrl_std_val_to_sym,
1257                 .sym_to_val = ctrl_std_sym_to_val,
1258                 .type = pvr2_ctl_bitmask,
1259         },{
1260                 .desc = "Video Standards Detected Mask",
1261                 .name = "video_standard_mask_detected",
1262                 .internal_id = PVR2_CID_STDDETECT,
1263                 .skip_init = !0,
1264                 .get_value = ctrl_stddetect_get,
1265                 .val_to_sym = ctrl_std_val_to_sym,
1266                 .sym_to_val = ctrl_std_sym_to_val,
1267                 .type = pvr2_ctl_bitmask,
1268         }
1269 };
1270
1271 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1272
1273
1274 const char *pvr2_config_get_name(enum pvr2_config cfg)
1275 {
1276         switch (cfg) {
1277         case pvr2_config_empty: return "empty";
1278         case pvr2_config_mpeg: return "mpeg";
1279         case pvr2_config_vbi: return "vbi";
1280         case pvr2_config_pcm: return "pcm";
1281         case pvr2_config_rawvideo: return "raw video";
1282         }
1283         return "<unknown>";
1284 }
1285
1286
1287 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1288 {
1289         return hdw->usb_dev;
1290 }
1291
1292
1293 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1294 {
1295         return hdw->serial_number;
1296 }
1297
1298
1299 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1300 {
1301         return hdw->bus_info;
1302 }
1303
1304
1305 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1306 {
1307         return hdw->identifier;
1308 }
1309
1310
1311 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1312 {
1313         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1314 }
1315
1316 /* Set the currently tuned frequency and account for all possible
1317    driver-core side effects of this action. */
1318 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1319 {
1320         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1321                 if (hdw->freqSelector) {
1322                         /* Swing over to radio frequency selection */
1323                         hdw->freqSelector = 0;
1324                         hdw->freqDirty = !0;
1325                 }
1326                 if (hdw->freqValRadio != val) {
1327                         hdw->freqValRadio = val;
1328                         hdw->freqSlotRadio = 0;
1329                         hdw->freqDirty = !0;
1330                 }
1331         } else {
1332                 if (!(hdw->freqSelector)) {
1333                         /* Swing over to television frequency selection */
1334                         hdw->freqSelector = 1;
1335                         hdw->freqDirty = !0;
1336                 }
1337                 if (hdw->freqValTelevision != val) {
1338                         hdw->freqValTelevision = val;
1339                         hdw->freqSlotTelevision = 0;
1340                         hdw->freqDirty = !0;
1341                 }
1342         }
1343 }
1344
1345 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1346 {
1347         return hdw->unit_number;
1348 }
1349
1350
1351 /* Attempt to locate one of the given set of files.  Messages are logged
1352    appropriate to what has been found.  The return value will be 0 or
1353    greater on success (it will be the index of the file name found) and
1354    fw_entry will be filled in.  Otherwise a negative error is returned on
1355    failure.  If the return value is -ENOENT then no viable firmware file
1356    could be located. */
1357 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1358                                 const struct firmware **fw_entry,
1359                                 const char *fwtypename,
1360                                 unsigned int fwcount,
1361                                 const char *fwnames[])
1362 {
1363         unsigned int idx;
1364         int ret = -EINVAL;
1365         for (idx = 0; idx < fwcount; idx++) {
1366                 ret = reject_firmware(fw_entry,
1367                                        fwnames[idx],
1368                                        &hdw->usb_dev->dev);
1369                 if (!ret) {
1370                         trace_firmware("Located %s firmware: %s; uploading...",
1371                                        fwtypename,
1372                                        fwnames[idx]);
1373                         return idx;
1374                 }
1375                 if (ret == -ENOENT) continue;
1376                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1377                            "request_firmware fatal error with code=%d",ret);
1378                 return ret;
1379         }
1380         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1381                    "***WARNING*** Device %s firmware seems to be missing.",
1382                    fwtypename);
1383         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1384                    "Did you install the pvrusb2 firmware files in their proper location?");
1385         if (fwcount == 1) {
1386                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1387                            "request_firmware unable to locate %s file %s",
1388                            fwtypename,fwnames[0]);
1389         } else {
1390                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391                            "request_firmware unable to locate one of the following %s files:",
1392                            fwtypename);
1393                 for (idx = 0; idx < fwcount; idx++) {
1394                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1395                                    "reject_firmware: Failed to find %s",
1396                                    fwnames[idx]);
1397                 }
1398         }
1399         return ret;
1400 }
1401
1402
1403 /*
1404  * pvr2_upload_firmware1().
1405  *
1406  * Send the 8051 firmware to the device.  After the upload, arrange for
1407  * device to re-enumerate.
1408  *
1409  * NOTE : the pointer to the firmware data given by reject_firmware()
1410  * is not suitable for an usb transaction.
1411  *
1412  */
1413 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1414 {
1415         const struct firmware *fw_entry = NULL;
1416         void  *fw_ptr;
1417         unsigned int pipe;
1418         unsigned int fwsize;
1419         int ret;
1420         u16 address;
1421
1422         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1423                 hdw->fw1_state = FW1_STATE_OK;
1424                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425                            "Connected device type defines no firmware to upload; ignoring firmware");
1426                 return -ENOTTY;
1427         }
1428
1429         hdw->fw1_state = FW1_STATE_FAILED; // default result
1430
1431         trace_firmware("pvr2_upload_firmware1");
1432
1433         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1434                                    hdw->hdw_desc->fx2_firmware.cnt,
1435                                    hdw->hdw_desc->fx2_firmware.lst);
1436         if (ret < 0) {
1437                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1438                 return ret;
1439         }
1440
1441         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1442
1443         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1444         fwsize = fw_entry->size;
1445
1446         if ((fwsize != 0x2000) &&
1447             (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1448                 if (hdw->hdw_desc->flag_fx2_16kb) {
1449                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1450                                    "Wrong fx2 firmware size (expected 8192 or 16384, got %u)",
1451                                    fwsize);
1452                 } else {
1453                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1454                                    "Wrong fx2 firmware size (expected 8192, got %u)",
1455                                    fwsize);
1456                 }
1457                 release_firmware(fw_entry);
1458                 return -ENOMEM;
1459         }
1460
1461         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1462         if (fw_ptr == NULL){
1463                 release_firmware(fw_entry);
1464                 return -ENOMEM;
1465         }
1466
1467         /* We have to hold the CPU during firmware upload. */
1468         pvr2_hdw_cpureset_assert(hdw,1);
1469
1470         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1471            chunk. */
1472
1473         ret = 0;
1474         for (address = 0; address < fwsize; address += 0x800) {
1475                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1476                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1477                                        0, fw_ptr, 0x800, HZ);
1478         }
1479
1480         trace_firmware("Upload done, releasing device's CPU");
1481
1482         /* Now release the CPU.  It will disconnect and reconnect later. */
1483         pvr2_hdw_cpureset_assert(hdw,0);
1484
1485         kfree(fw_ptr);
1486         release_firmware(fw_entry);
1487
1488         trace_firmware("Upload done (%d bytes sent)",ret);
1489
1490         /* We should have written fwsize bytes */
1491         if (ret == fwsize) {
1492                 hdw->fw1_state = FW1_STATE_RELOAD;
1493                 return 0;
1494         }
1495
1496         return -EIO;
1497 }
1498
1499
1500 /*
1501  * pvr2_upload_firmware2()
1502  *
1503  * This uploads encoder firmware on endpoint 2.
1504  *
1505  */
1506
1507 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1508 {
1509         const struct firmware *fw_entry = NULL;
1510         void  *fw_ptr;
1511         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1512         int actual_length;
1513         int ret = 0;
1514         int fwidx;
1515         static const char *fw_files[] = {
1516                 CX2341X_FIRM_ENC_FILENAME,
1517         };
1518
1519         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1520                 return 0;
1521         }
1522
1523         trace_firmware("pvr2_upload_firmware2");
1524
1525         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1526                                    ARRAY_SIZE(fw_files), fw_files);
1527         if (ret < 0) return ret;
1528         fwidx = ret;
1529         ret = 0;
1530         /* Since we're about to completely reinitialize the encoder,
1531            invalidate our cached copy of its configuration state.  Next
1532            time we configure the encoder, then we'll fully configure it. */
1533         hdw->enc_cur_valid = 0;
1534
1535         /* Encoder is about to be reset so note that as far as we're
1536            concerned now, the encoder has never been run. */
1537         del_timer_sync(&hdw->encoder_run_timer);
1538         if (hdw->state_encoder_runok) {
1539                 hdw->state_encoder_runok = 0;
1540                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1541         }
1542
1543         /* First prepare firmware loading */
1544         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1545         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1546         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1547         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1548         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1549         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1550         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1551         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1552         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1553         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1554         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1555         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1556         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1557         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1558         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1559         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1560         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1561         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1562
1563         if (ret) {
1564                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1565                            "firmware2 upload prep failed, ret=%d",ret);
1566                 release_firmware(fw_entry);
1567                 goto done;
1568         }
1569
1570         /* Now send firmware */
1571
1572         fw_len = fw_entry->size;
1573
1574         if (fw_len % sizeof(u32)) {
1575                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1576                            "size of %s firmware must be a multiple of %zu bytes",
1577                            fw_files[fwidx],sizeof(u32));
1578                 release_firmware(fw_entry);
1579                 ret = -EINVAL;
1580                 goto done;
1581         }
1582
1583         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1584         if (fw_ptr == NULL){
1585                 release_firmware(fw_entry);
1586                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1587                            "failed to allocate memory for firmware2 upload");
1588                 ret = -ENOMEM;
1589                 goto done;
1590         }
1591
1592         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1593
1594         fw_done = 0;
1595         for (fw_done = 0; fw_done < fw_len;) {
1596                 bcnt = fw_len - fw_done;
1597                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1598                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1599                 /* Usbsnoop log shows that we must swap bytes... */
1600                 /* Some background info: The data being swapped here is a
1601                    firmware image destined for the mpeg encoder chip that
1602                    lives at the other end of a USB endpoint.  The encoder
1603                    chip always talks in 32 bit chunks and its storage is
1604                    organized into 32 bit words.  However from the file
1605                    system to the encoder chip everything is purely a byte
1606                    stream.  The firmware file's contents are always 32 bit
1607                    swapped from what the encoder expects.  Thus the need
1608                    always exists to swap the bytes regardless of the endian
1609                    type of the host processor and therefore swab32() makes
1610                    the most sense. */
1611                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1612                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1613
1614                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1615                                     &actual_length, HZ);
1616                 ret |= (actual_length != bcnt);
1617                 if (ret) break;
1618                 fw_done += bcnt;
1619         }
1620
1621         trace_firmware("upload of %s : %i / %i ",
1622                        fw_files[fwidx],fw_done,fw_len);
1623
1624         kfree(fw_ptr);
1625         release_firmware(fw_entry);
1626
1627         if (ret) {
1628                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1629                            "firmware2 upload transfer failure");
1630                 goto done;
1631         }
1632
1633         /* Finish upload */
1634
1635         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1636         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1637         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1638
1639         if (ret) {
1640                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1641                            "firmware2 upload post-proc failure");
1642         }
1643
1644  done:
1645         if (hdw->hdw_desc->signal_routing_scheme ==
1646             PVR2_ROUTING_SCHEME_GOTVIEW) {
1647                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1648                    hardware. */
1649                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1650         }
1651         return ret;
1652 }
1653
1654
1655 static const char *pvr2_get_state_name(unsigned int st)
1656 {
1657         if (st < ARRAY_SIZE(pvr2_state_names)) {
1658                 return pvr2_state_names[st];
1659         }
1660         return "???";
1661 }
1662
1663 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1664 {
1665         /* Even though we really only care about the video decoder chip at
1666            this point, we'll broadcast stream on/off to all sub-devices
1667            anyway, just in case somebody else wants to hear the
1668            command... */
1669         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1670                    (enablefl ? "on" : "off"));
1671         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1672         v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1673         if (hdw->decoder_client_id) {
1674                 /* We get here if the encoder has been noticed.  Otherwise
1675                    we'll issue a warning to the user (which should
1676                    normally never happen). */
1677                 return 0;
1678         }
1679         if (!hdw->flag_decoder_missed) {
1680                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1681                            "WARNING: No decoder present");
1682                 hdw->flag_decoder_missed = !0;
1683                 trace_stbit("flag_decoder_missed",
1684                             hdw->flag_decoder_missed);
1685         }
1686         return -EIO;
1687 }
1688
1689
1690 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1691 {
1692         return hdw->master_state;
1693 }
1694
1695
1696 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1697 {
1698         if (!hdw->flag_tripped) return 0;
1699         hdw->flag_tripped = 0;
1700         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1701                    "Clearing driver error statuss");
1702         return !0;
1703 }
1704
1705
1706 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1707 {
1708         int fl;
1709         LOCK_TAKE(hdw->big_lock); do {
1710                 fl = pvr2_hdw_untrip_unlocked(hdw);
1711         } while (0); LOCK_GIVE(hdw->big_lock);
1712         if (fl) pvr2_hdw_state_sched(hdw);
1713         return 0;
1714 }
1715
1716
1717
1718
1719 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1720 {
1721         return hdw->state_pipeline_req != 0;
1722 }
1723
1724
1725 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1726 {
1727         int ret,st;
1728         LOCK_TAKE(hdw->big_lock); do {
1729                 pvr2_hdw_untrip_unlocked(hdw);
1730                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1731                         hdw->state_pipeline_req = enable_flag != 0;
1732                         pvr2_trace(PVR2_TRACE_START_STOP,
1733                                    "/*--TRACE_STREAM--*/ %s",
1734                                    enable_flag ? "enable" : "disable");
1735                 }
1736                 pvr2_hdw_state_sched(hdw);
1737         } while (0); LOCK_GIVE(hdw->big_lock);
1738         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1739         if (enable_flag) {
1740                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1741                         if (st != PVR2_STATE_READY) return -EIO;
1742                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1743                 }
1744         }
1745         return 0;
1746 }
1747
1748
1749 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1750 {
1751         int fl;
1752         LOCK_TAKE(hdw->big_lock);
1753         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1754                 hdw->desired_stream_type = config;
1755                 hdw->state_pipeline_config = 0;
1756                 trace_stbit("state_pipeline_config",
1757                             hdw->state_pipeline_config);
1758                 pvr2_hdw_state_sched(hdw);
1759         }
1760         LOCK_GIVE(hdw->big_lock);
1761         if (fl) return 0;
1762         return pvr2_hdw_wait(hdw,0);
1763 }
1764
1765
1766 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1767 {
1768         int unit_number = hdw->unit_number;
1769         int tp = -1;
1770         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1771                 tp = tuner[unit_number];
1772         }
1773         if (tp < 0) return -EINVAL;
1774         hdw->tuner_type = tp;
1775         hdw->tuner_updated = !0;
1776         return 0;
1777 }
1778
1779
1780 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1781 {
1782         int unit_number = hdw->unit_number;
1783         int tp = 0;
1784         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1785                 tp = video_std[unit_number];
1786                 if (tp) return tp;
1787         }
1788         return 0;
1789 }
1790
1791
1792 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1793 {
1794         int unit_number = hdw->unit_number;
1795         int tp = 0;
1796         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1797                 tp = tolerance[unit_number];
1798         }
1799         return tp;
1800 }
1801
1802
1803 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1804 {
1805         /* Try a harmless request to fetch the eeprom's address over
1806            endpoint 1.  See what happens.  Only the full FX2 image can
1807            respond to this.  If this probe fails then likely the FX2
1808            firmware needs be loaded. */
1809         int result;
1810         LOCK_TAKE(hdw->ctl_lock); do {
1811                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1812                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1813                                            hdw->cmd_buffer,1,
1814                                            hdw->cmd_buffer,1);
1815                 if (result < 0) break;
1816         } while(0); LOCK_GIVE(hdw->ctl_lock);
1817         if (result) {
1818                 pvr2_trace(PVR2_TRACE_INIT,
1819                            "Probe of device endpoint 1 result status %d",
1820                            result);
1821         } else {
1822                 pvr2_trace(PVR2_TRACE_INIT,
1823                            "Probe of device endpoint 1 succeeded");
1824         }
1825         return result == 0;
1826 }
1827
1828 struct pvr2_std_hack {
1829         v4l2_std_id pat;  /* Pattern to match */
1830         v4l2_std_id msk;  /* Which bits we care about */
1831         v4l2_std_id std;  /* What additional standards or default to set */
1832 };
1833
1834 /* This data structure labels specific combinations of standards from
1835    tveeprom that we'll try to recognize.  If we recognize one, then assume
1836    a specified default standard to use.  This is here because tveeprom only
1837    tells us about available standards not the intended default standard (if
1838    any) for the device in question.  We guess the default based on what has
1839    been reported as available.  Note that this is only for guessing a
1840    default - which can always be overridden explicitly - and if the user
1841    has otherwise named a default then that default will always be used in
1842    place of this table. */
1843 static const struct pvr2_std_hack std_eeprom_maps[] = {
1844         {       /* PAL(B/G) */
1845                 .pat = V4L2_STD_B|V4L2_STD_GH,
1846                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1847         },
1848         {       /* NTSC(M) */
1849                 .pat = V4L2_STD_MN,
1850                 .std = V4L2_STD_NTSC_M,
1851         },
1852         {       /* PAL(I) */
1853                 .pat = V4L2_STD_PAL_I,
1854                 .std = V4L2_STD_PAL_I,
1855         },
1856         {       /* SECAM(L/L') */
1857                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1858                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1859         },
1860         {       /* PAL(D/D1/K) */
1861                 .pat = V4L2_STD_DK,
1862                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1863         },
1864 };
1865
1866 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1867 {
1868         char buf[40];
1869         unsigned int bcnt;
1870         v4l2_std_id std1,std2,std3;
1871
1872         std1 = get_default_standard(hdw);
1873         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1874
1875         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1876         pvr2_trace(PVR2_TRACE_STD,
1877                    "Supported video standard(s) reported available in hardware: %.*s",
1878                    bcnt,buf);
1879
1880         hdw->std_mask_avail = hdw->std_mask_eeprom;
1881
1882         std2 = (std1|std3) & ~hdw->std_mask_avail;
1883         if (std2) {
1884                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1885                 pvr2_trace(PVR2_TRACE_STD,
1886                            "Expanding supported video standards to include: %.*s",
1887                            bcnt,buf);
1888                 hdw->std_mask_avail |= std2;
1889         }
1890
1891         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1892
1893         if (std1) {
1894                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1895                 pvr2_trace(PVR2_TRACE_STD,
1896                            "Initial video standard forced to %.*s",
1897                            bcnt,buf);
1898                 hdw->std_mask_cur = std1;
1899                 hdw->std_dirty = !0;
1900                 return;
1901         }
1902         if (std3) {
1903                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1904                 pvr2_trace(PVR2_TRACE_STD,
1905                            "Initial video standard (determined by device type): %.*s",
1906                            bcnt, buf);
1907                 hdw->std_mask_cur = std3;
1908                 hdw->std_dirty = !0;
1909                 return;
1910         }
1911
1912         {
1913                 unsigned int idx;
1914                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1915                         if (std_eeprom_maps[idx].msk ?
1916                             ((std_eeprom_maps[idx].pat ^
1917                              hdw->std_mask_eeprom) &
1918                              std_eeprom_maps[idx].msk) :
1919                             (std_eeprom_maps[idx].pat !=
1920                              hdw->std_mask_eeprom)) continue;
1921                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1922                                                   std_eeprom_maps[idx].std);
1923                         pvr2_trace(PVR2_TRACE_STD,
1924                                    "Initial video standard guessed as %.*s",
1925                                    bcnt,buf);
1926                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1927                         hdw->std_dirty = !0;
1928                         return;
1929                 }
1930         }
1931
1932 }
1933
1934
1935 static unsigned int pvr2_copy_i2c_addr_list(
1936         unsigned short *dst, const unsigned char *src,
1937         unsigned int dst_max)
1938 {
1939         unsigned int cnt = 0;
1940         if (!src) return 0;
1941         while (src[cnt] && (cnt + 1) < dst_max) {
1942                 dst[cnt] = src[cnt];
1943                 cnt++;
1944         }
1945         dst[cnt] = I2C_CLIENT_END;
1946         return cnt;
1947 }
1948
1949
1950 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1951 {
1952         /*
1953           Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1954           for cx25840 causes that module to correctly set up its video
1955           scaling.  This is really a problem in the cx25840 module itself,
1956           but we work around it here.  The problem has not been seen in
1957           ivtv because there VBI is supported and set up.  We don't do VBI
1958           here (at least not yet) and thus we never attempted to even set
1959           it up.
1960         */
1961         struct v4l2_format fmt;
1962         if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1963                 /* We're not using a cx25840 so don't enable the hack */
1964                 return;
1965         }
1966
1967         pvr2_trace(PVR2_TRACE_INIT,
1968                    "Module ID %u: Executing cx25840 VBI hack",
1969                    hdw->decoder_client_id);
1970         memset(&fmt, 0, sizeof(fmt));
1971         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1972         fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1973         fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1974         v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1975                              vbi, s_sliced_fmt, &fmt.fmt.sliced);
1976 }
1977
1978
1979 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1980                                 const struct pvr2_device_client_desc *cd)
1981 {
1982         const char *fname;
1983         unsigned char mid;
1984         struct v4l2_subdev *sd;
1985         unsigned int i2ccnt;
1986         const unsigned char *p;
1987         /* Arbitrary count - max # i2c addresses we will probe */
1988         unsigned short i2caddr[25];
1989
1990         mid = cd->module_id;
1991         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1992         if (!fname) {
1993                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1994                            "Module ID %u for device %s has no name?  The driver might have a configuration problem.",
1995                            mid,
1996                            hdw->hdw_desc->description);
1997                 return -EINVAL;
1998         }
1999         pvr2_trace(PVR2_TRACE_INIT,
2000                    "Module ID %u (%s) for device %s being loaded...",
2001                    mid, fname,
2002                    hdw->hdw_desc->description);
2003
2004         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2005                                          ARRAY_SIZE(i2caddr));
2006         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2007                          module_i2c_addresses[mid] : NULL) != NULL)) {
2008                 /* Second chance: Try default i2c address list */
2009                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2010                                                  ARRAY_SIZE(i2caddr));
2011                 if (i2ccnt) {
2012                         pvr2_trace(PVR2_TRACE_INIT,
2013                                    "Module ID %u: Using default i2c address list",
2014                                    mid);
2015                 }
2016         }
2017
2018         if (!i2ccnt) {
2019                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2020                            "Module ID %u (%s) for device %s: No i2c addresses.  The driver might have a configuration problem.",
2021                            mid, fname, hdw->hdw_desc->description);
2022                 return -EINVAL;
2023         }
2024
2025         if (i2ccnt == 1) {
2026                 pvr2_trace(PVR2_TRACE_INIT,
2027                            "Module ID %u: Setting up with specified i2c address 0x%x",
2028                            mid, i2caddr[0]);
2029                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2030                                          fname, i2caddr[0], NULL);
2031         } else {
2032                 pvr2_trace(PVR2_TRACE_INIT,
2033                            "Module ID %u: Setting up with address probe list",
2034                            mid);
2035                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2036                                          fname, 0, i2caddr);
2037         }
2038
2039         if (!sd) {
2040                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2041                            "Module ID %u (%s) for device %s failed to load.  Possible missing sub-device kernel module or initialization failure within module.",
2042                            mid, fname, hdw->hdw_desc->description);
2043                 return -EIO;
2044         }
2045
2046         /* Tag this sub-device instance with the module ID we know about.
2047            In other places we'll use that tag to determine if the instance
2048            requires special handling. */
2049         sd->grp_id = mid;
2050
2051         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2052
2053
2054         /* client-specific setup... */
2055         switch (mid) {
2056         case PVR2_CLIENT_ID_CX25840:
2057         case PVR2_CLIENT_ID_SAA7115:
2058                 hdw->decoder_client_id = mid;
2059                 break;
2060         default: break;
2061         }
2062
2063         return 0;
2064 }
2065
2066
2067 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2068 {
2069         unsigned int idx;
2070         const struct pvr2_string_table *cm;
2071         const struct pvr2_device_client_table *ct;
2072         int okFl = !0;
2073
2074         cm = &hdw->hdw_desc->client_modules;
2075         for (idx = 0; idx < cm->cnt; idx++) {
2076                 request_module(cm->lst[idx]);
2077         }
2078
2079         ct = &hdw->hdw_desc->client_table;
2080         for (idx = 0; idx < ct->cnt; idx++) {
2081                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2082         }
2083         if (!okFl) {
2084                 hdw->flag_modulefail = !0;
2085                 pvr2_hdw_render_useless(hdw);
2086         }
2087 }
2088
2089
2090 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2091 {
2092         int ret;
2093         unsigned int idx;
2094         struct pvr2_ctrl *cptr;
2095         int reloadFl = 0;
2096         if (hdw->hdw_desc->fx2_firmware.cnt) {
2097                 if (!reloadFl) {
2098                         reloadFl =
2099                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2100                                  == 0);
2101                         if (reloadFl) {
2102                                 pvr2_trace(PVR2_TRACE_INIT,
2103                                            "USB endpoint config looks strange; possibly firmware needs to be loaded");
2104                         }
2105                 }
2106                 if (!reloadFl) {
2107                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2108                         if (reloadFl) {
2109                                 pvr2_trace(PVR2_TRACE_INIT,
2110                                            "Check for FX2 firmware failed; possibly firmware needs to be loaded");
2111                         }
2112                 }
2113                 if (reloadFl) {
2114                         if (pvr2_upload_firmware1(hdw) != 0) {
2115                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2116                                            "Failure uploading firmware1");
2117                         }
2118                         return;
2119                 }
2120         }
2121         hdw->fw1_state = FW1_STATE_OK;
2122
2123         if (!pvr2_hdw_dev_ok(hdw)) return;
2124
2125         hdw->force_dirty = !0;
2126
2127         if (!hdw->hdw_desc->flag_no_powerup) {
2128                 pvr2_hdw_cmd_powerup(hdw);
2129                 if (!pvr2_hdw_dev_ok(hdw)) return;
2130         }
2131
2132         /* Take the IR chip out of reset, if appropriate */
2133         if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2134                 pvr2_issue_simple_cmd(hdw,
2135                                       FX2CMD_HCW_ZILOG_RESET |
2136                                       (1 << 8) |
2137                                       ((0) << 16));
2138         }
2139
2140         // This step MUST happen after the earlier powerup step.
2141         pvr2_i2c_core_init(hdw);
2142         if (!pvr2_hdw_dev_ok(hdw)) return;
2143
2144         pvr2_hdw_load_modules(hdw);
2145         if (!pvr2_hdw_dev_ok(hdw)) return;
2146
2147         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2148
2149         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2150                 cptr = hdw->controls + idx;
2151                 if (cptr->info->skip_init) continue;
2152                 if (!cptr->info->set_value) continue;
2153                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2154         }
2155
2156         pvr2_hdw_cx25840_vbi_hack(hdw);
2157
2158         /* Set up special default values for the television and radio
2159            frequencies here.  It's not really important what these defaults
2160            are, but I set them to something usable in the Chicago area just
2161            to make driver testing a little easier. */
2162
2163         hdw->freqValTelevision = default_tv_freq;
2164         hdw->freqValRadio = default_radio_freq;
2165
2166         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2167         // thread-safe against the normal pvr2_send_request() mechanism.
2168         // (We should make it thread safe).
2169
2170         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2171                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2172                 if (!pvr2_hdw_dev_ok(hdw)) return;
2173                 if (ret < 0) {
2174                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2175                                    "Unable to determine location of eeprom, skipping");
2176                 } else {
2177                         hdw->eeprom_addr = ret;
2178                         pvr2_eeprom_analyze(hdw);
2179                         if (!pvr2_hdw_dev_ok(hdw)) return;
2180                 }
2181         } else {
2182                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2183                 hdw->tuner_updated = !0;
2184                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2185         }
2186
2187         if (hdw->serial_number) {
2188                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2189                                 "sn-%lu", hdw->serial_number);
2190         } else if (hdw->unit_number >= 0) {
2191                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2192                                 "unit-%c",
2193                                 hdw->unit_number + 'a');
2194         } else {
2195                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2196                                 "unit-??");
2197         }
2198         hdw->identifier[idx] = 0;
2199
2200         pvr2_hdw_setup_std(hdw);
2201
2202         if (!get_default_tuner_type(hdw)) {
2203                 pvr2_trace(PVR2_TRACE_INIT,
2204                            "pvr2_hdw_setup: Tuner type overridden to %d",
2205                            hdw->tuner_type);
2206         }
2207
2208
2209         if (!pvr2_hdw_dev_ok(hdw)) return;
2210
2211         if (hdw->hdw_desc->signal_routing_scheme ==
2212             PVR2_ROUTING_SCHEME_GOTVIEW) {
2213                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2214                    hardware. */
2215                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2216         }
2217
2218         pvr2_hdw_commit_setup(hdw);
2219
2220         hdw->vid_stream = pvr2_stream_create();
2221         if (!pvr2_hdw_dev_ok(hdw)) return;
2222         pvr2_trace(PVR2_TRACE_INIT,
2223                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2224         if (hdw->vid_stream) {
2225                 idx = get_default_error_tolerance(hdw);
2226                 if (idx) {
2227                         pvr2_trace(PVR2_TRACE_INIT,
2228                                    "pvr2_hdw_setup: video stream %p setting tolerance %u",
2229                                    hdw->vid_stream,idx);
2230                 }
2231                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2232                                   PVR2_VID_ENDPOINT,idx);
2233         }
2234
2235         if (!pvr2_hdw_dev_ok(hdw)) return;
2236
2237         hdw->flag_init_ok = !0;
2238
2239         pvr2_hdw_state_sched(hdw);
2240 }
2241
2242
2243 /* Set up the structure and attempt to put the device into a usable state.
2244    This can be a time-consuming operation, which is why it is not done
2245    internally as part of the create() step. */
2246 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2247 {
2248         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2249         do {
2250                 pvr2_hdw_setup_low(hdw);
2251                 pvr2_trace(PVR2_TRACE_INIT,
2252                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2253                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2254                 if (pvr2_hdw_dev_ok(hdw)) {
2255                         if (hdw->flag_init_ok) {
2256                                 pvr2_trace(
2257                                         PVR2_TRACE_INFO,
2258                                         "Device initialization completed successfully.");
2259                                 break;
2260                         }
2261                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2262                                 pvr2_trace(
2263                                         PVR2_TRACE_INFO,
2264                                         "Device microcontroller firmware (re)loaded; it should now reset and reconnect.");
2265                                 break;
2266                         }
2267                         pvr2_trace(
2268                                 PVR2_TRACE_ERROR_LEGS,
2269                                 "Device initialization was not successful.");
2270                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2271                                 pvr2_trace(
2272                                         PVR2_TRACE_ERROR_LEGS,
2273                                         "Giving up since device microcontroller firmware appears to be missing.");
2274                                 break;
2275                         }
2276                 }
2277                 if (hdw->flag_modulefail) {
2278                         pvr2_trace(
2279                                 PVR2_TRACE_ERROR_LEGS,
2280                                 "***WARNING*** pvrusb2 driver initialization failed due to the failure of one or more sub-device kernel modules.");
2281                         pvr2_trace(
2282                                 PVR2_TRACE_ERROR_LEGS,
2283                                 "You need to resolve the failing condition before this driver can function.  There should be some earlier messages giving more information about the problem.");
2284                         break;
2285                 }
2286                 if (procreload) {
2287                         pvr2_trace(
2288                                 PVR2_TRACE_ERROR_LEGS,
2289                                 "Attempting pvrusb2 recovery by reloading primary firmware.");
2290                         pvr2_trace(
2291                                 PVR2_TRACE_ERROR_LEGS,
2292                                 "If this works, device should disconnect and reconnect in a sane state.");
2293                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2294                         pvr2_upload_firmware1(hdw);
2295                 } else {
2296                         pvr2_trace(
2297                                 PVR2_TRACE_ERROR_LEGS,
2298                                 "***WARNING*** pvrusb2 device hardware appears to be jammed and I can't clear it.");
2299                         pvr2_trace(
2300                                 PVR2_TRACE_ERROR_LEGS,
2301                                 "You might need to power cycle the pvrusb2 device in order to recover.");
2302                 }
2303         } while (0);
2304         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2305 }
2306
2307
2308 /* Perform second stage initialization.  Set callback pointer first so that
2309    we can avoid a possible initialization race (if the kernel thread runs
2310    before the callback has been set). */
2311 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2312                         void (*callback_func)(void *),
2313                         void *callback_data)
2314 {
2315         LOCK_TAKE(hdw->big_lock); do {
2316                 if (hdw->flag_disconnected) {
2317                         /* Handle a race here: If we're already
2318                            disconnected by this point, then give up.  If we
2319                            get past this then we'll remain connected for
2320                            the duration of initialization since the entire
2321                            initialization sequence is now protected by the
2322                            big_lock. */
2323                         break;
2324                 }
2325                 hdw->state_data = callback_data;
2326                 hdw->state_func = callback_func;
2327                 pvr2_hdw_setup(hdw);
2328         } while (0); LOCK_GIVE(hdw->big_lock);
2329         return hdw->flag_init_ok;
2330 }
2331
2332
2333 /* Create, set up, and return a structure for interacting with the
2334    underlying hardware.  */
2335 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2336                                  const struct usb_device_id *devid)
2337 {
2338         unsigned int idx,cnt1,cnt2,m;
2339         struct pvr2_hdw *hdw = NULL;
2340         int valid_std_mask;
2341         struct pvr2_ctrl *cptr;
2342         struct usb_device *usb_dev;
2343         const struct pvr2_device_desc *hdw_desc;
2344         __u8 ifnum;
2345         struct v4l2_queryctrl qctrl;
2346         struct pvr2_ctl_info *ciptr;
2347
2348         usb_dev = interface_to_usbdev(intf);
2349
2350         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2351
2352         if (hdw_desc == NULL) {
2353                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create: No device description pointer, unable to continue.");
2354                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type, please contact Mike Isely <isely@pobox.com> to get it included in the driver\n");
2355                 goto fail;
2356         }
2357
2358         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2359         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2360                    hdw,hdw_desc->description);
2361         pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2362                 hdw_desc->description);
2363         if (hdw_desc->flag_is_experimental) {
2364                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2365                 pvr2_trace(PVR2_TRACE_INFO,
2366                            "WARNING: Support for this device (%s) is experimental.",
2367                                                               hdw_desc->description);
2368                 pvr2_trace(PVR2_TRACE_INFO,
2369                            "Important functionality might not be entirely working.");
2370                 pvr2_trace(PVR2_TRACE_INFO,
2371                            "Please consider contacting the driver author to help with further stabilization of the driver.");
2372                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2373         }
2374         if (!hdw) goto fail;
2375
2376         setup_timer(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout,
2377                     (unsigned long)hdw);
2378
2379         setup_timer(&hdw->decoder_stabilization_timer,
2380                     pvr2_hdw_decoder_stabilization_timeout,
2381                     (unsigned long)hdw);
2382
2383         setup_timer(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2384                     (unsigned long)hdw);
2385
2386         setup_timer(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout,
2387                     (unsigned long)hdw);
2388
2389         hdw->master_state = PVR2_STATE_DEAD;
2390
2391         init_waitqueue_head(&hdw->state_wait_data);
2392
2393         hdw->tuner_signal_stale = !0;
2394         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2395
2396         /* Calculate which inputs are OK */
2397         m = 0;
2398         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2399         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2400                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2401         }
2402         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2403         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2404         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2405         hdw->input_avail_mask = m;
2406         hdw->input_allowed_mask = hdw->input_avail_mask;
2407
2408         /* If not a hybrid device, pathway_state never changes.  So
2409            initialize it here to what it should forever be. */
2410         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2411                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2412         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2413                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2414         }
2415
2416         hdw->control_cnt = CTRLDEF_COUNT;
2417         hdw->control_cnt += MPEGDEF_COUNT;
2418         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2419                                 GFP_KERNEL);
2420         if (!hdw->controls) goto fail;
2421         hdw->hdw_desc = hdw_desc;
2422         hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2423         for (idx = 0; idx < hdw->control_cnt; idx++) {
2424                 cptr = hdw->controls + idx;
2425                 cptr->hdw = hdw;
2426         }
2427         for (idx = 0; idx < 32; idx++) {
2428                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2429         }
2430         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2431                 cptr = hdw->controls + idx;
2432                 cptr->info = control_defs+idx;
2433         }
2434
2435         /* Ensure that default input choice is a valid one. */
2436         m = hdw->input_avail_mask;
2437         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2438                 if (!((1 << idx) & m)) continue;
2439                 hdw->input_val = idx;
2440                 break;
2441         }
2442
2443         /* Define and configure additional controls from cx2341x module. */
2444         hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2445                                       sizeof(*(hdw->mpeg_ctrl_info)),
2446                                       GFP_KERNEL);
2447         if (!hdw->mpeg_ctrl_info) goto fail;
2448         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2449                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2450                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2451                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2452                 ciptr->name = mpeg_ids[idx].strid;
2453                 ciptr->v4l_id = mpeg_ids[idx].id;
2454                 ciptr->skip_init = !0;
2455                 ciptr->get_value = ctrl_cx2341x_get;
2456                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2457                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2458                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2459                 qctrl.id = ciptr->v4l_id;
2460                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2461                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2462                         ciptr->set_value = ctrl_cx2341x_set;
2463                 }
2464                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2465                         PVR2_CTLD_INFO_DESC_SIZE);
2466                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2467                 ciptr->default_value = qctrl.default_value;
2468                 switch (qctrl.type) {
2469                 default:
2470                 case V4L2_CTRL_TYPE_INTEGER:
2471                         ciptr->type = pvr2_ctl_int;
2472                         ciptr->def.type_int.min_value = qctrl.minimum;
2473                         ciptr->def.type_int.max_value = qctrl.maximum;
2474                         break;
2475                 case V4L2_CTRL_TYPE_BOOLEAN:
2476                         ciptr->type = pvr2_ctl_bool;
2477                         break;
2478                 case V4L2_CTRL_TYPE_MENU:
2479                         ciptr->type = pvr2_ctl_enum;
2480                         ciptr->def.type_enum.value_names =
2481                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2482                                                                 ciptr->v4l_id);
2483                         for (cnt1 = 0;
2484                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2485                              cnt1++) { }
2486                         ciptr->def.type_enum.count = cnt1;
2487                         break;
2488                 }
2489                 cptr->info = ciptr;
2490         }
2491
2492         // Initialize control data regarding video standard masks
2493         valid_std_mask = pvr2_std_get_usable();
2494         for (idx = 0; idx < 32; idx++) {
2495                 if (!(valid_std_mask & (1 << idx))) continue;
2496                 cnt1 = pvr2_std_id_to_str(
2497                         hdw->std_mask_names[idx],
2498                         sizeof(hdw->std_mask_names[idx])-1,
2499                         1 << idx);
2500                 hdw->std_mask_names[idx][cnt1] = 0;
2501         }
2502         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2503         if (cptr) {
2504                 memcpy(&hdw->std_info_avail,cptr->info,
2505                        sizeof(hdw->std_info_avail));
2506                 cptr->info = &hdw->std_info_avail;
2507                 hdw->std_info_avail.def.type_bitmask.bit_names =
2508                         hdw->std_mask_ptrs;
2509                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2510                         valid_std_mask;
2511         }
2512         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2513         if (cptr) {
2514                 memcpy(&hdw->std_info_cur,cptr->info,
2515                        sizeof(hdw->std_info_cur));
2516                 cptr->info = &hdw->std_info_cur;
2517                 hdw->std_info_cur.def.type_bitmask.bit_names =
2518                         hdw->std_mask_ptrs;
2519                 hdw->std_info_cur.def.type_bitmask.valid_bits =
2520                         valid_std_mask;
2521         }
2522         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2523         if (cptr) {
2524                 memcpy(&hdw->std_info_detect,cptr->info,
2525                        sizeof(hdw->std_info_detect));
2526                 cptr->info = &hdw->std_info_detect;
2527                 hdw->std_info_detect.def.type_bitmask.bit_names =
2528                         hdw->std_mask_ptrs;
2529                 hdw->std_info_detect.def.type_bitmask.valid_bits =
2530                         valid_std_mask;
2531         }
2532
2533         hdw->cropcap_stale = !0;
2534         hdw->eeprom_addr = -1;
2535         hdw->unit_number = -1;
2536         hdw->v4l_minor_number_video = -1;
2537         hdw->v4l_minor_number_vbi = -1;
2538         hdw->v4l_minor_number_radio = -1;
2539         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2540         if (!hdw->ctl_write_buffer) goto fail;
2541         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2542         if (!hdw->ctl_read_buffer) goto fail;
2543         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2544         if (!hdw->ctl_write_urb) goto fail;
2545         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2546         if (!hdw->ctl_read_urb) goto fail;
2547
2548         if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2549                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2550                            "Error registering with v4l core, giving up");
2551                 goto fail;
2552         }
2553         mutex_lock(&pvr2_unit_mtx);
2554         do {
2555                 for (idx = 0; idx < PVR_NUM; idx++) {
2556                         if (unit_pointers[idx]) continue;
2557                         hdw->unit_number = idx;
2558                         unit_pointers[idx] = hdw;
2559                         break;
2560                 }
2561         } while (0);
2562         mutex_unlock(&pvr2_unit_mtx);
2563
2564         cnt1 = 0;
2565         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2566         cnt1 += cnt2;
2567         if (hdw->unit_number >= 0) {
2568                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2569                                  ('a' + hdw->unit_number));
2570                 cnt1 += cnt2;
2571         }
2572         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2573         hdw->name[cnt1] = 0;
2574
2575         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2576
2577         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2578                    hdw->unit_number,hdw->name);
2579
2580         hdw->tuner_type = -1;
2581         hdw->flag_ok = !0;
2582
2583         hdw->usb_intf = intf;
2584         hdw->usb_dev = usb_dev;
2585
2586         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2587
2588         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2589         usb_set_interface(hdw->usb_dev,ifnum,0);
2590
2591         mutex_init(&hdw->ctl_lock_mutex);
2592         mutex_init(&hdw->big_lock_mutex);
2593
2594         return hdw;
2595  fail:
2596         if (hdw) {
2597                 del_timer_sync(&hdw->quiescent_timer);
2598                 del_timer_sync(&hdw->decoder_stabilization_timer);
2599                 del_timer_sync(&hdw->encoder_run_timer);
2600                 del_timer_sync(&hdw->encoder_wait_timer);
2601                 flush_work(&hdw->workpoll);
2602                 usb_free_urb(hdw->ctl_read_urb);
2603                 usb_free_urb(hdw->ctl_write_urb);
2604                 kfree(hdw->ctl_read_buffer);
2605                 kfree(hdw->ctl_write_buffer);
2606                 kfree(hdw->controls);
2607                 kfree(hdw->mpeg_ctrl_info);
2608                 kfree(hdw);
2609         }
2610         return NULL;
2611 }
2612
2613
2614 /* Remove _all_ associations between this driver and the underlying USB
2615    layer. */
2616 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2617 {
2618         if (hdw->flag_disconnected) return;
2619         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2620         if (hdw->ctl_read_urb) {
2621                 usb_kill_urb(hdw->ctl_read_urb);
2622                 usb_free_urb(hdw->ctl_read_urb);
2623                 hdw->ctl_read_urb = NULL;
2624         }
2625         if (hdw->ctl_write_urb) {
2626                 usb_kill_urb(hdw->ctl_write_urb);
2627                 usb_free_urb(hdw->ctl_write_urb);
2628                 hdw->ctl_write_urb = NULL;
2629         }
2630         if (hdw->ctl_read_buffer) {
2631                 kfree(hdw->ctl_read_buffer);
2632                 hdw->ctl_read_buffer = NULL;
2633         }
2634         if (hdw->ctl_write_buffer) {
2635                 kfree(hdw->ctl_write_buffer);
2636                 hdw->ctl_write_buffer = NULL;
2637         }
2638         hdw->flag_disconnected = !0;
2639         /* If we don't do this, then there will be a dangling struct device
2640            reference to our disappearing device persisting inside the V4L
2641            core... */
2642         v4l2_device_disconnect(&hdw->v4l2_dev);
2643         hdw->usb_dev = NULL;
2644         hdw->usb_intf = NULL;
2645         pvr2_hdw_render_useless(hdw);
2646 }
2647
2648 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2649 {
2650         vdev->v4l2_dev = &hdw->v4l2_dev;
2651 }
2652
2653 /* Destroy hardware interaction structure */
2654 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2655 {
2656         if (!hdw) return;
2657         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2658         flush_work(&hdw->workpoll);
2659         del_timer_sync(&hdw->quiescent_timer);
2660         del_timer_sync(&hdw->decoder_stabilization_timer);
2661         del_timer_sync(&hdw->encoder_run_timer);
2662         del_timer_sync(&hdw->encoder_wait_timer);
2663         if (hdw->fw_buffer) {
2664                 kfree(hdw->fw_buffer);
2665                 hdw->fw_buffer = NULL;
2666         }
2667         if (hdw->vid_stream) {
2668                 pvr2_stream_destroy(hdw->vid_stream);
2669                 hdw->vid_stream = NULL;
2670         }
2671         pvr2_i2c_core_done(hdw);
2672         v4l2_device_unregister(&hdw->v4l2_dev);
2673         pvr2_hdw_remove_usb_stuff(hdw);
2674         mutex_lock(&pvr2_unit_mtx);
2675         do {
2676                 if ((hdw->unit_number >= 0) &&
2677                     (hdw->unit_number < PVR_NUM) &&
2678                     (unit_pointers[hdw->unit_number] == hdw)) {
2679                         unit_pointers[hdw->unit_number] = NULL;
2680                 }
2681         } while (0);
2682         mutex_unlock(&pvr2_unit_mtx);
2683         kfree(hdw->controls);
2684         kfree(hdw->mpeg_ctrl_info);
2685         kfree(hdw);
2686 }
2687
2688
2689 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2690 {
2691         return (hdw && hdw->flag_ok);
2692 }
2693
2694
2695 /* Called when hardware has been unplugged */
2696 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2697 {
2698         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2699         LOCK_TAKE(hdw->big_lock);
2700         LOCK_TAKE(hdw->ctl_lock);
2701         pvr2_hdw_remove_usb_stuff(hdw);
2702         LOCK_GIVE(hdw->ctl_lock);
2703         LOCK_GIVE(hdw->big_lock);
2704 }
2705
2706
2707 /* Get the number of defined controls */
2708 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2709 {
2710         return hdw->control_cnt;
2711 }
2712
2713
2714 /* Retrieve a control handle given its index (0..count-1) */
2715 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2716                                              unsigned int idx)
2717 {
2718         if (idx >= hdw->control_cnt) return NULL;
2719         return hdw->controls + idx;
2720 }
2721
2722
2723 /* Retrieve a control handle given its index (0..count-1) */
2724 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2725                                           unsigned int ctl_id)
2726 {
2727         struct pvr2_ctrl *cptr;
2728         unsigned int idx;
2729         int i;
2730
2731         /* This could be made a lot more efficient, but for now... */
2732         for (idx = 0; idx < hdw->control_cnt; idx++) {
2733                 cptr = hdw->controls + idx;
2734                 i = cptr->info->internal_id;
2735                 if (i && (i == ctl_id)) return cptr;
2736         }
2737         return NULL;
2738 }
2739
2740
2741 /* Given a V4L ID, retrieve the control structure associated with it. */
2742 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2743 {
2744         struct pvr2_ctrl *cptr;
2745         unsigned int idx;
2746         int i;
2747
2748         /* This could be made a lot more efficient, but for now... */
2749         for (idx = 0; idx < hdw->control_cnt; idx++) {
2750                 cptr = hdw->controls + idx;
2751                 i = cptr->info->v4l_id;
2752                 if (i && (i == ctl_id)) return cptr;
2753         }
2754         return NULL;
2755 }
2756
2757
2758 /* Given a V4L ID for its immediate predecessor, retrieve the control
2759    structure associated with it. */
2760 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2761                                             unsigned int ctl_id)
2762 {
2763         struct pvr2_ctrl *cptr,*cp2;
2764         unsigned int idx;
2765         int i;
2766
2767         /* This could be made a lot more efficient, but for now... */
2768         cp2 = NULL;
2769         for (idx = 0; idx < hdw->control_cnt; idx++) {
2770                 cptr = hdw->controls + idx;
2771                 i = cptr->info->v4l_id;
2772                 if (!i) continue;
2773                 if (i <= ctl_id) continue;
2774                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2775                 cp2 = cptr;
2776         }
2777         return cp2;
2778         return NULL;
2779 }
2780
2781
2782 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2783 {
2784         switch (tp) {
2785         case pvr2_ctl_int: return "integer";
2786         case pvr2_ctl_enum: return "enum";
2787         case pvr2_ctl_bool: return "boolean";
2788         case pvr2_ctl_bitmask: return "bitmask";
2789         }
2790         return "";
2791 }
2792
2793
2794 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2795                                     const char *name, int val)
2796 {
2797         struct v4l2_control ctrl;
2798         struct v4l2_subdev *sd;
2799
2800         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2801         memset(&ctrl, 0, sizeof(ctrl));
2802         ctrl.id = id;
2803         ctrl.value = val;
2804
2805         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2806                 v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl);
2807 }
2808
2809 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2810         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2811                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2812         }
2813
2814 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2815 {
2816         v4l2_std_id std;
2817         std = (v4l2_std_id)hdw->std_mask_avail;
2818         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2819                              video, querystd, &std);
2820         return std;
2821 }
2822
2823 /* Execute whatever commands are required to update the state of all the
2824    sub-devices so that they match our current control values. */
2825 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2826 {
2827         struct v4l2_subdev *sd;
2828         unsigned int id;
2829         pvr2_subdev_update_func fp;
2830
2831         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2832
2833         if (hdw->tuner_updated || hdw->force_dirty) {
2834                 struct tuner_setup setup;
2835                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2836                            hdw->tuner_type);
2837                 if (((int)(hdw->tuner_type)) >= 0) {
2838                         memset(&setup, 0, sizeof(setup));
2839                         setup.addr = ADDR_UNSET;
2840                         setup.type = hdw->tuner_type;
2841                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
2842                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2843                                              tuner, s_type_addr, &setup);
2844                 }
2845         }
2846
2847         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2848                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2849                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2850                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2851                                              tuner, s_radio);
2852                 } else {
2853                         v4l2_std_id vs;
2854                         vs = hdw->std_mask_cur;
2855                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2856                                              video, s_std, vs);
2857                         pvr2_hdw_cx25840_vbi_hack(hdw);
2858                 }
2859                 hdw->tuner_signal_stale = !0;
2860                 hdw->cropcap_stale = !0;
2861         }
2862
2863         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2864         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2865         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2866         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2867         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2868         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2869         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2870         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2871         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2872
2873         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2874                 struct v4l2_tuner vt;
2875                 memset(&vt, 0, sizeof(vt));
2876                 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2877                         V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2878                 vt.audmode = hdw->audiomode_val;
2879                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2880         }
2881
2882         if (hdw->freqDirty || hdw->force_dirty) {
2883                 unsigned long fv;
2884                 struct v4l2_frequency freq;
2885                 fv = pvr2_hdw_get_cur_freq(hdw);
2886                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2887                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2888                 memset(&freq, 0, sizeof(freq));
2889                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2890                         /* ((fv * 1000) / 62500) */
2891                         freq.frequency = (fv * 2) / 125;
2892                 } else {
2893                         freq.frequency = fv / 62500;
2894                 }
2895                 /* tuner-core currently doesn't seem to care about this, but
2896                    let's set it anyway for completeness. */
2897                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2898                         freq.type = V4L2_TUNER_RADIO;
2899                 } else {
2900                         freq.type = V4L2_TUNER_ANALOG_TV;
2901                 }
2902                 freq.tuner = 0;
2903                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2904                                      s_frequency, &freq);
2905         }
2906
2907         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2908                 struct v4l2_subdev_format format = {
2909                         .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2910                 };
2911
2912                 format.format.width = hdw->res_hor_val;
2913                 format.format.height = hdw->res_ver_val;
2914                 format.format.code = MEDIA_BUS_FMT_FIXED;
2915                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2916                            format.format.width, format.format.height);
2917                 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2918                                      NULL, &format);
2919         }
2920
2921         if (hdw->srate_dirty || hdw->force_dirty) {
2922                 u32 val;
2923                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2924                            hdw->srate_val);
2925                 switch (hdw->srate_val) {
2926                 default:
2927                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2928                         val = 48000;
2929                         break;
2930                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2931                         val = 44100;
2932                         break;
2933                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2934                         val = 32000;
2935                         break;
2936                 }
2937                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2938                                      audio, s_clock_freq, val);
2939         }
2940
2941         /* Unable to set crop parameters; there is apparently no equivalent
2942            for VIDIOC_S_CROP */
2943
2944         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2945                 id = sd->grp_id;
2946                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
2947                 fp = pvr2_module_update_functions[id];
2948                 if (!fp) continue;
2949                 (*fp)(hdw, sd);
2950         }
2951
2952         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2953                 pvr2_hdw_status_poll(hdw);
2954         }
2955 }
2956
2957
2958 /* Figure out if we need to commit control changes.  If so, mark internal
2959    state flags to indicate this fact and return true.  Otherwise do nothing
2960    else and return false. */
2961 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2962 {
2963         unsigned int idx;
2964         struct pvr2_ctrl *cptr;
2965         int value;
2966         int commit_flag = hdw->force_dirty;
2967         char buf[100];
2968         unsigned int bcnt,ccnt;
2969
2970         for (idx = 0; idx < hdw->control_cnt; idx++) {
2971                 cptr = hdw->controls + idx;
2972                 if (!cptr->info->is_dirty) continue;
2973                 if (!cptr->info->is_dirty(cptr)) continue;
2974                 commit_flag = !0;
2975
2976                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2977                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2978                                  cptr->info->name);
2979                 value = 0;
2980                 cptr->info->get_value(cptr,&value);
2981                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2982                                                 buf+bcnt,
2983                                                 sizeof(buf)-bcnt,&ccnt);
2984                 bcnt += ccnt;
2985                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2986                                   get_ctrl_typename(cptr->info->type));
2987                 pvr2_trace(PVR2_TRACE_CTL,
2988                            "/*--TRACE_COMMIT--*/ %.*s",
2989                            bcnt,buf);
2990         }
2991
2992         if (!commit_flag) {
2993                 /* Nothing has changed */
2994                 return 0;
2995         }
2996
2997         hdw->state_pipeline_config = 0;
2998         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2999         pvr2_hdw_state_sched(hdw);
3000
3001         return !0;
3002 }
3003
3004
3005 /* Perform all operations needed to commit all control changes.  This must
3006    be performed in synchronization with the pipeline state and is thus
3007    expected to be called as part of the driver's worker thread.  Return
3008    true if commit successful, otherwise return false to indicate that
3009    commit isn't possible at this time. */
3010 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3011 {
3012         unsigned int idx;
3013         struct pvr2_ctrl *cptr;
3014         int disruptive_change;
3015
3016         if (hdw->input_dirty && hdw->state_pathway_ok &&
3017             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3018               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3019              hdw->pathway_state)) {
3020                 /* Change of mode being asked for... */
3021                 hdw->state_pathway_ok = 0;
3022                 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3023         }
3024         if (!hdw->state_pathway_ok) {
3025                 /* Can't commit anything until pathway is ok. */
3026                 return 0;
3027         }
3028
3029         /* Handle some required side effects when the video standard is
3030            changed.... */
3031         if (hdw->std_dirty) {
3032                 int nvres;
3033                 int gop_size;
3034                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3035                         nvres = 480;
3036                         gop_size = 15;
3037                 } else {
3038                         nvres = 576;
3039                         gop_size = 12;
3040                 }
3041                 /* Rewrite the vertical resolution to be appropriate to the
3042                    video standard that has been selected. */
3043                 if (nvres != hdw->res_ver_val) {
3044                         hdw->res_ver_val = nvres;
3045                         hdw->res_ver_dirty = !0;
3046                 }
3047                 /* Rewrite the GOP size to be appropriate to the video
3048                    standard that has been selected. */
3049                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3050                         struct v4l2_ext_controls cs;
3051                         struct v4l2_ext_control c1;
3052                         memset(&cs, 0, sizeof(cs));
3053                         memset(&c1, 0, sizeof(c1));
3054                         cs.controls = &c1;
3055                         cs.count = 1;
3056                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3057                         c1.value = gop_size;
3058                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3059                                           VIDIOC_S_EXT_CTRLS);
3060                 }
3061         }
3062
3063         /* The broadcast decoder can only scale down, so if
3064          * res_*_dirty && crop window < output format ==> enlarge crop.
3065          *
3066          * The mpeg encoder receives fields of res_hor_val dots and
3067          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3068          */
3069         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3070                 hdw->cropw_val = hdw->res_hor_val;
3071                 hdw->cropw_dirty = !0;
3072         } else if (hdw->cropw_dirty) {
3073                 hdw->res_hor_dirty = !0;           /* must rescale */
3074                 hdw->res_hor_val = min(720, hdw->cropw_val);
3075         }
3076         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3077                 hdw->croph_val = hdw->res_ver_val;
3078                 hdw->croph_dirty = !0;
3079         } else if (hdw->croph_dirty) {
3080                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3081                 hdw->res_ver_dirty = !0;
3082                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3083         }
3084
3085         /* If any of the below has changed, then we can't do the update
3086            while the pipeline is running.  Pipeline must be paused first
3087            and decoder -> encoder connection be made quiescent before we
3088            can proceed. */
3089         disruptive_change =
3090                 (hdw->std_dirty ||
3091                  hdw->enc_unsafe_stale ||
3092                  hdw->srate_dirty ||
3093                  hdw->res_ver_dirty ||
3094                  hdw->res_hor_dirty ||
3095                  hdw->cropw_dirty ||
3096                  hdw->croph_dirty ||
3097                  hdw->input_dirty ||
3098                  (hdw->active_stream_type != hdw->desired_stream_type));
3099         if (disruptive_change && !hdw->state_pipeline_idle) {
3100                 /* Pipeline is not idle; we can't proceed.  Arrange to
3101                    cause pipeline to stop so that we can try this again
3102                    later.... */
3103                 hdw->state_pipeline_pause = !0;
3104                 return 0;
3105         }
3106
3107         if (hdw->srate_dirty) {
3108                 /* Write new sample rate into control structure since
3109                  * the master copy is stale.  We must track srate
3110                  * separate from the mpeg control structure because
3111                  * other logic also uses this value. */
3112                 struct v4l2_ext_controls cs;
3113                 struct v4l2_ext_control c1;
3114                 memset(&cs,0,sizeof(cs));
3115                 memset(&c1,0,sizeof(c1));
3116                 cs.controls = &c1;
3117                 cs.count = 1;
3118                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3119                 c1.value = hdw->srate_val;
3120                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3121         }
3122
3123         if (hdw->active_stream_type != hdw->desired_stream_type) {
3124                 /* Handle any side effects of stream config here */
3125                 hdw->active_stream_type = hdw->desired_stream_type;
3126         }
3127
3128         if (hdw->hdw_desc->signal_routing_scheme ==
3129             PVR2_ROUTING_SCHEME_GOTVIEW) {
3130                 u32 b;
3131                 /* Handle GOTVIEW audio switching */
3132                 pvr2_hdw_gpio_get_out(hdw,&b);
3133                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3134                         /* Set GPIO 11 */
3135                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3136                 } else {
3137                         /* Clear GPIO 11 */
3138                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3139                 }
3140         }
3141
3142         /* Check and update state for all sub-devices. */
3143         pvr2_subdev_update(hdw);
3144
3145         hdw->tuner_updated = 0;
3146         hdw->force_dirty = 0;
3147         for (idx = 0; idx < hdw->control_cnt; idx++) {
3148                 cptr = hdw->controls + idx;
3149                 if (!cptr->info->clear_dirty) continue;
3150                 cptr->info->clear_dirty(cptr);
3151         }
3152
3153         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3154             hdw->state_encoder_run) {
3155                 /* If encoder isn't running or it can't be touched, then
3156                    this will get worked out later when we start the
3157                    encoder. */
3158                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3159         }
3160
3161         hdw->state_pipeline_config = !0;
3162         /* Hardware state may have changed in a way to cause the cropping
3163            capabilities to have changed.  So mark it stale, which will
3164            cause a later re-fetch. */
3165         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3166         return !0;
3167 }
3168
3169
3170 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3171 {
3172         int fl;
3173         LOCK_TAKE(hdw->big_lock);
3174         fl = pvr2_hdw_commit_setup(hdw);
3175         LOCK_GIVE(hdw->big_lock);
3176         if (!fl) return 0;
3177         return pvr2_hdw_wait(hdw,0);
3178 }
3179
3180
3181 static void pvr2_hdw_worker_poll(struct work_struct *work)
3182 {
3183         int fl = 0;
3184         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3185         LOCK_TAKE(hdw->big_lock); do {
3186                 fl = pvr2_hdw_state_eval(hdw);
3187         } while (0); LOCK_GIVE(hdw->big_lock);
3188         if (fl && hdw->state_func) {
3189                 hdw->state_func(hdw->state_data);
3190         }
3191 }
3192
3193
3194 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3195 {
3196         return wait_event_interruptible(
3197                 hdw->state_wait_data,
3198                 (hdw->state_stale == 0) &&
3199                 (!state || (hdw->master_state != state)));
3200 }
3201
3202
3203 /* Return name for this driver instance */
3204 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3205 {
3206         return hdw->name;
3207 }
3208
3209
3210 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3211 {
3212         return hdw->hdw_desc->description;
3213 }
3214
3215
3216 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3217 {
3218         return hdw->hdw_desc->shortname;
3219 }
3220
3221
3222 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3223 {
3224         int result;
3225         LOCK_TAKE(hdw->ctl_lock); do {
3226                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3227                 result = pvr2_send_request(hdw,
3228                                            hdw->cmd_buffer,1,
3229                                            hdw->cmd_buffer,1);
3230                 if (result < 0) break;
3231                 result = (hdw->cmd_buffer[0] != 0);
3232         } while(0); LOCK_GIVE(hdw->ctl_lock);
3233         return result;
3234 }
3235
3236
3237 /* Execute poll of tuner status */
3238 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3239 {
3240         LOCK_TAKE(hdw->big_lock); do {
3241                 pvr2_hdw_status_poll(hdw);
3242         } while (0); LOCK_GIVE(hdw->big_lock);
3243 }
3244
3245
3246 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3247 {
3248         if (!hdw->cropcap_stale) {
3249                 return 0;
3250         }
3251         pvr2_hdw_status_poll(hdw);
3252         if (hdw->cropcap_stale) {
3253                 return -EIO;
3254         }
3255         return 0;
3256 }
3257
3258
3259 /* Return information about cropping capabilities */
3260 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3261 {
3262         int stat = 0;
3263         LOCK_TAKE(hdw->big_lock);
3264         stat = pvr2_hdw_check_cropcap(hdw);
3265         if (!stat) {
3266                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3267         }
3268         LOCK_GIVE(hdw->big_lock);
3269         return stat;
3270 }
3271
3272
3273 /* Return information about the tuner */
3274 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3275 {
3276         LOCK_TAKE(hdw->big_lock); do {
3277                 if (hdw->tuner_signal_stale) {
3278                         pvr2_hdw_status_poll(hdw);
3279                 }
3280                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3281         } while (0); LOCK_GIVE(hdw->big_lock);
3282         return 0;
3283 }
3284
3285
3286 /* Get handle to video output stream */
3287 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3288 {
3289         return hp->vid_stream;
3290 }
3291
3292
3293 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3294 {
3295         int nr = pvr2_hdw_get_unit_number(hdw);
3296         LOCK_TAKE(hdw->big_lock);
3297         do {
3298                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3299                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3300                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3301                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3302                 pvr2_hdw_state_log_state(hdw);
3303                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3304         } while (0);
3305         LOCK_GIVE(hdw->big_lock);
3306 }
3307
3308
3309 /* Grab EEPROM contents, needed for direct method. */
3310 #define EEPROM_SIZE 8192
3311 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3312 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3313 {
3314         struct i2c_msg msg[2];
3315         u8 *eeprom;
3316         u8 iadd[2];
3317         u8 addr;
3318         u16 eepromSize;
3319         unsigned int offs;
3320         int ret;
3321         int mode16 = 0;
3322         unsigned pcnt,tcnt;
3323         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3324         if (!eeprom) {
3325                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3326                            "Failed to allocate memory required to read eeprom");
3327                 return NULL;
3328         }
3329
3330         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3331                      hdw->eeprom_addr);
3332         addr = hdw->eeprom_addr;
3333         /* Seems that if the high bit is set, then the *real* eeprom
3334            address is shifted right now bit position (noticed this in
3335            newer PVR USB2 hardware) */
3336         if (addr & 0x80) addr >>= 1;
3337
3338         /* FX2 documentation states that a 16bit-addressed eeprom is
3339            expected if the I2C address is an odd number (yeah, this is
3340            strange but it's what they do) */
3341         mode16 = (addr & 1);
3342         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3343         trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing",
3344                      eepromSize, addr,
3345                      mode16 ? 16 : 8);
3346
3347         msg[0].addr = addr;
3348         msg[0].flags = 0;
3349         msg[0].len = mode16 ? 2 : 1;
3350         msg[0].buf = iadd;
3351         msg[1].addr = addr;
3352         msg[1].flags = I2C_M_RD;
3353
3354         /* We have to do the actual eeprom data fetch ourselves, because
3355            (1) we're only fetching part of the eeprom, and (2) if we were
3356            getting the whole thing our I2C driver can't grab it in one
3357            pass - which is what tveeprom is otherwise going to attempt */
3358         memset(eeprom,0,EEPROM_SIZE);
3359         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3360                 pcnt = 16;
3361                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3362                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3363                 if (mode16) {
3364                         iadd[0] = offs >> 8;
3365                         iadd[1] = offs;
3366                 } else {
3367                         iadd[0] = offs;
3368                 }
3369                 msg[1].len = pcnt;
3370                 msg[1].buf = eeprom+tcnt;
3371                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3372                                         msg,ARRAY_SIZE(msg))) != 2) {
3373                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3374                                    "eeprom fetch set offs err=%d",ret);
3375                         kfree(eeprom);
3376                         return NULL;
3377                 }
3378         }
3379         return eeprom;
3380 }
3381
3382
3383 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3384                                 int mode,
3385                                 int enable_flag)
3386 {
3387         int ret;
3388         u16 address;
3389         unsigned int pipe;
3390         LOCK_TAKE(hdw->big_lock); do {
3391                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3392
3393                 if (!enable_flag) {
3394                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3395                                    "Cleaning up after CPU firmware fetch");
3396                         kfree(hdw->fw_buffer);
3397                         hdw->fw_buffer = NULL;
3398                         hdw->fw_size = 0;
3399                         if (hdw->fw_cpu_flag) {
3400                                 /* Now release the CPU.  It will disconnect
3401                                    and reconnect later. */
3402                                 pvr2_hdw_cpureset_assert(hdw,0);
3403                         }
3404                         break;
3405                 }
3406
3407                 hdw->fw_cpu_flag = (mode != 2);
3408                 if (hdw->fw_cpu_flag) {
3409                         hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3410                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3411                                    "Preparing to suck out CPU firmware (size=%u)",
3412                                    hdw->fw_size);
3413                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3414                         if (!hdw->fw_buffer) {
3415                                 hdw->fw_size = 0;
3416                                 break;
3417                         }
3418
3419                         /* We have to hold the CPU during firmware upload. */
3420                         pvr2_hdw_cpureset_assert(hdw,1);
3421
3422                         /* download the firmware from address 0000-1fff in 2048
3423                            (=0x800) bytes chunk. */
3424
3425                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3426                                    "Grabbing CPU firmware");
3427                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3428                         for(address = 0; address < hdw->fw_size;
3429                             address += 0x800) {
3430                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3431                                                       0xa0,0xc0,
3432                                                       address,0,
3433                                                       hdw->fw_buffer+address,
3434                                                       0x800,HZ);
3435                                 if (ret < 0) break;
3436                         }
3437
3438                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3439                                    "Done grabbing CPU firmware");
3440                 } else {
3441                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3442                                    "Sucking down EEPROM contents");
3443                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3444                         if (!hdw->fw_buffer) {
3445                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3446                                            "EEPROM content suck failed.");
3447                                 break;
3448                         }
3449                         hdw->fw_size = EEPROM_SIZE;
3450                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3451                                    "Done sucking down EEPROM contents");
3452                 }
3453
3454         } while (0); LOCK_GIVE(hdw->big_lock);
3455 }
3456
3457
3458 /* Return true if we're in a mode for retrieval CPU firmware */
3459 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3460 {
3461         return hdw->fw_buffer != NULL;
3462 }
3463
3464
3465 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3466                        char *buf,unsigned int cnt)
3467 {
3468         int ret = -EINVAL;
3469         LOCK_TAKE(hdw->big_lock); do {
3470                 if (!buf) break;
3471                 if (!cnt) break;
3472
3473                 if (!hdw->fw_buffer) {
3474                         ret = -EIO;
3475                         break;
3476                 }
3477
3478                 if (offs >= hdw->fw_size) {
3479                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3480                                    "Read firmware data offs=%d EOF",
3481                                    offs);
3482                         ret = 0;
3483                         break;
3484                 }
3485
3486                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3487
3488                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3489
3490                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3491                            "Read firmware data offs=%d cnt=%d",
3492                            offs,cnt);
3493                 ret = cnt;
3494         } while (0); LOCK_GIVE(hdw->big_lock);
3495
3496         return ret;
3497 }
3498
3499
3500 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3501                                   enum pvr2_v4l_type index)
3502 {
3503         switch (index) {
3504         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3505         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3506         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3507         default: return -1;
3508         }
3509 }
3510
3511
3512 /* Store a v4l minor device number */
3513 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3514                                      enum pvr2_v4l_type index,int v)
3515 {
3516         switch (index) {
3517         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3518         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3519         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3520         default: break;
3521         }
3522 }
3523
3524
3525 static void pvr2_ctl_write_complete(struct urb *urb)
3526 {
3527         struct pvr2_hdw *hdw = urb->context;
3528         hdw->ctl_write_pend_flag = 0;
3529         if (hdw->ctl_read_pend_flag) return;
3530         complete(&hdw->ctl_done);
3531 }
3532
3533
3534 static void pvr2_ctl_read_complete(struct urb *urb)
3535 {
3536         struct pvr2_hdw *hdw = urb->context;
3537         hdw->ctl_read_pend_flag = 0;
3538         if (hdw->ctl_write_pend_flag) return;
3539         complete(&hdw->ctl_done);
3540 }
3541
3542
3543 static void pvr2_ctl_timeout(unsigned long data)
3544 {
3545         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3546         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3547                 hdw->ctl_timeout_flag = !0;
3548                 if (hdw->ctl_write_pend_flag)
3549                         usb_unlink_urb(hdw->ctl_write_urb);
3550                 if (hdw->ctl_read_pend_flag)
3551                         usb_unlink_urb(hdw->ctl_read_urb);
3552         }
3553 }
3554
3555
3556 /* Issue a command and get a response from the device.  This extended
3557    version includes a probe flag (which if set means that device errors
3558    should not be logged or treated as fatal) and a timeout in jiffies.
3559    This can be used to non-lethally probe the health of endpoint 1. */
3560 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3561                                 unsigned int timeout,int probe_fl,
3562                                 void *write_data,unsigned int write_len,
3563                                 void *read_data,unsigned int read_len)
3564 {
3565         unsigned int idx;
3566         int status = 0;
3567         struct timer_list timer;
3568         if (!hdw->ctl_lock_held) {
3569                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3570                            "Attempted to execute control transfer without lock!!");
3571                 return -EDEADLK;
3572         }
3573         if (!hdw->flag_ok && !probe_fl) {
3574                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3575                            "Attempted to execute control transfer when device not ok");
3576                 return -EIO;
3577         }
3578         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3579                 if (!probe_fl) {
3580                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3581                                    "Attempted to execute control transfer when USB is disconnected");
3582                 }
3583                 return -ENOTTY;
3584         }
3585
3586         /* Ensure that we have sane parameters */
3587         if (!write_data) write_len = 0;
3588         if (!read_data) read_len = 0;
3589         if (write_len > PVR2_CTL_BUFFSIZE) {
3590                 pvr2_trace(
3591                         PVR2_TRACE_ERROR_LEGS,
3592                         "Attempted to execute %d byte control-write transfer (limit=%d)",
3593                         write_len,PVR2_CTL_BUFFSIZE);
3594                 return -EINVAL;
3595         }
3596         if (read_len > PVR2_CTL_BUFFSIZE) {
3597                 pvr2_trace(
3598                         PVR2_TRACE_ERROR_LEGS,
3599                         "Attempted to execute %d byte control-read transfer (limit=%d)",
3600                         write_len,PVR2_CTL_BUFFSIZE);
3601                 return -EINVAL;
3602         }
3603         if ((!write_len) && (!read_len)) {
3604                 pvr2_trace(
3605                         PVR2_TRACE_ERROR_LEGS,
3606                         "Attempted to execute null control transfer?");
3607                 return -EINVAL;
3608         }
3609
3610
3611         hdw->cmd_debug_state = 1;
3612         if (write_len && write_data)
3613                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3614         else
3615                 hdw->cmd_debug_code = 0;
3616         hdw->cmd_debug_write_len = write_len;
3617         hdw->cmd_debug_read_len = read_len;
3618
3619         /* Initialize common stuff */
3620         init_completion(&hdw->ctl_done);
3621         hdw->ctl_timeout_flag = 0;
3622         hdw->ctl_write_pend_flag = 0;
3623         hdw->ctl_read_pend_flag = 0;
3624         setup_timer(&timer, pvr2_ctl_timeout, (unsigned long)hdw);
3625         timer.expires = jiffies + timeout;
3626
3627         if (write_len && write_data) {
3628                 hdw->cmd_debug_state = 2;
3629                 /* Transfer write data to internal buffer */
3630                 for (idx = 0; idx < write_len; idx++) {
3631                         hdw->ctl_write_buffer[idx] =
3632                                 ((unsigned char *)write_data)[idx];
3633                 }
3634                 /* Initiate a write request */
3635                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3636                                   hdw->usb_dev,
3637                                   usb_sndbulkpipe(hdw->usb_dev,
3638                                                   PVR2_CTL_WRITE_ENDPOINT),
3639                                   hdw->ctl_write_buffer,
3640                                   write_len,
3641                                   pvr2_ctl_write_complete,
3642                                   hdw);
3643                 hdw->ctl_write_urb->actual_length = 0;
3644                 hdw->ctl_write_pend_flag = !0;
3645                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3646                 if (status < 0) {
3647                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3648                                    "Failed to submit write-control URB status=%d",
3649 status);
3650                         hdw->ctl_write_pend_flag = 0;
3651                         goto done;
3652                 }
3653         }
3654
3655         if (read_len) {
3656                 hdw->cmd_debug_state = 3;
3657                 memset(hdw->ctl_read_buffer,0x43,read_len);
3658                 /* Initiate a read request */
3659                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3660                                   hdw->usb_dev,
3661                                   usb_rcvbulkpipe(hdw->usb_dev,
3662                                                   PVR2_CTL_READ_ENDPOINT),
3663                                   hdw->ctl_read_buffer,
3664                                   read_len,
3665                                   pvr2_ctl_read_complete,
3666                                   hdw);
3667                 hdw->ctl_read_urb->actual_length = 0;
3668                 hdw->ctl_read_pend_flag = !0;
3669                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3670                 if (status < 0) {
3671                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3672                                    "Failed to submit read-control URB status=%d",
3673 status);
3674                         hdw->ctl_read_pend_flag = 0;
3675                         goto done;
3676                 }
3677         }
3678
3679         /* Start timer */
3680         add_timer(&timer);
3681
3682         /* Now wait for all I/O to complete */
3683         hdw->cmd_debug_state = 4;
3684         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3685                 wait_for_completion(&hdw->ctl_done);
3686         }
3687         hdw->cmd_debug_state = 5;
3688
3689         /* Stop timer */
3690         del_timer_sync(&timer);
3691
3692         hdw->cmd_debug_state = 6;
3693         status = 0;
3694
3695         if (hdw->ctl_timeout_flag) {
3696                 status = -ETIMEDOUT;
3697                 if (!probe_fl) {
3698                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3699                                    "Timed out control-write");
3700                 }
3701                 goto done;
3702         }
3703
3704         if (write_len) {
3705                 /* Validate results of write request */
3706                 if ((hdw->ctl_write_urb->status != 0) &&
3707                     (hdw->ctl_write_urb->status != -ENOENT) &&
3708                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3709                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3710                         /* USB subsystem is reporting some kind of failure
3711                            on the write */
3712                         status = hdw->ctl_write_urb->status;
3713                         if (!probe_fl) {
3714                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3715                                            "control-write URB failure, status=%d",
3716                                            status);
3717                         }
3718                         goto done;
3719                 }
3720                 if (hdw->ctl_write_urb->actual_length < write_len) {
3721                         /* Failed to write enough data */
3722                         status = -EIO;
3723                         if (!probe_fl) {
3724                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3725                                            "control-write URB short, expected=%d got=%d",
3726                                            write_len,
3727                                            hdw->ctl_write_urb->actual_length);
3728                         }
3729                         goto done;
3730                 }
3731         }
3732         if (read_len && read_data) {
3733                 /* Validate results of read request */
3734                 if ((hdw->ctl_read_urb->status != 0) &&
3735                     (hdw->ctl_read_urb->status != -ENOENT) &&
3736                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3737                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3738                         /* USB subsystem is reporting some kind of failure
3739                            on the read */
3740                         status = hdw->ctl_read_urb->status;
3741                         if (!probe_fl) {
3742                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3743                                            "control-read URB failure, status=%d",
3744                                            status);
3745                         }
3746                         goto done;
3747                 }
3748                 if (hdw->ctl_read_urb->actual_length < read_len) {
3749                         /* Failed to read enough data */
3750                         status = -EIO;
3751                         if (!probe_fl) {
3752                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3753                                            "control-read URB short, expected=%d got=%d",
3754                                            read_len,
3755                                            hdw->ctl_read_urb->actual_length);
3756                         }
3757                         goto done;
3758                 }
3759                 /* Transfer retrieved data out from internal buffer */
3760                 for (idx = 0; idx < read_len; idx++) {
3761                         ((unsigned char *)read_data)[idx] =
3762                                 hdw->ctl_read_buffer[idx];
3763                 }
3764         }
3765
3766  done:
3767
3768         hdw->cmd_debug_state = 0;
3769         if ((status < 0) && (!probe_fl)) {
3770                 pvr2_hdw_render_useless(hdw);
3771         }
3772         return status;
3773 }
3774
3775
3776 int pvr2_send_request(struct pvr2_hdw *hdw,
3777                       void *write_data,unsigned int write_len,
3778                       void *read_data,unsigned int read_len)
3779 {
3780         return pvr2_send_request_ex(hdw,HZ*4,0,
3781                                     write_data,write_len,
3782                                     read_data,read_len);
3783 }
3784
3785
3786 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3787 {
3788         int ret;
3789         unsigned int cnt = 1;
3790         unsigned int args = 0;
3791         LOCK_TAKE(hdw->ctl_lock);
3792         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3793         args = (cmdcode >> 8) & 0xffu;
3794         args = (args > 2) ? 2 : args;
3795         if (args) {
3796                 cnt += args;
3797                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3798                 if (args > 1) {
3799                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3800                 }
3801         }
3802         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3803                 unsigned int idx;
3804                 unsigned int ccnt,bcnt;
3805                 char tbuf[50];
3806                 cmdcode &= 0xffu;
3807                 bcnt = 0;
3808                 ccnt = scnprintf(tbuf+bcnt,
3809                                  sizeof(tbuf)-bcnt,
3810                                  "Sending FX2 command 0x%x",cmdcode);
3811                 bcnt += ccnt;
3812                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3813                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3814                                 ccnt = scnprintf(tbuf+bcnt,
3815                                                  sizeof(tbuf)-bcnt,
3816                                                  " \"%s\"",
3817                                                  pvr2_fx2cmd_desc[idx].desc);
3818                                 bcnt += ccnt;
3819                                 break;
3820                         }
3821                 }
3822                 if (args) {
3823                         ccnt = scnprintf(tbuf+bcnt,
3824                                          sizeof(tbuf)-bcnt,
3825                                          " (%u",hdw->cmd_buffer[1]);
3826                         bcnt += ccnt;
3827                         if (args > 1) {
3828                                 ccnt = scnprintf(tbuf+bcnt,
3829                                                  sizeof(tbuf)-bcnt,
3830                                                  ",%u",hdw->cmd_buffer[2]);
3831                                 bcnt += ccnt;
3832                         }
3833                         ccnt = scnprintf(tbuf+bcnt,
3834                                          sizeof(tbuf)-bcnt,
3835                                          ")");
3836                         bcnt += ccnt;
3837                 }
3838                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3839         }
3840         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3841         LOCK_GIVE(hdw->ctl_lock);
3842         return ret;
3843 }
3844
3845
3846 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3847 {
3848         int ret;
3849
3850         LOCK_TAKE(hdw->ctl_lock);
3851
3852         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3853         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3854         hdw->cmd_buffer[5] = 0;
3855         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3856         hdw->cmd_buffer[7] = reg & 0xff;
3857
3858
3859         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3860
3861         LOCK_GIVE(hdw->ctl_lock);
3862
3863         return ret;
3864 }
3865
3866
3867 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3868 {
3869         int ret = 0;
3870
3871         LOCK_TAKE(hdw->ctl_lock);
3872
3873         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3874         hdw->cmd_buffer[1] = 0;
3875         hdw->cmd_buffer[2] = 0;
3876         hdw->cmd_buffer[3] = 0;
3877         hdw->cmd_buffer[4] = 0;
3878         hdw->cmd_buffer[5] = 0;
3879         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3880         hdw->cmd_buffer[7] = reg & 0xff;
3881
3882         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3883         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3884
3885         LOCK_GIVE(hdw->ctl_lock);
3886
3887         return ret;
3888 }
3889
3890
3891 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3892 {
3893         if (!hdw->flag_ok) return;
3894         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3895                    "Device being rendered inoperable");
3896         if (hdw->vid_stream) {
3897                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3898         }
3899         hdw->flag_ok = 0;
3900         trace_stbit("flag_ok",hdw->flag_ok);
3901         pvr2_hdw_state_sched(hdw);
3902 }
3903
3904
3905 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3906 {
3907         int ret;
3908         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3909         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3910         if (ret == 0) {
3911                 ret = usb_reset_device(hdw->usb_dev);
3912                 usb_unlock_device(hdw->usb_dev);
3913         } else {
3914                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3915                            "Failed to lock USB device ret=%d",ret);
3916         }
3917         if (init_pause_msec) {
3918                 pvr2_trace(PVR2_TRACE_INFO,
3919                            "Waiting %u msec for hardware to settle",
3920                            init_pause_msec);
3921                 msleep(init_pause_msec);
3922         }
3923
3924 }
3925
3926
3927 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3928 {
3929         char *da;
3930         unsigned int pipe;
3931         int ret;
3932
3933         if (!hdw->usb_dev) return;
3934
3935         da = kmalloc(16, GFP_KERNEL);
3936
3937         if (da == NULL) {
3938                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3939                            "Unable to allocate memory to control CPU reset");
3940                 return;
3941         }
3942
3943         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3944
3945         da[0] = val ? 0x01 : 0x00;
3946
3947         /* Write the CPUCS register on the 8051.  The lsb of the register
3948            is the reset bit; a 1 asserts reset while a 0 clears it. */
3949         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3950         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3951         if (ret < 0) {
3952                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3953                            "cpureset_assert(%d) error=%d",val,ret);
3954                 pvr2_hdw_render_useless(hdw);
3955         }
3956
3957         kfree(da);
3958 }
3959
3960
3961 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3962 {
3963         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3964 }
3965
3966
3967 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3968 {
3969         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3970 }
3971
3972
3973
3974 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3975 {
3976         pvr2_trace(PVR2_TRACE_INIT,
3977                    "Requesting decoder reset");
3978         if (hdw->decoder_client_id) {
3979                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
3980                                      core, reset, 0);
3981                 pvr2_hdw_cx25840_vbi_hack(hdw);
3982                 return 0;
3983         }
3984         pvr2_trace(PVR2_TRACE_INIT,
3985                    "Unable to reset decoder: nothing attached");
3986         return -ENOTTY;
3987 }
3988
3989
3990 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3991 {
3992         hdw->flag_ok = !0;
3993         return pvr2_issue_simple_cmd(hdw,
3994                                      FX2CMD_HCW_DEMOD_RESETIN |
3995                                      (1 << 8) |
3996                                      ((onoff ? 1 : 0) << 16));
3997 }
3998
3999
4000 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4001 {
4002         hdw->flag_ok = !0;
4003         return pvr2_issue_simple_cmd(hdw,(onoff ?
4004                                           FX2CMD_ONAIR_DTV_POWER_ON :
4005                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4006 }
4007
4008
4009 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4010                                                 int onoff)
4011 {
4012         return pvr2_issue_simple_cmd(hdw,(onoff ?
4013                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4014                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4015 }
4016
4017
4018 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4019 {
4020         int cmode;
4021         /* Compare digital/analog desired setting with current setting.  If
4022            they don't match, fix it... */
4023         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4024         if (cmode == hdw->pathway_state) {
4025                 /* They match; nothing to do */
4026                 return;
4027         }
4028
4029         switch (hdw->hdw_desc->digital_control_scheme) {
4030         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4031                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4032                 if (cmode == PVR2_PATHWAY_ANALOG) {
4033                         /* If moving to analog mode, also force the decoder
4034                            to reset.  If no decoder is attached, then it's
4035                            ok to ignore this because if/when the decoder
4036                            attaches, it will reset itself at that time. */
4037                         pvr2_hdw_cmd_decoder_reset(hdw);
4038                 }
4039                 break;
4040         case PVR2_DIGITAL_SCHEME_ONAIR:
4041                 /* Supposedly we should always have the power on whether in
4042                    digital or analog mode.  But for now do what appears to
4043                    work... */
4044                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4045                 break;
4046         default: break;
4047         }
4048
4049         pvr2_hdw_untrip_unlocked(hdw);
4050         hdw->pathway_state = cmode;
4051 }
4052
4053
4054 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4055 {
4056         /* change some GPIO data
4057          *
4058          * note: bit d7 of dir appears to control the LED,
4059          * so we shut it off here.
4060          *
4061          */
4062         if (onoff) {
4063                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4064         } else {
4065                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4066         }
4067         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4068 }
4069
4070
4071 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4072
4073 static led_method_func led_methods[] = {
4074         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4075 };
4076
4077
4078 /* Toggle LED */
4079 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4080 {
4081         unsigned int scheme_id;
4082         led_method_func fp;
4083
4084         if ((!onoff) == (!hdw->led_on)) return;
4085
4086         hdw->led_on = onoff != 0;
4087
4088         scheme_id = hdw->hdw_desc->led_scheme;
4089         if (scheme_id < ARRAY_SIZE(led_methods)) {
4090                 fp = led_methods[scheme_id];
4091         } else {
4092                 fp = NULL;
4093         }
4094
4095         if (fp) (*fp)(hdw,onoff);
4096 }
4097
4098
4099 /* Stop / start video stream transport */
4100 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4101 {
4102         int ret;
4103
4104         /* If we're in analog mode, then just issue the usual analog
4105            command. */
4106         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4107                 return pvr2_issue_simple_cmd(hdw,
4108                                              (runFl ?
4109                                               FX2CMD_STREAMING_ON :
4110                                               FX2CMD_STREAMING_OFF));
4111                 /*Note: Not reached */
4112         }
4113
4114         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4115                 /* Whoops, we don't know what mode we're in... */
4116                 return -EINVAL;
4117         }
4118
4119         /* To get here we have to be in digital mode.  The mechanism here
4120            is unfortunately different for different vendors.  So we switch
4121            on the device's digital scheme attribute in order to figure out
4122            what to do. */
4123         switch (hdw->hdw_desc->digital_control_scheme) {
4124         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4125                 return pvr2_issue_simple_cmd(hdw,
4126                                              (runFl ?
4127                                               FX2CMD_HCW_DTV_STREAMING_ON :
4128                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4129         case PVR2_DIGITAL_SCHEME_ONAIR:
4130                 ret = pvr2_issue_simple_cmd(hdw,
4131                                             (runFl ?
4132                                              FX2CMD_STREAMING_ON :
4133                                              FX2CMD_STREAMING_OFF));
4134                 if (ret) return ret;
4135                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4136         default:
4137                 return -EINVAL;
4138         }
4139 }
4140
4141
4142 /* Evaluate whether or not state_pathway_ok can change */
4143 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4144 {
4145         if (hdw->state_pathway_ok) {
4146                 /* Nothing to do if pathway is already ok */
4147                 return 0;
4148         }
4149         if (!hdw->state_pipeline_idle) {
4150                 /* Not allowed to change anything if pipeline is not idle */
4151                 return 0;
4152         }
4153         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4154         hdw->state_pathway_ok = !0;
4155         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4156         return !0;
4157 }
4158
4159
4160 /* Evaluate whether or not state_encoder_ok can change */
4161 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4162 {
4163         if (hdw->state_encoder_ok) return 0;
4164         if (hdw->flag_tripped) return 0;
4165         if (hdw->state_encoder_run) return 0;
4166         if (hdw->state_encoder_config) return 0;
4167         if (hdw->state_decoder_run) return 0;
4168         if (hdw->state_usbstream_run) return 0;
4169         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4170                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4171         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4172                 return 0;
4173         }
4174
4175         if (pvr2_upload_firmware2(hdw) < 0) {
4176                 hdw->flag_tripped = !0;
4177                 trace_stbit("flag_tripped",hdw->flag_tripped);
4178                 return !0;
4179         }
4180         hdw->state_encoder_ok = !0;
4181         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4182         return !0;
4183 }
4184
4185
4186 /* Evaluate whether or not state_encoder_config can change */
4187 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4188 {
4189         if (hdw->state_encoder_config) {
4190                 if (hdw->state_encoder_ok) {
4191                         if (hdw->state_pipeline_req &&
4192                             !hdw->state_pipeline_pause) return 0;
4193                 }
4194                 hdw->state_encoder_config = 0;
4195                 hdw->state_encoder_waitok = 0;
4196                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4197                 /* paranoia - solve race if timer just completed */
4198                 del_timer_sync(&hdw->encoder_wait_timer);
4199         } else {
4200                 if (!hdw->state_pathway_ok ||
4201                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4202                     !hdw->state_encoder_ok ||
4203                     !hdw->state_pipeline_idle ||
4204                     hdw->state_pipeline_pause ||
4205                     !hdw->state_pipeline_req ||
4206                     !hdw->state_pipeline_config) {
4207                         /* We must reset the enforced wait interval if
4208                            anything has happened that might have disturbed
4209                            the encoder.  This should be a rare case. */
4210                         if (timer_pending(&hdw->encoder_wait_timer)) {
4211                                 del_timer_sync(&hdw->encoder_wait_timer);
4212                         }
4213                         if (hdw->state_encoder_waitok) {
4214                                 /* Must clear the state - therefore we did
4215                                    something to a state bit and must also
4216                                    return true. */
4217                                 hdw->state_encoder_waitok = 0;
4218                                 trace_stbit("state_encoder_waitok",
4219                                             hdw->state_encoder_waitok);
4220                                 return !0;
4221                         }
4222                         return 0;
4223                 }
4224                 if (!hdw->state_encoder_waitok) {
4225                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4226                                 /* waitok flag wasn't set and timer isn't
4227                                    running.  Check flag once more to avoid
4228                                    a race then start the timer.  This is
4229                                    the point when we measure out a minimal
4230                                    quiet interval before doing something to
4231                                    the encoder. */
4232                                 if (!hdw->state_encoder_waitok) {
4233                                         hdw->encoder_wait_timer.expires =
4234                                                 jiffies + msecs_to_jiffies(
4235                                                 TIME_MSEC_ENCODER_WAIT);
4236                                         add_timer(&hdw->encoder_wait_timer);
4237                                 }
4238                         }
4239                         /* We can't continue until we know we have been
4240                            quiet for the interval measured by this
4241                            timer. */
4242                         return 0;
4243                 }
4244                 pvr2_encoder_configure(hdw);
4245                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4246         }
4247         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4248         return !0;
4249 }
4250
4251
4252 /* Return true if the encoder should not be running. */
4253 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4254 {
4255         if (!hdw->state_encoder_ok) {
4256                 /* Encoder isn't healthy at the moment, so stop it. */
4257                 return !0;
4258         }
4259         if (!hdw->state_pathway_ok) {
4260                 /* Mode is not understood at the moment (i.e. it wants to
4261                    change), so encoder must be stopped. */
4262                 return !0;
4263         }
4264
4265         switch (hdw->pathway_state) {
4266         case PVR2_PATHWAY_ANALOG:
4267                 if (!hdw->state_decoder_run) {
4268                         /* We're in analog mode and the decoder is not
4269                            running; thus the encoder should be stopped as
4270                            well. */
4271                         return !0;
4272                 }
4273                 break;
4274         case PVR2_PATHWAY_DIGITAL:
4275                 if (hdw->state_encoder_runok) {
4276                         /* This is a funny case.  We're in digital mode so
4277                            really the encoder should be stopped.  However
4278                            if it really is running, only kill it after
4279                            runok has been set.  This gives a chance for the
4280                            onair quirk to function (encoder must run
4281                            briefly first, at least once, before onair
4282                            digital streaming can work). */
4283                         return !0;
4284                 }
4285                 break;
4286         default:
4287                 /* Unknown mode; so encoder should be stopped. */
4288                 return !0;
4289         }
4290
4291         /* If we get here, we haven't found a reason to stop the
4292            encoder. */
4293         return 0;
4294 }
4295
4296
4297 /* Return true if the encoder should be running. */
4298 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4299 {
4300         if (!hdw->state_encoder_ok) {
4301                 /* Don't run the encoder if it isn't healthy... */
4302                 return 0;
4303         }
4304         if (!hdw->state_pathway_ok) {
4305                 /* Don't run the encoder if we don't (yet) know what mode
4306                    we need to be in... */
4307                 return 0;
4308         }
4309
4310         switch (hdw->pathway_state) {
4311         case PVR2_PATHWAY_ANALOG:
4312                 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4313                         /* In analog mode, if the decoder is running, then
4314                            run the encoder. */
4315                         return !0;
4316                 }
4317                 break;
4318         case PVR2_PATHWAY_DIGITAL:
4319                 if ((hdw->hdw_desc->digital_control_scheme ==
4320                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4321                     !hdw->state_encoder_runok) {
4322                         /* This is a quirk.  OnAir hardware won't stream
4323                            digital until the encoder has been run at least
4324                            once, for a minimal period of time (empiricially
4325                            measured to be 1/4 second).  So if we're on
4326                            OnAir hardware and the encoder has never been
4327                            run at all, then start the encoder.  Normal
4328                            state machine logic in the driver will
4329                            automatically handle the remaining bits. */
4330                         return !0;
4331                 }
4332                 break;
4333         default:
4334                 /* For completeness (unknown mode; encoder won't run ever) */
4335                 break;
4336         }
4337         /* If we get here, then we haven't found any reason to run the
4338            encoder, so don't run it. */
4339         return 0;
4340 }
4341
4342
4343 /* Evaluate whether or not state_encoder_run can change */
4344 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4345 {
4346         if (hdw->state_encoder_run) {
4347                 if (!state_check_disable_encoder_run(hdw)) return 0;
4348                 if (hdw->state_encoder_ok) {
4349                         del_timer_sync(&hdw->encoder_run_timer);
4350                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4351                 }
4352                 hdw->state_encoder_run = 0;
4353         } else {
4354                 if (!state_check_enable_encoder_run(hdw)) return 0;
4355                 if (pvr2_encoder_start(hdw) < 0) return !0;
4356                 hdw->state_encoder_run = !0;
4357                 if (!hdw->state_encoder_runok) {
4358                         hdw->encoder_run_timer.expires = jiffies +
4359                                  msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
4360                         add_timer(&hdw->encoder_run_timer);
4361                 }
4362         }
4363         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4364         return !0;
4365 }
4366
4367
4368 /* Timeout function for quiescent timer. */
4369 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4370 {
4371         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4372         hdw->state_decoder_quiescent = !0;
4373         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4374         hdw->state_stale = !0;
4375         schedule_work(&hdw->workpoll);
4376 }
4377
4378
4379 /* Timeout function for decoder stabilization timer. */
4380 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4381 {
4382         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4383         hdw->state_decoder_ready = !0;
4384         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4385         hdw->state_stale = !0;
4386         schedule_work(&hdw->workpoll);
4387 }
4388
4389
4390 /* Timeout function for encoder wait timer. */
4391 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4392 {
4393         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4394         hdw->state_encoder_waitok = !0;
4395         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4396         hdw->state_stale = !0;
4397         schedule_work(&hdw->workpoll);
4398 }
4399
4400
4401 /* Timeout function for encoder run timer. */
4402 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4403 {
4404         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4405         if (!hdw->state_encoder_runok) {
4406                 hdw->state_encoder_runok = !0;
4407                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4408                 hdw->state_stale = !0;
4409                 schedule_work(&hdw->workpoll);
4410         }
4411 }
4412
4413
4414 /* Evaluate whether or not state_decoder_run can change */
4415 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4416 {
4417         if (hdw->state_decoder_run) {
4418                 if (hdw->state_encoder_ok) {
4419                         if (hdw->state_pipeline_req &&
4420                             !hdw->state_pipeline_pause &&
4421                             hdw->state_pathway_ok) return 0;
4422                 }
4423                 if (!hdw->flag_decoder_missed) {
4424                         pvr2_decoder_enable(hdw,0);
4425                 }
4426                 hdw->state_decoder_quiescent = 0;
4427                 hdw->state_decoder_run = 0;
4428                 /* paranoia - solve race if timer(s) just completed */
4429                 del_timer_sync(&hdw->quiescent_timer);
4430                 /* Kill the stabilization timer, in case we're killing the
4431                    encoder before the previous stabilization interval has
4432                    been properly timed. */
4433                 del_timer_sync(&hdw->decoder_stabilization_timer);
4434                 hdw->state_decoder_ready = 0;
4435         } else {
4436                 if (!hdw->state_decoder_quiescent) {
4437                         if (!timer_pending(&hdw->quiescent_timer)) {
4438                                 /* We don't do something about the
4439                                    quiescent timer until right here because
4440                                    we also want to catch cases where the
4441                                    decoder was already not running (like
4442                                    after initialization) as opposed to
4443                                    knowing that we had just stopped it.
4444                                    The second flag check is here to cover a
4445                                    race - the timer could have run and set
4446                                    this flag just after the previous check
4447                                    but before we did the pending check. */
4448                                 if (!hdw->state_decoder_quiescent) {
4449                                         hdw->quiescent_timer.expires =
4450                                                 jiffies + msecs_to_jiffies(
4451                                                 TIME_MSEC_DECODER_WAIT);
4452                                         add_timer(&hdw->quiescent_timer);
4453                                 }
4454                         }
4455                         /* Don't allow decoder to start again until it has
4456                            been quiesced first.  This little detail should
4457                            hopefully further stabilize the encoder. */
4458                         return 0;
4459                 }
4460                 if (!hdw->state_pathway_ok ||
4461                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4462                     !hdw->state_pipeline_req ||
4463                     hdw->state_pipeline_pause ||
4464                     !hdw->state_pipeline_config ||
4465                     !hdw->state_encoder_config ||
4466                     !hdw->state_encoder_ok) return 0;
4467                 del_timer_sync(&hdw->quiescent_timer);
4468                 if (hdw->flag_decoder_missed) return 0;
4469                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4470                 hdw->state_decoder_quiescent = 0;
4471                 hdw->state_decoder_ready = 0;
4472                 hdw->state_decoder_run = !0;
4473                 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4474                         hdw->decoder_stabilization_timer.expires =
4475                                 jiffies + msecs_to_jiffies(
4476                                 TIME_MSEC_DECODER_STABILIZATION_WAIT);
4477                         add_timer(&hdw->decoder_stabilization_timer);
4478                 } else {
4479                         hdw->state_decoder_ready = !0;
4480                 }
4481         }
4482         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4483         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4484         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4485         return !0;
4486 }
4487
4488
4489 /* Evaluate whether or not state_usbstream_run can change */
4490 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4491 {
4492         if (hdw->state_usbstream_run) {
4493                 int fl = !0;
4494                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4495                         fl = (hdw->state_encoder_ok &&
4496                               hdw->state_encoder_run);
4497                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4498                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4499                         fl = hdw->state_encoder_ok;
4500                 }
4501                 if (fl &&
4502                     hdw->state_pipeline_req &&
4503                     !hdw->state_pipeline_pause &&
4504                     hdw->state_pathway_ok) {
4505                         return 0;
4506                 }
4507                 pvr2_hdw_cmd_usbstream(hdw,0);
4508                 hdw->state_usbstream_run = 0;
4509         } else {
4510                 if (!hdw->state_pipeline_req ||
4511                     hdw->state_pipeline_pause ||
4512                     !hdw->state_pathway_ok) return 0;
4513                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4514                         if (!hdw->state_encoder_ok ||
4515                             !hdw->state_encoder_run) return 0;
4516                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4517                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4518                         if (!hdw->state_encoder_ok) return 0;
4519                         if (hdw->state_encoder_run) return 0;
4520                         if (hdw->hdw_desc->digital_control_scheme ==
4521                             PVR2_DIGITAL_SCHEME_ONAIR) {
4522                                 /* OnAir digital receivers won't stream
4523                                    unless the analog encoder has run first.
4524                                    Why?  I have no idea.  But don't even
4525                                    try until we know the analog side is
4526                                    known to have run. */
4527                                 if (!hdw->state_encoder_runok) return 0;
4528                         }
4529                 }
4530                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4531                 hdw->state_usbstream_run = !0;
4532         }
4533         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4534         return !0;
4535 }
4536
4537
4538 /* Attempt to configure pipeline, if needed */
4539 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4540 {
4541         if (hdw->state_pipeline_config ||
4542             hdw->state_pipeline_pause) return 0;
4543         pvr2_hdw_commit_execute(hdw);
4544         return !0;
4545 }
4546
4547
4548 /* Update pipeline idle and pipeline pause tracking states based on other
4549    inputs.  This must be called whenever the other relevant inputs have
4550    changed. */
4551 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4552 {
4553         unsigned int st;
4554         int updatedFl = 0;
4555         /* Update pipeline state */
4556         st = !(hdw->state_encoder_run ||
4557                hdw->state_decoder_run ||
4558                hdw->state_usbstream_run ||
4559                (!hdw->state_decoder_quiescent));
4560         if (!st != !hdw->state_pipeline_idle) {
4561                 hdw->state_pipeline_idle = st;
4562                 updatedFl = !0;
4563         }
4564         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4565                 hdw->state_pipeline_pause = 0;
4566                 updatedFl = !0;
4567         }
4568         return updatedFl;
4569 }
4570
4571
4572 typedef int (*state_eval_func)(struct pvr2_hdw *);
4573
4574 /* Set of functions to be run to evaluate various states in the driver. */
4575 static const state_eval_func eval_funcs[] = {
4576         state_eval_pathway_ok,
4577         state_eval_pipeline_config,
4578         state_eval_encoder_ok,
4579         state_eval_encoder_config,
4580         state_eval_decoder_run,
4581         state_eval_encoder_run,
4582         state_eval_usbstream_run,
4583 };
4584
4585
4586 /* Process various states and return true if we did anything interesting. */
4587 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4588 {
4589         unsigned int i;
4590         int state_updated = 0;
4591         int check_flag;
4592
4593         if (!hdw->state_stale) return 0;
4594         if ((hdw->fw1_state != FW1_STATE_OK) ||
4595             !hdw->flag_ok) {
4596                 hdw->state_stale = 0;
4597                 return !0;
4598         }
4599         /* This loop is the heart of the entire driver.  It keeps trying to
4600            evaluate various bits of driver state until nothing changes for
4601            one full iteration.  Each "bit of state" tracks some global
4602            aspect of the driver, e.g. whether decoder should run, if
4603            pipeline is configured, usb streaming is on, etc.  We separately
4604            evaluate each of those questions based on other driver state to
4605            arrive at the correct running configuration. */
4606         do {
4607                 check_flag = 0;
4608                 state_update_pipeline_state(hdw);
4609                 /* Iterate over each bit of state */
4610                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4611                         if ((*eval_funcs[i])(hdw)) {
4612                                 check_flag = !0;
4613                                 state_updated = !0;
4614                                 state_update_pipeline_state(hdw);
4615                         }
4616                 }
4617         } while (check_flag && hdw->flag_ok);
4618         hdw->state_stale = 0;
4619         trace_stbit("state_stale",hdw->state_stale);
4620         return state_updated;
4621 }
4622
4623
4624 static unsigned int print_input_mask(unsigned int msk,
4625                                      char *buf,unsigned int acnt)
4626 {
4627         unsigned int idx,ccnt;
4628         unsigned int tcnt = 0;
4629         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4630                 if (!((1 << idx) & msk)) continue;
4631                 ccnt = scnprintf(buf+tcnt,
4632                                  acnt-tcnt,
4633                                  "%s%s",
4634                                  (tcnt ? ", " : ""),
4635                                  control_values_input[idx]);
4636                 tcnt += ccnt;
4637         }
4638         return tcnt;
4639 }
4640
4641
4642 static const char *pvr2_pathway_state_name(int id)
4643 {
4644         switch (id) {
4645         case PVR2_PATHWAY_ANALOG: return "analog";
4646         case PVR2_PATHWAY_DIGITAL: return "digital";
4647         default: return "unknown";
4648         }
4649 }
4650
4651
4652 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4653                                              char *buf,unsigned int acnt)
4654 {
4655         switch (which) {
4656         case 0:
4657                 return scnprintf(
4658                         buf,acnt,
4659                         "driver:%s%s%s%s%s <mode=%s>",
4660                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4661                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4662                         (hdw->flag_disconnected ? " <disconnected>" :
4663                          " <connected>"),
4664                         (hdw->flag_tripped ? " <tripped>" : ""),
4665                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4666                         pvr2_pathway_state_name(hdw->pathway_state));
4667
4668         case 1:
4669                 return scnprintf(
4670                         buf,acnt,
4671                         "pipeline:%s%s%s%s",
4672                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4673                         (hdw->state_pipeline_config ?
4674                          " <configok>" : " <stale>"),
4675                         (hdw->state_pipeline_req ? " <req>" : ""),
4676                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4677         case 2:
4678                 return scnprintf(
4679                         buf,acnt,
4680                         "worker:%s%s%s%s%s%s%s",
4681                         (hdw->state_decoder_run ?
4682                          (hdw->state_decoder_ready ?
4683                           "<decode:run>" : " <decode:start>") :
4684                          (hdw->state_decoder_quiescent ?
4685                           "" : " <decode:stop>")),
4686                         (hdw->state_decoder_quiescent ?
4687                          " <decode:quiescent>" : ""),
4688                         (hdw->state_encoder_ok ?
4689                          "" : " <encode:init>"),
4690                         (hdw->state_encoder_run ?
4691                          (hdw->state_encoder_runok ?
4692                           " <encode:run>" :
4693                           " <encode:firstrun>") :
4694                          (hdw->state_encoder_runok ?
4695                           " <encode:stop>" :
4696                           " <encode:virgin>")),
4697                         (hdw->state_encoder_config ?
4698                          " <encode:configok>" :
4699                          (hdw->state_encoder_waitok ?
4700                           "" : " <encode:waitok>")),
4701                         (hdw->state_usbstream_run ?
4702                          " <usb:run>" : " <usb:stop>"),
4703                         (hdw->state_pathway_ok ?
4704                          " <pathway:ok>" : ""));
4705         case 3:
4706                 return scnprintf(
4707                         buf,acnt,
4708                         "state: %s",
4709                         pvr2_get_state_name(hdw->master_state));
4710         case 4: {
4711                 unsigned int tcnt = 0;
4712                 unsigned int ccnt;
4713
4714                 ccnt = scnprintf(buf,
4715                                  acnt,
4716                                  "Hardware supported inputs: ");
4717                 tcnt += ccnt;
4718                 tcnt += print_input_mask(hdw->input_avail_mask,
4719                                          buf+tcnt,
4720                                          acnt-tcnt);
4721                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4722                         ccnt = scnprintf(buf+tcnt,
4723                                          acnt-tcnt,
4724                                          "; allowed inputs: ");
4725                         tcnt += ccnt;
4726                         tcnt += print_input_mask(hdw->input_allowed_mask,
4727                                                  buf+tcnt,
4728                                                  acnt-tcnt);
4729                 }
4730                 return tcnt;
4731         }
4732         case 5: {
4733                 struct pvr2_stream_stats stats;
4734                 if (!hdw->vid_stream) break;
4735                 pvr2_stream_get_stats(hdw->vid_stream,
4736                                       &stats,
4737                                       0);
4738                 return scnprintf(
4739                         buf,acnt,
4740                         "Bytes streamed=%u URBs: queued=%u idle=%u ready=%u processed=%u failed=%u",
4741                         stats.bytes_processed,
4742                         stats.buffers_in_queue,
4743                         stats.buffers_in_idle,
4744                         stats.buffers_in_ready,
4745                         stats.buffers_processed,
4746                         stats.buffers_failed);
4747         }
4748         case 6: {
4749                 unsigned int id = hdw->ir_scheme_active;
4750                 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4751                                  (id >= ARRAY_SIZE(ir_scheme_names) ?
4752                                   "?" : ir_scheme_names[id]));
4753         }
4754         default: break;
4755         }
4756         return 0;
4757 }
4758
4759
4760 /* Generate report containing info about attached sub-devices and attached
4761    i2c clients, including an indication of which attached i2c clients are
4762    actually sub-devices. */
4763 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4764                                             char *buf, unsigned int acnt)
4765 {
4766         struct v4l2_subdev *sd;
4767         unsigned int tcnt = 0;
4768         unsigned int ccnt;
4769         struct i2c_client *client;
4770         const char *p;
4771         unsigned int id;
4772
4773         ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4774         tcnt += ccnt;
4775         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4776                 id = sd->grp_id;
4777                 p = NULL;
4778                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4779                 if (p) {
4780                         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4781                         tcnt += ccnt;
4782                 } else {
4783                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4784                                          "  (unknown id=%u):", id);
4785                         tcnt += ccnt;
4786                 }
4787                 client = v4l2_get_subdevdata(sd);
4788                 if (client) {
4789                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4790                                          " %s @ %02x\n", client->name,
4791                                          client->addr);
4792                         tcnt += ccnt;
4793                 } else {
4794                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4795                                          " no i2c client\n");
4796                         tcnt += ccnt;
4797                 }
4798         }
4799         return tcnt;
4800 }
4801
4802
4803 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4804                                    char *buf,unsigned int acnt)
4805 {
4806         unsigned int bcnt,ccnt,idx;
4807         bcnt = 0;
4808         LOCK_TAKE(hdw->big_lock);
4809         for (idx = 0; ; idx++) {
4810                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4811                 if (!ccnt) break;
4812                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4813                 if (!acnt) break;
4814                 buf[0] = '\n'; ccnt = 1;
4815                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4816         }
4817         ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4818         bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4819         LOCK_GIVE(hdw->big_lock);
4820         return bcnt;
4821 }
4822
4823
4824 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4825 {
4826         char buf[256];
4827         unsigned int idx, ccnt;
4828         unsigned int lcnt, ucnt;
4829
4830         for (idx = 0; ; idx++) {
4831                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4832                 if (!ccnt) break;
4833                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4834         }
4835         ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4836         if (ccnt >= sizeof(buf))
4837                 ccnt = sizeof(buf);
4838
4839         ucnt = 0;
4840         while (ucnt < ccnt) {
4841                 lcnt = 0;
4842                 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4843                         lcnt++;
4844                 }
4845                 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4846                 ucnt += lcnt + 1;
4847         }
4848 }
4849
4850
4851 /* Evaluate and update the driver's current state, taking various actions
4852    as appropriate for the update. */
4853 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4854 {
4855         unsigned int st;
4856         int state_updated = 0;
4857         int callback_flag = 0;
4858         int analog_mode;
4859
4860         pvr2_trace(PVR2_TRACE_STBITS,
4861                    "Drive state check START");
4862         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4863                 pvr2_hdw_state_log_state(hdw);
4864         }
4865
4866         /* Process all state and get back over disposition */
4867         state_updated = pvr2_hdw_state_update(hdw);
4868
4869         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4870
4871         /* Update master state based upon all other states. */
4872         if (!hdw->flag_ok) {
4873                 st = PVR2_STATE_DEAD;
4874         } else if (hdw->fw1_state != FW1_STATE_OK) {
4875                 st = PVR2_STATE_COLD;
4876         } else if ((analog_mode ||
4877                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4878                    !hdw->state_encoder_ok) {
4879                 st = PVR2_STATE_WARM;
4880         } else if (hdw->flag_tripped ||
4881                    (analog_mode && hdw->flag_decoder_missed)) {
4882                 st = PVR2_STATE_ERROR;
4883         } else if (hdw->state_usbstream_run &&
4884                    (!analog_mode ||
4885                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4886                 st = PVR2_STATE_RUN;
4887         } else {
4888                 st = PVR2_STATE_READY;
4889         }
4890         if (hdw->master_state != st) {
4891                 pvr2_trace(PVR2_TRACE_STATE,
4892                            "Device state change from %s to %s",
4893                            pvr2_get_state_name(hdw->master_state),
4894                            pvr2_get_state_name(st));
4895                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4896                 hdw->master_state = st;
4897                 state_updated = !0;
4898                 callback_flag = !0;
4899         }
4900         if (state_updated) {
4901                 /* Trigger anyone waiting on any state changes here. */
4902                 wake_up(&hdw->state_wait_data);
4903         }
4904
4905         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4906                 pvr2_hdw_state_log_state(hdw);
4907         }
4908         pvr2_trace(PVR2_TRACE_STBITS,
4909                    "Drive state check DONE callback=%d",callback_flag);
4910
4911         return callback_flag;
4912 }
4913
4914
4915 /* Cause kernel thread to check / update driver state */
4916 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4917 {
4918         if (hdw->state_stale) return;
4919         hdw->state_stale = !0;
4920         trace_stbit("state_stale",hdw->state_stale);
4921         schedule_work(&hdw->workpoll);
4922 }
4923
4924
4925 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4926 {
4927         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4928 }
4929
4930
4931 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4932 {
4933         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4934 }
4935
4936
4937 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4938 {
4939         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4940 }
4941
4942
4943 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4944 {
4945         u32 cval,nval;
4946         int ret;
4947         if (~msk) {
4948                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4949                 if (ret) return ret;
4950                 nval = (cval & ~msk) | (val & msk);
4951                 pvr2_trace(PVR2_TRACE_GPIO,
4952                            "GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x",
4953                            msk,val,cval,nval);
4954         } else {
4955                 nval = val;
4956                 pvr2_trace(PVR2_TRACE_GPIO,
4957                            "GPIO direction changing to 0x%x",nval);
4958         }
4959         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4960 }
4961
4962
4963 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4964 {
4965         u32 cval,nval;
4966         int ret;
4967         if (~msk) {
4968                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4969                 if (ret) return ret;
4970                 nval = (cval & ~msk) | (val & msk);
4971                 pvr2_trace(PVR2_TRACE_GPIO,
4972                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4973                            msk,val,cval,nval);
4974         } else {
4975                 nval = val;
4976                 pvr2_trace(PVR2_TRACE_GPIO,
4977                            "GPIO output changing to 0x%x",nval);
4978         }
4979         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4980 }
4981
4982
4983 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
4984 {
4985         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
4986         memset(vtp, 0, sizeof(*vtp));
4987         vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
4988                 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
4989         hdw->tuner_signal_stale = 0;
4990         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
4991            using v4l2-subdev - therefore we can't support that AT ALL right
4992            now.  (Of course, no sub-drivers seem to implement it either.
4993            But now it's a a chicken and egg problem...) */
4994         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
4995         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi=%u",
4996                    vtp->type,
4997                    vtp->signal, vtp->rxsubchans, vtp->capability,
4998                    vtp->rangelow, vtp->rangehigh);
4999
5000         /* We have to do this to avoid getting into constant polling if
5001            there's nobody to answer a poll of cropcap info. */
5002         hdw->cropcap_stale = 0;
5003 }
5004
5005
5006 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5007 {
5008         return hdw->input_avail_mask;
5009 }
5010
5011
5012 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5013 {
5014         return hdw->input_allowed_mask;
5015 }
5016
5017
5018 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5019 {
5020         if (hdw->input_val != v) {
5021                 hdw->input_val = v;
5022                 hdw->input_dirty = !0;
5023         }
5024
5025         /* Handle side effects - if we switch to a mode that needs the RF
5026            tuner, then select the right frequency choice as well and mark
5027            it dirty. */
5028         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5029                 hdw->freqSelector = 0;
5030                 hdw->freqDirty = !0;
5031         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5032                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5033                 hdw->freqSelector = 1;
5034                 hdw->freqDirty = !0;
5035         }
5036         return 0;
5037 }
5038
5039
5040 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5041                                unsigned int change_mask,
5042                                unsigned int change_val)
5043 {
5044         int ret = 0;
5045         unsigned int nv,m,idx;
5046         LOCK_TAKE(hdw->big_lock);
5047         do {
5048                 nv = hdw->input_allowed_mask & ~change_mask;
5049                 nv |= (change_val & change_mask);
5050                 nv &= hdw->input_avail_mask;
5051                 if (!nv) {
5052                         /* No legal modes left; return error instead. */
5053                         ret = -EPERM;
5054                         break;
5055                 }
5056                 hdw->input_allowed_mask = nv;
5057                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5058                         /* Current mode is still in the allowed mask, so
5059                            we're done. */
5060                         break;
5061                 }
5062                 /* Select and switch to a mode that is still in the allowed
5063                    mask */
5064                 if (!hdw->input_allowed_mask) {
5065                         /* Nothing legal; give up */
5066                         break;
5067                 }
5068                 m = hdw->input_allowed_mask;
5069                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5070                         if (!((1 << idx) & m)) continue;
5071                         pvr2_hdw_set_input(hdw,idx);
5072                         break;
5073                 }
5074         } while (0);
5075         LOCK_GIVE(hdw->big_lock);
5076         return ret;
5077 }
5078
5079
5080 /* Find I2C address of eeprom */
5081 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5082 {
5083         int result;
5084         LOCK_TAKE(hdw->ctl_lock); do {
5085                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5086                 result = pvr2_send_request(hdw,
5087                                            hdw->cmd_buffer,1,
5088                                            hdw->cmd_buffer,1);
5089                 if (result < 0) break;
5090                 result = hdw->cmd_buffer[0];
5091         } while(0); LOCK_GIVE(hdw->ctl_lock);
5092         return result;
5093 }