1 #define EM_GPIO_0 (1 << 0)
2 #define EM_GPIO_1 (1 << 1)
3 #define EM_GPIO_2 (1 << 2)
4 #define EM_GPIO_3 (1 << 3)
5 #define EM_GPIO_4 (1 << 4)
6 #define EM_GPIO_5 (1 << 5)
7 #define EM_GPIO_6 (1 << 6)
8 #define EM_GPIO_7 (1 << 7)
10 #define EM_GPO_0 (1 << 0)
11 #define EM_GPO_1 (1 << 1)
12 #define EM_GPO_2 (1 << 2)
13 #define EM_GPO_3 (1 << 3)
15 /* em28xx endpoints */
16 /* 0x82: (always ?) analog */
17 #define EM28XX_EP_AUDIO 0x83
18 /* 0x84: digital or analog */
20 /* em2800 registers */
21 #define EM2800_R08_AUDIOSRC 0x08
23 /* em28xx registers */
25 #define EM28XX_R00_CHIPCFG 0x00
27 /* em28xx Chip Configuration 0x00 */
28 #define EM28XX_CHIPCFG_VENDOR_AUDIO 0x80
29 #define EM28XX_CHIPCFG_I2S_VOLUME_CAPABLE 0x40
30 #define EM28XX_CHIPCFG_I2S_5_SAMPRATES 0x30
31 #define EM28XX_CHIPCFG_I2S_3_SAMPRATES 0x20
32 #define EM28XX_CHIPCFG_AC97 0x10
33 #define EM28XX_CHIPCFG_AUDIOMASK 0x30
35 #define EM28XX_R01_CHIPCFG2 0x01
37 /* em28xx Chip Configuration 2 0x01 */
38 #define EM28XX_CHIPCFG2_TS_PRESENT 0x10
39 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK 0x0c /* bits 3-2 */
40 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF 0x00
41 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF 0x04
42 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF 0x08
43 #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF 0x0c
44 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK 0x03 /* bits 0-1 */
45 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_188 0x00
46 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_376 0x01
47 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_564 0x02
48 #define EM28XX_CHIPCFG2_TS_PACKETSIZE_752 0x03
51 /* GPIO/GPO registers */
52 #define EM2880_R04_GPO 0x04 /* em2880-em2883 only */
53 #define EM2820_R08_GPIO_CTRL 0x08 /* em2820-em2873/83 only */
54 #define EM2820_R09_GPIO_STATE 0x09 /* em2820-em2873/83 only */
56 #define EM28XX_R06_I2C_CLK 0x06
58 /* em28xx I2C Clock Register (0x06) */
59 #define EM28XX_I2C_CLK_ACK_LAST_READ 0x80
60 #define EM28XX_I2C_CLK_WAIT_ENABLE 0x40
61 #define EM28XX_I2C_EEPROM_ON_BOARD 0x08
62 #define EM28XX_I2C_EEPROM_KEY_VALID 0x04
63 #define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c busses */
64 #define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */
65 #define EM28XX_I2C_FREQ_25_KHZ 0x02
66 #define EM28XX_I2C_FREQ_400_KHZ 0x01
67 #define EM28XX_I2C_FREQ_100_KHZ 0x00
70 #define EM28XX_R0A_CHIPID 0x0a
71 #define EM28XX_R0C_USBSUSP 0x0c
72 #define EM28XX_R0C_USBSUSP_SNAPSHOT 0x20 /* 1=button pressed, needs reset */
74 #define EM28XX_R0E_AUDIOSRC 0x0e
75 #define EM28XX_R0F_XCLK 0x0f
77 /* em28xx XCLK Register (0x0f) */
78 #define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */
79 #define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */
80 #define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */
81 #define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x10
82 #define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */
83 #define EM28XX_XCLK_FREQUENCY_15MHZ 0x01
84 #define EM28XX_XCLK_FREQUENCY_10MHZ 0x02
85 #define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x03
86 #define EM28XX_XCLK_FREQUENCY_6MHZ 0x04
87 #define EM28XX_XCLK_FREQUENCY_5MHZ 0x05
88 #define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x06
89 #define EM28XX_XCLK_FREQUENCY_12MHZ 0x07
90 #define EM28XX_XCLK_FREQUENCY_20MHZ 0x08
91 #define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x09
92 #define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a
93 #define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b
95 #define EM28XX_R10_VINMODE 0x10
97 #define EM28XX_R11_VINCTRL 0x11
99 /* em28xx Video Input Control Register 0x11 */
100 #define EM28XX_VINCTRL_VBI_SLICED 0x80
101 #define EM28XX_VINCTRL_VBI_RAW 0x40
102 #define EM28XX_VINCTRL_VOUT_MODE_IN 0x20 /* HREF,VREF,VACT in output */
103 #define EM28XX_VINCTRL_CCIR656_ENABLE 0x10
104 #define EM28XX_VINCTRL_VBI_16BIT_RAW 0x08 /* otherwise 8-bit raw */
105 #define EM28XX_VINCTRL_FID_ON_HREF 0x04
106 #define EM28XX_VINCTRL_DUAL_EDGE_STROBE 0x02
107 #define EM28XX_VINCTRL_INTERLACED 0x01
109 #define EM28XX_R12_VINENABLE 0x12 /* */
111 #define EM28XX_R14_GAMMA 0x14
112 #define EM28XX_R15_RGAIN 0x15
113 #define EM28XX_R16_GGAIN 0x16
114 #define EM28XX_R17_BGAIN 0x17
115 #define EM28XX_R18_ROFFSET 0x18
116 #define EM28XX_R19_GOFFSET 0x19
117 #define EM28XX_R1A_BOFFSET 0x1a
119 #define EM28XX_R1B_OFLOW 0x1b
120 #define EM28XX_R1C_HSTART 0x1c
121 #define EM28XX_R1D_VSTART 0x1d
122 #define EM28XX_R1E_CWIDTH 0x1e
123 #define EM28XX_R1F_CHEIGHT 0x1f
125 #define EM28XX_R20_YGAIN 0x20 /* contrast [0:4] */
126 #define CONTRAST_DEFAULT 0x10
128 #define EM28XX_R21_YOFFSET 0x21 /* brightness */ /* signed */
129 #define BRIGHTNESS_DEFAULT 0x00
131 #define EM28XX_R22_UVGAIN 0x22 /* saturation [0:4] */
132 #define SATURATION_DEFAULT 0x10
134 #define EM28XX_R23_UOFFSET 0x23 /* blue balance */ /* signed */
135 #define BLUE_BALANCE_DEFAULT 0x00
137 #define EM28XX_R24_VOFFSET 0x24 /* red balance */ /* signed */
138 #define RED_BALANCE_DEFAULT 0x00
140 #define EM28XX_R25_SHARPNESS 0x25 /* sharpness [0:4] */
141 #define SHARPNESS_DEFAULT 0x00
143 #define EM28XX_R26_COMPR 0x26
144 #define EM28XX_R27_OUTFMT 0x27
146 /* em28xx Output Format Register (0x27) */
147 #define EM28XX_OUTFMT_RGB_8_RGRG 0x00
148 #define EM28XX_OUTFMT_RGB_8_GRGR 0x01
149 #define EM28XX_OUTFMT_RGB_8_GBGB 0x02
150 #define EM28XX_OUTFMT_RGB_8_BGBG 0x03
151 #define EM28XX_OUTFMT_RGB_16_656 0x04
152 #define EM28XX_OUTFMT_RGB_8_BAYER 0x08 /* Pattern in Reg 0x10[1-0] */
153 #define EM28XX_OUTFMT_YUV211 0x10
154 #define EM28XX_OUTFMT_YUV422_Y0UY1V 0x14
155 #define EM28XX_OUTFMT_YUV422_Y1UY0V 0x15
156 #define EM28XX_OUTFMT_YUV411 0x18
159 #define EM28XX_R28_XMIN 0x28
160 #define EM28XX_R29_XMAX 0x29
161 #define EM28XX_R2A_YMIN 0x2a
162 #define EM28XX_R2B_YMAX 0x2b
164 #define EM28XX_R30_HSCALELOW 0x30
165 #define EM28XX_R31_HSCALEHIGH 0x31
166 #define EM28XX_R32_VSCALELOW 0x32
167 #define EM28XX_R33_VSCALEHIGH 0x33
168 #define EM28XX_HVSCALE_MAX 0x3fff /* => 20% */
170 #define EM28XX_R34_VBI_START_H 0x34
171 #define EM28XX_R35_VBI_START_V 0x35
173 * NOTE: the EM276x (and EM25xx, EM277x/8x ?) (camera bridges) use these
174 * registers for a different unknown purpose.
175 * => register 0x34 is set to capture width / 16
176 * => register 0x35 is set to capture height / 16
179 #define EM28XX_R36_VBI_WIDTH 0x36
180 #define EM28XX_R37_VBI_HEIGHT 0x37
182 #define EM28XX_R40_AC97LSB 0x40
183 #define EM28XX_R41_AC97MSB 0x41
184 #define EM28XX_R42_AC97ADDR 0x42
185 #define EM28XX_R43_AC97BUSY 0x43
187 #define EM28XX_R45_IR 0x45
188 /* 0x45 bit 7 - parity bit
194 /* em2874 registers */
195 #define EM2874_R50_IR_CONFIG 0x50
196 #define EM2874_R51_IR 0x51
197 #define EM2874_R5F_TS_ENABLE 0x5f
199 /* em2874/174/84, em25xx, em276x/7x/8x GPIO registers */
201 * NOTE: not all ports are bonded out;
202 * Some ports are multiplexed with special function I/O
204 #define EM2874_R80_GPIO_P0_CTRL 0x80
205 #define EM2874_R81_GPIO_P1_CTRL 0x81
206 #define EM2874_R82_GPIO_P2_CTRL 0x82
207 #define EM2874_R83_GPIO_P3_CTRL 0x83
208 #define EM2874_R84_GPIO_P0_STATE 0x84
209 #define EM2874_R85_GPIO_P1_STATE 0x85
210 #define EM2874_R86_GPIO_P2_STATE 0x86
211 #define EM2874_R87_GPIO_P3_STATE 0x87
213 /* em2874 IR config register (0x50) */
214 #define EM2874_IR_NEC 0x00
215 #define EM2874_IR_NEC_NO_PARITY 0x01
216 #define EM2874_IR_RC5 0x04
217 #define EM2874_IR_RC6_MODE_0 0x08
218 #define EM2874_IR_RC6_MODE_6A 0x0b
220 /* em2874 Transport Stream Enable Register (0x5f) */
221 #define EM2874_TS1_CAPTURE_ENABLE (1 << 0)
222 #define EM2874_TS1_FILTER_ENABLE (1 << 1)
223 #define EM2874_TS1_NULL_DISCARD (1 << 2)
224 #define EM2874_TS2_CAPTURE_ENABLE (1 << 4)
225 #define EM2874_TS2_FILTER_ENABLE (1 << 5)
226 #define EM2874_TS2_NULL_DISCARD (1 << 6)
228 /* register settings */
229 #define EM2800_AUDIO_SRC_TUNER 0x0d
230 #define EM2800_AUDIO_SRC_LINE 0x0c
231 #define EM28XX_AUDIO_SRC_TUNER 0xc0
232 #define EM28XX_AUDIO_SRC_LINE 0x80
234 /* FIXME: Need to be populated with the other chip ID's */
235 enum em28xx_chip_id {
238 CHIP_ID_EM2820 = 18, /* Also used by some em2710 */
247 CHIP_ID_EM28174 = 113,
251 * Registers used by em202
254 /* EMP202 vendor registers */
255 #define EM202_EXT_MODEM_CTRL 0x3e
256 #define EM202_GPIO_CONF 0x4c
257 #define EM202_GPIO_POLARITY 0x4e
258 #define EM202_GPIO_STICKY 0x50
259 #define EM202_GPIO_MASK 0x52
260 #define EM202_GPIO_STATUS 0x54
261 #define EM202_SPDIF_OUT_SEL 0x6a
262 #define EM202_ANTIPOP 0x72
263 #define EM202_EAPD_GPIO_ACCESS 0x74