drivers/media/usb/cx231xx/cx231xx-417.c

   1 /*
   2  *
   3  *  Support for a cx23417 mpeg encoder via cx231xx host port.
   4  *
   5  *    (c) 2004 Jelle Foks <jelle@foks.us>
   6  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
   7  *    (c) 2008 Steven Toth <stoth@linuxtv.org>
   8  *      - CX23885/7/8 support
   9  *
  10  *  Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
  11  *
  12  *  This program is free software; you can redistribute it and/or modify
  13  *  it under the terms of the GNU General Public License as published by
  14  *  the Free Software Foundation; either version 2 of the License, or
  15  *  (at your option) any later version.
  16  *
  17  *  This program is distributed in the hope that it will be useful,
  18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *  GNU General Public License for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License
  23  *  along with this program; if not, write to the Free Software
  24  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26
  27 #include "cx231xx.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/init.h>
  32 #include <linux/fs.h>
  33 #include <linux/delay.h>
  34 #include <linux/device.h>
  35 #include <linux/firmware.h>
  36 #include <linux/vmalloc.h>
  37 #include <media/v4l2-common.h>
  38 #include <media/v4l2-ioctl.h>
  39 #include <media/v4l2-event.h>
  40 #include <media/drv-intf/cx2341x.h>
  41 #include <media/tuner.h>
  42
  43 #define CX231xx_FIRM_IMAGE_SIZE 376836
  44 #define CX231xx_FIRM_IMAGE_NAME "/*(DEBLOBBED)*/"
  45
  46 /* for polaris ITVC */
  47 #define ITVC_WRITE_DIR          0x03FDFC00
  48 #define ITVC_READ_DIR            0x0001FC00
  49
  50 #define  MCI_MEMORY_DATA_BYTE0          0x00
  51 #define  MCI_MEMORY_DATA_BYTE1          0x08
  52 #define  MCI_MEMORY_DATA_BYTE2          0x10
  53 #define  MCI_MEMORY_DATA_BYTE3          0x18
  54
  55 #define  MCI_MEMORY_ADDRESS_BYTE2       0x20
  56 #define  MCI_MEMORY_ADDRESS_BYTE1       0x28
  57 #define  MCI_MEMORY_ADDRESS_BYTE0       0x30
  58
  59 #define  MCI_REGISTER_DATA_BYTE0        0x40
  60 #define  MCI_REGISTER_DATA_BYTE1        0x48
  61 #define  MCI_REGISTER_DATA_BYTE2        0x50
  62 #define  MCI_REGISTER_DATA_BYTE3        0x58
  63
  64 #define  MCI_REGISTER_ADDRESS_BYTE0     0x60
  65 #define  MCI_REGISTER_ADDRESS_BYTE1     0x68
  66
  67 #define  MCI_REGISTER_MODE              0x70
  68
  69 /* Read and write modes for polaris ITVC */
  70 #define  MCI_MODE_REGISTER_READ         0x000
  71 #define  MCI_MODE_REGISTER_WRITE        0x100
  72 #define  MCI_MODE_MEMORY_READ           0x000
  73 #define  MCI_MODE_MEMORY_WRITE          0x4000
  74
  75 static unsigned int mpegbufs = 8;
  76 module_param(mpegbufs, int, 0644);
  77 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
  78
  79 static unsigned int mpeglines = 128;
  80 module_param(mpeglines, int, 0644);
  81 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
  82
  83 static unsigned int mpeglinesize = 512;
  84 module_param(mpeglinesize, int, 0644);
  85 MODULE_PARM_DESC(mpeglinesize,
  86         "number of bytes in each line of an MPEG buffer, range 512-1024");
  87
  88 static unsigned int v4l_debug = 1;
  89 module_param(v4l_debug, int, 0644);
  90 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
  91
  92 #define dprintk(level, fmt, arg...)     \
  93         do {                            \
  94                 if (v4l_debug >= level) \
  95                         printk(KERN_DEBUG pr_fmt(fmt), ## arg); \
  96         } while (0)
  97
  98 static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
  99         {
 100                 .name      = "NTSC-M",
 101                 .id        = V4L2_STD_NTSC_M,
 102         }, {
 103                 .name      = "NTSC-JP",
 104                 .id        = V4L2_STD_NTSC_M_JP,
 105         }, {
 106                 .name      = "PAL-BG",
 107                 .id        = V4L2_STD_PAL_BG,
 108         }, {
 109                 .name      = "PAL-DK",
 110                 .id        = V4L2_STD_PAL_DK,
 111         }, {
 112                 .name      = "PAL-I",
 113                 .id        = V4L2_STD_PAL_I,
 114         }, {
 115                 .name      = "PAL-M",
 116                 .id        = V4L2_STD_PAL_M,
 117         }, {
 118                 .name      = "PAL-N",
 119                 .id        = V4L2_STD_PAL_N,
 120         }, {
 121                 .name      = "PAL-Nc",
 122                 .id        = V4L2_STD_PAL_Nc,
 123         }, {
 124                 .name      = "PAL-60",
 125                 .id        = V4L2_STD_PAL_60,
 126         }, {
 127                 .name      = "SECAM-L",
 128                 .id        = V4L2_STD_SECAM_L,
 129         }, {
 130                 .name      = "SECAM-DK",
 131                 .id        = V4L2_STD_SECAM_DK,
 132         }
 133 };
 134
 135 /* ------------------------------------------------------------------ */
 136
 137 enum cx231xx_capture_type {
 138         CX231xx_MPEG_CAPTURE,
 139         CX231xx_RAW_CAPTURE,
 140         CX231xx_RAW_PASSTHRU_CAPTURE
 141 };
 142
 143 enum cx231xx_capture_bits {
 144         CX231xx_RAW_BITS_NONE             = 0x00,
 145         CX231xx_RAW_BITS_YUV_CAPTURE      = 0x01,
 146         CX231xx_RAW_BITS_PCM_CAPTURE      = 0x02,
 147         CX231xx_RAW_BITS_VBI_CAPTURE      = 0x04,
 148         CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
 149         CX231xx_RAW_BITS_TO_HOST_CAPTURE  = 0x10
 150 };
 151
 152 enum cx231xx_capture_end {
 153         CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
 154         CX231xx_END_NOW, /* stop immediately, no irq */
 155 };
 156
 157 enum cx231xx_framerate {
 158         CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
 159         CX231xx_FRAMERATE_PAL_25   /* PAL: 25fps */
 160 };
 161
 162 enum cx231xx_stream_port {
 163         CX231xx_OUTPUT_PORT_MEMORY,
 164         CX231xx_OUTPUT_PORT_STREAMING,
 165         CX231xx_OUTPUT_PORT_SERIAL
 166 };
 167
 168 enum cx231xx_data_xfer_status {
 169         CX231xx_MORE_BUFFERS_FOLLOW,
 170         CX231xx_LAST_BUFFER,
 171 };
 172
 173 enum cx231xx_picture_mask {
 174         CX231xx_PICTURE_MASK_NONE,
 175         CX231xx_PICTURE_MASK_I_FRAMES,
 176         CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
 177         CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
 178 };
 179
 180 enum cx231xx_vbi_mode_bits {
 181         CX231xx_VBI_BITS_SLICED,
 182         CX231xx_VBI_BITS_RAW,
 183 };
 184
 185 enum cx231xx_vbi_insertion_bits {
 186         CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
 187         CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
 188         CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
 189         CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
 190         CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
 191 };
 192
 193 enum cx231xx_dma_unit {
 194         CX231xx_DMA_BYTES,
 195         CX231xx_DMA_FRAMES,
 196 };
 197
 198 enum cx231xx_dma_transfer_status_bits {
 199         CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
 200         CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
 201         CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
 202 };
 203
 204 enum cx231xx_pause {
 205         CX231xx_PAUSE_ENCODING,
 206         CX231xx_RESUME_ENCODING,
 207 };
 208
 209 enum cx231xx_copyright {
 210         CX231xx_COPYRIGHT_OFF,
 211         CX231xx_COPYRIGHT_ON,
 212 };
 213
 214 enum cx231xx_notification_type {
 215         CX231xx_NOTIFICATION_REFRESH,
 216 };
 217
 218 enum cx231xx_notification_status {
 219         CX231xx_NOTIFICATION_OFF,
 220         CX231xx_NOTIFICATION_ON,
 221 };
 222
 223 enum cx231xx_notification_mailbox {
 224         CX231xx_NOTIFICATION_NO_MAILBOX = -1,
 225 };
 226
 227 enum cx231xx_field1_lines {
 228         CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
 229         CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
 230         CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
 231 };
 232
 233 enum cx231xx_field2_lines {
 234         CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
 235         CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
 236         CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
 237 };
 238
 239 enum cx231xx_custom_data_type {
 240         CX231xx_CUSTOM_EXTENSION_USR_DATA,
 241         CX231xx_CUSTOM_PRIVATE_PACKET,
 242 };
 243
 244 enum cx231xx_mute {
 245         CX231xx_UNMUTE,
 246         CX231xx_MUTE,
 247 };
 248
 249 enum cx231xx_mute_video_mask {
 250         CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
 251         CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
 252         CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
 253 };
 254
 255 enum cx231xx_mute_video_shift {
 256         CX231xx_MUTE_VIDEO_V_SHIFT = 8,
 257         CX231xx_MUTE_VIDEO_U_SHIFT = 16,
 258         CX231xx_MUTE_VIDEO_Y_SHIFT = 24,
 259 };
 260
 261 /* defines below are from ivtv-driver.h */
 262 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
 263
 264 /* Firmware API commands */
 265 #define IVTV_API_STD_TIMEOUT 500
 266
 267 /* Registers */
 268 /* IVTV_REG_OFFSET */
 269 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
 270 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
 271 #define IVTV_REG_SPU (0x9050)
 272 #define IVTV_REG_HW_BLOCKS (0x9054)
 273 #define IVTV_REG_VPU (0x9058)
 274 #define IVTV_REG_APU (0xA064)
 275
 276 /*
 277  * Bit definitions for MC417_RWD and MC417_OEN registers
 278  *
 279  * bits 31-16
 280  *+-----------+
 281  *| Reserved  |
 282  *|+-----------+
 283  *|  bit 15  bit 14  bit 13 bit 12  bit 11  bit 10  bit 9   bit 8
 284  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 285  *|| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
 286  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 287  *| bit 7   bit 6   bit 5   bit 4   bit 3   bit 2   bit 1   bit 0
 288  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 289  *||MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
 290  *|+-------+-------+-------+-------+-------+-------+-------+-------+
 291  */
 292 #define MC417_MIWR      0x8000
 293 #define MC417_MIRD      0x4000
 294 #define MC417_MICS      0x2000
 295 #define MC417_MIRDY     0x1000
 296 #define MC417_MIADDR    0x0F00
 297 #define MC417_MIDATA    0x00FF
 298
 299
 300 /* Bit definitions for MC417_CTL register ****
 301  *bits 31-6   bits 5-4   bit 3    bits 2-1       Bit 0
 302  *+--------+-------------+--------+--------------+------------+
 303  *|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
 304  *+--------+-------------+--------+--------------+------------+
 305  */
 306 #define MC417_SPD_CTL(x)        (((x) << 4) & 0x00000030)
 307 #define MC417_GPIO_SEL(x)       (((x) << 1) & 0x00000006)
 308 #define MC417_UART_GPIO_EN      0x00000001
 309
 310 /* Values for speed control */
 311 #define MC417_SPD_CTL_SLOW      0x1
 312 #define MC417_SPD_CTL_MEDIUM    0x0
 313 #define MC417_SPD_CTL_FAST      0x3     /* b'1x, but we use b'11 */
 314
 315 /* Values for GPIO select */
 316 #define MC417_GPIO_SEL_GPIO3    0x3
 317 #define MC417_GPIO_SEL_GPIO2    0x2
 318 #define MC417_GPIO_SEL_GPIO1    0x1
 319 #define MC417_GPIO_SEL_GPIO0    0x0
 320
 321
 322 #define CX23417_GPIO_MASK 0xFC0003FF
 323
 324 static int set_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 value)
 325 {
 326         int status = 0;
 327         u32 _gpio_direction = 0;
 328
 329         _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
 330         _gpio_direction = _gpio_direction | gpio_direction;
 331         status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
 332                          (u8 *)&value, 4, 0, 0);
 333         return status;
 334 }
 335
 336 static int get_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 *val_ptr)
 337 {
 338         int status = 0;
 339         u32 _gpio_direction = 0;
 340
 341         _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
 342         _gpio_direction = _gpio_direction | gpio_direction;
 343
 344         status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
 345                  (u8 *)val_ptr, 4, 0, 1);
 346         return status;
 347 }
 348
 349 static int wait_for_mci_complete(struct cx231xx *dev)
 350 {
 351         u32 gpio;
 352         u32 gpio_direction = 0;
 353         u8 count = 0;
 354         get_itvc_reg(dev, gpio_direction, &gpio);
 355
 356         while (!(gpio&0x020000)) {
 357                 msleep(10);
 358
 359                 get_itvc_reg(dev, gpio_direction, &gpio);
 360
 361                 if (count++ > 100) {
 362                         dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
 363                         return -EIO;
 364                 }
 365         }
 366         return 0;
 367 }
 368
 369 static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
 370 {
 371         u32 temp;
 372         int status = 0;
 373
 374         temp = 0x82 | MCI_REGISTER_DATA_BYTE0 | ((value & 0x000000FF) << 8);
 375         temp = temp << 10;
 376         status = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 377         if (status < 0)
 378                 return status;
 379         temp = temp | (0x05 << 10);
 380         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 381
 382         /*write data byte 1;*/
 383         temp = 0x82 | MCI_REGISTER_DATA_BYTE1 | (value & 0x0000FF00);
 384         temp = temp << 10;
 385         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 386         temp = temp | (0x05 << 10);
 387         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 388
 389         /*write data byte 2;*/
 390         temp = 0x82 | MCI_REGISTER_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
 391         temp = temp << 10;
 392         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 393         temp = temp | (0x05 << 10);
 394         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 395
 396         /*write data byte 3;*/
 397         temp = 0x82 | MCI_REGISTER_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
 398         temp = temp << 10;
 399         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 400         temp = temp | (0x05 << 10);
 401         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 402
 403         /*write address byte 0;*/
 404         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x000000FF) << 8);
 405         temp = temp << 10;
 406         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 407         temp = temp | (0x05 << 10);
 408         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 409
 410         /*write address byte 1;*/
 411         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0x0000FF00);
 412         temp = temp << 10;
 413         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 414         temp = temp | (0x05 << 10);
 415         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 416
 417         /*Write that the mode is write.*/
 418         temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
 419         temp = temp << 10;
 420         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 421         temp = temp | (0x05 << 10);
 422         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 423
 424         return wait_for_mci_complete(dev);
 425 }
 426
 427 static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
 428 {
 429         /*write address byte 0;*/
 430         u32 temp;
 431         u32 return_value = 0;
 432         int ret = 0;
 433
 434         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
 435         temp = temp << 10;
 436         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 437         temp = temp | ((0x05) << 10);
 438         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 439
 440         /*write address byte 1;*/
 441         temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
 442         temp = temp << 10;
 443         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 444         temp = temp | ((0x05) << 10);
 445         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 446
 447         /*write that the mode is read;*/
 448         temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
 449         temp = temp << 10;
 450         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 451         temp = temp | ((0x05) << 10);
 452         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 453
 454         /*wait for the MIRDY line to be asserted ,
 455         signalling that the read is done;*/
 456         ret = wait_for_mci_complete(dev);
 457
 458         /*switch the DATA- GPIO to input mode;*/
 459
 460         /*Read data byte 0;*/
 461         temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
 462         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 463         temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
 464         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 465         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 466         return_value |= ((temp & 0x03FC0000) >> 18);
 467         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 468
 469         /* Read data byte 1;*/
 470         temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
 471         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 472         temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
 473         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 474         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 475
 476         return_value |= ((temp & 0x03FC0000) >> 10);
 477         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 478
 479         /*Read data byte 2;*/
 480         temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
 481         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 482         temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
 483         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 484         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 485         return_value |= ((temp & 0x03FC0000) >> 2);
 486         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 487
 488         /*Read data byte 3;*/
 489         temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
 490         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 491         temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
 492         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 493         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 494         return_value |= ((temp & 0x03FC0000) << 6);
 495         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 496
 497         *value  = return_value;
 498         return ret;
 499 }
 500
 501 static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
 502 {
 503         /*write data byte 0;*/
 504
 505         u32 temp;
 506         int ret = 0;
 507
 508         temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
 509         temp = temp << 10;
 510         ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 511         if (ret < 0)
 512                 return ret;
 513         temp = temp | (0x05 << 10);
 514         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 515
 516         /*write data byte 1;*/
 517         temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
 518         temp = temp << 10;
 519         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 520         temp = temp | (0x05 << 10);
 521         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 522
 523         /*write data byte 2;*/
 524         temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
 525         temp = temp << 10;
 526         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 527         temp = temp | (0x05 << 10);
 528         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 529
 530         /*write data byte 3;*/
 531         temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
 532         temp = temp << 10;
 533         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 534         temp = temp | (0x05 << 10);
 535         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 536
 537         /* write address byte 2;*/
 538         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
 539                 ((address & 0x003F0000) >> 8);
 540         temp = temp << 10;
 541         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 542         temp = temp | (0x05 << 10);
 543         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 544
 545         /* write address byte 1;*/
 546         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
 547         temp = temp << 10;
 548         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 549         temp = temp | (0x05 << 10);
 550         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 551
 552         /* write address byte 0;*/
 553         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
 554         temp = temp << 10;
 555         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 556         temp = temp | (0x05 << 10);
 557         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 558
 559         /*wait for MIRDY line;*/
 560         wait_for_mci_complete(dev);
 561
 562         return 0;
 563 }
 564
 565 static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
 566 {
 567         u32 temp = 0;
 568         u32 return_value = 0;
 569         int ret = 0;
 570
 571         /*write address byte 2;*/
 572         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
 573                 ((address & 0x003F0000) >> 8);
 574         temp = temp << 10;
 575         ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 576         if (ret < 0)
 577                 return ret;
 578         temp = temp | (0x05 << 10);
 579         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 580
 581         /*write address byte 1*/
 582         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
 583         temp = temp << 10;
 584         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 585         temp = temp | (0x05 << 10);
 586         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 587
 588         /*write address byte 0*/
 589         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
 590         temp = temp << 10;
 591         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 592         temp = temp | (0x05 << 10);
 593         set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
 594
 595         /*Wait for MIRDY line*/
 596         ret = wait_for_mci_complete(dev);
 597
 598
 599         /*Read data byte 3;*/
 600         temp = (0x82 | MCI_MEMORY_DATA_BYTE3) << 10;
 601         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 602         temp = ((0x81 | MCI_MEMORY_DATA_BYTE3) << 10);
 603         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 604         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 605         return_value |= ((temp & 0x03FC0000) << 6);
 606         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 607
 608         /*Read data byte 2;*/
 609         temp = (0x82 | MCI_MEMORY_DATA_BYTE2) << 10;
 610         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 611         temp = ((0x81 | MCI_MEMORY_DATA_BYTE2) << 10);
 612         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 613         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 614         return_value |= ((temp & 0x03FC0000) >> 2);
 615         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 616
 617         /* Read data byte 1;*/
 618         temp = (0x82 | MCI_MEMORY_DATA_BYTE1) << 10;
 619         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 620         temp = ((0x81 | MCI_MEMORY_DATA_BYTE1) << 10);
 621         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 622         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 623         return_value |= ((temp & 0x03FC0000) >> 10);
 624         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 625
 626         /*Read data byte 0;*/
 627         temp = (0x82 | MCI_MEMORY_DATA_BYTE0) << 10;
 628         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 629         temp = ((0x81 | MCI_MEMORY_DATA_BYTE0) << 10);
 630         set_itvc_reg(dev, ITVC_READ_DIR, temp);
 631         get_itvc_reg(dev, ITVC_READ_DIR, &temp);
 632         return_value |= ((temp & 0x03FC0000) >> 18);
 633         set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
 634
 635         *value  = return_value;
 636         return ret;
 637 }
 638
 639 /* ------------------------------------------------------------------ */
 640
 641 /* MPEG encoder API */
 642 static char *cmd_to_str(int cmd)
 643 {
 644         switch (cmd) {
 645         case CX2341X_ENC_PING_FW:
 646                 return "PING_FW";
 647         case CX2341X_ENC_START_CAPTURE:
 648                 return "START_CAPTURE";
 649         case CX2341X_ENC_STOP_CAPTURE:
 650                 return "STOP_CAPTURE";
 651         case CX2341X_ENC_SET_AUDIO_ID:
 652                 return "SET_AUDIO_ID";
 653         case CX2341X_ENC_SET_VIDEO_ID:
 654                 return "SET_VIDEO_ID";
 655         case CX2341X_ENC_SET_PCR_ID:
 656                 return "SET_PCR_PID";
 657         case CX2341X_ENC_SET_FRAME_RATE:
 658                 return "SET_FRAME_RATE";
 659         case CX2341X_ENC_SET_FRAME_SIZE:
 660                 return "SET_FRAME_SIZE";
 661         case CX2341X_ENC_SET_BIT_RATE:
 662                 return "SET_BIT_RATE";
 663         case CX2341X_ENC_SET_GOP_PROPERTIES:
 664                 return "SET_GOP_PROPERTIES";
 665         case CX2341X_ENC_SET_ASPECT_RATIO:
 666                 return "SET_ASPECT_RATIO";
 667         case CX2341X_ENC_SET_DNR_FILTER_MODE:
 668                 return "SET_DNR_FILTER_PROPS";
 669         case CX2341X_ENC_SET_DNR_FILTER_PROPS:
 670                 return "SET_DNR_FILTER_PROPS";
 671         case CX2341X_ENC_SET_CORING_LEVELS:
 672                 return "SET_CORING_LEVELS";
 673         case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
 674                 return "SET_SPATIAL_FILTER_TYPE";
 675         case CX2341X_ENC_SET_VBI_LINE:
 676                 return "SET_VBI_LINE";
 677         case CX2341X_ENC_SET_STREAM_TYPE:
 678                 return "SET_STREAM_TYPE";
 679         case CX2341X_ENC_SET_OUTPUT_PORT:
 680                 return "SET_OUTPUT_PORT";
 681         case CX2341X_ENC_SET_AUDIO_PROPERTIES:
 682                 return "SET_AUDIO_PROPERTIES";
 683         case CX2341X_ENC_HALT_FW:
 684                 return "HALT_FW";
 685         case CX2341X_ENC_GET_VERSION:
 686                 return "GET_VERSION";
 687         case CX2341X_ENC_SET_GOP_CLOSURE:
 688                 return "SET_GOP_CLOSURE";
 689         case CX2341X_ENC_GET_SEQ_END:
 690                 return "GET_SEQ_END";
 691         case CX2341X_ENC_SET_PGM_INDEX_INFO:
 692                 return "SET_PGM_INDEX_INFO";
 693         case CX2341X_ENC_SET_VBI_CONFIG:
 694                 return "SET_VBI_CONFIG";
 695         case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
 696                 return "SET_DMA_BLOCK_SIZE";
 697         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
 698                 return "GET_PREV_DMA_INFO_MB_10";
 699         case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
 700                 return "GET_PREV_DMA_INFO_MB_9";
 701         case CX2341X_ENC_SCHED_DMA_TO_HOST:
 702                 return "SCHED_DMA_TO_HOST";
 703         case CX2341X_ENC_INITIALIZE_INPUT:
 704                 return "INITIALIZE_INPUT";
 705         case CX2341X_ENC_SET_FRAME_DROP_RATE:
 706                 return "SET_FRAME_DROP_RATE";
 707         case CX2341X_ENC_PAUSE_ENCODER:
 708                 return "PAUSE_ENCODER";
 709         case CX2341X_ENC_REFRESH_INPUT:
 710                 return "REFRESH_INPUT";
 711         case CX2341X_ENC_SET_COPYRIGHT:
 712                 return "SET_COPYRIGHT";
 713         case CX2341X_ENC_SET_EVENT_NOTIFICATION:
 714                 return "SET_EVENT_NOTIFICATION";
 715         case CX2341X_ENC_SET_NUM_VSYNC_LINES:
 716                 return "SET_NUM_VSYNC_LINES";
 717         case CX2341X_ENC_SET_PLACEHOLDER:
 718                 return "SET_PLACEHOLDER";
 719         case CX2341X_ENC_MUTE_VIDEO:
 720                 return "MUTE_VIDEO";
 721         case CX2341X_ENC_MUTE_AUDIO:
 722                 return "MUTE_AUDIO";
 723         case CX2341X_ENC_MISC:
 724                 return "MISC";
 725         default:
 726                 return "UNKNOWN";
 727         }
 728 }
 729
 730 static int cx231xx_mbox_func(void *priv, u32 command, int in, int out,
 731                              u32 data[CX2341X_MBOX_MAX_DATA])
 732 {
 733         struct cx231xx *dev = priv;
 734         unsigned long timeout;
 735         u32 value, flag, retval = 0;
 736         int i;
 737
 738         dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
 739                 cmd_to_str(command));
 740
 741         /* this may not be 100% safe if we can't read any memory location
 742            without side effects */
 743         mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
 744         if (value != 0x12345678) {
 745                 dprintk(3, "Firmware and/or mailbox pointer not initialized or corrupted, signature = 0x%x, cmd = %s\n",
 746                         value, cmd_to_str(command));
 747                 return -EIO;
 748         }
 749
 750         /* This read looks at 32 bits, but flag is only 8 bits.
 751          * Seems we also bail if CMD or TIMEOUT bytes are set???
 752          */
 753         mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 754         if (flag) {
 755                 dprintk(3, "ERROR: Mailbox appears to be in use (%x), cmd = %s\n",
 756                                 flag, cmd_to_str(command));
 757                 return -EBUSY;
 758         }
 759
 760         flag |= 1; /* tell 'em we're working on it */
 761         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 762
 763         /* write command + args + fill remaining with zeros */
 764         /* command code */
 765         mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
 766         mc417_memory_write(dev, dev->cx23417_mailbox + 3,
 767                 IVTV_API_STD_TIMEOUT); /* timeout */
 768         for (i = 0; i < in; i++) {
 769                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
 770                 dprintk(3, "API Input %d = %d\n", i, data[i]);
 771         }
 772         for (; i < CX2341X_MBOX_MAX_DATA; i++)
 773                 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
 774
 775         flag |= 3; /* tell 'em we're done writing */
 776         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 777
 778         /* wait for firmware to handle the API command */
 779         timeout = jiffies + msecs_to_jiffies(10);
 780         for (;;) {
 781                 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
 782                 if (0 != (flag & 4))
 783                         break;
 784                 if (time_after(jiffies, timeout)) {
 785                         dprintk(3, "ERROR: API Mailbox timeout\n");
 786                         return -EIO;
 787                 }
 788                 udelay(10);
 789         }
 790
 791         /* read output values */
 792         for (i = 0; i < out; i++) {
 793                 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
 794                 dprintk(3, "API Output %d = %d\n", i, data[i]);
 795         }
 796
 797         mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
 798         dprintk(3, "API result = %d\n", retval);
 799
 800         flag = 0;
 801         mc417_memory_write(dev, dev->cx23417_mailbox, flag);
 802
 803         return 0;
 804 }
 805
 806 /* We don't need to call the API often, so using just one
 807  * mailbox will probably suffice
 808  */
 809 static int cx231xx_api_cmd(struct cx231xx *dev, u32 command,
 810                 u32 inputcnt, u32 outputcnt, ...)
 811 {
 812         u32 data[CX2341X_MBOX_MAX_DATA];
 813         va_list vargs;
 814         int i, err;
 815
 816         dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
 817
 818         va_start(vargs, outputcnt);
 819         for (i = 0; i < inputcnt; i++)
 820                 data[i] = va_arg(vargs, int);
 821
 822         err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
 823         for (i = 0; i < outputcnt; i++) {
 824                 int *vptr = va_arg(vargs, int *);
 825                 *vptr = data[i];
 826         }
 827         va_end(vargs);
 828
 829         return err;
 830 }
 831
 832
 833 static int cx231xx_find_mailbox(struct cx231xx *dev)
 834 {
 835         u32 signature[4] = {
 836                 0x12345678, 0x34567812, 0x56781234, 0x78123456
 837         };
 838         int signaturecnt = 0;
 839         u32 value;
 840         int i;
 841         int ret = 0;
 842
 843         dprintk(2, "%s()\n", __func__);
 844
 845         for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
 846                 ret = mc417_memory_read(dev, i, &value);
 847                 if (ret < 0)
 848                         return ret;
 849                 if (value == signature[signaturecnt])
 850                         signaturecnt++;
 851                 else
 852                         signaturecnt = 0;
 853                 if (4 == signaturecnt) {
 854                         dprintk(1, "Mailbox signature found at 0x%x\n", i + 1);
 855                         return i + 1;
 856                 }
 857         }
 858         dprintk(3, "Mailbox signature values not found!\n");
 859         return -EIO;
 860 }
 861
 862 static void mci_write_memory_to_gpio(struct cx231xx *dev, u32 address, u32 value,
 863                 u32 *p_fw_image)
 864 {
 865         u32 temp = 0;
 866         int i = 0;
 867
 868         temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
 869         temp = temp << 10;
 870         *p_fw_image = temp;
 871         p_fw_image++;
 872         temp = temp | (0x05 << 10);
 873         *p_fw_image = temp;
 874         p_fw_image++;
 875
 876         /*write data byte 1;*/
 877         temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
 878         temp = temp << 10;
 879         *p_fw_image = temp;
 880         p_fw_image++;
 881         temp = temp | (0x05 << 10);
 882         *p_fw_image = temp;
 883         p_fw_image++;
 884
 885         /*write data byte 2;*/
 886         temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
 887         temp = temp << 10;
 888         *p_fw_image = temp;
 889         p_fw_image++;
 890         temp = temp | (0x05 << 10);
 891         *p_fw_image = temp;
 892         p_fw_image++;
 893
 894         /*write data byte 3;*/
 895         temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
 896         temp = temp << 10;
 897         *p_fw_image = temp;
 898         p_fw_image++;
 899         temp = temp | (0x05 << 10);
 900         *p_fw_image = temp;
 901         p_fw_image++;
 902
 903         /* write address byte 2;*/
 904         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
 905                 ((address & 0x003F0000) >> 8);
 906         temp = temp << 10;
 907         *p_fw_image = temp;
 908         p_fw_image++;
 909         temp = temp | (0x05 << 10);
 910         *p_fw_image = temp;
 911         p_fw_image++;
 912
 913         /* write address byte 1;*/
 914         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
 915         temp = temp << 10;
 916         *p_fw_image = temp;
 917         p_fw_image++;
 918         temp = temp | (0x05 << 10);
 919         *p_fw_image = temp;
 920         p_fw_image++;
 921
 922         /* write address byte 0;*/
 923         temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
 924         temp = temp << 10;
 925         *p_fw_image = temp;
 926         p_fw_image++;
 927         temp = temp | (0x05 << 10);
 928         *p_fw_image = temp;
 929         p_fw_image++;
 930
 931         for (i = 0; i < 6; i++) {
 932                 *p_fw_image = 0xFFFFFFFF;
 933                 p_fw_image++;
 934         }
 935 }
 936
 937
 938 static int cx231xx_load_firmware(struct cx231xx *dev)
 939 {
 940         static const unsigned char magic[8] = {
 941                 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
 942         };
 943         const struct firmware *firmware;
 944         int i, retval = 0;
 945         u32 value = 0;
 946         u32 gpio_output = 0;
 947         /*u32 checksum = 0;*/
 948         /*u32 *dataptr;*/
 949         u32 transfer_size = 0;
 950         u32 fw_data = 0;
 951         u32 address = 0;
 952         /*u32 current_fw[800];*/
 953         u32 *p_current_fw, *p_fw;
 954         u32 *p_fw_data;
 955         int frame = 0;
 956         u16 _buffer_size = 4096;
 957         u8 *p_buffer;
 958
 959         p_current_fw = vmalloc(1884180 * 4);
 960         p_fw = p_current_fw;
 961         if (p_current_fw == NULL) {
 962                 dprintk(2, "FAIL!!!\n");
 963                 return -ENOMEM;
 964         }
 965
 966         p_buffer = vmalloc(4096);
 967         if (p_buffer == NULL) {
 968                 dprintk(2, "FAIL!!!\n");
 969                 vfree(p_current_fw);
 970                 return -ENOMEM;
 971         }
 972
 973         dprintk(2, "%s()\n", __func__);
 974
 975         /* Save GPIO settings before reset of APU */
 976         retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
 977         retval |= mc417_memory_read(dev, 0x900C, &value);
 978
 979         retval  = mc417_register_write(dev,
 980                 IVTV_REG_VPU, 0xFFFFFFED);
 981         retval |= mc417_register_write(dev,
 982                 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
 983         retval |= mc417_register_write(dev,
 984                 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
 985         retval |= mc417_register_write(dev,
 986                 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
 987         retval |= mc417_register_write(dev,
 988                 IVTV_REG_APU, 0);
 989
 990         if (retval != 0) {
 991                 dev_err(dev->dev,
 992                         "%s: Error with mc417_register_write\n", __func__);
 993                 vfree(p_current_fw);
 994                 vfree(p_buffer);
 995                 return retval;
 996         }
 997
 998         retval = reject_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
 999                                   dev->dev);
1000
1001         if (retval != 0) {
1002                 dev_err(dev->dev,
1003                         "ERROR: Hotplug firmware request failed (%s).\n",
1004                         CX231xx_FIRM_IMAGE_NAME);
1005                 dev_err(dev->dev,
1006                         "Please fix your hotplug setup, the board will not work without firmware loaded!\n");
1007                 vfree(p_current_fw);
1008                 vfree(p_buffer);
1009                 return retval;
1010         }
1011
1012         if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
1013                 dev_err(dev->dev,
1014                         "ERROR: Firmware size mismatch (have %zd, expected %d)\n",
1015                         firmware->size, CX231xx_FIRM_IMAGE_SIZE);
1016                 release_firmware(firmware);
1017                 vfree(p_current_fw);
1018                 vfree(p_buffer);
1019                 return -EINVAL;
1020         }
1021
1022         if (0 != memcmp(firmware->data, magic, 8)) {
1023                 dev_err(dev->dev,
1024                         "ERROR: Firmware magic mismatch, wrong file?\n");
1025                 release_firmware(firmware);
1026                 vfree(p_current_fw);
1027                 vfree(p_buffer);
1028                 return -EINVAL;
1029         }
1030
1031         initGPIO(dev);
1032
1033         /* transfer to the chip */
1034         dprintk(2, "Loading firmware to GPIO...\n");
1035         p_fw_data = (u32 *)firmware->data;
1036         dprintk(2, "firmware->size=%zd\n", firmware->size);
1037         for (transfer_size = 0; transfer_size < firmware->size;
1038                  transfer_size += 4) {
1039                 fw_data = *p_fw_data;
1040
1041                 mci_write_memory_to_gpio(dev, address, fw_data, p_current_fw);
1042                 address = address + 1;
1043                 p_current_fw += 20;
1044                 p_fw_data += 1;
1045         }
1046
1047         /*download the firmware by ep5-out*/
1048
1049         for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
1050              frame++) {
1051                 for (i = 0; i < _buffer_size; i++) {
1052                         *(p_buffer + i) = (u8)(*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x000000FF);
1053                         i++;
1054                         *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x0000FF00) >> 8);
1055                         i++;
1056                         *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0x00FF0000) >> 16);
1057                         i++;
1058                         *(p_buffer + i) = (u8)((*(p_fw + (frame * 128 * 8 + (i / 4))) & 0xFF000000) >> 24);
1059                 }
1060                 cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
1061         }
1062
1063         p_current_fw = p_fw;
1064         vfree(p_current_fw);
1065         p_current_fw = NULL;
1066         uninitGPIO(dev);
1067         release_firmware(firmware);
1068         dprintk(1, "Firmware upload successful.\n");
1069
1070         retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
1071                 IVTV_CMD_HW_BLOCKS_RST);
1072         if (retval < 0) {
1073                 dev_err(dev->dev,
1074                         "%s: Error with mc417_register_write\n",
1075                         __func__);
1076                 return retval;
1077         }
1078         /* F/W power up disturbs the GPIOs, restore state */
1079         retval |= mc417_register_write(dev, 0x9020, gpio_output);
1080         retval |= mc417_register_write(dev, 0x900C, value);
1081
1082         retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
1083         retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
1084
1085         if (retval < 0) {
1086                 dev_err(dev->dev,
1087                         "%s: Error with mc417_register_write\n",
1088                         __func__);
1089                 return retval;
1090         }
1091         return 0;
1092 }
1093
1094 static void cx231xx_417_check_encoder(struct cx231xx *dev)
1095 {
1096         u32 status, seq;
1097
1098         status = 0;
1099         seq = 0;
1100         cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1101         dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1102 }
1103
1104 static void cx231xx_codec_settings(struct cx231xx *dev)
1105 {
1106         dprintk(1, "%s()\n", __func__);
1107
1108         /* assign frame size */
1109         cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1110                                 dev->ts1.height, dev->ts1.width);
1111
1112         dev->mpeg_ctrl_handler.width = dev->ts1.width;
1113         dev->mpeg_ctrl_handler.height = dev->ts1.height;
1114
1115         cx2341x_handler_setup(&dev->mpeg_ctrl_handler);
1116
1117         cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1118         cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1119 }
1120
1121 static int cx231xx_initialize_codec(struct cx231xx *dev)
1122 {
1123         int version;
1124         int retval;
1125         u32 i;
1126         u32 val = 0;
1127
1128         dprintk(1, "%s()\n", __func__);
1129         cx231xx_disable656(dev);
1130         retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1131         if (retval < 0) {
1132                 dprintk(2, "%s: PING OK\n", __func__);
1133                 retval = cx231xx_load_firmware(dev);
1134                 if (retval < 0) {
1135                         dev_err(dev->dev,
1136                                 "%s: f/w load failed\n", __func__);
1137                         return retval;
1138                 }
1139                 retval = cx231xx_find_mailbox(dev);
1140                 if (retval < 0) {
1141                         dev_err(dev->dev, "%s: mailbox < 0, error\n",
1142                                 __func__);
1143                         return retval;
1144                 }
1145                 dev->cx23417_mailbox = retval;
1146                 retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1147                 if (retval < 0) {
1148                         dev_err(dev->dev,
1149                                 "ERROR: cx23417 firmware ping failed!\n");
1150                         return retval;
1151                 }
1152                 retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1153                         &version);
1154                 if (retval < 0) {
1155                         dev_err(dev->dev,
1156                                 "ERROR: cx23417 firmware get encoder: version failed!\n");
1157                         return retval;
1158                 }
1159                 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1160                 msleep(200);
1161         }
1162
1163         for (i = 0; i < 1; i++) {
1164                 retval = mc417_register_read(dev, 0x20f8, &val);
1165                 dprintk(3, "***before enable656() VIM Capture Lines = %d ***\n",
1166                                  val);
1167                 if (retval < 0)
1168                         return retval;
1169         }
1170
1171         cx231xx_enable656(dev);
1172
1173         /* stop mpeg capture */
1174         cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE, 3, 0, 1, 3, 4);
1175
1176         cx231xx_codec_settings(dev);
1177         msleep(60);
1178
1179 /*      cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1180                 CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1181         cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1182                 CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1183                 0, 0);
1184 */
1185
1186 #if 0
1187         /* TODO */
1188         u32 data[7];
1189
1190         /* Setup to capture VBI */
1191         data[0] = 0x0001BD00;
1192         data[1] = 1;          /* frames per interrupt */
1193         data[2] = 4;          /* total bufs */
1194         data[3] = 0x91559155; /* start codes */
1195         data[4] = 0x206080C0; /* stop codes */
1196         data[5] = 6;          /* lines */
1197         data[6] = 64;         /* BPL */
1198
1199         cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1200                 data[2], data[3], data[4], data[5], data[6]);
1201
1202         for (i = 2; i <= 24; i++) {
1203                 int valid;
1204
1205                 valid = ((i >= 19) && (i <= 21));
1206                 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1207                                 valid, 0 , 0, 0);
1208                 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1209                                 i | 0x80000000, valid, 0, 0, 0);
1210         }
1211 #endif
1212 /*      cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1213         msleep(60);
1214 */
1215         /* initialize the video input */
1216         retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1217         if (retval < 0)
1218                 return retval;
1219         msleep(60);
1220
1221         /* Enable VIP style pixel invalidation so we work with scaled mode */
1222         mc417_memory_write(dev, 2120, 0x00000080);
1223
1224         /* start capturing to the host interface */
1225         retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1226                 CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE);
1227         if (retval < 0)
1228                 return retval;
1229         msleep(10);
1230
1231         for (i = 0; i < 1; i++) {
1232                 mc417_register_read(dev, 0x20f8, &val);
1233                 dprintk(3, "***VIM Capture Lines =%d ***\n", val);
1234         }
1235
1236         return 0;
1237 }
1238
1239 /* ------------------------------------------------------------------ */
1240
1241 static int bb_buf_setup(struct videobuf_queue *q,
1242         unsigned int *count, unsigned int *size)
1243 {
1244         struct cx231xx_fh *fh = q->priv_data;
1245
1246         fh->dev->ts1.ts_packet_size  = mpeglinesize;
1247         fh->dev->ts1.ts_packet_count = mpeglines;
1248
1249         *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1250         *count = mpegbufs;
1251
1252         return 0;
1253 }
1254
1255 static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
1256 {
1257         struct cx231xx_fh *fh = vq->priv_data;
1258         struct cx231xx *dev = fh->dev;
1259         unsigned long flags = 0;
1260
1261         BUG_ON(in_interrupt());
1262
1263         spin_lock_irqsave(&dev->video_mode.slock, flags);
1264         if (dev->USE_ISO) {
1265                 if (dev->video_mode.isoc_ctl.buf == buf)
1266                         dev->video_mode.isoc_ctl.buf = NULL;
1267         } else {
1268                 if (dev->video_mode.bulk_ctl.buf == buf)
1269                         dev->video_mode.bulk_ctl.buf = NULL;
1270         }
1271         spin_unlock_irqrestore(&dev->video_mode.slock, flags);
1272         videobuf_waiton(vq, &buf->vb, 0, 0);
1273         videobuf_vmalloc_free(&buf->vb);
1274         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1275 }
1276
1277 static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
1278                 struct cx231xx_dmaqueue *dma_q)
1279 {
1280         void *vbuf;
1281         struct cx231xx_buffer *buf;
1282         u32 tail_data = 0;
1283         char *p_data;
1284
1285         if (dma_q->mpeg_buffer_done == 0) {
1286                 if (list_empty(&dma_q->active))
1287                         return;
1288
1289                 buf = list_entry(dma_q->active.next,
1290                                 struct cx231xx_buffer, vb.queue);
1291                 dev->video_mode.isoc_ctl.buf = buf;
1292                 dma_q->mpeg_buffer_done = 1;
1293         }
1294         /* Fill buffer */
1295         buf = dev->video_mode.isoc_ctl.buf;
1296         vbuf = videobuf_to_vmalloc(&buf->vb);
1297
1298         if ((dma_q->mpeg_buffer_completed+len) <
1299                         mpeglines*mpeglinesize) {
1300                 if (dma_q->add_ps_package_head ==
1301                                 CX231XX_NEED_ADD_PS_PACKAGE_HEAD) {
1302                         memcpy(vbuf+dma_q->mpeg_buffer_completed,
1303                                         dma_q->ps_head, 3);
1304                         dma_q->mpeg_buffer_completed =
1305                                 dma_q->mpeg_buffer_completed + 3;
1306                         dma_q->add_ps_package_head =
1307                                 CX231XX_NONEED_PS_PACKAGE_HEAD;
1308                 }
1309                 memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
1310                 dma_q->mpeg_buffer_completed =
1311                         dma_q->mpeg_buffer_completed + len;
1312         } else {
1313                 dma_q->mpeg_buffer_done = 0;
1314
1315                 tail_data =
1316                         mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
1317                 memcpy(vbuf+dma_q->mpeg_buffer_completed,
1318                                 data, tail_data);
1319
1320                 buf->vb.state = VIDEOBUF_DONE;
1321                 buf->vb.field_count++;
1322                 v4l2_get_timestamp(&buf->vb.ts);
1323                 list_del(&buf->vb.queue);
1324                 wake_up(&buf->vb.done);
1325                 dma_q->mpeg_buffer_completed = 0;
1326
1327                 if (len - tail_data > 0) {
1328                         p_data = data + tail_data;
1329                         dma_q->left_data_count = len - tail_data;
1330                         memcpy(dma_q->p_left_data,
1331                                         p_data, len - tail_data);
1332                 }
1333         }
1334 }
1335
1336 static void buffer_filled(char *data, int len, struct urb *urb,
1337                 struct cx231xx_dmaqueue *dma_q)
1338 {
1339         void *vbuf;
1340         struct cx231xx_buffer *buf;
1341
1342         if (list_empty(&dma_q->active))
1343                 return;
1344
1345         buf = list_entry(dma_q->active.next,
1346                         struct cx231xx_buffer, vb.queue);
1347
1348         /* Fill buffer */
1349         vbuf = videobuf_to_vmalloc(&buf->vb);
1350         memcpy(vbuf, data, len);
1351         buf->vb.state = VIDEOBUF_DONE;
1352         buf->vb.field_count++;
1353         v4l2_get_timestamp(&buf->vb.ts);
1354         list_del(&buf->vb.queue);
1355         wake_up(&buf->vb.done);
1356 }
1357
1358 static int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
1359 {
1360         struct cx231xx_dmaqueue *dma_q = urb->context;
1361         unsigned char *p_buffer;
1362         u32 buffer_size = 0;
1363         u32 i = 0;
1364
1365         for (i = 0; i < urb->number_of_packets; i++) {
1366                 if (dma_q->left_data_count > 0) {
1367                         buffer_copy(dev, dma_q->p_left_data,
1368                                     dma_q->left_data_count, urb, dma_q);
1369                         dma_q->mpeg_buffer_completed = dma_q->left_data_count;
1370                         dma_q->left_data_count = 0;
1371                 }
1372
1373                 p_buffer = urb->transfer_buffer +
1374                                 urb->iso_frame_desc[i].offset;
1375                 buffer_size = urb->iso_frame_desc[i].actual_length;
1376
1377                 if (buffer_size > 0)
1378                         buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
1379         }
1380
1381         return 0;
1382 }
1383
1384 static int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
1385 {
1386         struct cx231xx_dmaqueue *dma_q = urb->context;
1387         unsigned char *p_buffer, *buffer;
1388         u32 buffer_size = 0;
1389
1390         p_buffer = urb->transfer_buffer;
1391         buffer_size = urb->actual_length;
1392
1393         buffer = kmalloc(buffer_size, GFP_ATOMIC);
1394         if (!buffer)
1395                 return -ENOMEM;
1396
1397         memcpy(buffer, dma_q->ps_head, 3);
1398         memcpy(buffer+3, p_buffer, buffer_size-3);
1399         memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
1400
1401         p_buffer = buffer;
1402         buffer_filled(p_buffer, buffer_size, urb, dma_q);
1403
1404         kfree(buffer);
1405         return 0;
1406 }
1407
1408 static int bb_buf_prepare(struct videobuf_queue *q,
1409         struct videobuf_buffer *vb, enum v4l2_field field)
1410 {
1411         struct cx231xx_fh *fh = q->priv_data;
1412         struct cx231xx_buffer *buf =
1413             container_of(vb, struct cx231xx_buffer, vb);
1414         struct cx231xx *dev = fh->dev;
1415         int rc = 0, urb_init = 0;
1416         int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1417
1418         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1419                 return -EINVAL;
1420         buf->vb.width = fh->dev->ts1.ts_packet_size;
1421         buf->vb.height = fh->dev->ts1.ts_packet_count;
1422         buf->vb.size = size;
1423         buf->vb.field = field;
1424
1425         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1426                 rc = videobuf_iolock(q, &buf->vb, NULL);
1427                 if (rc < 0)
1428                         goto fail;
1429         }
1430
1431         if (dev->USE_ISO) {
1432                 if (!dev->video_mode.isoc_ctl.num_bufs)
1433                         urb_init = 1;
1434         } else {
1435                 if (!dev->video_mode.bulk_ctl.num_bufs)
1436                         urb_init = 1;
1437         }
1438         dev_dbg(dev->dev,
1439                 "urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1440                 urb_init, dev->video_mode.max_pkt_size);
1441         dev->mode_tv = 1;
1442
1443         if (urb_init) {
1444                 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1445                 rc = cx231xx_unmute_audio(dev);
1446                 if (dev->USE_ISO) {
1447                         cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
1448                         rc = cx231xx_init_isoc(dev, mpeglines,
1449                                        mpegbufs,
1450                                        dev->ts1_mode.max_pkt_size,
1451                                        cx231xx_isoc_copy);
1452                 } else {
1453                         cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1454                         rc = cx231xx_init_bulk(dev, mpeglines,
1455                                        mpegbufs,
1456                                        dev->ts1_mode.max_pkt_size,
1457                                        cx231xx_bulk_copy);
1458                 }
1459                 if (rc < 0)
1460                         goto fail;
1461         }
1462
1463         buf->vb.state = VIDEOBUF_PREPARED;
1464         return 0;
1465
1466 fail:
1467         free_buffer(q, buf);
1468         return rc;
1469 }
1470
1471 static void bb_buf_queue(struct videobuf_queue *q,
1472         struct videobuf_buffer *vb)
1473 {
1474         struct cx231xx_fh *fh = q->priv_data;
1475
1476         struct cx231xx_buffer *buf =
1477             container_of(vb, struct cx231xx_buffer, vb);
1478         struct cx231xx *dev = fh->dev;
1479         struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
1480
1481         buf->vb.state = VIDEOBUF_QUEUED;
1482         list_add_tail(&buf->vb.queue, &vidq->active);
1483
1484 }
1485
1486 static void bb_buf_release(struct videobuf_queue *q,
1487         struct videobuf_buffer *vb)
1488 {
1489         struct cx231xx_buffer *buf =
1490             container_of(vb, struct cx231xx_buffer, vb);
1491         /*struct cx231xx_fh *fh = q->priv_data;*/
1492         /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1493
1494         free_buffer(q, buf);
1495 }
1496
1497 static struct videobuf_queue_ops cx231xx_qops = {
1498         .buf_setup    = bb_buf_setup,
1499         .buf_prepare  = bb_buf_prepare,
1500         .buf_queue    = bb_buf_queue,
1501         .buf_release  = bb_buf_release,
1502 };
1503
1504 /* ------------------------------------------------------------------ */
1505
1506 static int vidioc_cropcap(struct file *file, void *priv,
1507                           struct v4l2_cropcap *cc)
1508 {
1509         struct cx231xx_fh *fh = priv;
1510         struct cx231xx *dev = fh->dev;
1511         bool is_50hz = dev->encodernorm.id & V4L2_STD_625_50;
1512
1513         if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1514                 return -EINVAL;
1515
1516         cc->bounds.left = 0;
1517         cc->bounds.top = 0;
1518         cc->bounds.width = dev->ts1.width;
1519         cc->bounds.height = dev->ts1.height;
1520         cc->defrect = cc->bounds;
1521         cc->pixelaspect.numerator = is_50hz ? 54 : 11;
1522         cc->pixelaspect.denominator = is_50hz ? 59 : 10;
1523
1524         return 0;
1525 }
1526
1527 static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
1528 {
1529         struct cx231xx_fh  *fh  = file->private_data;
1530         struct cx231xx *dev = fh->dev;
1531
1532         *norm = dev->encodernorm.id;
1533         return 0;
1534 }
1535
1536 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id id)
1537 {
1538         struct cx231xx_fh  *fh  = file->private_data;
1539         struct cx231xx *dev = fh->dev;
1540         unsigned int i;
1541
1542         for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
1543                 if (id & cx231xx_tvnorms[i].id)
1544                         break;
1545         if (i == ARRAY_SIZE(cx231xx_tvnorms))
1546                 return -EINVAL;
1547         dev->encodernorm = cx231xx_tvnorms[i];
1548
1549         if (dev->encodernorm.id & 0xb000) {
1550                 dprintk(3, "encodernorm set to NTSC\n");
1551                 dev->norm = V4L2_STD_NTSC;
1552                 dev->ts1.height = 480;
1553                 cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false);
1554         } else {
1555                 dprintk(3, "encodernorm set to PAL\n");
1556                 dev->norm = V4L2_STD_PAL_B;
1557                 dev->ts1.height = 576;
1558                 cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, true);
1559         }
1560         call_all(dev, video, s_std, dev->norm);
1561         /* do mode control overrides */
1562         cx231xx_do_mode_ctrl_overrides(dev);
1563
1564         dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
1565         return 0;
1566 }
1567
1568 static int vidioc_s_ctrl(struct file *file, void *priv,
1569                                 struct v4l2_control *ctl)
1570 {
1571         struct cx231xx_fh  *fh  = file->private_data;
1572         struct cx231xx *dev = fh->dev;
1573         struct v4l2_subdev *sd;
1574
1575         dprintk(3, "enter vidioc_s_ctrl()\n");
1576         /* Update the A/V core */
1577         v4l2_device_for_each_subdev(sd, &dev->v4l2_dev)
1578                 v4l2_s_ctrl(NULL, sd->ctrl_handler, ctl);
1579         dprintk(3, "exit vidioc_s_ctrl()\n");
1580         return 0;
1581 }
1582
1583 static int vidioc_enum_fmt_vid_cap(struct file *file, void  *priv,
1584                                         struct v4l2_fmtdesc *f)
1585 {
1586         if (f->index != 0)
1587                 return -EINVAL;
1588
1589         strlcpy(f->description, "MPEG", sizeof(f->description));
1590         f->pixelformat = V4L2_PIX_FMT_MPEG;
1591
1592         return 0;
1593 }
1594
1595 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1596                                 struct v4l2_format *f)
1597 {
1598         struct cx231xx_fh  *fh  = file->private_data;
1599         struct cx231xx *dev = fh->dev;
1600
1601         dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1602         f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1603         f->fmt.pix.bytesperline = 0;
1604         f->fmt.pix.sizeimage = mpeglines * mpeglinesize;
1605         f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
1606         f->fmt.pix.width = dev->ts1.width;
1607         f->fmt.pix.height = dev->ts1.height;
1608         f->fmt.pix.field = V4L2_FIELD_INTERLACED;
1609         dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d\n",
1610                 dev->ts1.width, dev->ts1.height);
1611         dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1612         return 0;
1613 }
1614
1615 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1616                                 struct v4l2_format *f)
1617 {
1618         struct cx231xx_fh  *fh  = file->private_data;
1619         struct cx231xx *dev = fh->dev;
1620
1621         dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1622         f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1623         f->fmt.pix.bytesperline = 0;
1624         f->fmt.pix.sizeimage = mpeglines * mpeglinesize;
1625         f->fmt.pix.field = V4L2_FIELD_INTERLACED;
1626         f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
1627         dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d\n",
1628                 dev->ts1.width, dev->ts1.height);
1629         dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1630         return 0;
1631 }
1632
1633 static int vidioc_reqbufs(struct file *file, void *priv,
1634                                 struct v4l2_requestbuffers *p)
1635 {
1636         struct cx231xx_fh  *fh  = file->private_data;
1637
1638         return videobuf_reqbufs(&fh->vidq, p);
1639 }
1640
1641 static int vidioc_querybuf(struct file *file, void *priv,
1642                                 struct v4l2_buffer *p)
1643 {
1644         struct cx231xx_fh  *fh  = file->private_data;
1645
1646         return videobuf_querybuf(&fh->vidq, p);
1647 }
1648
1649 static int vidioc_qbuf(struct file *file, void *priv,
1650                                 struct v4l2_buffer *p)
1651 {
1652         struct cx231xx_fh  *fh  = file->private_data;
1653
1654         return videobuf_qbuf(&fh->vidq, p);
1655 }
1656
1657 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1658 {
1659         struct cx231xx_fh  *fh  = priv;
1660
1661         return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
1662 }
1663
1664
1665 static int vidioc_streamon(struct file *file, void *priv,
1666                                 enum v4l2_buf_type i)
1667 {
1668         struct cx231xx_fh  *fh  = file->private_data;
1669         struct cx231xx *dev = fh->dev;
1670
1671         dprintk(3, "enter vidioc_streamon()\n");
1672         cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1673         cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1674         if (dev->USE_ISO)
1675                 cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
1676                                 CX231XX_NUM_BUFS,
1677                                 dev->video_mode.max_pkt_size,
1678                                 cx231xx_isoc_copy);
1679         else {
1680                 cx231xx_init_bulk(dev, 320,
1681                                 5,
1682                                 dev->ts1_mode.max_pkt_size,
1683                                 cx231xx_bulk_copy);
1684         }
1685         dprintk(3, "exit vidioc_streamon()\n");
1686         return videobuf_streamon(&fh->vidq);
1687 }
1688
1689 static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1690 {
1691         struct cx231xx_fh  *fh  = file->private_data;
1692
1693         return videobuf_streamoff(&fh->vidq);
1694 }
1695
1696 static int vidioc_log_status(struct file *file, void *priv)
1697 {
1698         struct cx231xx_fh  *fh  = priv;
1699         struct cx231xx *dev = fh->dev;
1700
1701         call_all(dev, core, log_status);
1702         return v4l2_ctrl_log_status(file, priv);
1703 }
1704
1705 static int mpeg_open(struct file *file)
1706 {
1707         struct video_device *vdev = video_devdata(file);
1708         struct cx231xx *dev = video_drvdata(file);
1709         struct cx231xx_fh *fh;
1710
1711         dprintk(2, "%s()\n", __func__);
1712
1713         if (mutex_lock_interruptible(&dev->lock))
1714                 return -ERESTARTSYS;
1715
1716         /* allocate + initialize per filehandle data */
1717         fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1718         if (NULL == fh) {
1719                 mutex_unlock(&dev->lock);
1720                 return -ENOMEM;
1721         }
1722
1723         file->private_data = fh;
1724         v4l2_fh_init(&fh->fh, vdev);
1725         fh->dev = dev;
1726
1727
1728         videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
1729                             NULL, &dev->video_mode.slock,
1730                             V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED,
1731                             sizeof(struct cx231xx_buffer), fh, &dev->lock);
1732 /*
1733         videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1734                             dev->dev, &dev->ts1.slock,
1735                             V4L2_BUF_TYPE_VIDEO_CAPTURE,
1736                             V4L2_FIELD_INTERLACED,
1737                             sizeof(struct cx231xx_buffer),
1738                             fh, &dev->lock);
1739 */
1740
1741         cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
1742         cx231xx_set_gpio_value(dev, 2, 0);
1743
1744         cx231xx_initialize_codec(dev);
1745
1746         mutex_unlock(&dev->lock);
1747         v4l2_fh_add(&fh->fh);
1748         cx231xx_start_TS1(dev);
1749
1750         return 0;
1751 }
1752
1753 static int mpeg_release(struct file *file)
1754 {
1755         struct cx231xx_fh  *fh  = file->private_data;
1756         struct cx231xx *dev = fh->dev;
1757
1758         dprintk(3, "mpeg_release()! dev=0x%p\n", dev);
1759
1760         mutex_lock(&dev->lock);
1761
1762         cx231xx_stop_TS1(dev);
1763
1764         /* do this before setting alternate! */
1765         if (dev->USE_ISO)
1766                 cx231xx_uninit_isoc(dev);
1767         else
1768                 cx231xx_uninit_bulk(dev);
1769         cx231xx_set_mode(dev, CX231XX_SUSPEND);
1770
1771         cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1772                         CX231xx_END_NOW, CX231xx_MPEG_CAPTURE,
1773                         CX231xx_RAW_BITS_NONE);
1774
1775         /* FIXME: Review this crap */
1776         /* Shut device down on last close */
1777         if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1778                 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1779                         /* stop mpeg capture */
1780
1781                         msleep(500);
1782                         cx231xx_417_check_encoder(dev);
1783
1784                 }
1785         }
1786
1787         if (fh->vidq.streaming)
1788                 videobuf_streamoff(&fh->vidq);
1789         if (fh->vidq.reading)
1790                 videobuf_read_stop(&fh->vidq);
1791
1792         videobuf_mmap_free(&fh->vidq);
1793         v4l2_fh_del(&fh->fh);
1794         v4l2_fh_exit(&fh->fh);
1795         kfree(fh);
1796         mutex_unlock(&dev->lock);
1797         return 0;
1798 }
1799
1800 static ssize_t mpeg_read(struct file *file, char __user *data,
1801         size_t count, loff_t *ppos)
1802 {
1803         struct cx231xx_fh *fh = file->private_data;
1804         struct cx231xx *dev = fh->dev;
1805
1806         /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1807         /* Start mpeg encoder on first read. */
1808         if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1809                 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1810                         if (cx231xx_initialize_codec(dev) < 0)
1811                                 return -EINVAL;
1812                 }
1813         }
1814
1815         return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
1816                                     file->f_flags & O_NONBLOCK);
1817 }
1818
1819 static unsigned int mpeg_poll(struct file *file,
1820         struct poll_table_struct *wait)
1821 {
1822         unsigned long req_events = poll_requested_events(wait);
1823         struct cx231xx_fh *fh = file->private_data;
1824         struct cx231xx *dev = fh->dev;
1825         unsigned int res = 0;
1826
1827         if (v4l2_event_pending(&fh->fh))
1828                 res |= POLLPRI;
1829         else
1830                 poll_wait(file, &fh->fh.wait, wait);
1831
1832         if (!(req_events & (POLLIN | POLLRDNORM)))
1833                 return res;
1834
1835         mutex_lock(&dev->lock);
1836         res |= videobuf_poll_stream(file, &fh->vidq, wait);
1837         mutex_unlock(&dev->lock);
1838         return res;
1839 }
1840
1841 static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1842 {
1843         struct cx231xx_fh *fh = file->private_data;
1844
1845         dprintk(2, "%s()\n", __func__);
1846
1847         return videobuf_mmap_mapper(&fh->vidq, vma);
1848 }
1849
1850 static struct v4l2_file_operations mpeg_fops = {
1851         .owner         = THIS_MODULE,
1852         .open          = mpeg_open,
1853         .release       = mpeg_release,
1854         .read          = mpeg_read,
1855         .poll          = mpeg_poll,
1856         .mmap          = mpeg_mmap,
1857         .unlocked_ioctl = video_ioctl2,
1858 };
1859
1860 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
1861         .vidioc_s_std            = vidioc_s_std,
1862         .vidioc_g_std            = vidioc_g_std,
1863         .vidioc_g_tuner          = cx231xx_g_tuner,
1864         .vidioc_s_tuner          = cx231xx_s_tuner,
1865         .vidioc_g_frequency      = cx231xx_g_frequency,
1866         .vidioc_s_frequency      = cx231xx_s_frequency,
1867         .vidioc_enum_input       = cx231xx_enum_input,
1868         .vidioc_g_input          = cx231xx_g_input,
1869         .vidioc_s_input          = cx231xx_s_input,
1870         .vidioc_s_ctrl           = vidioc_s_ctrl,
1871         .vidioc_cropcap          = vidioc_cropcap,
1872         .vidioc_querycap         = cx231xx_querycap,
1873         .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1874         .vidioc_g_fmt_vid_cap    = vidioc_g_fmt_vid_cap,
1875         .vidioc_try_fmt_vid_cap  = vidioc_try_fmt_vid_cap,
1876         .vidioc_s_fmt_vid_cap    = vidioc_try_fmt_vid_cap,
1877         .vidioc_reqbufs          = vidioc_reqbufs,
1878         .vidioc_querybuf         = vidioc_querybuf,
1879         .vidioc_qbuf             = vidioc_qbuf,
1880         .vidioc_dqbuf            = vidioc_dqbuf,
1881         .vidioc_streamon         = vidioc_streamon,
1882         .vidioc_streamoff        = vidioc_streamoff,
1883         .vidioc_log_status       = vidioc_log_status,
1884 #ifdef CONFIG_VIDEO_ADV_DEBUG
1885         .vidioc_g_register       = cx231xx_g_register,
1886         .vidioc_s_register       = cx231xx_s_register,
1887 #endif
1888         .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1889         .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1890 };
1891
1892 static struct video_device cx231xx_mpeg_template = {
1893         .name          = "cx231xx",
1894         .fops          = &mpeg_fops,
1895         .ioctl_ops     = &mpeg_ioctl_ops,
1896         .minor         = -1,
1897         .tvnorms       = V4L2_STD_ALL,
1898 };
1899
1900 void cx231xx_417_unregister(struct cx231xx *dev)
1901 {
1902         dprintk(1, "%s()\n", __func__);
1903         dprintk(3, "%s()\n", __func__);
1904
1905         if (video_is_registered(&dev->v4l_device)) {
1906                 video_unregister_device(&dev->v4l_device);
1907                 v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
1908         }
1909 }
1910
1911 static int cx231xx_s_video_encoding(struct cx2341x_handler *cxhdl, u32 val)
1912 {
1913         struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler);
1914         int is_mpeg1 = val == V4L2_MPEG_VIDEO_ENCODING_MPEG_1;
1915         struct v4l2_subdev_format format = {
1916                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1917         };
1918
1919         /* fix videodecoder resolution */
1920         format.format.width = cxhdl->width / (is_mpeg1 ? 2 : 1);
1921         format.format.height = cxhdl->height;
1922         format.format.code = MEDIA_BUS_FMT_FIXED;
1923         v4l2_subdev_call(dev->sd_cx25840, pad, set_fmt, NULL, &format);
1924         return 0;
1925 }
1926
1927 static int cx231xx_s_audio_sampling_freq(struct cx2341x_handler *cxhdl, u32 idx)
1928 {
1929         static const u32 freqs[3] = { 44100, 48000, 32000 };
1930         struct cx231xx *dev = container_of(cxhdl, struct cx231xx, mpeg_ctrl_handler);
1931
1932         /* The audio clock of the digitizer must match the codec sample
1933            rate otherwise you get some very strange effects. */
1934         if (idx < ARRAY_SIZE(freqs))
1935                 call_all(dev, audio, s_clock_freq, freqs[idx]);
1936         return 0;
1937 }
1938
1939 static const struct cx2341x_handler_ops cx231xx_ops = {
1940         /* needed for the video clock freq */
1941         .s_audio_sampling_freq = cx231xx_s_audio_sampling_freq,
1942         /* needed for setting up the video resolution */
1943         .s_video_encoding = cx231xx_s_video_encoding,
1944 };
1945
1946 static void cx231xx_video_dev_init(
1947         struct cx231xx *dev,
1948         struct usb_device *usbdev,
1949         struct video_device *vfd,
1950         const struct video_device *template,
1951         const char *type)
1952 {
1953         dprintk(1, "%s()\n", __func__);
1954         *vfd = *template;
1955         snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1956                 type, cx231xx_boards[dev->model].name);
1957
1958         vfd->v4l2_dev = &dev->v4l2_dev;
1959         vfd->lock = &dev->lock;
1960         vfd->release = video_device_release_empty;
1961         vfd->ctrl_handler = &dev->mpeg_ctrl_handler.hdl;
1962         video_set_drvdata(vfd, dev);
1963         if (dev->tuner_type == TUNER_ABSENT) {
1964                 v4l2_disable_ioctl(vfd, VIDIOC_G_FREQUENCY);
1965                 v4l2_disable_ioctl(vfd, VIDIOC_S_FREQUENCY);
1966                 v4l2_disable_ioctl(vfd, VIDIOC_G_TUNER);
1967                 v4l2_disable_ioctl(vfd, VIDIOC_S_TUNER);
1968         }
1969 }
1970
1971 int cx231xx_417_register(struct cx231xx *dev)
1972 {
1973         /* FIXME: Port1 hardcoded here */
1974         int err = -ENODEV;
1975         struct cx231xx_tsport *tsport = &dev->ts1;
1976
1977         dprintk(1, "%s()\n", __func__);
1978
1979         /* Set default TV standard */
1980         dev->encodernorm = cx231xx_tvnorms[0];
1981
1982         if (dev->encodernorm.id & V4L2_STD_525_60)
1983                 tsport->height = 480;
1984         else
1985                 tsport->height = 576;
1986
1987         tsport->width = 720;
1988         err = cx2341x_handler_init(&dev->mpeg_ctrl_handler, 50);
1989         if (err) {
1990                 dprintk(3, "%s: can't init cx2341x controls\n", dev->name);
1991                 return err;
1992         }
1993         dev->mpeg_ctrl_handler.func = cx231xx_mbox_func;
1994         dev->mpeg_ctrl_handler.priv = dev;
1995         dev->mpeg_ctrl_handler.ops = &cx231xx_ops;
1996         if (dev->sd_cx25840)
1997                 v4l2_ctrl_add_handler(&dev->mpeg_ctrl_handler.hdl,
1998                                 dev->sd_cx25840->ctrl_handler, NULL);
1999         if (dev->mpeg_ctrl_handler.hdl.error) {
2000                 err = dev->mpeg_ctrl_handler.hdl.error;
2001                 dprintk(3, "%s: can't add cx25840 controls\n", dev->name);
2002                 v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
2003                 return err;
2004         }
2005         dev->norm = V4L2_STD_NTSC;
2006
2007         dev->mpeg_ctrl_handler.port = CX2341X_PORT_SERIAL;
2008         cx2341x_handler_set_50hz(&dev->mpeg_ctrl_handler, false);
2009
2010         /* Allocate and initialize V4L video device */
2011         cx231xx_video_dev_init(dev, dev->udev,
2012                         &dev->v4l_device, &cx231xx_mpeg_template, "mpeg");
2013         err = video_register_device(&dev->v4l_device,
2014                 VFL_TYPE_GRABBER, -1);
2015         if (err < 0) {
2016                 dprintk(3, "%s: can't register mpeg device\n", dev->name);
2017                 v4l2_ctrl_handler_free(&dev->mpeg_ctrl_handler.hdl);
2018                 return err;
2019         }
2020
2021         dprintk(3, "%s: registered device video%d [mpeg]\n",
2022                dev->name, dev->v4l_device.num);
2023
2024         return 0;
2025 }
2026
2027 /*(DEBLOBBED)*/