2 * Copyright (C) 2005-2009 Texas Instruments Inc
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * CCDC hardware module for DM355
19 * ------------------------------
21 * This module is for configuring DM355 CCD controller of VPFE to capture
22 * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
23 * such as Defect Pixel Correction, Color Space Conversion etc to
24 * pre-process the Bayer RGB data, before writing it to SDRAM.
26 * TODO: 1) Raw bayer parameter settings and bayer capture
27 * 2) Split module parameter structure to module specific ioctl structs
28 * 3) add support for lense shading correction
29 * 4) investigate if enum used for user space type definition
30 * to be replaced by #defines or integer
32 #include <linux/platform_device.h>
33 #include <linux/uaccess.h>
34 #include <linux/videodev2.h>
35 #include <linux/err.h>
36 #include <linux/module.h>
38 #include <media/davinci/dm355_ccdc.h>
39 #include <media/davinci/vpss.h>
41 #include "dm355_ccdc_regs.h"
42 #include "ccdc_hw_device.h"
44 MODULE_LICENSE("GPL");
45 MODULE_DESCRIPTION("CCDC Driver for DM355");
46 MODULE_AUTHOR("Texas Instruments");
48 static struct ccdc_oper_config {
50 /* CCDC interface type */
51 enum vpfe_hw_if_type if_type;
52 /* Raw Bayer configuration */
53 struct ccdc_params_raw bayer;
54 /* YCbCr configuration */
55 struct ccdc_params_ycbcr ycbcr;
56 /* ccdc base address */
57 void __iomem *base_addr;
59 /* Raw configurations */
61 .pix_fmt = CCDC_PIXFMT_RAW,
62 .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
64 .fid_pol = VPFE_PINPOL_POSITIVE,
65 .vd_pol = VPFE_PINPOL_POSITIVE,
66 .hd_pol = VPFE_PINPOL_POSITIVE,
75 .mfilt1 = CCDC_NO_MEDIAN_FILTER1,
76 .mfilt2 = CCDC_NO_MEDIAN_FILTER2,
85 .olop = CCDC_GREEN_BLUE,
88 .elep = CCDC_GREEN_RED
91 .olop = CCDC_GREEN_BLUE,
94 .elep = CCDC_GREEN_RED
98 /* YCbCr configuration */
101 .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
102 .frm_fmt = CCDC_FRMFMT_INTERLACED,
103 .fid_pol = VPFE_PINPOL_POSITIVE,
104 .vd_pol = VPFE_PINPOL_POSITIVE,
105 .hd_pol = VPFE_PINPOL_POSITIVE,
107 .pix_order = CCDC_PIXORDER_CBYCRY,
108 .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
113 /* Raw Bayer formats */
114 static u32 ccdc_raw_bayer_pix_formats[] =
115 {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
117 /* Raw YUV formats */
118 static u32 ccdc_raw_yuv_pix_formats[] =
119 {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
121 /* register access routines */
122 static inline u32 regr(u32 offset)
124 return __raw_readl(ccdc_cfg.base_addr + offset);
127 static inline void regw(u32 val, u32 offset)
129 __raw_writel(val, ccdc_cfg.base_addr + offset);
132 static void ccdc_enable(int en)
136 temp &= (~CCDC_SYNCEN_VDHDEN_MASK);
137 temp |= (en & CCDC_SYNCEN_VDHDEN_MASK);
141 static void ccdc_enable_output_to_sdram(int en)
145 temp &= (~(CCDC_SYNCEN_WEN_MASK));
146 temp |= ((en << CCDC_SYNCEN_WEN_SHIFT) & CCDC_SYNCEN_WEN_MASK);
150 static void ccdc_config_gain_offset(void)
153 regw(ccdc_cfg.bayer.gain.r_ye, RYEGAIN);
154 regw(ccdc_cfg.bayer.gain.gr_cy, GRCYGAIN);
155 regw(ccdc_cfg.bayer.gain.gb_g, GBGGAIN);
156 regw(ccdc_cfg.bayer.gain.b_mg, BMGGAIN);
157 /* configure offset */
158 regw(ccdc_cfg.bayer.ccdc_offset, OFFSET);
162 * ccdc_restore_defaults()
163 * This function restore power on defaults in the ccdc registers
165 static int ccdc_restore_defaults(void)
169 dev_dbg(ccdc_cfg.dev, "\nstarting ccdc_restore_defaults...");
170 /* set all registers to zero */
171 for (i = 0; i <= CCDC_REG_LAST; i += 4)
174 /* now override the values with power on defaults in registers */
175 regw(MODESET_DEFAULT, MODESET);
176 /* no culling support */
177 regw(CULH_DEFAULT, CULH);
178 regw(CULV_DEFAULT, CULV);
179 /* Set default Gain and Offset */
180 ccdc_cfg.bayer.gain.r_ye = GAIN_DEFAULT;
181 ccdc_cfg.bayer.gain.gb_g = GAIN_DEFAULT;
182 ccdc_cfg.bayer.gain.gr_cy = GAIN_DEFAULT;
183 ccdc_cfg.bayer.gain.b_mg = GAIN_DEFAULT;
184 ccdc_config_gain_offset();
185 regw(OUTCLIP_DEFAULT, OUTCLIP);
186 regw(LSCCFG2_DEFAULT, LSCCFG2);
187 /* select ccdc input */
188 if (vpss_select_ccdc_source(VPSS_CCDCIN)) {
189 dev_dbg(ccdc_cfg.dev, "\ncouldn't select ccdc input source");
192 /* select ccdc clock */
193 if (vpss_enable_clock(VPSS_CCDC_CLOCK, 1) < 0) {
194 dev_dbg(ccdc_cfg.dev, "\ncouldn't enable ccdc clock");
197 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_restore_defaults...");
201 static int ccdc_open(struct device *device)
203 return ccdc_restore_defaults();
206 static int ccdc_close(struct device *device)
209 vpss_enable_clock(VPSS_CCDC_CLOCK, 0);
210 /* do nothing for now */
215 * This function will configure the window size to
216 * be capture in CCDC reg.
218 static void ccdc_setwin(struct v4l2_rect *image_win,
219 enum ccdc_frmfmt frm_fmt, int ppc)
221 int horz_start, horz_nr_pixels;
222 int vert_start, vert_nr_lines;
225 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
228 * ppc - per pixel count. indicates how many pixels per cell
229 * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
230 * raw capture this is 1
232 horz_start = image_win->left << (ppc - 1);
233 horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
235 /* Writing the horizontal info into the registers */
236 regw(horz_start, SPH);
237 regw(horz_nr_pixels, NPH);
238 vert_start = image_win->top;
240 if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
241 vert_nr_lines = (image_win->height >> 1) - 1;
243 /* Since first line doesn't have any data */
245 /* configure VDINT0 and VDINT1 */
246 regw(vert_start, VDINT0);
248 /* Since first line doesn't have any data */
250 vert_nr_lines = image_win->height - 1;
251 /* configure VDINT0 and VDINT1 */
252 mid_img = vert_start + (image_win->height / 2);
253 regw(vert_start, VDINT0);
254 regw(mid_img, VDINT1);
256 regw(vert_start & CCDC_START_VER_ONE_MASK, SLV0);
257 regw(vert_start & CCDC_START_VER_TWO_MASK, SLV1);
258 regw(vert_nr_lines & CCDC_NUM_LINES_VER, NLV);
259 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
262 /* This function will configure CCDC for YCbCr video capture */
263 static void ccdc_config_ycbcr(void)
265 struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
268 /* first set the CCDC power on defaults values in all registers */
269 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
270 ccdc_restore_defaults();
272 /* configure pixel format & video frame format */
273 temp = (((params->pix_fmt & CCDC_INPUT_MODE_MASK) <<
274 CCDC_INPUT_MODE_SHIFT) |
275 ((params->frm_fmt & CCDC_FRM_FMT_MASK) <<
276 CCDC_FRM_FMT_SHIFT));
278 /* setup BT.656 sync mode */
279 if (params->bt656_enable) {
280 regw(CCDC_REC656IF_BT656_EN, REC656IF);
282 * configure the FID, VD, HD pin polarity fld,hd pol positive,
283 * vd negative, 8-bit pack mode
285 temp |= CCDC_VD_POL_NEGATIVE;
286 } else { /* y/c external sync mode */
287 temp |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
288 CCDC_FID_POL_SHIFT) |
289 ((params->hd_pol & CCDC_HD_POL_MASK) <<
291 ((params->vd_pol & CCDC_VD_POL_MASK) <<
295 /* pack the data to 8-bit */
296 temp |= CCDC_DATA_PACK_ENABLE;
300 /* configure video window */
301 ccdc_setwin(¶ms->win, params->frm_fmt, 2);
303 /* configure the order of y cb cr in SD-RAM */
304 temp = (params->pix_order << CCDC_Y8POS_SHIFT);
305 temp |= CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC;
309 * configure the horizontal line offset. This is done by rounding up
310 * width to a multiple of 16 pixels and multiply by two to account for
313 regw(((params->win.width * 2 + 31) >> 5), HSIZE);
315 /* configure the memory line offset */
316 if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED) {
317 /* two fields are interleaved in memory */
318 regw(CCDC_SDOFST_FIELD_INTERLEAVED, SDOFST);
321 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
325 * ccdc_config_black_clamp()
326 * configure parameters for Optical Black Clamp
328 static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
332 if (!bclamp->b_clamp_enable) {
333 /* configure DCSub */
334 regw(bclamp->dc_sub & CCDC_BLK_DC_SUB_MASK, DCSUB);
338 /* Enable the Black clamping, set sample lines and pixels */
339 val = (bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) |
340 ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
341 CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE;
344 /* If Black clamping is enable then make dcsub 0 */
345 val = (bclamp->sample_ln & CCDC_NUM_LINE_CALC_MASK)
346 << CCDC_NUM_LINE_CALC_SHIFT;
351 * ccdc_config_black_compense()
352 * configure parameters for Black Compensation
354 static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
358 val = (bcomp->b & CCDC_BLK_COMP_MASK) |
359 ((bcomp->gb & CCDC_BLK_COMP_MASK) <<
360 CCDC_BLK_COMP_GB_COMP_SHIFT);
363 val = ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
364 CCDC_BLK_COMP_GR_COMP_SHIFT) |
365 ((bcomp->r & CCDC_BLK_COMP_MASK) <<
366 CCDC_BLK_COMP_R_COMP_SHIFT);
371 * ccdc_write_dfc_entry()
372 * write an entry in the dfc table.
374 int ccdc_write_dfc_entry(int index, struct ccdc_vertical_dft *dfc)
376 /* TODO This is to be re-visited and adjusted */
377 #define DFC_WRITE_WAIT_COUNT 1000
378 u32 val, count = DFC_WRITE_WAIT_COUNT;
380 regw(dfc->dft_corr_vert[index], DFCMEM0);
381 regw(dfc->dft_corr_horz[index], DFCMEM1);
382 regw(dfc->dft_corr_sub1[index], DFCMEM2);
383 regw(dfc->dft_corr_sub2[index], DFCMEM3);
384 regw(dfc->dft_corr_sub3[index], DFCMEM4);
385 /* set WR bit to write */
386 val = regr(DFCMEMCTL) | CCDC_DFCMEMCTL_DFCMWR_MASK;
387 regw(val, DFCMEMCTL);
390 * Assume, it is very short. If we get an error, we need to
393 while (regr(DFCMEMCTL) & CCDC_DFCMEMCTL_DFCMWR_MASK)
396 * TODO We expect the count to be non-zero to be successful. Adjust
397 * the count if write requires more time
401 dev_err(ccdc_cfg.dev, "defect table write timeout !!!\n");
409 * configure parameters for Vertical Defect Correction
411 static int ccdc_config_vdfc(struct ccdc_vertical_dft *dfc)
416 /* Configure General Defect Correction. The table used is from IPIPE */
417 val = dfc->gen_dft_en & CCDC_DFCCTL_GDFCEN_MASK;
419 /* Configure Vertical Defect Correction if needed */
420 if (!dfc->ver_dft_en) {
421 /* Enable only General Defect Correction */
426 if (dfc->table_size > CCDC_DFT_TABLE_SIZE)
429 val |= CCDC_DFCCTL_VDFC_DISABLE;
430 val |= (dfc->dft_corr_ctl.vdfcsl & CCDC_DFCCTL_VDFCSL_MASK) <<
431 CCDC_DFCCTL_VDFCSL_SHIFT;
432 val |= (dfc->dft_corr_ctl.vdfcuda & CCDC_DFCCTL_VDFCUDA_MASK) <<
433 CCDC_DFCCTL_VDFCUDA_SHIFT;
434 val |= (dfc->dft_corr_ctl.vdflsft & CCDC_DFCCTL_VDFLSFT_MASK) <<
435 CCDC_DFCCTL_VDFLSFT_SHIFT;
438 /* clear address ptr to offset 0 */
439 val = CCDC_DFCMEMCTL_DFCMARST_MASK << CCDC_DFCMEMCTL_DFCMARST_SHIFT;
441 /* write defect table entries */
442 for (i = 0; i < dfc->table_size; i++) {
443 /* increment address for non zero index */
445 val = CCDC_DFCMEMCTL_INC_ADDR;
446 regw(val, DFCMEMCTL);
447 if (ccdc_write_dfc_entry(i, dfc) < 0)
451 /* update saturation level and enable dfc */
452 regw(dfc->saturation_ctl & CCDC_VDC_DFCVSAT_MASK, DFCVSAT);
453 val = regr(DFCCTL) | (CCDC_DFCCTL_VDFCEN_MASK <<
454 CCDC_DFCCTL_VDFCEN_SHIFT);
461 * configure parameters for color space conversion
462 * Each register CSCM0-7 has two values in S8Q5 format.
464 static void ccdc_config_csc(struct ccdc_csc *csc)
472 /* Enable the CSC sub-module */
473 regw(CCDC_CSC_ENABLE, CSCCTL);
475 /* Converting the co-eff as per the format of the register */
476 for (i = 0; i < CCDC_CSC_COEFF_TABLE_SIZE; i++) {
479 val1 = (csc->coeff[i].integer &
480 CCDC_CSC_COEF_INTEG_MASK)
481 << CCDC_CSC_COEF_INTEG_SHIFT;
483 * convert decimal part to binary. Use 2 decimal
484 * precision, user values range from .00 - 0.99
486 val1 |= (((csc->coeff[i].decimal &
487 CCDC_CSC_COEF_DECIMAL_MASK) *
488 CCDC_CSC_DEC_MAX) / 100);
492 val2 = (csc->coeff[i].integer &
493 CCDC_CSC_COEF_INTEG_MASK)
494 << CCDC_CSC_COEF_INTEG_SHIFT;
495 val2 |= (((csc->coeff[i].decimal &
496 CCDC_CSC_COEF_DECIMAL_MASK) *
497 CCDC_CSC_DEC_MAX) / 100);
498 val2 <<= CCDC_CSCM_MSB_SHIFT;
500 regw(val2, (CSCM0 + ((i - 1) << 1)));
506 * ccdc_config_color_patterns()
507 * configure parameters for color patterns
509 static void ccdc_config_color_patterns(struct ccdc_col_pat *pat0,
510 struct ccdc_col_pat *pat1)
514 val = (pat0->olop | (pat0->olep << 2) | (pat0->elop << 4) |
515 (pat0->elep << 6) | (pat1->olop << 8) | (pat1->olep << 10) |
516 (pat1->elop << 12) | (pat1->elep << 14));
520 /* This function will configure CCDC for Raw mode image capture */
521 static int ccdc_config_raw(void)
523 struct ccdc_params_raw *params = &ccdc_cfg.bayer;
524 struct ccdc_config_params_raw *config_params =
525 &ccdc_cfg.bayer.config_params;
528 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
530 /* restore power on defaults to register */
531 ccdc_restore_defaults();
534 * set CCD Not to swap input since input is RAW data
535 * set FID detection function to Latch at V-Sync
536 * set WENLOG - ccdc valid area to AND
537 * set TRGSEL to WENBIT
538 * set EXTRG to DISABLE
539 * disable latching function on VSYNC - shadowed registers
541 regw(CCDC_YCINSWP_RAW | CCDC_CCDCFG_FIDMD_LATCH_VSYNC |
542 CCDC_CCDCFG_WENLOG_AND | CCDC_CCDCFG_TRGSEL_WEN |
543 CCDC_CCDCFG_EXTRG_DISABLE | CCDC_LATCH_ON_VSYNC_DISABLE, CCDCFG);
546 * Set VDHD direction to input, input type to raw input
547 * normal data polarity, do not use external WEN
549 val = (CCDC_VDHDOUT_INPUT | CCDC_RAW_IP_MODE | CCDC_DATAPOL_NORMAL |
553 * Configure the vertical sync polarity (MODESET.VDPOL), horizontal
554 * sync polarity (MODESET.HDPOL), field id polarity (MODESET.FLDPOL),
555 * frame format(progressive or interlace), & pixel format (Input mode)
557 val |= (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
558 ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
559 ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
560 ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
561 ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT));
563 /* set pack for alaw compression */
564 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
565 config_params->alaw.enable)
566 val |= CCDC_DATA_PACK_ENABLE;
568 /* Configure for LPF */
569 if (config_params->lpf_enable)
570 val |= (config_params->lpf_enable & CCDC_LPF_MASK) <<
573 /* Configure the data shift */
574 val |= (config_params->datasft & CCDC_DATASFT_MASK) <<
577 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to MODESET...\n", val);
579 /* Configure the Median Filter threshold */
580 regw((config_params->med_filt_thres) & CCDC_MED_FILT_THRESH, MEDFILT);
582 /* Configure GAMMAWD register. defaur 11-2, and Mosaic cfa pattern */
583 val = CCDC_GAMMA_BITS_11_2 << CCDC_GAMMAWD_INPUT_SHIFT |
586 /* Enable and configure aLaw register if needed */
587 if (config_params->alaw.enable) {
588 val |= (CCDC_ALAW_ENABLE |
589 ((config_params->alaw.gamma_wd &
590 CCDC_ALAW_GAMMA_WD_MASK) <<
591 CCDC_GAMMAWD_INPUT_SHIFT));
594 /* Configure Median filter1 & filter2 */
595 val |= ((config_params->mfilt1 << CCDC_MFILT1_SHIFT) |
596 (config_params->mfilt2 << CCDC_MFILT2_SHIFT));
599 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to GAMMAWD...\n", val);
601 /* configure video window */
602 ccdc_setwin(¶ms->win, params->frm_fmt, 1);
604 /* Optical Clamp Averaging */
605 ccdc_config_black_clamp(&config_params->blk_clamp);
607 /* Black level compensation */
608 ccdc_config_black_compense(&config_params->blk_comp);
610 /* Vertical Defect Correction if needed */
611 if (ccdc_config_vdfc(&config_params->vertical_dft) < 0)
614 /* color space conversion */
615 ccdc_config_csc(&config_params->csc);
618 ccdc_config_color_patterns(&config_params->col_pat_field0,
619 &config_params->col_pat_field1);
621 /* Configure the Gain & offset control */
622 ccdc_config_gain_offset();
624 dev_dbg(ccdc_cfg.dev, "\nWriting %x to COLPTN...\n", val);
626 /* Configure DATAOFST register */
627 val = (config_params->data_offset.horz_offset & CCDC_DATAOFST_MASK) <<
628 CCDC_DATAOFST_H_SHIFT;
629 val |= (config_params->data_offset.vert_offset & CCDC_DATAOFST_MASK) <<
630 CCDC_DATAOFST_V_SHIFT;
633 /* configuring HSIZE register */
634 val = (params->horz_flip_enable & CCDC_HSIZE_FLIP_MASK) <<
635 CCDC_HSIZE_FLIP_SHIFT;
637 /* If pack 8 is enable then 1 pixel will take 1 byte */
638 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
639 config_params->alaw.enable) {
640 val |= (((params->win.width) + 31) >> 5) &
643 /* adjust to multiple of 32 */
644 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n",
645 (((params->win.width) + 31) >> 5) &
646 CCDC_HSIZE_VAL_MASK);
648 /* else one pixel will take 2 byte */
649 val |= (((params->win.width * 2) + 31) >> 5) &
652 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n",
653 (((params->win.width * 2) + 31) >> 5) &
654 CCDC_HSIZE_VAL_MASK);
658 /* Configure SDOFST register */
659 if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
660 if (params->image_invert_enable) {
661 /* For interlace inverse mode */
662 regw(CCDC_SDOFST_INTERLACE_INVERSE, SDOFST);
663 dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
664 CCDC_SDOFST_INTERLACE_INVERSE);
666 /* For interlace non inverse mode */
667 regw(CCDC_SDOFST_INTERLACE_NORMAL, SDOFST);
668 dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
669 CCDC_SDOFST_INTERLACE_NORMAL);
671 } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
672 if (params->image_invert_enable) {
673 /* For progessive inverse mode */
674 regw(CCDC_SDOFST_PROGRESSIVE_INVERSE, SDOFST);
675 dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
676 CCDC_SDOFST_PROGRESSIVE_INVERSE);
678 /* For progessive non inverse mode */
679 regw(CCDC_SDOFST_PROGRESSIVE_NORMAL, SDOFST);
680 dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
681 CCDC_SDOFST_PROGRESSIVE_NORMAL);
684 dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
688 static int ccdc_configure(void)
690 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
691 return ccdc_config_raw();
697 static int ccdc_set_buftype(enum ccdc_buftype buf_type)
699 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
700 ccdc_cfg.bayer.buf_type = buf_type;
702 ccdc_cfg.ycbcr.buf_type = buf_type;
705 static enum ccdc_buftype ccdc_get_buftype(void)
707 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
708 return ccdc_cfg.bayer.buf_type;
709 return ccdc_cfg.ycbcr.buf_type;
712 static int ccdc_enum_pix(u32 *pix, int i)
715 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
716 if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
717 *pix = ccdc_raw_bayer_pix_formats[i];
721 if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
722 *pix = ccdc_raw_yuv_pix_formats[i];
729 static int ccdc_set_pixel_format(u32 pixfmt)
731 struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
733 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
734 ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
735 if (pixfmt == V4L2_PIX_FMT_SBGGR8)
737 else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
740 if (pixfmt == V4L2_PIX_FMT_YUYV)
741 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
742 else if (pixfmt == V4L2_PIX_FMT_UYVY)
743 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
749 static u32 ccdc_get_pixel_format(void)
751 struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
754 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
756 pixfmt = V4L2_PIX_FMT_SBGGR8;
758 pixfmt = V4L2_PIX_FMT_SBGGR16;
760 if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
761 pixfmt = V4L2_PIX_FMT_YUYV;
763 pixfmt = V4L2_PIX_FMT_UYVY;
767 static int ccdc_set_image_window(struct v4l2_rect *win)
769 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
770 ccdc_cfg.bayer.win = *win;
772 ccdc_cfg.ycbcr.win = *win;
776 static void ccdc_get_image_window(struct v4l2_rect *win)
778 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
779 *win = ccdc_cfg.bayer.win;
781 *win = ccdc_cfg.ycbcr.win;
784 static unsigned int ccdc_get_line_length(void)
786 struct ccdc_config_params_raw *config_params =
787 &ccdc_cfg.bayer.config_params;
790 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
791 if ((config_params->alaw.enable) ||
792 (config_params->data_sz == CCDC_DATA_8BITS))
793 len = ccdc_cfg.bayer.win.width;
795 len = ccdc_cfg.bayer.win.width * 2;
797 len = ccdc_cfg.ycbcr.win.width * 2;
798 return ALIGN(len, 32);
801 static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
803 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
804 ccdc_cfg.bayer.frm_fmt = frm_fmt;
806 ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
810 static enum ccdc_frmfmt ccdc_get_frame_format(void)
812 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
813 return ccdc_cfg.bayer.frm_fmt;
815 return ccdc_cfg.ycbcr.frm_fmt;
818 static int ccdc_getfid(void)
820 return (regr(MODESET) >> 15) & 1;
823 /* misc operations */
824 static inline void ccdc_setfbaddr(unsigned long addr)
826 regw((addr >> 21) & 0x007f, STADRH);
827 regw((addr >> 5) & 0x0ffff, STADRL);
830 static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
832 ccdc_cfg.if_type = params->if_type;
834 switch (params->if_type) {
836 case VPFE_YCBCR_SYNC_16:
837 case VPFE_YCBCR_SYNC_8:
838 ccdc_cfg.ycbcr.vd_pol = params->vdpol;
839 ccdc_cfg.ycbcr.hd_pol = params->hdpol;
842 /* TODO add support for raw bayer here */
848 static struct ccdc_hw_device ccdc_hw_dev = {
849 .name = "DM355 CCDC",
850 .owner = THIS_MODULE,
854 .enable = ccdc_enable,
855 .enable_out_to_sdram = ccdc_enable_output_to_sdram,
856 .set_hw_if_params = ccdc_set_hw_if_params,
857 .configure = ccdc_configure,
858 .set_buftype = ccdc_set_buftype,
859 .get_buftype = ccdc_get_buftype,
860 .enum_pix = ccdc_enum_pix,
861 .set_pixel_format = ccdc_set_pixel_format,
862 .get_pixel_format = ccdc_get_pixel_format,
863 .set_frame_format = ccdc_set_frame_format,
864 .get_frame_format = ccdc_get_frame_format,
865 .set_image_window = ccdc_set_image_window,
866 .get_image_window = ccdc_get_image_window,
867 .get_line_length = ccdc_get_line_length,
868 .setfbaddr = ccdc_setfbaddr,
869 .getfid = ccdc_getfid,
873 static int dm355_ccdc_probe(struct platform_device *pdev)
875 void (*setup_pinmux)(void);
876 struct resource *res;
880 * first try to register with vpfe. If not correct platform, then we
881 * don't have to iomap
883 status = vpfe_register_ccdc_device(&ccdc_hw_dev);
887 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
893 res = request_mem_region(res->start, resource_size(res), res->name);
899 ccdc_cfg.base_addr = ioremap_nocache(res->start, resource_size(res));
900 if (!ccdc_cfg.base_addr) {
905 /* Platform data holds setup_pinmux function ptr */
906 if (NULL == pdev->dev.platform_data) {
910 setup_pinmux = pdev->dev.platform_data;
912 * setup Mux configuration for ccdc which may be different for
913 * different SoCs using this CCDC
916 ccdc_cfg.dev = &pdev->dev;
917 printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
920 iounmap(ccdc_cfg.base_addr);
922 release_mem_region(res->start, resource_size(res));
924 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
928 static int dm355_ccdc_remove(struct platform_device *pdev)
930 struct resource *res;
932 iounmap(ccdc_cfg.base_addr);
933 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
935 release_mem_region(res->start, resource_size(res));
936 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
940 static struct platform_driver dm355_ccdc_driver = {
942 .name = "dm355_ccdc",
943 .owner = THIS_MODULE,
945 .remove = dm355_ccdc_remove,
946 .probe = dm355_ccdc_probe,
949 module_platform_driver(dm355_ccdc_driver);