drivers/media/i2c/adv7604.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * adv7604 - Analog Devices ADV7604 video decoder driver
   4  *
   5  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   6  *
   7  */
   8
   9 /*
  10  * References (c = chapter, p = page):
  11  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  12  *              Revision 2.5, June 2010
  13  * REF_02 - Analog devices, Register map documentation, Documentation of
  14  *              the register maps, Software manual, Rev. F, June 2010
  15  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  16  */
  17
  18 #include <linux/delay.h>
  19 #include <linux/gpio/consumer.h>
  20 #include <linux/hdmi.h>
  21 #include <linux/i2c.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/of_graph.h>
  25 #include <linux/slab.h>
  26 #include <linux/v4l2-dv-timings.h>
  27 #include <linux/videodev2.h>
  28 #include <linux/workqueue.h>
  29 #include <linux/regmap.h>
  30 #include <linux/interrupt.h>
  31
  32 #include <media/i2c/adv7604.h>
  33 #include <media/cec.h>
  34 #include <media/v4l2-ctrls.h>
  35 #include <media/v4l2-device.h>
  36 #include <media/v4l2-event.h>
  37 #include <media/v4l2-dv-timings.h>
  38 #include <media/v4l2-fwnode.h>
  39
  40 static int debug;
  41 module_param(debug, int, 0644);
  42 MODULE_PARM_DESC(debug, "debug level (0-2)");
  43
  44 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  46 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  47 MODULE_LICENSE("GPL");
  48
  49 /* ADV7604 system clock frequency */
  50 #define ADV76XX_FSC (28636360)
  51
  52 #define ADV76XX_RGB_OUT                                 (1 << 1)
  53
  54 #define ADV76XX_OP_FORMAT_SEL_8BIT                      (0 << 0)
  55 #define ADV7604_OP_FORMAT_SEL_10BIT                     (1 << 0)
  56 #define ADV76XX_OP_FORMAT_SEL_12BIT                     (2 << 0)
  57
  58 #define ADV76XX_OP_MODE_SEL_SDR_422                     (0 << 5)
  59 #define ADV7604_OP_MODE_SEL_DDR_422                     (1 << 5)
  60 #define ADV76XX_OP_MODE_SEL_SDR_444                     (2 << 5)
  61 #define ADV7604_OP_MODE_SEL_DDR_444                     (3 << 5)
  62 #define ADV76XX_OP_MODE_SEL_SDR_422_2X                  (4 << 5)
  63 #define ADV7604_OP_MODE_SEL_ADI_CM                      (5 << 5)
  64
  65 #define ADV76XX_OP_CH_SEL_GBR                           (0 << 5)
  66 #define ADV76XX_OP_CH_SEL_GRB                           (1 << 5)
  67 #define ADV76XX_OP_CH_SEL_BGR                           (2 << 5)
  68 #define ADV76XX_OP_CH_SEL_RGB                           (3 << 5)
  69 #define ADV76XX_OP_CH_SEL_BRG                           (4 << 5)
  70 #define ADV76XX_OP_CH_SEL_RBG                           (5 << 5)
  71
  72 #define ADV76XX_OP_SWAP_CB_CR                           (1 << 0)
  73
  74 #define ADV76XX_MAX_ADDRS (3)
  75
  76 enum adv76xx_type {
  77         ADV7604,
  78         ADV7611,
  79         ADV7612,
  80 };
  81
  82 struct adv76xx_reg_seq {
  83         unsigned int reg;
  84         u8 val;
  85 };
  86
  87 struct adv76xx_format_info {
  88         u32 code;
  89         u8 op_ch_sel;
  90         bool rgb_out;
  91         bool swap_cb_cr;
  92         u8 op_format_sel;
  93 };
  94
  95 struct adv76xx_cfg_read_infoframe {
  96         const char *desc;
  97         u8 present_mask;
  98         u8 head_addr;
  99         u8 payload_addr;
 100 };
 101
 102 struct adv76xx_chip_info {
 103         enum adv76xx_type type;
 104
 105         bool has_afe;
 106         unsigned int max_port;
 107         unsigned int num_dv_ports;
 108
 109         unsigned int edid_enable_reg;
 110         unsigned int edid_status_reg;
 111         unsigned int lcf_reg;
 112
 113         unsigned int cable_det_mask;
 114         unsigned int tdms_lock_mask;
 115         unsigned int fmt_change_digital_mask;
 116         unsigned int cp_csc;
 117
 118         unsigned int cec_irq_status;
 119         unsigned int cec_rx_enable;
 120         unsigned int cec_rx_enable_mask;
 121         bool cec_irq_swap;
 122
 123         const struct adv76xx_format_info *formats;
 124         unsigned int nformats;
 125
 126         void (*set_termination)(struct v4l2_subdev *sd, bool enable);
 127         void (*setup_irqs)(struct v4l2_subdev *sd);
 128         unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
 129         unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
 130
 131         /* 0 = AFE, 1 = HDMI */
 132         const struct adv76xx_reg_seq *recommended_settings[2];
 133         unsigned int num_recommended_settings[2];
 134
 135         unsigned long page_mask;
 136
 137         /* Masks for timings */
 138         unsigned int linewidth_mask;
 139         unsigned int field0_height_mask;
 140         unsigned int field1_height_mask;
 141         unsigned int hfrontporch_mask;
 142         unsigned int hsync_mask;
 143         unsigned int hbackporch_mask;
 144         unsigned int field0_vfrontporch_mask;
 145         unsigned int field1_vfrontporch_mask;
 146         unsigned int field0_vsync_mask;
 147         unsigned int field1_vsync_mask;
 148         unsigned int field0_vbackporch_mask;
 149         unsigned int field1_vbackporch_mask;
 150 };
 151
 152 /*
 153  **********************************************************************
 154  *
 155  *  Arrays with configuration parameters for the ADV7604
 156  *
 157  **********************************************************************
 158  */
 159
 160 struct adv76xx_state {
 161         const struct adv76xx_chip_info *info;
 162         struct adv76xx_platform_data pdata;
 163
 164         struct gpio_desc *hpd_gpio[4];
 165         struct gpio_desc *reset_gpio;
 166
 167         struct v4l2_subdev sd;
 168         struct media_pad pads[ADV76XX_PAD_MAX];
 169         unsigned int source_pad;
 170
 171         struct v4l2_ctrl_handler hdl;
 172
 173         enum adv76xx_pad selected_input;
 174
 175         struct v4l2_dv_timings timings;
 176         const struct adv76xx_format_info *format;
 177
 178         struct {
 179                 u8 edid[256];
 180                 u32 present;
 181                 unsigned blocks;
 182         } edid;
 183         u16 spa_port_a[2];
 184         struct v4l2_fract aspect_ratio;
 185         u32 rgb_quantization_range;
 186         struct delayed_work delayed_work_enable_hotplug;
 187         bool restart_stdi_once;
 188
 189         /* CEC */
 190         struct cec_adapter *cec_adap;
 191         u8   cec_addr[ADV76XX_MAX_ADDRS];
 192         u8   cec_valid_addrs;
 193         bool cec_enabled_adap;
 194
 195         /* i2c clients */
 196         struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
 197
 198         /* Regmaps */
 199         struct regmap *regmap[ADV76XX_PAGE_MAX];
 200
 201         /* controls */
 202         struct v4l2_ctrl *detect_tx_5v_ctrl;
 203         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 204         struct v4l2_ctrl *free_run_color_manual_ctrl;
 205         struct v4l2_ctrl *free_run_color_ctrl;
 206         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 207 };
 208
 209 static bool adv76xx_has_afe(struct adv76xx_state *state)
 210 {
 211         return state->info->has_afe;
 212 }
 213
 214 /* Unsupported timings. This device cannot support 720p30. */
 215 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
 216         V4L2_DV_BT_CEA_1280X720P30,
 217         { }
 218 };
 219
 220 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
 221 {
 222         int i;
 223
 224         for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
 225                 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
 226                         return false;
 227         return true;
 228 }
 229
 230 struct adv76xx_video_standards {
 231         struct v4l2_dv_timings timings;
 232         u8 vid_std;
 233         u8 v_freq;
 234 };
 235
 236 /* sorted by number of lines */
 237 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
 238         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 239         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 240         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 241         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 242         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 243         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 244         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 245         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 246         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 247         /* TODO add 1920x1080P60_RB (CVT timing) */
 248         { },
 249 };
 250
 251 /* sorted by number of lines */
 252 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
 253         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 254         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 255         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 256         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 257         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 258         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 259         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 260         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 261         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 262         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 263         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 264         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 265         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 266         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 267         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 268         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 269         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 270         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 271         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 272         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 273         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 274         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 275         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 276         { },
 277 };
 278
 279 /* sorted by number of lines */
 280 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
 281         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 282         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 283         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 284         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 285         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 286         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 287         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 288         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 289         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 290         { },
 291 };
 292
 293 /* sorted by number of lines */
 294 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
 295         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 296         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 297         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 298         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 299         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 300         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 301         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 302         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 303         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 304         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 305         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 306         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 307         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 308         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 309         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 310         { },
 311 };
 312
 313 static const struct v4l2_event adv76xx_ev_fmt = {
 314         .type = V4L2_EVENT_SOURCE_CHANGE,
 315         .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
 316 };
 317
 318 /* ----------------------------------------------------------------------- */
 319
 320 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
 321 {
 322         return container_of(sd, struct adv76xx_state, sd);
 323 }
 324
 325 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 326 {
 327         return V4L2_DV_BT_FRAME_WIDTH(t);
 328 }
 329
 330 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 331 {
 332         return V4L2_DV_BT_FRAME_HEIGHT(t);
 333 }
 334
 335 /* ----------------------------------------------------------------------- */
 336
 337 static int adv76xx_read_check(struct adv76xx_state *state,
 338                              int client_page, u8 reg)
 339 {
 340         struct i2c_client *client = state->i2c_clients[client_page];
 341         int err;
 342         unsigned int val;
 343
 344         err = regmap_read(state->regmap[client_page], reg, &val);
 345
 346         if (err) {
 347                 v4l_err(client, "error reading %02x, %02x\n",
 348                                 client->addr, reg);
 349                 return err;
 350         }
 351         return val;
 352 }
 353
 354 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
 355  * size to one or more registers.
 356  *
 357  * A value of zero will be returned on success, a negative errno will
 358  * be returned in error cases.
 359  */
 360 static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
 361                               unsigned int init_reg, const void *val,
 362                               size_t val_len)
 363 {
 364         struct regmap *regmap = state->regmap[client_page];
 365
 366         if (val_len > I2C_SMBUS_BLOCK_MAX)
 367                 val_len = I2C_SMBUS_BLOCK_MAX;
 368
 369         return regmap_raw_write(regmap, init_reg, val, val_len);
 370 }
 371
 372 /* ----------------------------------------------------------------------- */
 373
 374 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 375 {
 376         struct adv76xx_state *state = to_state(sd);
 377
 378         return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
 379 }
 380
 381 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 382 {
 383         struct adv76xx_state *state = to_state(sd);
 384
 385         return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
 386 }
 387
 388 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
 389                                    u8 val)
 390 {
 391         return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
 392 }
 393
 394 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 395 {
 396         struct adv76xx_state *state = to_state(sd);
 397
 398         return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
 399 }
 400
 401 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 402 {
 403         struct adv76xx_state *state = to_state(sd);
 404
 405         return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
 406 }
 407
 408 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 409 {
 410         struct adv76xx_state *state = to_state(sd);
 411
 412         return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
 413 }
 414
 415 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 416 {
 417         struct adv76xx_state *state = to_state(sd);
 418
 419         return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
 420 }
 421
 422 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
 423                                    u8 val)
 424 {
 425         return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
 426 }
 427
 428 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 429 {
 430         struct adv76xx_state *state = to_state(sd);
 431
 432         return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
 433 }
 434
 435 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 436 {
 437         struct adv76xx_state *state = to_state(sd);
 438
 439         return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
 440 }
 441
 442 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 443 {
 444         struct adv76xx_state *state = to_state(sd);
 445
 446         return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
 447 }
 448
 449 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 450 {
 451         struct adv76xx_state *state = to_state(sd);
 452
 453         return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
 454 }
 455
 456 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 457 {
 458         struct adv76xx_state *state = to_state(sd);
 459
 460         return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
 461 }
 462
 463 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 464 {
 465         struct adv76xx_state *state = to_state(sd);
 466
 467         return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
 468 }
 469
 470 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 471 {
 472         return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
 473 }
 474
 475 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 476 {
 477         struct adv76xx_state *state = to_state(sd);
 478
 479         return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
 480 }
 481
 482 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 483 {
 484         struct adv76xx_state *state = to_state(sd);
 485
 486         return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
 487 }
 488
 489 static inline int edid_write_block(struct v4l2_subdev *sd,
 490                                         unsigned int total_len, const u8 *val)
 491 {
 492         struct adv76xx_state *state = to_state(sd);
 493         int err = 0;
 494         int i = 0;
 495         int len = 0;
 496
 497         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
 498                                 __func__, total_len);
 499
 500         while (!err && i < total_len) {
 501                 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
 502                                 I2C_SMBUS_BLOCK_MAX :
 503                                 (total_len - i);
 504
 505                 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
 506                                 i, val + i, len);
 507                 i += len;
 508         }
 509
 510         return err;
 511 }
 512
 513 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
 514 {
 515         unsigned int i;
 516
 517         for (i = 0; i < state->info->num_dv_ports; ++i)
 518                 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
 519
 520         v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
 521 }
 522
 523 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
 524 {
 525         struct delayed_work *dwork = to_delayed_work(work);
 526         struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
 527                                                 delayed_work_enable_hotplug);
 528         struct v4l2_subdev *sd = &state->sd;
 529
 530         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 531
 532         adv76xx_set_hpd(state, state->edid.present);
 533 }
 534
 535 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 536 {
 537         struct adv76xx_state *state = to_state(sd);
 538
 539         return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
 540 }
 541
 542 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 543 {
 544         return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
 545 }
 546
 547 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 548 {
 549         struct adv76xx_state *state = to_state(sd);
 550
 551         return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
 552 }
 553
 554 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 555 {
 556         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
 557 }
 558
 559 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 560 {
 561         struct adv76xx_state *state = to_state(sd);
 562
 563         return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
 564 }
 565
 566 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 567 {
 568         struct adv76xx_state *state = to_state(sd);
 569
 570         return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
 571 }
 572
 573 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 574 {
 575         return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
 576 }
 577
 578 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 579 {
 580         struct adv76xx_state *state = to_state(sd);
 581
 582         return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
 583 }
 584
 585 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 586 {
 587         return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
 588 }
 589
 590 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 591 {
 592         struct adv76xx_state *state = to_state(sd);
 593
 594         return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
 595 }
 596
 597 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 598 {
 599         struct adv76xx_state *state = to_state(sd);
 600
 601         return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
 602 }
 603
 604 #define ADV76XX_REG(page, offset)       (((page) << 8) | (offset))
 605 #define ADV76XX_REG_SEQ_TERM            0xffff
 606
 607 #ifdef CONFIG_VIDEO_ADV_DEBUG
 608 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
 609 {
 610         struct adv76xx_state *state = to_state(sd);
 611         unsigned int page = reg >> 8;
 612         unsigned int val;
 613         int err;
 614
 615         if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
 616                 return -EINVAL;
 617
 618         reg &= 0xff;
 619         err = regmap_read(state->regmap[page], reg, &val);
 620
 621         return err ? err : val;
 622 }
 623 #endif
 624
 625 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
 626 {
 627         struct adv76xx_state *state = to_state(sd);
 628         unsigned int page = reg >> 8;
 629
 630         if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
 631                 return -EINVAL;
 632
 633         reg &= 0xff;
 634
 635         return regmap_write(state->regmap[page], reg, val);
 636 }
 637
 638 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
 639                                   const struct adv76xx_reg_seq *reg_seq)
 640 {
 641         unsigned int i;
 642
 643         for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
 644                 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
 645 }
 646
 647 /* -----------------------------------------------------------------------------
 648  * Format helpers
 649  */
 650
 651 static const struct adv76xx_format_info adv7604_formats[] = {
 652         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 653           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 654         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 655           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 656         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 657           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 658         { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
 659           ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 660         { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
 661           ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 662         { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
 663           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 664         { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
 665           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 666         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 667           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 668         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 669           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 670         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 671           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 672         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 673           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 674         { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
 675           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 676         { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
 677           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 678         { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
 679           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 680         { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
 681           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 682         { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
 683           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 684         { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
 685           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 686         { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
 687           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 688         { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
 689           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 690 };
 691
 692 static const struct adv76xx_format_info adv7611_formats[] = {
 693         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 694           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 695         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 696           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 697         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 698           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 699         { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
 700           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 701         { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
 702           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 703         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 704           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 705         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 706           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 707         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 708           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 709         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 710           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 711         { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
 712           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 713         { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
 714           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 715         { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
 716           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 717         { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
 718           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 719 };
 720
 721 static const struct adv76xx_format_info adv7612_formats[] = {
 722         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 723           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 724         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 725           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 726         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 727           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 728         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 729           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 730         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 731           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 732         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 733           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 734         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 735           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 736 };
 737
 738 static const struct adv76xx_format_info *
 739 adv76xx_format_info(struct adv76xx_state *state, u32 code)
 740 {
 741         unsigned int i;
 742
 743         for (i = 0; i < state->info->nformats; ++i) {
 744                 if (state->info->formats[i].code == code)
 745                         return &state->info->formats[i];
 746         }
 747
 748         return NULL;
 749 }
 750
 751 /* ----------------------------------------------------------------------- */
 752
 753 static inline bool is_analog_input(struct v4l2_subdev *sd)
 754 {
 755         struct adv76xx_state *state = to_state(sd);
 756
 757         return state->selected_input == ADV7604_PAD_VGA_RGB ||
 758                state->selected_input == ADV7604_PAD_VGA_COMP;
 759 }
 760
 761 static inline bool is_digital_input(struct v4l2_subdev *sd)
 762 {
 763         struct adv76xx_state *state = to_state(sd);
 764
 765         return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
 766                state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
 767                state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
 768                state->selected_input == ADV7604_PAD_HDMI_PORT_D;
 769 }
 770
 771 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
 772         .type = V4L2_DV_BT_656_1120,
 773         /* keep this initialization for compatibility with GCC < 4.4.6 */
 774         .reserved = { 0 },
 775         V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
 776                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 777                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 778                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 779                         V4L2_DV_BT_CAP_CUSTOM)
 780 };
 781
 782 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
 783         .type = V4L2_DV_BT_656_1120,
 784         /* keep this initialization for compatibility with GCC < 4.4.6 */
 785         .reserved = { 0 },
 786         V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
 787                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 788                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 789                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 790                         V4L2_DV_BT_CAP_CUSTOM)
 791 };
 792
 793 /*
 794  * Return the DV timings capabilities for the requested sink pad. As a special
 795  * case, pad value -1 returns the capabilities for the currently selected input.
 796  */
 797 static const struct v4l2_dv_timings_cap *
 798 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
 799 {
 800         if (pad == -1) {
 801                 struct adv76xx_state *state = to_state(sd);
 802
 803                 pad = state->selected_input;
 804         }
 805
 806         switch (pad) {
 807         case ADV76XX_PAD_HDMI_PORT_A:
 808         case ADV7604_PAD_HDMI_PORT_B:
 809         case ADV7604_PAD_HDMI_PORT_C:
 810         case ADV7604_PAD_HDMI_PORT_D:
 811                 return &adv76xx_timings_cap_digital;
 812
 813         case ADV7604_PAD_VGA_RGB:
 814         case ADV7604_PAD_VGA_COMP:
 815         default:
 816                 return &adv7604_timings_cap_analog;
 817         }
 818 }
 819
 820
 821 /* ----------------------------------------------------------------------- */
 822
 823 #ifdef CONFIG_VIDEO_ADV_DEBUG
 824 static void adv76xx_inv_register(struct v4l2_subdev *sd)
 825 {
 826         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 827         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 828         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 829         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 830         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 831         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 832         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 833         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 834         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 835         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 836         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 837         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 838         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 839 }
 840
 841 static int adv76xx_g_register(struct v4l2_subdev *sd,
 842                                         struct v4l2_dbg_register *reg)
 843 {
 844         int ret;
 845
 846         ret = adv76xx_read_reg(sd, reg->reg);
 847         if (ret < 0) {
 848                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 849                 adv76xx_inv_register(sd);
 850                 return ret;
 851         }
 852
 853         reg->size = 1;
 854         reg->val = ret;
 855
 856         return 0;
 857 }
 858
 859 static int adv76xx_s_register(struct v4l2_subdev *sd,
 860                                         const struct v4l2_dbg_register *reg)
 861 {
 862         int ret;
 863
 864         ret = adv76xx_write_reg(sd, reg->reg, reg->val);
 865         if (ret < 0) {
 866                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 867                 adv76xx_inv_register(sd);
 868                 return ret;
 869         }
 870
 871         return 0;
 872 }
 873 #endif
 874
 875 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
 876 {
 877         u8 value = io_read(sd, 0x6f);
 878
 879         return ((value & 0x10) >> 4)
 880              | ((value & 0x08) >> 2)
 881              | ((value & 0x04) << 0)
 882              | ((value & 0x02) << 2);
 883 }
 884
 885 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
 886 {
 887         u8 value = io_read(sd, 0x6f);
 888
 889         return value & 1;
 890 }
 891
 892 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
 893 {
 894         /*  Reads CABLE_DET_A_RAW. For input B support, need to
 895          *  account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
 896          */
 897         u8 value = io_read(sd, 0x6f);
 898
 899         return value & 1;
 900 }
 901
 902 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 903 {
 904         struct adv76xx_state *state = to_state(sd);
 905         const struct adv76xx_chip_info *info = state->info;
 906         u16 cable_det = info->read_cable_det(sd);
 907
 908         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
 909 }
 910
 911 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 912                 u8 prim_mode,
 913                 const struct adv76xx_video_standards *predef_vid_timings,
 914                 const struct v4l2_dv_timings *timings)
 915 {
 916         int i;
 917
 918         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 919                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 920                                 is_digital_input(sd) ? 250000 : 1000000, false))
 921                         continue;
 922                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 923                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 924                                 prim_mode); /* v_freq and prim mode */
 925                 return 0;
 926         }
 927
 928         return -1;
 929 }
 930
 931 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 932                 struct v4l2_dv_timings *timings)
 933 {
 934         struct adv76xx_state *state = to_state(sd);
 935         int err;
 936
 937         v4l2_dbg(1, debug, sd, "%s", __func__);
 938
 939         if (adv76xx_has_afe(state)) {
 940                 /* reset to default values */
 941                 io_write(sd, 0x16, 0x43);
 942                 io_write(sd, 0x17, 0x5a);
 943         }
 944         /* disable embedded syncs for auto graphics mode */
 945         cp_write_clr_set(sd, 0x81, 0x10, 0x00);
 946         cp_write(sd, 0x8f, 0x00);
 947         cp_write(sd, 0x90, 0x00);
 948         cp_write(sd, 0xa2, 0x00);
 949         cp_write(sd, 0xa3, 0x00);
 950         cp_write(sd, 0xa4, 0x00);
 951         cp_write(sd, 0xa5, 0x00);
 952         cp_write(sd, 0xa6, 0x00);
 953         cp_write(sd, 0xa7, 0x00);
 954         cp_write(sd, 0xab, 0x00);
 955         cp_write(sd, 0xac, 0x00);
 956
 957         if (is_analog_input(sd)) {
 958                 err = find_and_set_predefined_video_timings(sd,
 959                                 0x01, adv7604_prim_mode_comp, timings);
 960                 if (err)
 961                         err = find_and_set_predefined_video_timings(sd,
 962                                         0x02, adv7604_prim_mode_gr, timings);
 963         } else if (is_digital_input(sd)) {
 964                 err = find_and_set_predefined_video_timings(sd,
 965                                 0x05, adv76xx_prim_mode_hdmi_comp, timings);
 966                 if (err)
 967                         err = find_and_set_predefined_video_timings(sd,
 968                                         0x06, adv76xx_prim_mode_hdmi_gr, timings);
 969         } else {
 970                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 971                                 __func__, state->selected_input);
 972                 err = -1;
 973         }
 974
 975
 976         return err;
 977 }
 978
 979 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 980                 const struct v4l2_bt_timings *bt)
 981 {
 982         struct adv76xx_state *state = to_state(sd);
 983         u32 width = htotal(bt);
 984         u32 height = vtotal(bt);
 985         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 986         u16 cp_start_eav = width - bt->hfrontporch;
 987         u16 cp_start_vbi = height - bt->vfrontporch;
 988         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 989         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 990                 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 991         const u8 pll[2] = {
 992                 0xc0 | ((width >> 8) & 0x1f),
 993                 width & 0xff
 994         };
 995
 996         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 997
 998         if (is_analog_input(sd)) {
 999                 /* auto graphics */
1000                 io_write(sd, 0x00, 0x07); /* video std */
1001                 io_write(sd, 0x01, 0x02); /* prim mode */
1002                 /* enable embedded syncs for auto graphics mode */
1003                 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1004
1005                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1006                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1007                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1008                 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
1009                                         0x16, pll, 2))
1010                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1011
1012                 /* active video - horizontal timing */
1013                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1014                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1015                                    ((cp_start_eav >> 8) & 0x0f));
1016                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1017
1018                 /* active video - vertical timing */
1019                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1020                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1021                                    ((cp_end_vbi >> 8) & 0xf));
1022                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1023         } else if (is_digital_input(sd)) {
1024                 /* set default prim_mode/vid_std for HDMI
1025                    according to [REF_03, c. 4.2] */
1026                 io_write(sd, 0x00, 0x02); /* video std */
1027                 io_write(sd, 0x01, 0x06); /* prim mode */
1028         } else {
1029                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1030                                 __func__, state->selected_input);
1031         }
1032
1033         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1034         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1035         cp_write(sd, 0xab, (height >> 4) & 0xff);
1036         cp_write(sd, 0xac, (height & 0x0f) << 4);
1037 }
1038
1039 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1040 {
1041         struct adv76xx_state *state = to_state(sd);
1042         u8 offset_buf[4];
1043
1044         if (auto_offset) {
1045                 offset_a = 0x3ff;
1046                 offset_b = 0x3ff;
1047                 offset_c = 0x3ff;
1048         }
1049
1050         v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1051                         __func__, auto_offset ? "Auto" : "Manual",
1052                         offset_a, offset_b, offset_c);
1053
1054         offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1055         offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1056         offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1057         offset_buf[3] = offset_c & 0x0ff;
1058
1059         /* Registers must be written in this order with no i2c access in between */
1060         if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1061                         0x77, offset_buf, 4))
1062                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1063 }
1064
1065 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1066 {
1067         struct adv76xx_state *state = to_state(sd);
1068         u8 gain_buf[4];
1069         u8 gain_man = 1;
1070         u8 agc_mode_man = 1;
1071
1072         if (auto_gain) {
1073                 gain_man = 0;
1074                 agc_mode_man = 0;
1075                 gain_a = 0x100;
1076                 gain_b = 0x100;
1077                 gain_c = 0x100;
1078         }
1079
1080         v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1081                         __func__, auto_gain ? "Auto" : "Manual",
1082                         gain_a, gain_b, gain_c);
1083
1084         gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1085         gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1086         gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1087         gain_buf[3] = ((gain_c & 0x0ff));
1088
1089         /* Registers must be written in this order with no i2c access in between */
1090         if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1091                              0x73, gain_buf, 4))
1092                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1093 }
1094
1095 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1096 {
1097         struct adv76xx_state *state = to_state(sd);
1098         bool rgb_output = io_read(sd, 0x02) & 0x02;
1099         bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1100         u8 y = HDMI_COLORSPACE_RGB;
1101
1102         if (hdmi_signal && (io_read(sd, 0x60) & 1))
1103                 y = infoframe_read(sd, 0x01) >> 5;
1104
1105         v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1106                         __func__, state->rgb_quantization_range,
1107                         rgb_output, hdmi_signal);
1108
1109         adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1110         adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1111         io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1112
1113         switch (state->rgb_quantization_range) {
1114         case V4L2_DV_RGB_RANGE_AUTO:
1115                 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1116                         /* Receiving analog RGB signal
1117                          * Set RGB full range (0-255) */
1118                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1119                         break;
1120                 }
1121
1122                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1123                         /* Receiving analog YPbPr signal
1124                          * Set automode */
1125                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1126                         break;
1127                 }
1128
1129                 if (hdmi_signal) {
1130                         /* Receiving HDMI signal
1131                          * Set automode */
1132                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1133                         break;
1134                 }
1135
1136                 /* Receiving DVI-D signal
1137                  * ADV7604 selects RGB limited range regardless of
1138                  * input format (CE/IT) in automatic mode */
1139                 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1140                         /* RGB limited range (16-235) */
1141                         io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1142                 } else {
1143                         /* RGB full range (0-255) */
1144                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1145
1146                         if (is_digital_input(sd) && rgb_output) {
1147                                 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1148                         } else {
1149                                 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1150                                 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1151                         }
1152                 }
1153                 break;
1154         case V4L2_DV_RGB_RANGE_LIMITED:
1155                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1156                         /* YCrCb limited range (16-235) */
1157                         io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1158                         break;
1159                 }
1160
1161                 if (y != HDMI_COLORSPACE_RGB)
1162                         break;
1163
1164                 /* RGB limited range (16-235) */
1165                 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1166
1167                 break;
1168         case V4L2_DV_RGB_RANGE_FULL:
1169                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1170                         /* YCrCb full range (0-255) */
1171                         io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1172                         break;
1173                 }
1174
1175                 if (y != HDMI_COLORSPACE_RGB)
1176                         break;
1177
1178                 /* RGB full range (0-255) */
1179                 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1180
1181                 if (is_analog_input(sd) || hdmi_signal)
1182                         break;
1183
1184                 /* Adjust gain/offset for DVI-D signals only */
1185                 if (rgb_output) {
1186                         adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1187                 } else {
1188                         adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1189                         adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1190                 }
1191                 break;
1192         }
1193 }
1194
1195 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1196 {
1197         struct v4l2_subdev *sd =
1198                 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1199
1200         struct adv76xx_state *state = to_state(sd);
1201
1202         switch (ctrl->id) {
1203         case V4L2_CID_BRIGHTNESS:
1204                 cp_write(sd, 0x3c, ctrl->val);
1205                 return 0;
1206         case V4L2_CID_CONTRAST:
1207                 cp_write(sd, 0x3a, ctrl->val);
1208                 return 0;
1209         case V4L2_CID_SATURATION:
1210                 cp_write(sd, 0x3b, ctrl->val);
1211                 return 0;
1212         case V4L2_CID_HUE:
1213                 cp_write(sd, 0x3d, ctrl->val);
1214                 return 0;
1215         case  V4L2_CID_DV_RX_RGB_RANGE:
1216                 state->rgb_quantization_range = ctrl->val;
1217                 set_rgb_quantization_range(sd);
1218                 return 0;
1219         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1220                 if (!adv76xx_has_afe(state))
1221                         return -EINVAL;
1222                 /* Set the analog sampling phase. This is needed to find the
1223                    best sampling phase for analog video: an application or
1224                    driver has to try a number of phases and analyze the picture
1225                    quality before settling on the best performing phase. */
1226                 afe_write(sd, 0xc8, ctrl->val);
1227                 return 0;
1228         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1229                 /* Use the default blue color for free running mode,
1230                    or supply your own. */
1231                 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1232                 return 0;
1233         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1234                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1235                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1236                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1237                 return 0;
1238         }
1239         return -EINVAL;
1240 }
1241
1242 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1243 {
1244         struct v4l2_subdev *sd =
1245                 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1246
1247         if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1248                 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1249                 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1250                         ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1251                 return 0;
1252         }
1253         return -EINVAL;
1254 }
1255
1256 /* ----------------------------------------------------------------------- */
1257
1258 static inline bool no_power(struct v4l2_subdev *sd)
1259 {
1260         /* Entire chip or CP powered off */
1261         return io_read(sd, 0x0c) & 0x24;
1262 }
1263
1264 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1265 {
1266         struct adv76xx_state *state = to_state(sd);
1267
1268         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1269 }
1270
1271 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1272 {
1273         struct adv76xx_state *state = to_state(sd);
1274         const struct adv76xx_chip_info *info = state->info;
1275
1276         return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1277 }
1278
1279 static inline bool is_hdmi(struct v4l2_subdev *sd)
1280 {
1281         return hdmi_read(sd, 0x05) & 0x80;
1282 }
1283
1284 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1285 {
1286         struct adv76xx_state *state = to_state(sd);
1287
1288         /*
1289          * Chips without a AFE don't expose registers for the SSPD, so just assume
1290          * that we have a lock.
1291          */
1292         if (adv76xx_has_afe(state))
1293                 return false;
1294
1295         /* TODO channel 2 */
1296         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1297 }
1298
1299 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1300 {
1301         /* TODO channel 2 */
1302         return !(cp_read(sd, 0xb1) & 0x80);
1303 }
1304
1305 static inline bool no_signal(struct v4l2_subdev *sd)
1306 {
1307         bool ret;
1308
1309         ret = no_power(sd);
1310
1311         ret |= no_lock_stdi(sd);
1312         ret |= no_lock_sspd(sd);
1313
1314         if (is_digital_input(sd)) {
1315                 ret |= no_lock_tmds(sd);
1316                 ret |= no_signal_tmds(sd);
1317         }
1318
1319         return ret;
1320 }
1321
1322 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1323 {
1324         struct adv76xx_state *state = to_state(sd);
1325
1326         if (!adv76xx_has_afe(state))
1327                 return false;
1328
1329         /* CP has detected a non standard number of lines on the incoming
1330            video compared to what it is configured to receive by s_dv_timings */
1331         return io_read(sd, 0x12) & 0x01;
1332 }
1333
1334 static inline bool in_free_run(struct v4l2_subdev *sd)
1335 {
1336         return cp_read(sd, 0xff) & 0x10;
1337 }
1338
1339 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1340 {
1341         *status = 0;
1342         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1343         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1344         if (!in_free_run(sd) && no_lock_cp(sd))
1345                 *status |= is_digital_input(sd) ?
1346                            V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1347
1348         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1349
1350         return 0;
1351 }
1352
1353 /* ----------------------------------------------------------------------- */
1354
1355 struct stdi_readback {
1356         u16 bl, lcf, lcvs;
1357         u8 hs_pol, vs_pol;
1358         bool interlaced;
1359 };
1360
1361 static int stdi2dv_timings(struct v4l2_subdev *sd,
1362                 struct stdi_readback *stdi,
1363                 struct v4l2_dv_timings *timings)
1364 {
1365         struct adv76xx_state *state = to_state(sd);
1366         u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1367         u32 pix_clk;
1368         int i;
1369
1370         for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1371                 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1372
1373                 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1374                                            adv76xx_get_dv_timings_cap(sd, -1),
1375                                            adv76xx_check_dv_timings, NULL))
1376                         continue;
1377                 if (vtotal(bt) != stdi->lcf + 1)
1378                         continue;
1379                 if (bt->vsync != stdi->lcvs)
1380                         continue;
1381
1382                 pix_clk = hfreq * htotal(bt);
1383
1384                 if ((pix_clk < bt->pixelclock + 1000000) &&
1385                     (pix_clk > bt->pixelclock - 1000000)) {
1386                         *timings = v4l2_dv_timings_presets[i];
1387                         return 0;
1388                 }
1389         }
1390
1391         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1392                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1393                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1394                         false, timings))
1395                 return 0;
1396         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1397                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1398                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1399                         false, state->aspect_ratio, timings))
1400                 return 0;
1401
1402         v4l2_dbg(2, debug, sd,
1403                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1404                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1405                 stdi->hs_pol, stdi->vs_pol);
1406         return -1;
1407 }
1408
1409
1410 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1411 {
1412         struct adv76xx_state *state = to_state(sd);
1413         const struct adv76xx_chip_info *info = state->info;
1414         u8 polarity;
1415
1416         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1417                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1418                 return -1;
1419         }
1420
1421         /* read STDI */
1422         stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1423         stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1424         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1425         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1426
1427         if (adv76xx_has_afe(state)) {
1428                 /* read SSPD */
1429                 polarity = cp_read(sd, 0xb5);
1430                 if ((polarity & 0x03) == 0x01) {
1431                         stdi->hs_pol = polarity & 0x10
1432                                      ? (polarity & 0x08 ? '+' : '-') : 'x';
1433                         stdi->vs_pol = polarity & 0x40
1434                                      ? (polarity & 0x20 ? '+' : '-') : 'x';
1435                 } else {
1436                         stdi->hs_pol = 'x';
1437                         stdi->vs_pol = 'x';
1438                 }
1439         } else {
1440                 polarity = hdmi_read(sd, 0x05);
1441                 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1442                 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1443         }
1444
1445         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1446                 v4l2_dbg(2, debug, sd,
1447                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1448                 return -1;
1449         }
1450
1451         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1452                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1453                 memset(stdi, 0, sizeof(struct stdi_readback));
1454                 return -1;
1455         }
1456
1457         v4l2_dbg(2, debug, sd,
1458                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1459                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1460                 stdi->hs_pol, stdi->vs_pol,
1461                 stdi->interlaced ? "interlaced" : "progressive");
1462
1463         return 0;
1464 }
1465
1466 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1467                         struct v4l2_enum_dv_timings *timings)
1468 {
1469         struct adv76xx_state *state = to_state(sd);
1470
1471         if (timings->pad >= state->source_pad)
1472                 return -EINVAL;
1473
1474         return v4l2_enum_dv_timings_cap(timings,
1475                 adv76xx_get_dv_timings_cap(sd, timings->pad),
1476                 adv76xx_check_dv_timings, NULL);
1477 }
1478
1479 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1480                         struct v4l2_dv_timings_cap *cap)
1481 {
1482         struct adv76xx_state *state = to_state(sd);
1483         unsigned int pad = cap->pad;
1484
1485         if (cap->pad >= state->source_pad)
1486                 return -EINVAL;
1487
1488         *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1489         cap->pad = pad;
1490
1491         return 0;
1492 }
1493
1494 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1495    if the format is listed in adv76xx_timings[] */
1496 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1497                 struct v4l2_dv_timings *timings)
1498 {
1499         v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1500                                  is_digital_input(sd) ? 250000 : 1000000,
1501                                  adv76xx_check_dv_timings, NULL);
1502 }
1503
1504 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1505 {
1506         unsigned int freq;
1507         int a, b;
1508
1509         a = hdmi_read(sd, 0x06);
1510         b = hdmi_read(sd, 0x3b);
1511         if (a < 0 || b < 0)
1512                 return 0;
1513         freq =  a * 1000000 + ((b & 0x30) >> 4) * 250000;
1514
1515         if (is_hdmi(sd)) {
1516                 /* adjust for deep color mode */
1517                 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1518
1519                 freq = freq * 8 / bits_per_channel;
1520         }
1521
1522         return freq;
1523 }
1524
1525 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1526 {
1527         int a, b;
1528
1529         a = hdmi_read(sd, 0x51);
1530         b = hdmi_read(sd, 0x52);
1531         if (a < 0 || b < 0)
1532                 return 0;
1533         return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1534 }
1535
1536 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1537                         struct v4l2_dv_timings *timings)
1538 {
1539         struct adv76xx_state *state = to_state(sd);
1540         const struct adv76xx_chip_info *info = state->info;
1541         struct v4l2_bt_timings *bt = &timings->bt;
1542         struct stdi_readback stdi;
1543
1544         if (!timings)
1545                 return -EINVAL;
1546
1547         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1548
1549         if (no_signal(sd)) {
1550                 state->restart_stdi_once = true;
1551                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1552                 return -ENOLINK;
1553         }
1554
1555         /* read STDI */
1556         if (read_stdi(sd, &stdi)) {
1557                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1558                 return -ENOLINK;
1559         }
1560         bt->interlaced = stdi.interlaced ?
1561                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1562
1563         if (is_digital_input(sd)) {
1564                 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1565                 u8 vic = 0;
1566                 u32 w, h;
1567
1568                 w = hdmi_read16(sd, 0x07, info->linewidth_mask);
1569                 h = hdmi_read16(sd, 0x09, info->field0_height_mask);
1570
1571                 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1572                         vic = infoframe_read(sd, 0x04);
1573
1574                 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&
1575                     bt->width == w && bt->height == h)
1576                         goto found;
1577
1578                 timings->type = V4L2_DV_BT_656_1120;
1579
1580                 bt->width = w;
1581                 bt->height = h;
1582                 bt->pixelclock = info->read_hdmi_pixelclock(sd);
1583                 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1584                 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1585                 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1586                 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1587                         info->field0_vfrontporch_mask) / 2;
1588                 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1589                 bt->vbackporch = hdmi_read16(sd, 0x32,
1590                         info->field0_vbackporch_mask) / 2;
1591                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1592                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1593                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1594                         bt->height += hdmi_read16(sd, 0x0b,
1595                                 info->field1_height_mask);
1596                         bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1597                                 info->field1_vfrontporch_mask) / 2;
1598                         bt->il_vsync = hdmi_read16(sd, 0x30,
1599                                 info->field1_vsync_mask) / 2;
1600                         bt->il_vbackporch = hdmi_read16(sd, 0x34,
1601                                 info->field1_vbackporch_mask) / 2;
1602                 }
1603                 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1604         } else {
1605                 /* find format
1606                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1607                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1608                  */
1609                 if (!stdi2dv_timings(sd, &stdi, timings))
1610                         goto found;
1611                 stdi.lcvs += 1;
1612                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1613                 if (!stdi2dv_timings(sd, &stdi, timings))
1614                         goto found;
1615                 stdi.lcvs -= 2;
1616                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1617                 if (stdi2dv_timings(sd, &stdi, timings)) {
1618                         /*
1619                          * The STDI block may measure wrong values, especially
1620                          * for lcvs and lcf. If the driver can not find any
1621                          * valid timing, the STDI block is restarted to measure
1622                          * the video timings again. The function will return an
1623                          * error, but the restart of STDI will generate a new
1624                          * STDI interrupt and the format detection process will
1625                          * restart.
1626                          */
1627                         if (state->restart_stdi_once) {
1628                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1629                                 /* TODO restart STDI for Sync Channel 2 */
1630                                 /* enter one-shot mode */
1631                                 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1632                                 /* trigger STDI restart */
1633                                 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1634                                 /* reset to continuous mode */
1635                                 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1636                                 state->restart_stdi_once = false;
1637                                 return -ENOLINK;
1638                         }
1639                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1640                         return -ERANGE;
1641                 }
1642                 state->restart_stdi_once = true;
1643         }
1644 found:
1645
1646         if (no_signal(sd)) {
1647                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1648                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1649                 return -ENOLINK;
1650         }
1651
1652         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1653                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1654                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1655                                 __func__, (u32)bt->pixelclock);
1656                 return -ERANGE;
1657         }
1658
1659         if (debug > 1)
1660                 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1661                                       timings, true);
1662
1663         return 0;
1664 }
1665
1666 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1667                 struct v4l2_dv_timings *timings)
1668 {
1669         struct adv76xx_state *state = to_state(sd);
1670         struct v4l2_bt_timings *bt;
1671         int err;
1672
1673         if (!timings)
1674                 return -EINVAL;
1675
1676         if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1677                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1678                 return 0;
1679         }
1680
1681         bt = &timings->bt;
1682
1683         if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1684                                    adv76xx_check_dv_timings, NULL))
1685                 return -ERANGE;
1686
1687         adv76xx_fill_optional_dv_timings_fields(sd, timings);
1688
1689         state->timings = *timings;
1690
1691         cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1692
1693         /* Use prim_mode and vid_std when available */
1694         err = configure_predefined_video_timings(sd, timings);
1695         if (err) {
1696                 /* custom settings when the video format
1697                  does not have prim_mode/vid_std */
1698                 configure_custom_video_timings(sd, bt);
1699         }
1700
1701         set_rgb_quantization_range(sd);
1702
1703         if (debug > 1)
1704                 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1705                                       timings, true);
1706         return 0;
1707 }
1708
1709 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1710                 struct v4l2_dv_timings *timings)
1711 {
1712         struct adv76xx_state *state = to_state(sd);
1713
1714         *timings = state->timings;
1715         return 0;
1716 }
1717
1718 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1719 {
1720         hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1721 }
1722
1723 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1724 {
1725         hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1726 }
1727
1728 static void enable_input(struct v4l2_subdev *sd)
1729 {
1730         struct adv76xx_state *state = to_state(sd);
1731
1732         if (is_analog_input(sd)) {
1733                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1734         } else if (is_digital_input(sd)) {
1735                 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1736                 state->info->set_termination(sd, true);
1737                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1738                 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1739         } else {
1740                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1741                                 __func__, state->selected_input);
1742         }
1743 }
1744
1745 static void disable_input(struct v4l2_subdev *sd)
1746 {
1747         struct adv76xx_state *state = to_state(sd);
1748
1749         hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1750         msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1751         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1752         state->info->set_termination(sd, false);
1753 }
1754
1755 static void select_input(struct v4l2_subdev *sd)
1756 {
1757         struct adv76xx_state *state = to_state(sd);
1758         const struct adv76xx_chip_info *info = state->info;
1759
1760         if (is_analog_input(sd)) {
1761                 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1762
1763                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1764                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1765                 afe_write(sd, 0xc8, 0x00); /* phase control */
1766         } else if (is_digital_input(sd)) {
1767                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1768
1769                 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1770
1771                 if (adv76xx_has_afe(state)) {
1772                         afe_write(sd, 0x00, 0xff); /* power down ADC */
1773                         afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1774                         afe_write(sd, 0xc8, 0x40); /* phase control */
1775                 }
1776
1777                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1778                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1779                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1780         } else {
1781                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1782                                 __func__, state->selected_input);
1783         }
1784 }
1785
1786 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1787                 u32 input, u32 output, u32 config)
1788 {
1789         struct adv76xx_state *state = to_state(sd);
1790
1791         v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1792                         __func__, input, state->selected_input);
1793
1794         if (input == state->selected_input)
1795                 return 0;
1796
1797         if (input > state->info->max_port)
1798                 return -EINVAL;
1799
1800         state->selected_input = input;
1801
1802         disable_input(sd);
1803         select_input(sd);
1804         enable_input(sd);
1805
1806         v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1807
1808         return 0;
1809 }
1810
1811 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1812                                   struct v4l2_subdev_pad_config *cfg,
1813                                   struct v4l2_subdev_mbus_code_enum *code)
1814 {
1815         struct adv76xx_state *state = to_state(sd);
1816
1817         if (code->index >= state->info->nformats)
1818                 return -EINVAL;
1819
1820         code->code = state->info->formats[code->index].code;
1821
1822         return 0;
1823 }
1824
1825 static void adv76xx_fill_format(struct adv76xx_state *state,
1826                                 struct v4l2_mbus_framefmt *format)
1827 {
1828         memset(format, 0, sizeof(*format));
1829
1830         format->width = state->timings.bt.width;
1831         format->height = state->timings.bt.height;
1832         format->field = V4L2_FIELD_NONE;
1833         format->colorspace = V4L2_COLORSPACE_SRGB;
1834
1835         if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1836                 format->colorspace = (state->timings.bt.height <= 576) ?
1837                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1838 }
1839
1840 /*
1841  * Compute the op_ch_sel value required to obtain on the bus the component order
1842  * corresponding to the selected format taking into account bus reordering
1843  * applied by the board at the output of the device.
1844  *
1845  * The following table gives the op_ch_value from the format component order
1846  * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1847  * adv76xx_bus_order value in row).
1848  *
1849  *           |  GBR(0)  GRB(1)  BGR(2)  RGB(3)  BRG(4)  RBG(5)
1850  * ----------+-------------------------------------------------
1851  * RGB (NOP) |  GBR     GRB     BGR     RGB     BRG     RBG
1852  * GRB (1-2) |  BGR     RGB     GBR     GRB     RBG     BRG
1853  * RBG (2-3) |  GRB     GBR     BRG     RBG     BGR     RGB
1854  * BGR (1-3) |  RBG     BRG     RGB     BGR     GRB     GBR
1855  * BRG (ROR) |  BRG     RBG     GRB     GBR     RGB     BGR
1856  * GBR (ROL) |  RGB     BGR     RBG     BRG     GBR     GRB
1857  */
1858 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1859 {
1860 #define _SEL(a,b,c,d,e,f)       { \
1861         ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1862         ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1863 #define _BUS(x)                 [ADV7604_BUS_ORDER_##x]
1864
1865         static const unsigned int op_ch_sel[6][6] = {
1866                 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1867                 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1868                 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1869                 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1870                 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1871                 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1872         };
1873
1874         return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1875 }
1876
1877 static void adv76xx_setup_format(struct adv76xx_state *state)
1878 {
1879         struct v4l2_subdev *sd = &state->sd;
1880
1881         io_write_clr_set(sd, 0x02, 0x02,
1882                         state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1883         io_write(sd, 0x03, state->format->op_format_sel |
1884                  state->pdata.op_format_mode_sel);
1885         io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1886         io_write_clr_set(sd, 0x05, 0x01,
1887                         state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1888         set_rgb_quantization_range(sd);
1889 }
1890
1891 static int adv76xx_get_format(struct v4l2_subdev *sd,
1892                               struct v4l2_subdev_pad_config *cfg,
1893                               struct v4l2_subdev_format *format)
1894 {
1895         struct adv76xx_state *state = to_state(sd);
1896
1897         if (format->pad != state->source_pad)
1898                 return -EINVAL;
1899
1900         adv76xx_fill_format(state, &format->format);
1901
1902         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1903                 struct v4l2_mbus_framefmt *fmt;
1904
1905                 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1906                 format->format.code = fmt->code;
1907         } else {
1908                 format->format.code = state->format->code;
1909         }
1910
1911         return 0;
1912 }
1913
1914 static int adv76xx_get_selection(struct v4l2_subdev *sd,
1915                                  struct v4l2_subdev_pad_config *cfg,
1916                                  struct v4l2_subdev_selection *sel)
1917 {
1918         struct adv76xx_state *state = to_state(sd);
1919
1920         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1921                 return -EINVAL;
1922         /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1923         if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1924                 return -EINVAL;
1925
1926         sel->r.left     = 0;
1927         sel->r.top      = 0;
1928         sel->r.width    = state->timings.bt.width;
1929         sel->r.height   = state->timings.bt.height;
1930
1931         return 0;
1932 }
1933
1934 static int adv76xx_set_format(struct v4l2_subdev *sd,
1935                               struct v4l2_subdev_pad_config *cfg,
1936                               struct v4l2_subdev_format *format)
1937 {
1938         struct adv76xx_state *state = to_state(sd);
1939         const struct adv76xx_format_info *info;
1940
1941         if (format->pad != state->source_pad)
1942                 return -EINVAL;
1943
1944         info = adv76xx_format_info(state, format->format.code);
1945         if (!info)
1946                 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1947
1948         adv76xx_fill_format(state, &format->format);
1949         format->format.code = info->code;
1950
1951         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1952                 struct v4l2_mbus_framefmt *fmt;
1953
1954                 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1955                 fmt->code = format->format.code;
1956         } else {
1957                 state->format = info;
1958                 adv76xx_setup_format(state);
1959         }
1960
1961         return 0;
1962 }
1963
1964 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
1965 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
1966 {
1967         struct adv76xx_state *state = to_state(sd);
1968
1969         if ((cec_read(sd, 0x11) & 0x01) == 0) {
1970                 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
1971                 return;
1972         }
1973
1974         if (tx_raw_status & 0x02) {
1975                 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
1976                          __func__);
1977                 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
1978                                   1, 0, 0, 0);
1979                 return;
1980         }
1981         if (tx_raw_status & 0x04) {
1982                 u8 status;
1983                 u8 nack_cnt;
1984                 u8 low_drive_cnt;
1985
1986                 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
1987                 /*
1988                  * We set this status bit since this hardware performs
1989                  * retransmissions.
1990                  */
1991                 status = CEC_TX_STATUS_MAX_RETRIES;
1992                 nack_cnt = cec_read(sd, 0x14) & 0xf;
1993                 if (nack_cnt)
1994                         status |= CEC_TX_STATUS_NACK;
1995                 low_drive_cnt = cec_read(sd, 0x14) >> 4;
1996                 if (low_drive_cnt)
1997                         status |= CEC_TX_STATUS_LOW_DRIVE;
1998                 cec_transmit_done(state->cec_adap, status,
1999                                   0, nack_cnt, low_drive_cnt, 0);
2000                 return;
2001         }
2002         if (tx_raw_status & 0x01) {
2003                 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2004                 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2005                 return;
2006         }
2007 }
2008
2009 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
2010 {
2011         struct adv76xx_state *state = to_state(sd);
2012         const struct adv76xx_chip_info *info = state->info;
2013         u8 cec_irq;
2014
2015         /* cec controller */
2016         cec_irq = io_read(sd, info->cec_irq_status) & 0x0f;
2017         if (!cec_irq)
2018                 return;
2019
2020         v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2021         adv76xx_cec_tx_raw_status(sd, cec_irq);
2022         if (cec_irq & 0x08) {
2023                 struct cec_msg msg;
2024
2025                 msg.len = cec_read(sd, 0x25) & 0x1f;
2026                 if (msg.len > 16)
2027                         msg.len = 16;
2028
2029                 if (msg.len) {
2030                         u8 i;
2031
2032                         for (i = 0; i < msg.len; i++)
2033                                 msg.msg[i] = cec_read(sd, i + 0x15);
2034                         cec_write(sd, info->cec_rx_enable,
2035                                   info->cec_rx_enable_mask); /* re-enable rx */
2036                         cec_received_msg(state->cec_adap, &msg);
2037                 }
2038         }
2039
2040         if (info->cec_irq_swap) {
2041                 /*
2042                  * Note: the bit order is swapped between 0x4d and 0x4e
2043                  * on adv7604
2044                  */
2045                 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
2046                           ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
2047         }
2048         io_write(sd, info->cec_irq_status + 1, cec_irq);
2049
2050         if (handled)
2051                 *handled = true;
2052 }
2053
2054 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
2055 {
2056         struct adv76xx_state *state = cec_get_drvdata(adap);
2057         const struct adv76xx_chip_info *info = state->info;
2058         struct v4l2_subdev *sd = &state->sd;
2059
2060         if (!state->cec_enabled_adap && enable) {
2061                 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2062                 cec_write(sd, 0x2c, 0x01);      /* cec soft reset */
2063                 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2064                 /* enabled irqs: */
2065                 /* tx: ready */
2066                 /* tx: arbitration lost */
2067                 /* tx: retry timeout */
2068                 /* rx: ready */
2069                 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f);
2070                 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask);
2071         } else if (state->cec_enabled_adap && !enable) {
2072                 /* disable cec interrupts */
2073                 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00);
2074                 /* disable address mask 1-3 */
2075                 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2076                 /* power down cec section */
2077                 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2078                 state->cec_valid_addrs = 0;
2079         }
2080         state->cec_enabled_adap = enable;
2081         adv76xx_s_detect_tx_5v_ctrl(sd);
2082         return 0;
2083 }
2084
2085 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2086 {
2087         struct adv76xx_state *state = cec_get_drvdata(adap);
2088         struct v4l2_subdev *sd = &state->sd;
2089         unsigned int i, free_idx = ADV76XX_MAX_ADDRS;
2090
2091         if (!state->cec_enabled_adap)
2092                 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2093
2094         if (addr == CEC_LOG_ADDR_INVALID) {
2095                 cec_write_clr_set(sd, 0x27, 0x70, 0);
2096                 state->cec_valid_addrs = 0;
2097                 return 0;
2098         }
2099
2100         for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2101                 bool is_valid = state->cec_valid_addrs & (1 << i);
2102
2103                 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
2104                         free_idx = i;
2105                 if (is_valid && state->cec_addr[i] == addr)
2106                         return 0;
2107         }
2108         if (i == ADV76XX_MAX_ADDRS) {
2109                 i = free_idx;
2110                 if (i == ADV76XX_MAX_ADDRS)
2111                         return -ENXIO;
2112         }
2113         state->cec_addr[i] = addr;
2114         state->cec_valid_addrs |= 1 << i;
2115
2116         switch (i) {
2117         case 0:
2118                 /* enable address mask 0 */
2119                 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2120                 /* set address for mask 0 */
2121                 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2122                 break;
2123         case 1:
2124                 /* enable address mask 1 */
2125                 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2126                 /* set address for mask 1 */
2127                 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2128                 break;
2129         case 2:
2130                 /* enable address mask 2 */
2131                 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2132                 /* set address for mask 1 */
2133                 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2134                 break;
2135         }
2136         return 0;
2137 }
2138
2139 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2140                                      u32 signal_free_time, struct cec_msg *msg)
2141 {
2142         struct adv76xx_state *state = cec_get_drvdata(adap);
2143         struct v4l2_subdev *sd = &state->sd;
2144         u8 len = msg->len;
2145         unsigned int i;
2146
2147         /*
2148          * The number of retries is the number of attempts - 1, but retry
2149          * at least once. It's not clear if a value of 0 is allowed, so
2150          * let's do at least one retry.
2151          */
2152         cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2153
2154         if (len > 16) {
2155                 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2156                 return -EINVAL;
2157         }
2158
2159         /* write data */
2160         for (i = 0; i < len; i++)
2161                 cec_write(sd, i, msg->msg[i]);
2162
2163         /* set length (data + header) */
2164         cec_write(sd, 0x10, len);
2165         /* start transmit, enable tx */
2166         cec_write(sd, 0x11, 0x01);
2167         return 0;
2168 }
2169
2170 static const struct cec_adap_ops adv76xx_cec_adap_ops = {
2171         .adap_enable = adv76xx_cec_adap_enable,
2172         .adap_log_addr = adv76xx_cec_adap_log_addr,
2173         .adap_transmit = adv76xx_cec_adap_transmit,
2174 };
2175 #endif
2176
2177 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2178 {
2179         struct adv76xx_state *state = to_state(sd);
2180         const struct adv76xx_chip_info *info = state->info;
2181         const u8 irq_reg_0x43 = io_read(sd, 0x43);
2182         const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2183         const u8 irq_reg_0x70 = io_read(sd, 0x70);
2184         u8 fmt_change_digital;
2185         u8 fmt_change;
2186         u8 tx_5v;
2187
2188         if (irq_reg_0x43)
2189                 io_write(sd, 0x44, irq_reg_0x43);
2190         if (irq_reg_0x70)
2191                 io_write(sd, 0x71, irq_reg_0x70);
2192         if (irq_reg_0x6b)
2193                 io_write(sd, 0x6c, irq_reg_0x6b);
2194
2195         v4l2_dbg(2, debug, sd, "%s: ", __func__);
2196
2197         /* format change */
2198         fmt_change = irq_reg_0x43 & 0x98;
2199         fmt_change_digital = is_digital_input(sd)
2200                            ? irq_reg_0x6b & info->fmt_change_digital_mask
2201                            : 0;
2202
2203         if (fmt_change || fmt_change_digital) {
2204                 v4l2_dbg(1, debug, sd,
2205                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
2206                         __func__, fmt_change, fmt_change_digital);
2207
2208                 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2209
2210                 if (handled)
2211                         *handled = true;
2212         }
2213         /* HDMI/DVI mode */
2214         if (irq_reg_0x6b & 0x01) {
2215                 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2216                         (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2217                 set_rgb_quantization_range(sd);
2218                 if (handled)
2219                         *handled = true;
2220         }
2221
2222 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
2223         /* cec */
2224         adv76xx_cec_isr(sd, handled);
2225 #endif
2226
2227         /* tx 5v detect */
2228         tx_5v = irq_reg_0x70 & info->cable_det_mask;
2229         if (tx_5v) {
2230                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2231                 adv76xx_s_detect_tx_5v_ctrl(sd);
2232                 if (handled)
2233                         *handled = true;
2234         }
2235         return 0;
2236 }
2237
2238 static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id)
2239 {
2240         struct adv76xx_state *state = dev_id;
2241         bool handled = false;
2242
2243         adv76xx_isr(&state->sd, 0, &handled);
2244
2245         return handled ? IRQ_HANDLED : IRQ_NONE;
2246 }
2247
2248 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2249 {
2250         struct adv76xx_state *state = to_state(sd);
2251         u8 *data = NULL;
2252
2253         memset(edid->reserved, 0, sizeof(edid->reserved));
2254
2255         switch (edid->pad) {
2256         case ADV76XX_PAD_HDMI_PORT_A:
2257         case ADV7604_PAD_HDMI_PORT_B:
2258         case ADV7604_PAD_HDMI_PORT_C:
2259         case ADV7604_PAD_HDMI_PORT_D:
2260                 if (state->edid.present & (1 << edid->pad))
2261                         data = state->edid.edid;
2262                 break;
2263         default:
2264                 return -EINVAL;
2265         }
2266
2267         if (edid->start_block == 0 && edid->blocks == 0) {
2268                 edid->blocks = data ? state->edid.blocks : 0;
2269                 return 0;
2270         }
2271
2272         if (!data)
2273                 return -ENODATA;
2274
2275         if (edid->start_block >= state->edid.blocks)
2276                 return -EINVAL;
2277
2278         if (edid->start_block + edid->blocks > state->edid.blocks)
2279                 edid->blocks = state->edid.blocks - edid->start_block;
2280
2281         memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2282
2283         return 0;
2284 }
2285
2286 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2287 {
2288         struct adv76xx_state *state = to_state(sd);
2289         const struct adv76xx_chip_info *info = state->info;
2290         unsigned int spa_loc;
2291         u16 pa;
2292         int err;
2293         int i;
2294
2295         memset(edid->reserved, 0, sizeof(edid->reserved));
2296
2297         if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2298                 return -EINVAL;
2299         if (edid->start_block != 0)
2300                 return -EINVAL;
2301         if (edid->blocks == 0) {
2302                 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2303                 state->edid.present &= ~(1 << edid->pad);
2304                 adv76xx_set_hpd(state, state->edid.present);
2305                 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2306
2307                 /* Fall back to a 16:9 aspect ratio */
2308                 state->aspect_ratio.numerator = 16;
2309                 state->aspect_ratio.denominator = 9;
2310
2311                 if (!state->edid.present) {
2312                         state->edid.blocks = 0;
2313                         cec_phys_addr_invalidate(state->cec_adap);
2314                 }
2315
2316                 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2317                                 __func__, edid->pad, state->edid.present);
2318                 return 0;
2319         }
2320         if (edid->blocks > 2) {
2321                 edid->blocks = 2;
2322                 return -E2BIG;
2323         }
2324         pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
2325         err = v4l2_phys_addr_validate(pa, &pa, NULL);
2326         if (err)
2327                 return err;
2328
2329         v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2330                         __func__, edid->pad, state->edid.present);
2331
2332         /* Disable hotplug and I2C access to EDID RAM from DDC port */
2333         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2334         adv76xx_set_hpd(state, 0);
2335         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2336
2337         /*
2338          * Return an error if no location of the source physical address
2339          * was found.
2340          */
2341         if (spa_loc == 0)
2342                 return -EINVAL;
2343
2344         switch (edid->pad) {
2345         case ADV76XX_PAD_HDMI_PORT_A:
2346                 state->spa_port_a[0] = edid->edid[spa_loc];
2347                 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2348                 break;
2349         case ADV7604_PAD_HDMI_PORT_B:
2350                 rep_write(sd, 0x70, edid->edid[spa_loc]);
2351                 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2352                 break;
2353         case ADV7604_PAD_HDMI_PORT_C:
2354                 rep_write(sd, 0x72, edid->edid[spa_loc]);
2355                 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2356                 break;
2357         case ADV7604_PAD_HDMI_PORT_D:
2358                 rep_write(sd, 0x74, edid->edid[spa_loc]);
2359                 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2360                 break;
2361         default:
2362                 return -EINVAL;
2363         }
2364
2365         if (info->type == ADV7604) {
2366                 rep_write(sd, 0x76, spa_loc & 0xff);
2367                 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2368         } else {
2369                 /* ADV7612 Software Manual Rev. A, p. 15 */
2370                 rep_write(sd, 0x70, spa_loc & 0xff);
2371                 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2372         }
2373
2374         edid->edid[spa_loc] = state->spa_port_a[0];
2375         edid->edid[spa_loc + 1] = state->spa_port_a[1];
2376
2377         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2378         state->edid.blocks = edid->blocks;
2379         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2380                         edid->edid[0x16]);
2381         state->edid.present |= 1 << edid->pad;
2382
2383         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2384         if (err < 0) {
2385                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2386                 return err;
2387         }
2388
2389         /* adv76xx calculates the checksums and enables I2C access to internal
2390            EDID RAM from DDC port. */
2391         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2392
2393         for (i = 0; i < 1000; i++) {
2394                 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2395                         break;
2396                 mdelay(1);
2397         }
2398         if (i == 1000) {
2399                 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2400                 return -EIO;
2401         }
2402         cec_s_phys_addr(state->cec_adap, pa, false);
2403
2404         /* enable hotplug after 100 ms */
2405         schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
2406         return 0;
2407 }
2408
2409 /*********** avi info frame CEA-861-E **************/
2410
2411 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2412         { "AVI", 0x01, 0xe0, 0x00 },
2413         { "Audio", 0x02, 0xe3, 0x1c },
2414         { "SDP", 0x04, 0xe6, 0x2a },
2415         { "Vendor", 0x10, 0xec, 0x54 }
2416 };
2417
2418 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2419                                   union hdmi_infoframe *frame)
2420 {
2421         uint8_t buffer[32];
2422         u8 len;
2423         int i;
2424
2425         if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2426                 v4l2_info(sd, "%s infoframe not received\n",
2427                           adv76xx_cri[index].desc);
2428                 return -ENOENT;
2429         }
2430
2431         for (i = 0; i < 3; i++)
2432                 buffer[i] = infoframe_read(sd,
2433                                            adv76xx_cri[index].head_addr + i);
2434
2435         len = buffer[2] + 1;
2436
2437         if (len + 3 > sizeof(buffer)) {
2438                 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2439                          adv76xx_cri[index].desc, len);
2440                 return -ENOENT;
2441         }
2442
2443         for (i = 0; i < len; i++)
2444                 buffer[i + 3] = infoframe_read(sd,
2445                                        adv76xx_cri[index].payload_addr + i);
2446
2447         if (hdmi_infoframe_unpack(frame, buffer, sizeof(buffer)) < 0) {
2448                 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2449                          adv76xx_cri[index].desc);
2450                 return -ENOENT;
2451         }
2452         return 0;
2453 }
2454
2455 static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2456 {
2457         int i;
2458
2459         if (!is_hdmi(sd)) {
2460                 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2461                 return;
2462         }
2463
2464         for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2465                 union hdmi_infoframe frame;
2466                 struct i2c_client *client = v4l2_get_subdevdata(sd);
2467
2468                 if (adv76xx_read_infoframe(sd, i, &frame))
2469                         return;
2470                 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2471         }
2472 }
2473
2474 static int adv76xx_log_status(struct v4l2_subdev *sd)
2475 {
2476         struct adv76xx_state *state = to_state(sd);
2477         const struct adv76xx_chip_info *info = state->info;
2478         struct v4l2_dv_timings timings;
2479         struct stdi_readback stdi;
2480         u8 reg_io_0x02 = io_read(sd, 0x02);
2481         u8 edid_enabled;
2482         u8 cable_det;
2483
2484         static const char * const csc_coeff_sel_rb[16] = {
2485                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2486                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2487                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2488                 "reserved", "reserved", "reserved", "reserved", "manual"
2489         };
2490         static const char * const input_color_space_txt[16] = {
2491                 "RGB limited range (16-235)", "RGB full range (0-255)",
2492                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2493                 "xvYCC Bt.601", "xvYCC Bt.709",
2494                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2495                 "invalid", "invalid", "invalid", "invalid", "invalid",
2496                 "invalid", "invalid", "automatic"
2497         };
2498         static const char * const hdmi_color_space_txt[16] = {
2499                 "RGB limited range (16-235)", "RGB full range (0-255)",
2500                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2501                 "xvYCC Bt.601", "xvYCC Bt.709",
2502                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2503                 "sYCC", "opYCC 601", "opRGB", "invalid", "invalid",
2504                 "invalid", "invalid", "invalid"
2505         };
2506         static const char * const rgb_quantization_range_txt[] = {
2507                 "Automatic",
2508                 "RGB limited range (16-235)",
2509                 "RGB full range (0-255)",
2510         };
2511         static const char * const deep_color_mode_txt[4] = {
2512                 "8-bits per channel",
2513                 "10-bits per channel",
2514                 "12-bits per channel",
2515                 "16-bits per channel (not supported)"
2516         };
2517
2518         v4l2_info(sd, "-----Chip status-----\n");
2519         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2520         edid_enabled = rep_read(sd, info->edid_status_reg);
2521         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2522                         ((edid_enabled & 0x01) ? "Yes" : "No"),
2523                         ((edid_enabled & 0x02) ? "Yes" : "No"),
2524                         ((edid_enabled & 0x04) ? "Yes" : "No"),
2525                         ((edid_enabled & 0x08) ? "Yes" : "No"));
2526         v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2527                         "enabled" : "disabled");
2528         if (state->cec_enabled_adap) {
2529                 int i;
2530
2531                 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2532                         bool is_valid = state->cec_valid_addrs & (1 << i);
2533
2534                         if (is_valid)
2535                                 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2536                                           state->cec_addr[i]);
2537                 }
2538         }
2539
2540         v4l2_info(sd, "-----Signal status-----\n");
2541         cable_det = info->read_cable_det(sd);
2542         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2543                         ((cable_det & 0x01) ? "Yes" : "No"),
2544                         ((cable_det & 0x02) ? "Yes" : "No"),
2545                         ((cable_det & 0x04) ? "Yes" : "No"),
2546                         ((cable_det & 0x08) ? "Yes" : "No"));
2547         v4l2_info(sd, "TMDS signal detected: %s\n",
2548                         no_signal_tmds(sd) ? "false" : "true");
2549         v4l2_info(sd, "TMDS signal locked: %s\n",
2550                         no_lock_tmds(sd) ? "false" : "true");
2551         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2552         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2553         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2554         v4l2_info(sd, "CP free run: %s\n",
2555                         (in_free_run(sd)) ? "on" : "off");
2556         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2557                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2558                         (io_read(sd, 0x01) & 0x70) >> 4);
2559
2560         v4l2_info(sd, "-----Video Timings-----\n");
2561         if (read_stdi(sd, &stdi))
2562                 v4l2_info(sd, "STDI: not locked\n");
2563         else
2564                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2565                                 stdi.lcf, stdi.bl, stdi.lcvs,
2566                                 stdi.interlaced ? "interlaced" : "progressive",
2567                                 stdi.hs_pol, stdi.vs_pol);
2568         if (adv76xx_query_dv_timings(sd, &timings))
2569                 v4l2_info(sd, "No video detected\n");
2570         else
2571                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2572                                       &timings, true);
2573         v4l2_print_dv_timings(sd->name, "Configured format: ",
2574                               &state->timings, true);
2575
2576         if (no_signal(sd))
2577                 return 0;
2578
2579         v4l2_info(sd, "-----Color space-----\n");
2580         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2581                         rgb_quantization_range_txt[state->rgb_quantization_range]);
2582         v4l2_info(sd, "Input color space: %s\n",
2583                         input_color_space_txt[reg_io_0x02 >> 4]);
2584         v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2585                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2586                         (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2587                                 "(16-235)" : "(0-255)",
2588                         (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2589         v4l2_info(sd, "Color space conversion: %s\n",
2590                         csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2591
2592         if (!is_digital_input(sd))
2593                 return 0;
2594
2595         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2596         v4l2_info(sd, "Digital video port selected: %c\n",
2597                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
2598         v4l2_info(sd, "HDCP encrypted content: %s\n",
2599                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2600         v4l2_info(sd, "HDCP keys read: %s%s\n",
2601                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2602                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2603         if (is_hdmi(sd)) {
2604                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2605                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2606                 bool audio_mute = io_read(sd, 0x65) & 0x40;
2607
2608                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2609                                 audio_pll_locked ? "locked" : "not locked",
2610                                 audio_sample_packet_detect ? "detected" : "not detected",
2611                                 audio_mute ? "muted" : "enabled");
2612                 if (audio_pll_locked && audio_sample_packet_detect) {
2613                         v4l2_info(sd, "Audio format: %s\n",
2614                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2615                 }
2616                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2617                                 (hdmi_read(sd, 0x5c) << 8) +
2618                                 (hdmi_read(sd, 0x5d) & 0xf0));
2619                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2620                                 (hdmi_read(sd, 0x5e) << 8) +
2621                                 hdmi_read(sd, 0x5f));
2622                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2623
2624                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2625                 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2626
2627                 adv76xx_log_infoframes(sd);
2628         }
2629
2630         return 0;
2631 }
2632
2633 static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2634                                    struct v4l2_fh *fh,
2635                                    struct v4l2_event_subscription *sub)
2636 {
2637         switch (sub->type) {
2638         case V4L2_EVENT_SOURCE_CHANGE:
2639                 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2640         case V4L2_EVENT_CTRL:
2641                 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2642         default:
2643                 return -EINVAL;
2644         }
2645 }
2646
2647 static int adv76xx_registered(struct v4l2_subdev *sd)
2648 {
2649         struct adv76xx_state *state = to_state(sd);
2650         struct i2c_client *client = v4l2_get_subdevdata(sd);
2651         int err;
2652
2653         err = cec_register_adapter(state->cec_adap, &client->dev);
2654         if (err)
2655                 cec_delete_adapter(state->cec_adap);
2656         return err;
2657 }
2658
2659 static void adv76xx_unregistered(struct v4l2_subdev *sd)
2660 {
2661         struct adv76xx_state *state = to_state(sd);
2662
2663         cec_unregister_adapter(state->cec_adap);
2664 }
2665
2666 /* ----------------------------------------------------------------------- */
2667
2668 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2669         .s_ctrl = adv76xx_s_ctrl,
2670         .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2671 };
2672
2673 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2674         .log_status = adv76xx_log_status,
2675         .interrupt_service_routine = adv76xx_isr,
2676         .subscribe_event = adv76xx_subscribe_event,
2677         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2678 #ifdef CONFIG_VIDEO_ADV_DEBUG
2679         .g_register = adv76xx_g_register,
2680         .s_register = adv76xx_s_register,
2681 #endif
2682 };
2683
2684 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2685         .s_routing = adv76xx_s_routing,
2686         .g_input_status = adv76xx_g_input_status,
2687         .s_dv_timings = adv76xx_s_dv_timings,
2688         .g_dv_timings = adv76xx_g_dv_timings,
2689         .query_dv_timings = adv76xx_query_dv_timings,
2690 };
2691
2692 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2693         .enum_mbus_code = adv76xx_enum_mbus_code,
2694         .get_selection = adv76xx_get_selection,
2695         .get_fmt = adv76xx_get_format,
2696         .set_fmt = adv76xx_set_format,
2697         .get_edid = adv76xx_get_edid,
2698         .set_edid = adv76xx_set_edid,
2699         .dv_timings_cap = adv76xx_dv_timings_cap,
2700         .enum_dv_timings = adv76xx_enum_dv_timings,
2701 };
2702
2703 static const struct v4l2_subdev_ops adv76xx_ops = {
2704         .core = &adv76xx_core_ops,
2705         .video = &adv76xx_video_ops,
2706         .pad = &adv76xx_pad_ops,
2707 };
2708
2709 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
2710         .registered = adv76xx_registered,
2711         .unregistered = adv76xx_unregistered,
2712 };
2713
2714 /* -------------------------- custom ctrls ---------------------------------- */
2715
2716 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2717         .ops = &adv76xx_ctrl_ops,
2718         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2719         .name = "Analog Sampling Phase",
2720         .type = V4L2_CTRL_TYPE_INTEGER,
2721         .min = 0,
2722         .max = 0x1f,
2723         .step = 1,
2724         .def = 0,
2725 };
2726
2727 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2728         .ops = &adv76xx_ctrl_ops,
2729         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2730         .name = "Free Running Color, Manual",
2731         .type = V4L2_CTRL_TYPE_BOOLEAN,
2732         .min = false,
2733         .max = true,
2734         .step = 1,
2735         .def = false,
2736 };
2737
2738 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2739         .ops = &adv76xx_ctrl_ops,
2740         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2741         .name = "Free Running Color",
2742         .type = V4L2_CTRL_TYPE_INTEGER,
2743         .min = 0x0,
2744         .max = 0xffffff,
2745         .step = 0x1,
2746         .def = 0x0,
2747 };
2748
2749 /* ----------------------------------------------------------------------- */
2750
2751 struct adv76xx_register_map {
2752         const char *name;
2753         u8 default_addr;
2754 };
2755
2756 static const struct adv76xx_register_map adv76xx_default_addresses[] = {
2757         [ADV76XX_PAGE_IO] = { "main", 0x4c },
2758         [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 },
2759         [ADV76XX_PAGE_CEC] = { "cec", 0x40 },
2760         [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e },
2761         [ADV7604_PAGE_ESDP] = { "esdp", 0x38 },
2762         [ADV7604_PAGE_DPP] = { "dpp", 0x3c },
2763         [ADV76XX_PAGE_AFE] = { "afe", 0x26 },
2764         [ADV76XX_PAGE_REP] = { "rep", 0x32 },
2765         [ADV76XX_PAGE_EDID] = { "edid", 0x36 },
2766         [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 },
2767         [ADV76XX_PAGE_TEST] = { "test", 0x30 },
2768         [ADV76XX_PAGE_CP] = { "cp", 0x22 },
2769         [ADV7604_PAGE_VDP] = { "vdp", 0x24 },
2770 };
2771
2772 static int adv76xx_core_init(struct v4l2_subdev *sd)
2773 {
2774         struct adv76xx_state *state = to_state(sd);
2775         const struct adv76xx_chip_info *info = state->info;
2776         struct adv76xx_platform_data *pdata = &state->pdata;
2777
2778         hdmi_write(sd, 0x48,
2779                 (pdata->disable_pwrdnb ? 0x80 : 0) |
2780                 (pdata->disable_cable_det_rst ? 0x40 : 0));
2781
2782         disable_input(sd);
2783
2784         if (pdata->default_input >= 0 &&
2785             pdata->default_input < state->source_pad) {
2786                 state->selected_input = pdata->default_input;
2787                 select_input(sd);
2788                 enable_input(sd);
2789         }
2790
2791         /* power */
2792         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2793         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2794         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2795
2796         /* video format */
2797         io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2798         io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2799                         pdata->insert_av_codes << 2 |
2800                         pdata->replicate_av_codes << 1);
2801         adv76xx_setup_format(state);
2802
2803         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2804
2805         /* VS, HS polarities */
2806         io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2807                  pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2808
2809         /* Adjust drive strength */
2810         io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2811                                 pdata->dr_str_clk << 2 |
2812                                 pdata->dr_str_sync);
2813
2814         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2815         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2816         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2817                                       ADI recommended setting [REF_01, c. 2.3.3] */
2818         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2819                                       ADI recommended setting [REF_01, c. 2.3.3] */
2820         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2821                                      for digital formats */
2822
2823         /* HDMI audio */
2824         hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2825         hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2826         hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2827
2828         /* TODO from platform data */
2829         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2830
2831         if (adv76xx_has_afe(state)) {
2832                 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2833                 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2834         }
2835
2836         /* interrupts */
2837         io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2838         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2839         io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2840         io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2841         info->setup_irqs(sd);
2842
2843         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2844 }
2845
2846 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2847 {
2848         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2849 }
2850
2851 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2852 {
2853         io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2854 }
2855
2856 static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2857 {
2858         io_write(sd, 0x41, 0xd0); /* disable INT2 */
2859 }
2860
2861 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2862 {
2863         unsigned int i;
2864
2865         for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i)
2866                 i2c_unregister_device(state->i2c_clients[i]);
2867 }
2868
2869 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2870                                                unsigned int page)
2871 {
2872         struct i2c_client *client = v4l2_get_subdevdata(sd);
2873         struct adv76xx_state *state = to_state(sd);
2874         struct adv76xx_platform_data *pdata = &state->pdata;
2875         unsigned int io_reg = 0xf2 + page;
2876         struct i2c_client *new_client;
2877
2878         if (pdata && pdata->i2c_addresses[page])
2879                 new_client = i2c_new_dummy_device(client->adapter,
2880                                            pdata->i2c_addresses[page]);
2881         else
2882                 new_client = i2c_new_ancillary_device(client,
2883                                 adv76xx_default_addresses[page].name,
2884                                 adv76xx_default_addresses[page].default_addr);
2885
2886         if (!IS_ERR(new_client))
2887                 io_write(sd, io_reg, new_client->addr << 1);
2888
2889         return new_client;
2890 }
2891
2892 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2893         /* reset ADI recommended settings for HDMI: */
2894         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2895         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2896         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2897         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2898         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2899         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2900         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2901         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2902         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2903         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2904         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2905         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2906         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2907
2908         /* set ADI recommended settings for digitizer */
2909         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2910         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2911         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2912         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2913         { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2914         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2915
2916         { ADV76XX_REG_SEQ_TERM, 0 },
2917 };
2918
2919 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2920         /* set ADI recommended settings for HDMI: */
2921         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2922         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2923         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2924         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2925         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2926         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2927         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2928         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2929         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2930         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2931         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2932         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2933
2934         /* reset ADI recommended settings for digitizer */
2935         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2936         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2937         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2938
2939         { ADV76XX_REG_SEQ_TERM, 0 },
2940 };
2941
2942 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2943         /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2944         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2945         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2946         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2947         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2948         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2949         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2950         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2951         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2952         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2953         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2954         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2955
2956         { ADV76XX_REG_SEQ_TERM, 0 },
2957 };
2958
2959 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
2960         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2961         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2962         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2963         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2964         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2965         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2966         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2967         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2968         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2969         { ADV76XX_REG_SEQ_TERM, 0 },
2970 };
2971
2972 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2973         [ADV7604] = {
2974                 .type = ADV7604,
2975                 .has_afe = true,
2976                 .max_port = ADV7604_PAD_VGA_COMP,
2977                 .num_dv_ports = 4,
2978                 .edid_enable_reg = 0x77,
2979                 .edid_status_reg = 0x7d,
2980                 .lcf_reg = 0xb3,
2981                 .tdms_lock_mask = 0xe0,
2982                 .cable_det_mask = 0x1e,
2983                 .fmt_change_digital_mask = 0xc1,
2984                 .cp_csc = 0xfc,
2985                 .cec_irq_status = 0x4d,
2986                 .cec_rx_enable = 0x26,
2987                 .cec_rx_enable_mask = 0x01,
2988                 .cec_irq_swap = true,
2989                 .formats = adv7604_formats,
2990                 .nformats = ARRAY_SIZE(adv7604_formats),
2991                 .set_termination = adv7604_set_termination,
2992                 .setup_irqs = adv7604_setup_irqs,
2993                 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2994                 .read_cable_det = adv7604_read_cable_det,
2995                 .recommended_settings = {
2996                     [0] = adv7604_recommended_settings_afe,
2997                     [1] = adv7604_recommended_settings_hdmi,
2998                 },
2999                 .num_recommended_settings = {
3000                     [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
3001                     [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
3002                 },
3003                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
3004                         BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
3005                         BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
3006                         BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
3007                         BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
3008                         BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
3009                         BIT(ADV7604_PAGE_VDP),
3010                 .linewidth_mask = 0xfff,
3011                 .field0_height_mask = 0xfff,
3012                 .field1_height_mask = 0xfff,
3013                 .hfrontporch_mask = 0x3ff,
3014                 .hsync_mask = 0x3ff,
3015                 .hbackporch_mask = 0x3ff,
3016                 .field0_vfrontporch_mask = 0x1fff,
3017                 .field0_vsync_mask = 0x1fff,
3018                 .field0_vbackporch_mask = 0x1fff,
3019                 .field1_vfrontporch_mask = 0x1fff,
3020                 .field1_vsync_mask = 0x1fff,
3021                 .field1_vbackporch_mask = 0x1fff,
3022         },
3023         [ADV7611] = {
3024                 .type = ADV7611,
3025                 .has_afe = false,
3026                 .max_port = ADV76XX_PAD_HDMI_PORT_A,
3027                 .num_dv_ports = 1,
3028                 .edid_enable_reg = 0x74,
3029                 .edid_status_reg = 0x76,
3030                 .lcf_reg = 0xa3,
3031                 .tdms_lock_mask = 0x43,
3032                 .cable_det_mask = 0x01,
3033                 .fmt_change_digital_mask = 0x03,
3034                 .cp_csc = 0xf4,
3035                 .cec_irq_status = 0x93,
3036                 .cec_rx_enable = 0x2c,
3037                 .cec_rx_enable_mask = 0x02,
3038                 .formats = adv7611_formats,
3039                 .nformats = ARRAY_SIZE(adv7611_formats),
3040                 .set_termination = adv7611_set_termination,
3041                 .setup_irqs = adv7611_setup_irqs,
3042                 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3043                 .read_cable_det = adv7611_read_cable_det,
3044                 .recommended_settings = {
3045                     [1] = adv7611_recommended_settings_hdmi,
3046                 },
3047                 .num_recommended_settings = {
3048                     [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
3049                 },
3050                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3051                         BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3052                         BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
3053                         BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3054                 .linewidth_mask = 0x1fff,
3055                 .field0_height_mask = 0x1fff,
3056                 .field1_height_mask = 0x1fff,
3057                 .hfrontporch_mask = 0x1fff,
3058                 .hsync_mask = 0x1fff,
3059                 .hbackporch_mask = 0x1fff,
3060                 .field0_vfrontporch_mask = 0x3fff,
3061                 .field0_vsync_mask = 0x3fff,
3062                 .field0_vbackporch_mask = 0x3fff,
3063                 .field1_vfrontporch_mask = 0x3fff,
3064                 .field1_vsync_mask = 0x3fff,
3065                 .field1_vbackporch_mask = 0x3fff,
3066         },
3067         [ADV7612] = {
3068                 .type = ADV7612,
3069                 .has_afe = false,
3070                 .max_port = ADV76XX_PAD_HDMI_PORT_A,    /* B not supported */
3071                 .num_dv_ports = 1,                      /* normally 2 */
3072                 .edid_enable_reg = 0x74,
3073                 .edid_status_reg = 0x76,
3074                 .lcf_reg = 0xa3,
3075                 .tdms_lock_mask = 0x43,
3076                 .cable_det_mask = 0x01,
3077                 .fmt_change_digital_mask = 0x03,
3078                 .cp_csc = 0xf4,
3079                 .cec_irq_status = 0x93,
3080                 .cec_rx_enable = 0x2c,
3081                 .cec_rx_enable_mask = 0x02,
3082                 .formats = adv7612_formats,
3083                 .nformats = ARRAY_SIZE(adv7612_formats),
3084                 .set_termination = adv7611_set_termination,
3085                 .setup_irqs = adv7612_setup_irqs,
3086                 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3087                 .read_cable_det = adv7612_read_cable_det,
3088                 .recommended_settings = {
3089                     [1] = adv7612_recommended_settings_hdmi,
3090                 },
3091                 .num_recommended_settings = {
3092                     [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
3093                 },
3094                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3095                         BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3096                         BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
3097                         BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3098                 .linewidth_mask = 0x1fff,
3099                 .field0_height_mask = 0x1fff,
3100                 .field1_height_mask = 0x1fff,
3101                 .hfrontporch_mask = 0x1fff,
3102                 .hsync_mask = 0x1fff,
3103                 .hbackporch_mask = 0x1fff,
3104                 .field0_vfrontporch_mask = 0x3fff,
3105                 .field0_vsync_mask = 0x3fff,
3106                 .field0_vbackporch_mask = 0x3fff,
3107                 .field1_vfrontporch_mask = 0x3fff,
3108                 .field1_vsync_mask = 0x3fff,
3109                 .field1_vbackporch_mask = 0x3fff,
3110         },
3111 };
3112
3113 static const struct i2c_device_id adv76xx_i2c_id[] = {
3114         { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
3115         { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3116         { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3117         { }
3118 };
3119 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3120
3121 static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3122         { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
3123         { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3124         { }
3125 };
3126 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3127
3128 static int adv76xx_parse_dt(struct adv76xx_state *state)
3129 {
3130         struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
3131         struct device_node *endpoint;
3132         struct device_node *np;
3133         unsigned int flags;
3134         int ret;
3135         u32 v;
3136
3137         np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
3138
3139         /* Parse the endpoint. */
3140         endpoint = of_graph_get_next_endpoint(np, NULL);
3141         if (!endpoint)
3142                 return -EINVAL;
3143
3144         ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg);
3145         of_node_put(endpoint);
3146         if (ret)
3147                 return ret;
3148
3149         if (!of_property_read_u32(np, "default-input", &v))
3150                 state->pdata.default_input = v;
3151         else
3152                 state->pdata.default_input = -1;
3153
3154         flags = bus_cfg.bus.parallel.flags;
3155
3156         if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
3157                 state->pdata.inv_hs_pol = 1;
3158
3159         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
3160                 state->pdata.inv_vs_pol = 1;
3161
3162         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
3163                 state->pdata.inv_llc_pol = 1;
3164
3165         if (bus_cfg.bus_type == V4L2_MBUS_BT656)
3166                 state->pdata.insert_av_codes = 1;
3167
3168         /* Disable the interrupt for now as no DT-based board uses it. */
3169         state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH;
3170
3171         /* Hardcode the remaining platform data fields. */
3172         state->pdata.disable_pwrdnb = 0;
3173         state->pdata.disable_cable_det_rst = 0;
3174         state->pdata.blank_data = 1;
3175         state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
3176         state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3177         state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH;
3178         state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH;
3179         state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH;
3180
3181         return 0;
3182 }
3183
3184 static const struct regmap_config adv76xx_regmap_cnf[] = {
3185         {
3186                 .name                   = "io",
3187                 .reg_bits               = 8,
3188                 .val_bits               = 8,
3189
3190                 .max_register           = 0xff,
3191                 .cache_type             = REGCACHE_NONE,
3192         },
3193         {
3194                 .name                   = "avlink",
3195                 .reg_bits               = 8,
3196                 .val_bits               = 8,
3197
3198                 .max_register           = 0xff,
3199                 .cache_type             = REGCACHE_NONE,
3200         },
3201         {
3202                 .name                   = "cec",
3203                 .reg_bits               = 8,
3204                 .val_bits               = 8,
3205
3206                 .max_register           = 0xff,
3207                 .cache_type             = REGCACHE_NONE,
3208         },
3209         {
3210                 .name                   = "infoframe",
3211                 .reg_bits               = 8,
3212                 .val_bits               = 8,
3213
3214                 .max_register           = 0xff,
3215                 .cache_type             = REGCACHE_NONE,
3216         },
3217         {
3218                 .name                   = "esdp",
3219                 .reg_bits               = 8,
3220                 .val_bits               = 8,
3221
3222                 .max_register           = 0xff,
3223                 .cache_type             = REGCACHE_NONE,
3224         },
3225         {
3226                 .name                   = "epp",
3227                 .reg_bits               = 8,
3228                 .val_bits               = 8,
3229
3230                 .max_register           = 0xff,
3231                 .cache_type             = REGCACHE_NONE,
3232         },
3233         {
3234                 .name                   = "afe",
3235                 .reg_bits               = 8,
3236                 .val_bits               = 8,
3237
3238                 .max_register           = 0xff,
3239                 .cache_type             = REGCACHE_NONE,
3240         },
3241         {
3242                 .name                   = "rep",
3243                 .reg_bits               = 8,
3244                 .val_bits               = 8,
3245
3246                 .max_register           = 0xff,
3247                 .cache_type             = REGCACHE_NONE,
3248         },
3249         {
3250                 .name                   = "edid",
3251                 .reg_bits               = 8,
3252                 .val_bits               = 8,
3253
3254                 .max_register           = 0xff,
3255                 .cache_type             = REGCACHE_NONE,
3256         },
3257
3258         {
3259                 .name                   = "hdmi",
3260                 .reg_bits               = 8,
3261                 .val_bits               = 8,
3262
3263                 .max_register           = 0xff,
3264                 .cache_type             = REGCACHE_NONE,
3265         },
3266         {
3267                 .name                   = "test",
3268                 .reg_bits               = 8,
3269                 .val_bits               = 8,
3270
3271                 .max_register           = 0xff,
3272                 .cache_type             = REGCACHE_NONE,
3273         },
3274         {
3275                 .name                   = "cp",
3276                 .reg_bits               = 8,
3277                 .val_bits               = 8,
3278
3279                 .max_register           = 0xff,
3280                 .cache_type             = REGCACHE_NONE,
3281         },
3282         {
3283                 .name                   = "vdp",
3284                 .reg_bits               = 8,
3285                 .val_bits               = 8,
3286
3287                 .max_register           = 0xff,
3288                 .cache_type             = REGCACHE_NONE,
3289         },
3290 };
3291
3292 static int configure_regmap(struct adv76xx_state *state, int region)
3293 {
3294         int err;
3295
3296         if (!state->i2c_clients[region])
3297                 return -ENODEV;
3298
3299         state->regmap[region] =
3300                 devm_regmap_init_i2c(state->i2c_clients[region],
3301                                      &adv76xx_regmap_cnf[region]);
3302
3303         if (IS_ERR(state->regmap[region])) {
3304                 err = PTR_ERR(state->regmap[region]);
3305                 v4l_err(state->i2c_clients[region],
3306                         "Error initializing regmap %d with error %d\n",
3307                         region, err);
3308                 return -EINVAL;
3309         }
3310
3311         return 0;
3312 }
3313
3314 static int configure_regmaps(struct adv76xx_state *state)
3315 {
3316         int i, err;
3317
3318         for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3319                 err = configure_regmap(state, i);
3320                 if (err && (err != -ENODEV))
3321                         return err;
3322         }
3323         return 0;
3324 }
3325
3326 static void adv76xx_reset(struct adv76xx_state *state)
3327 {
3328         if (state->reset_gpio) {
3329                 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
3330                 gpiod_set_value_cansleep(state->reset_gpio, 0);
3331                 usleep_range(5000, 10000);
3332                 gpiod_set_value_cansleep(state->reset_gpio, 1);
3333                 /* It is recommended to wait 5 ms after the low pulse before */
3334                 /* an I2C write is performed to the ADV76XX. */
3335                 usleep_range(5000, 10000);
3336         }
3337 }
3338
3339 static int adv76xx_probe(struct i2c_client *client,
3340                          const struct i2c_device_id *id)
3341 {
3342         static const struct v4l2_dv_timings cea640x480 =
3343                 V4L2_DV_BT_CEA_640X480P59_94;
3344         struct adv76xx_state *state;
3345         struct v4l2_ctrl_handler *hdl;
3346         struct v4l2_ctrl *ctrl;
3347         struct v4l2_subdev *sd;
3348         unsigned int i;
3349         unsigned int val, val2;
3350         int err;
3351
3352         /* Check if the adapter supports the needed features */
3353         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3354                 return -EIO;
3355         v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3356                         client->addr << 1);
3357
3358         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3359         if (!state)
3360                 return -ENOMEM;
3361
3362         state->i2c_clients[ADV76XX_PAGE_IO] = client;
3363
3364         /* initialize variables */
3365         state->restart_stdi_once = true;
3366         state->selected_input = ~0;
3367
3368         if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3369                 const struct of_device_id *oid;
3370
3371                 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3372                 state->info = oid->data;
3373
3374                 err = adv76xx_parse_dt(state);
3375                 if (err < 0) {
3376                         v4l_err(client, "DT parsing error\n");
3377                         return err;
3378                 }
3379         } else if (client->dev.platform_data) {
3380                 struct adv76xx_platform_data *pdata = client->dev.platform_data;
3381
3382                 state->info = (const struct adv76xx_chip_info *)id->driver_data;
3383                 state->pdata = *pdata;
3384         } else {
3385                 v4l_err(client, "No platform data!\n");
3386                 return -ENODEV;
3387         }
3388
3389         /* Request GPIOs. */
3390         for (i = 0; i < state->info->num_dv_ports; ++i) {
3391                 state->hpd_gpio[i] =
3392                         devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3393                                                       GPIOD_OUT_LOW);
3394                 if (IS_ERR(state->hpd_gpio[i]))
3395                         return PTR_ERR(state->hpd_gpio[i]);
3396
3397                 if (state->hpd_gpio[i])
3398                         v4l_info(client, "Handling HPD %u GPIO\n", i);
3399         }
3400         state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3401                                                                 GPIOD_OUT_HIGH);
3402         if (IS_ERR(state->reset_gpio))
3403                 return PTR_ERR(state->reset_gpio);
3404
3405         adv76xx_reset(state);
3406
3407         state->timings = cea640x480;
3408         state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3409
3410         sd = &state->sd;
3411         v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3412         snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3413                 id->name, i2c_adapter_id(client->adapter),
3414                 client->addr);
3415         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3416         sd->internal_ops = &adv76xx_int_ops;
3417
3418         /* Configure IO Regmap region */
3419         err = configure_regmap(state, ADV76XX_PAGE_IO);
3420
3421         if (err) {
3422                 v4l2_err(sd, "Error configuring IO regmap region\n");
3423                 return -ENODEV;
3424         }
3425
3426         /*
3427          * Verify that the chip is present. On ADV7604 the RD_INFO register only
3428          * identifies the revision, while on ADV7611 it identifies the model as
3429          * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3430          */
3431         switch (state->info->type) {
3432         case ADV7604:
3433                 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3434                 if (err) {
3435                         v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3436                         return -ENODEV;
3437                 }
3438                 if (val != 0x68) {
3439                         v4l2_err(sd, "not an adv7604 on address 0x%x\n",
3440                                         client->addr << 1);
3441                         return -ENODEV;
3442                 }
3443                 break;
3444         case ADV7611:
3445         case ADV7612:
3446                 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3447                                 0xea,
3448                                 &val);
3449                 if (err) {
3450                         v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3451                         return -ENODEV;
3452                 }
3453                 val2 = val << 8;
3454                 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3455                             0xeb,
3456                             &val);
3457                 if (err) {
3458                         v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3459                         return -ENODEV;
3460                 }
3461                 val |= val2;
3462                 if ((state->info->type == ADV7611 && val != 0x2051) ||
3463                         (state->info->type == ADV7612 && val != 0x2041)) {
3464                         v4l2_err(sd, "not an adv761x on address 0x%x\n",
3465                                         client->addr << 1);
3466                         return -ENODEV;
3467                 }
3468                 break;
3469         }
3470
3471         /* control handlers */
3472         hdl = &state->hdl;
3473         v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3474
3475         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3476                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3477         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3478                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
3479         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3480                         V4L2_CID_SATURATION, 0, 255, 1, 128);
3481         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3482                         V4L2_CID_HUE, 0, 128, 1, 0);
3483         ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3484                         V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3485                         0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3486         if (ctrl)
3487                 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3488
3489         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3490                         V4L2_CID_DV_RX_POWER_PRESENT, 0,
3491                         (1 << state->info->num_dv_ports) - 1, 0, 0);
3492         state->rgb_quantization_range_ctrl =
3493                 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3494                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3495                         0, V4L2_DV_RGB_RANGE_AUTO);
3496
3497         /* custom controls */
3498         if (adv76xx_has_afe(state))
3499                 state->analog_sampling_phase_ctrl =
3500                         v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3501         state->free_run_color_manual_ctrl =
3502                 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3503         state->free_run_color_ctrl =
3504                 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3505
3506         sd->ctrl_handler = hdl;
3507         if (hdl->error) {
3508                 err = hdl->error;
3509                 goto err_hdl;
3510         }
3511         if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3512                 err = -ENODEV;
3513                 goto err_hdl;
3514         }
3515
3516         for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3517                 struct i2c_client *dummy_client;
3518
3519                 if (!(BIT(i) & state->info->page_mask))
3520                         continue;
3521
3522                 dummy_client = adv76xx_dummy_client(sd, i);
3523                 if (IS_ERR(dummy_client)) {
3524                         err = PTR_ERR(dummy_client);
3525                         v4l2_err(sd, "failed to create i2c client %u\n", i);
3526                         goto err_i2c;
3527                 }
3528
3529                 state->i2c_clients[i] = dummy_client;
3530         }
3531
3532         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3533                         adv76xx_delayed_work_enable_hotplug);
3534
3535         state->source_pad = state->info->num_dv_ports
3536                           + (state->info->has_afe ? 2 : 0);
3537         for (i = 0; i < state->source_pad; ++i)
3538                 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3539         state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3540         sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3541
3542         err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3543                                 state->pads);
3544         if (err)
3545                 goto err_work_queues;
3546
3547         /* Configure regmaps */
3548         err = configure_regmaps(state);
3549         if (err)
3550                 goto err_entity;
3551
3552         err = adv76xx_core_init(sd);
3553         if (err)
3554                 goto err_entity;
3555
3556         if (client->irq) {
3557                 err = devm_request_threaded_irq(&client->dev,
3558                                                 client->irq,
3559                                                 NULL, adv76xx_irq_handler,
3560                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
3561                                                 client->name, state);
3562                 if (err)
3563                         goto err_entity;
3564         }
3565
3566 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
3567         state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
3568                 state, dev_name(&client->dev),
3569                 CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS);
3570         err = PTR_ERR_OR_ZERO(state->cec_adap);
3571         if (err)
3572                 goto err_entity;
3573 #endif
3574
3575         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3576                         client->addr << 1, client->adapter->name);
3577
3578         err = v4l2_async_register_subdev(sd);
3579         if (err)
3580                 goto err_entity;
3581
3582         return 0;
3583
3584 err_entity:
3585         media_entity_cleanup(&sd->entity);
3586 err_work_queues:
3587         cancel_delayed_work(&state->delayed_work_enable_hotplug);
3588 err_i2c:
3589         adv76xx_unregister_clients(state);
3590 err_hdl:
3591         v4l2_ctrl_handler_free(hdl);
3592         return err;
3593 }
3594
3595 /* ----------------------------------------------------------------------- */
3596
3597 static int adv76xx_remove(struct i2c_client *client)
3598 {
3599         struct v4l2_subdev *sd = i2c_get_clientdata(client);
3600         struct adv76xx_state *state = to_state(sd);
3601
3602         /* disable interrupts */
3603         io_write(sd, 0x40, 0);
3604         io_write(sd, 0x41, 0);
3605         io_write(sd, 0x46, 0);
3606         io_write(sd, 0x6e, 0);
3607         io_write(sd, 0x73, 0);
3608
3609         cancel_delayed_work(&state->delayed_work_enable_hotplug);
3610         v4l2_async_unregister_subdev(sd);
3611         media_entity_cleanup(&sd->entity);
3612         adv76xx_unregister_clients(to_state(sd));
3613         v4l2_ctrl_handler_free(sd->ctrl_handler);
3614         return 0;
3615 }
3616
3617 /* ----------------------------------------------------------------------- */
3618
3619 static struct i2c_driver adv76xx_driver = {
3620         .driver = {
3621                 .name = "adv7604",
3622                 .of_match_table = of_match_ptr(adv76xx_of_id),
3623         },
3624         .probe = adv76xx_probe,
3625         .remove = adv76xx_remove,
3626         .id_table = adv76xx_i2c_id,
3627 };
3628
3629 module_i2c_driver(adv76xx_driver);