drivers/media/dvb/frontends/ds3000.c

   1 /*
   2     Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver
   3     Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
   4
   5     Copyright (C) 2009 TurboSight.com
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/slab.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/firmware.h>
  28
  29 #include "dvb_frontend.h"
  30 #include "ds3000.h"
  31
  32 static int debug;
  33
  34 #define dprintk(args...) \
  35         do { \
  36                 if (debug) \
  37                         printk(args); \
  38         } while (0)
  39
  40 /*(DEBLOBBED)*/
  41
  42 #define DS3000_SAMPLE_RATE 96000 /* in kHz */
  43 #define DS3000_XTAL_FREQ   27000 /* in kHz */
  44
  45 /* Register values to initialise the demod in DVB-S mode */
  46 static u8 ds3000_dvbs_init_tab[] = {
  47         0x23, 0x05,
  48         0x08, 0x03,
  49         0x0c, 0x00,
  50         0x21, 0x54,
  51         0x25, 0x82,
  52         0x27, 0x31,
  53         0x30, 0x08,
  54         0x31, 0x40,
  55         0x32, 0x32,
  56         0x33, 0x35,
  57         0x35, 0xff,
  58         0x3a, 0x00,
  59         0x37, 0x10,
  60         0x38, 0x10,
  61         0x39, 0x02,
  62         0x42, 0x60,
  63         0x4a, 0x40,
  64         0x4b, 0x04,
  65         0x4d, 0x91,
  66         0x5d, 0xc8,
  67         0x50, 0x77,
  68         0x51, 0x77,
  69         0x52, 0x36,
  70         0x53, 0x36,
  71         0x56, 0x01,
  72         0x63, 0x43,
  73         0x64, 0x30,
  74         0x65, 0x40,
  75         0x68, 0x26,
  76         0x69, 0x4c,
  77         0x70, 0x20,
  78         0x71, 0x70,
  79         0x72, 0x04,
  80         0x73, 0x00,
  81         0x70, 0x40,
  82         0x71, 0x70,
  83         0x72, 0x04,
  84         0x73, 0x00,
  85         0x70, 0x60,
  86         0x71, 0x70,
  87         0x72, 0x04,
  88         0x73, 0x00,
  89         0x70, 0x80,
  90         0x71, 0x70,
  91         0x72, 0x04,
  92         0x73, 0x00,
  93         0x70, 0xa0,
  94         0x71, 0x70,
  95         0x72, 0x04,
  96         0x73, 0x00,
  97         0x70, 0x1f,
  98         0x76, 0x00,
  99         0x77, 0xd1,
 100         0x78, 0x0c,
 101         0x79, 0x80,
 102         0x7f, 0x04,
 103         0x7c, 0x00,
 104         0x80, 0x86,
 105         0x81, 0xa6,
 106         0x85, 0x04,
 107         0xcd, 0xf4,
 108         0x90, 0x33,
 109         0xa0, 0x44,
 110         0xc0, 0x18,
 111         0xc3, 0x10,
 112         0xc4, 0x08,
 113         0xc5, 0x80,
 114         0xc6, 0x80,
 115         0xc7, 0x0a,
 116         0xc8, 0x1a,
 117         0xc9, 0x80,
 118         0xfe, 0x92,
 119         0xe0, 0xf8,
 120         0xe6, 0x8b,
 121         0xd0, 0x40,
 122         0xf8, 0x20,
 123         0xfa, 0x0f,
 124         0xfd, 0x20,
 125         0xad, 0x20,
 126         0xae, 0x07,
 127         0xb8, 0x00,
 128 };
 129
 130 /* Register values to initialise the demod in DVB-S2 mode */
 131 static u8 ds3000_dvbs2_init_tab[] = {
 132         0x23, 0x0f,
 133         0x08, 0x07,
 134         0x0c, 0x00,
 135         0x21, 0x54,
 136         0x25, 0x82,
 137         0x27, 0x31,
 138         0x30, 0x08,
 139         0x31, 0x32,
 140         0x32, 0x32,
 141         0x33, 0x35,
 142         0x35, 0xff,
 143         0x3a, 0x00,
 144         0x37, 0x10,
 145         0x38, 0x10,
 146         0x39, 0x02,
 147         0x42, 0x60,
 148         0x4a, 0x80,
 149         0x4b, 0x04,
 150         0x4d, 0x81,
 151         0x5d, 0x88,
 152         0x50, 0x36,
 153         0x51, 0x36,
 154         0x52, 0x36,
 155         0x53, 0x36,
 156         0x63, 0x60,
 157         0x64, 0x10,
 158         0x65, 0x10,
 159         0x68, 0x04,
 160         0x69, 0x29,
 161         0x70, 0x20,
 162         0x71, 0x70,
 163         0x72, 0x04,
 164         0x73, 0x00,
 165         0x70, 0x40,
 166         0x71, 0x70,
 167         0x72, 0x04,
 168         0x73, 0x00,
 169         0x70, 0x60,
 170         0x71, 0x70,
 171         0x72, 0x04,
 172         0x73, 0x00,
 173         0x70, 0x80,
 174         0x71, 0x70,
 175         0x72, 0x04,
 176         0x73, 0x00,
 177         0x70, 0xa0,
 178         0x71, 0x70,
 179         0x72, 0x04,
 180         0x73, 0x00,
 181         0x70, 0x1f,
 182         0xa0, 0x44,
 183         0xc0, 0x08,
 184         0xc1, 0x10,
 185         0xc2, 0x08,
 186         0xc3, 0x10,
 187         0xc4, 0x08,
 188         0xc5, 0xf0,
 189         0xc6, 0xf0,
 190         0xc7, 0x0a,
 191         0xc8, 0x1a,
 192         0xc9, 0x80,
 193         0xca, 0x23,
 194         0xcb, 0x24,
 195         0xce, 0x74,
 196         0x90, 0x03,
 197         0x76, 0x80,
 198         0x77, 0x42,
 199         0x78, 0x0a,
 200         0x79, 0x80,
 201         0xad, 0x40,
 202         0xae, 0x07,
 203         0x7f, 0xd4,
 204         0x7c, 0x00,
 205         0x80, 0xa8,
 206         0x81, 0xda,
 207         0x7c, 0x01,
 208         0x80, 0xda,
 209         0x81, 0xec,
 210         0x7c, 0x02,
 211         0x80, 0xca,
 212         0x81, 0xeb,
 213         0x7c, 0x03,
 214         0x80, 0xba,
 215         0x81, 0xdb,
 216         0x85, 0x08,
 217         0x86, 0x00,
 218         0x87, 0x02,
 219         0x89, 0x80,
 220         0x8b, 0x44,
 221         0x8c, 0xaa,
 222         0x8a, 0x10,
 223         0xba, 0x00,
 224         0xf5, 0x04,
 225         0xfe, 0x44,
 226         0xd2, 0x32,
 227         0xb8, 0x00,
 228 };
 229
 230 struct ds3000_state {
 231         struct i2c_adapter *i2c;
 232         const struct ds3000_config *config;
 233         struct dvb_frontend frontend;
 234         u8 skip_fw_load;
 235         /* previous uncorrected block counter for DVB-S2 */
 236         u16 prevUCBS2;
 237 };
 238
 239 static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
 240 {
 241         u8 buf[] = { reg, data };
 242         struct i2c_msg msg = { .addr = state->config->demod_address,
 243                 .flags = 0, .buf = buf, .len = 2 };
 244         int err;
 245
 246         dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
 247
 248         err = i2c_transfer(state->i2c, &msg, 1);
 249         if (err != 1) {
 250                 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
 251                          " value == 0x%02x)\n", __func__, err, reg, data);
 252                 return -EREMOTEIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
 259 {
 260         u8 buf[] = { reg, data };
 261         struct i2c_msg msg = { .addr = 0x60,
 262                 .flags = 0, .buf = buf, .len = 2 };
 263         int err;
 264
 265         dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
 266
 267         ds3000_writereg(state, 0x03, 0x11);
 268         err = i2c_transfer(state->i2c, &msg, 1);
 269         if (err != 1) {
 270                 printk("%s: writereg error(err == %i, reg == 0x%02x,"
 271                          " value == 0x%02x)\n", __func__, err, reg, data);
 272                 return -EREMOTEIO;
 273         }
 274
 275         return 0;
 276 }
 277
 278 /* I2C write for 8k firmware load */
 279 static int ds3000_writeFW(struct ds3000_state *state, int reg,
 280                                 const u8 *data, u16 len)
 281 {
 282         int i, ret = -EREMOTEIO;
 283         struct i2c_msg msg;
 284         u8 *buf;
 285
 286         buf = kmalloc(33, GFP_KERNEL);
 287         if (buf == NULL) {
 288                 printk(KERN_ERR "Unable to kmalloc\n");
 289                 ret = -ENOMEM;
 290                 goto error;
 291         }
 292
 293         *(buf) = reg;
 294
 295         msg.addr = state->config->demod_address;
 296         msg.flags = 0;
 297         msg.buf = buf;
 298         msg.len = 33;
 299
 300         for (i = 0; i < len; i += 32) {
 301                 memcpy(buf + 1, data + i, 32);
 302
 303                 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
 304
 305                 ret = i2c_transfer(state->i2c, &msg, 1);
 306                 if (ret != 1) {
 307                         printk(KERN_ERR "%s: write error(err == %i, "
 308                                 "reg == 0x%02x\n", __func__, ret, reg);
 309                         ret = -EREMOTEIO;
 310                 }
 311         }
 312
 313 error:
 314         kfree(buf);
 315
 316         return ret;
 317 }
 318
 319 static int ds3000_readreg(struct ds3000_state *state, u8 reg)
 320 {
 321         int ret;
 322         u8 b0[] = { reg };
 323         u8 b1[] = { 0 };
 324         struct i2c_msg msg[] = {
 325                 {
 326                         .addr = state->config->demod_address,
 327                         .flags = 0,
 328                         .buf = b0,
 329                         .len = 1
 330                 }, {
 331                         .addr = state->config->demod_address,
 332                         .flags = I2C_M_RD,
 333                         .buf = b1,
 334                         .len = 1
 335                 }
 336         };
 337
 338         ret = i2c_transfer(state->i2c, msg, 2);
 339
 340         if (ret != 2) {
 341                 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
 342                 return ret;
 343         }
 344
 345         dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
 346
 347         return b1[0];
 348 }
 349
 350 static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
 351 {
 352         int ret;
 353         u8 b0[] = { reg };
 354         u8 b1[] = { 0 };
 355         struct i2c_msg msg[] = {
 356                 {
 357                         .addr = 0x60,
 358                         .flags = 0,
 359                         .buf = b0,
 360                         .len = 1
 361                 }, {
 362                         .addr = 0x60,
 363                         .flags = I2C_M_RD,
 364                         .buf = b1,
 365                         .len = 1
 366                 }
 367         };
 368
 369         ds3000_writereg(state, 0x03, 0x12);
 370         ret = i2c_transfer(state->i2c, msg, 2);
 371
 372         if (ret != 2) {
 373                 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
 374                 return ret;
 375         }
 376
 377         dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
 378
 379         return b1[0];
 380 }
 381
 382 static int ds3000_load_firmware(struct dvb_frontend *fe,
 383                                         const struct firmware *fw);
 384
 385 static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
 386 {
 387         struct ds3000_state *state = fe->demodulator_priv;
 388         const struct firmware *fw;
 389         int ret = 0;
 390
 391         dprintk("%s()\n", __func__);
 392
 393         if (ds3000_readreg(state, 0xb2) <= 0)
 394                 return ret;
 395
 396         if (state->skip_fw_load)
 397                 return 0;
 398         /* Load firmware */
 399         /* request the firmware, this will block until someone uploads it */
 400         printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
 401                                 "/*(DEBLOBBED)*/");
 402         ret = reject_firmware(&fw, "/*(DEBLOBBED)*/",
 403                                 state->i2c->dev.parent);
 404         printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
 405         if (ret) {
 406                 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
 407                                 "found?)\n", __func__);
 408                 return ret;
 409         }
 410
 411         /* Make sure we don't recurse back through here during loading */
 412         state->skip_fw_load = 1;
 413
 414         ret = ds3000_load_firmware(fe, fw);
 415         if (ret)
 416                 printk("%s: Writing firmware to device failed\n", __func__);
 417
 418         release_firmware(fw);
 419
 420         dprintk("%s: Firmware upload %s\n", __func__,
 421                         ret == 0 ? "complete" : "failed");
 422
 423         /* Ensure firmware is always loaded if required */
 424         state->skip_fw_load = 0;
 425
 426         return ret;
 427 }
 428
 429 static int ds3000_load_firmware(struct dvb_frontend *fe,
 430                                         const struct firmware *fw)
 431 {
 432         struct ds3000_state *state = fe->demodulator_priv;
 433
 434         dprintk("%s\n", __func__);
 435         dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
 436                         fw->size,
 437                         fw->data[0],
 438                         fw->data[1],
 439                         fw->data[fw->size - 2],
 440                         fw->data[fw->size - 1]);
 441
 442         /* Begin the firmware load process */
 443         ds3000_writereg(state, 0xb2, 0x01);
 444         /* write the entire firmware */
 445         ds3000_writeFW(state, 0xb0, fw->data, fw->size);
 446         ds3000_writereg(state, 0xb2, 0x00);
 447
 448         return 0;
 449 }
 450
 451 static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
 452 {
 453         struct ds3000_state *state = fe->demodulator_priv;
 454         u8 data;
 455
 456         dprintk("%s(%d)\n", __func__, voltage);
 457
 458         data = ds3000_readreg(state, 0xa2);
 459         data |= 0x03; /* bit0 V/H, bit1 off/on */
 460
 461         switch (voltage) {
 462         case SEC_VOLTAGE_18:
 463                 data &= ~0x03;
 464                 break;
 465         case SEC_VOLTAGE_13:
 466                 data &= ~0x03;
 467                 data |= 0x01;
 468                 break;
 469         case SEC_VOLTAGE_OFF:
 470                 break;
 471         }
 472
 473         ds3000_writereg(state, 0xa2, data);
 474
 475         return 0;
 476 }
 477
 478 static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
 479 {
 480         struct ds3000_state *state = fe->demodulator_priv;
 481         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 482         int lock;
 483
 484         *status = 0;
 485
 486         switch (c->delivery_system) {
 487         case SYS_DVBS:
 488                 lock = ds3000_readreg(state, 0xd1);
 489                 if ((lock & 0x07) == 0x07)
 490                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 491                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 492                                 FE_HAS_LOCK;
 493
 494                 break;
 495         case SYS_DVBS2:
 496                 lock = ds3000_readreg(state, 0x0d);
 497                 if ((lock & 0x8f) == 0x8f)
 498                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 499                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 500                                 FE_HAS_LOCK;
 501
 502                 break;
 503         default:
 504                 return 1;
 505         }
 506
 507         dprintk("%s: status = 0x%02x\n", __func__, lock);
 508
 509         return 0;
 510 }
 511
 512 /* read DS3000 BER value */
 513 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
 514 {
 515         struct ds3000_state *state = fe->demodulator_priv;
 516         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 517         u8 data;
 518         u32 ber_reading, lpdc_frames;
 519
 520         dprintk("%s()\n", __func__);
 521
 522         switch (c->delivery_system) {
 523         case SYS_DVBS:
 524                 /* set the number of bytes checked during
 525                 BER estimation */
 526                 ds3000_writereg(state, 0xf9, 0x04);
 527                 /* read BER estimation status */
 528                 data = ds3000_readreg(state, 0xf8);
 529                 /* check if BER estimation is ready */
 530                 if ((data & 0x10) == 0) {
 531                         /* this is the number of error bits,
 532                         to calculate the bit error rate
 533                         divide to 8388608 */
 534                         *ber = (ds3000_readreg(state, 0xf7) << 8) |
 535                                 ds3000_readreg(state, 0xf6);
 536                         /* start counting error bits */
 537                         /* need to be set twice
 538                         otherwise it fails sometimes */
 539                         data |= 0x10;
 540                         ds3000_writereg(state, 0xf8, data);
 541                         ds3000_writereg(state, 0xf8, data);
 542                 } else
 543                         /* used to indicate that BER estimation
 544                         is not ready, i.e. BER is unknown */
 545                         *ber = 0xffffffff;
 546                 break;
 547         case SYS_DVBS2:
 548                 /* read the number of LPDC decoded frames */
 549                 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
 550                                 (ds3000_readreg(state, 0xd6) << 8) |
 551                                 ds3000_readreg(state, 0xd5);
 552                 /* read the number of packets with bad CRC */
 553                 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
 554                                 ds3000_readreg(state, 0xf7);
 555                 if (lpdc_frames > 750) {
 556                         /* clear LPDC frame counters */
 557                         ds3000_writereg(state, 0xd1, 0x01);
 558                         /* clear bad packets counter */
 559                         ds3000_writereg(state, 0xf9, 0x01);
 560                         /* enable bad packets counter */
 561                         ds3000_writereg(state, 0xf9, 0x00);
 562                         /* enable LPDC frame counters */
 563                         ds3000_writereg(state, 0xd1, 0x00);
 564                         *ber = ber_reading;
 565                 } else
 566                         /* used to indicate that BER estimation is not ready,
 567                         i.e. BER is unknown */
 568                         *ber = 0xffffffff;
 569                 break;
 570         default:
 571                 return 1;
 572         }
 573
 574         return 0;
 575 }
 576
 577 /* read TS2020 signal strength */
 578 static int ds3000_read_signal_strength(struct dvb_frontend *fe,
 579                                                 u16 *signal_strength)
 580 {
 581         struct ds3000_state *state = fe->demodulator_priv;
 582         u16 sig_reading, sig_strength;
 583         u8 rfgain, bbgain;
 584
 585         dprintk("%s()\n", __func__);
 586
 587         rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f;
 588         bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f;
 589
 590         if (rfgain > 15)
 591                 rfgain = 15;
 592         if (bbgain > 13)
 593                 bbgain = 13;
 594
 595         sig_reading = rfgain * 2 + bbgain * 3;
 596
 597         sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
 598
 599         /* cook the value to be suitable for szap-s2 human readable output */
 600         *signal_strength = sig_strength * 1000;
 601
 602         dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
 603                         sig_reading, *signal_strength);
 604
 605         return 0;
 606 }
 607
 608 /* calculate DS3000 snr value in dB */
 609 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
 610 {
 611         struct ds3000_state *state = fe->demodulator_priv;
 612         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 613         u8 snr_reading, snr_value;
 614         u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
 615         static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
 616                 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
 617                 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
 618                 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
 619         };
 620         static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
 621                 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
 622                 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
 623                 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
 624                 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
 625                 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
 626                 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
 627                 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
 628                 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
 629                 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
 630                 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
 631                 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
 632                 0x49e9, 0x4a20, 0x4a57
 633         };
 634
 635         dprintk("%s()\n", __func__);
 636
 637         switch (c->delivery_system) {
 638         case SYS_DVBS:
 639                 snr_reading = ds3000_readreg(state, 0xff);
 640                 snr_reading /= 8;
 641                 if (snr_reading == 0)
 642                         *snr = 0x0000;
 643                 else {
 644                         if (snr_reading > 20)
 645                                 snr_reading = 20;
 646                         snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
 647                         /* cook the value to be suitable for szap-s2
 648                         human readable output */
 649                         *snr = snr_value * 8 * 655;
 650                 }
 651                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 652                                 snr_reading, *snr);
 653                 break;
 654         case SYS_DVBS2:
 655                 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
 656                                 (ds3000_readreg(state, 0x8d) << 4);
 657                 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
 658                 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
 659                 if (tmp == 0) {
 660                         *snr = 0x0000;
 661                         return 0;
 662                 }
 663                 if (dvbs2_noise_reading == 0) {
 664                         snr_value = 0x0013;
 665                         /* cook the value to be suitable for szap-s2
 666                         human readable output */
 667                         *snr = 0xffff;
 668                         return 0;
 669                 }
 670                 if (tmp > dvbs2_noise_reading) {
 671                         snr_reading = tmp / dvbs2_noise_reading;
 672                         if (snr_reading > 80)
 673                                 snr_reading = 80;
 674                         snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
 675                         /* cook the value to be suitable for szap-s2
 676                         human readable output */
 677                         *snr = snr_value * 5 * 655;
 678                 } else {
 679                         snr_reading = dvbs2_noise_reading / tmp;
 680                         if (snr_reading > 80)
 681                                 snr_reading = 80;
 682                         *snr = -(dvbs2_snr_tab[snr_reading] / 1000);
 683                 }
 684                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 685                                 snr_reading, *snr);
 686                 break;
 687         default:
 688                 return 1;
 689         }
 690
 691         return 0;
 692 }
 693
 694 /* read DS3000 uncorrected blocks */
 695 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 696 {
 697         struct ds3000_state *state = fe->demodulator_priv;
 698         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 699         u8 data;
 700         u16 _ucblocks;
 701
 702         dprintk("%s()\n", __func__);
 703
 704         switch (c->delivery_system) {
 705         case SYS_DVBS:
 706                 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
 707                                 ds3000_readreg(state, 0xf4);
 708                 data = ds3000_readreg(state, 0xf8);
 709                 /* clear packet counters */
 710                 data &= ~0x20;
 711                 ds3000_writereg(state, 0xf8, data);
 712                 /* enable packet counters */
 713                 data |= 0x20;
 714                 ds3000_writereg(state, 0xf8, data);
 715                 break;
 716         case SYS_DVBS2:
 717                 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
 718                                 ds3000_readreg(state, 0xe1);
 719                 if (_ucblocks > state->prevUCBS2)
 720                         *ucblocks = _ucblocks - state->prevUCBS2;
 721                 else
 722                         *ucblocks = state->prevUCBS2 - _ucblocks;
 723                 state->prevUCBS2 = _ucblocks;
 724                 break;
 725         default:
 726                 return 1;
 727         }
 728
 729         return 0;
 730 }
 731
 732 static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
 733 {
 734         struct ds3000_state *state = fe->demodulator_priv;
 735         u8 data;
 736
 737         dprintk("%s(%d)\n", __func__, tone);
 738         if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
 739                 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
 740                 return -EINVAL;
 741         }
 742
 743         data = ds3000_readreg(state, 0xa2);
 744         data &= ~0xc0;
 745         ds3000_writereg(state, 0xa2, data);
 746
 747         switch (tone) {
 748         case SEC_TONE_ON:
 749                 dprintk("%s: setting tone on\n", __func__);
 750                 data = ds3000_readreg(state, 0xa1);
 751                 data &= ~0x43;
 752                 data |= 0x04;
 753                 ds3000_writereg(state, 0xa1, data);
 754                 break;
 755         case SEC_TONE_OFF:
 756                 dprintk("%s: setting tone off\n", __func__);
 757                 data = ds3000_readreg(state, 0xa2);
 758                 data |= 0x80;
 759                 ds3000_writereg(state, 0xa2, data);
 760                 break;
 761         }
 762
 763         return 0;
 764 }
 765
 766 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
 767                                 struct dvb_diseqc_master_cmd *d)
 768 {
 769         struct ds3000_state *state = fe->demodulator_priv;
 770         int i;
 771         u8 data;
 772
 773         /* Dump DiSEqC message */
 774         dprintk("%s(", __func__);
 775         for (i = 0 ; i < d->msg_len;) {
 776                 dprintk("0x%02x", d->msg[i]);
 777                 if (++i < d->msg_len)
 778                         dprintk(", ");
 779         }
 780
 781         /* enable DiSEqC message send pin */
 782         data = ds3000_readreg(state, 0xa2);
 783         data &= ~0xc0;
 784         ds3000_writereg(state, 0xa2, data);
 785
 786         /* DiSEqC message */
 787         for (i = 0; i < d->msg_len; i++)
 788                 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
 789
 790         data = ds3000_readreg(state, 0xa1);
 791         /* clear DiSEqC message length and status,
 792         enable DiSEqC message send */
 793         data &= ~0xf8;
 794         /* set DiSEqC mode, modulation active during 33 pulses,
 795         set DiSEqC message length */
 796         data |= ((d->msg_len - 1) << 3) | 0x07;
 797         ds3000_writereg(state, 0xa1, data);
 798
 799         /* wait up to 150ms for DiSEqC transmission to complete */
 800         for (i = 0; i < 15; i++) {
 801                 data = ds3000_readreg(state, 0xa1);
 802                 if ((data & 0x40) == 0)
 803                         break;
 804                 msleep(10);
 805         }
 806
 807         /* DiSEqC timeout after 150ms */
 808         if (i == 15) {
 809                 data = ds3000_readreg(state, 0xa1);
 810                 data &= ~0x80;
 811                 data |= 0x40;
 812                 ds3000_writereg(state, 0xa1, data);
 813
 814                 data = ds3000_readreg(state, 0xa2);
 815                 data &= ~0xc0;
 816                 data |= 0x80;
 817                 ds3000_writereg(state, 0xa2, data);
 818
 819                 return 1;
 820         }
 821
 822         data = ds3000_readreg(state, 0xa2);
 823         data &= ~0xc0;
 824         data |= 0x80;
 825         ds3000_writereg(state, 0xa2, data);
 826
 827         return 0;
 828 }
 829
 830 /* Send DiSEqC burst */
 831 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
 832                                         fe_sec_mini_cmd_t burst)
 833 {
 834         struct ds3000_state *state = fe->demodulator_priv;
 835         int i;
 836         u8 data;
 837
 838         dprintk("%s()\n", __func__);
 839
 840         data = ds3000_readreg(state, 0xa2);
 841         data &= ~0xc0;
 842         ds3000_writereg(state, 0xa2, data);
 843
 844         /* DiSEqC burst */
 845         if (burst == SEC_MINI_A)
 846                 /* Unmodulated tone burst */
 847                 ds3000_writereg(state, 0xa1, 0x02);
 848         else if (burst == SEC_MINI_B)
 849                 /* Modulated tone burst */
 850                 ds3000_writereg(state, 0xa1, 0x01);
 851         else
 852                 return -EINVAL;
 853
 854         msleep(13);
 855         for (i = 0; i < 5; i++) {
 856                 data = ds3000_readreg(state, 0xa1);
 857                 if ((data & 0x40) == 0)
 858                         break;
 859                 msleep(1);
 860         }
 861
 862         if (i == 5) {
 863                 data = ds3000_readreg(state, 0xa1);
 864                 data &= ~0x80;
 865                 data |= 0x40;
 866                 ds3000_writereg(state, 0xa1, data);
 867
 868                 data = ds3000_readreg(state, 0xa2);
 869                 data &= ~0xc0;
 870                 data |= 0x80;
 871                 ds3000_writereg(state, 0xa2, data);
 872
 873                 return 1;
 874         }
 875
 876         data = ds3000_readreg(state, 0xa2);
 877         data &= ~0xc0;
 878         data |= 0x80;
 879         ds3000_writereg(state, 0xa2, data);
 880
 881         return 0;
 882 }
 883
 884 static void ds3000_release(struct dvb_frontend *fe)
 885 {
 886         struct ds3000_state *state = fe->demodulator_priv;
 887         dprintk("%s\n", __func__);
 888         kfree(state);
 889 }
 890
 891 static struct dvb_frontend_ops ds3000_ops;
 892
 893 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
 894                                     struct i2c_adapter *i2c)
 895 {
 896         struct ds3000_state *state = NULL;
 897         int ret;
 898
 899         dprintk("%s\n", __func__);
 900
 901         /* allocate memory for the internal state */
 902         state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL);
 903         if (state == NULL) {
 904                 printk(KERN_ERR "Unable to kmalloc\n");
 905                 goto error2;
 906         }
 907
 908         state->config = config;
 909         state->i2c = i2c;
 910         state->prevUCBS2 = 0;
 911
 912         /* check if the demod is present */
 913         ret = ds3000_readreg(state, 0x00) & 0xfe;
 914         if (ret != 0xe0) {
 915                 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
 916                 goto error3;
 917         }
 918
 919         printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
 920                         ds3000_readreg(state, 0x02),
 921                         ds3000_readreg(state, 0x01));
 922
 923         memcpy(&state->frontend.ops, &ds3000_ops,
 924                         sizeof(struct dvb_frontend_ops));
 925         state->frontend.demodulator_priv = state;
 926
 927         /*
 928          * Some devices like T480 starts with voltage on. Be sure
 929          * to turn voltage off during init, as this can otherwise
 930          * interfere with Unicable SCR systems.
 931          */
 932         ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF);
 933         return &state->frontend;
 934
 935 error3:
 936         kfree(state);
 937 error2:
 938         return NULL;
 939 }
 940 EXPORT_SYMBOL(ds3000_attach);
 941
 942 static int ds3000_set_property(struct dvb_frontend *fe,
 943         struct dtv_property *tvp)
 944 {
 945         dprintk("%s(..)\n", __func__);
 946         return 0;
 947 }
 948
 949 static int ds3000_get_property(struct dvb_frontend *fe,
 950         struct dtv_property *tvp)
 951 {
 952         dprintk("%s(..)\n", __func__);
 953         return 0;
 954 }
 955
 956 static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
 957                                         s32 carrier_offset_khz)
 958 {
 959         struct ds3000_state *state = fe->demodulator_priv;
 960         s32 tmp;
 961
 962         tmp = carrier_offset_khz;
 963         tmp *= 65536;
 964         tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
 965
 966         if (tmp < 0)
 967                 tmp += 65536;
 968
 969         ds3000_writereg(state, 0x5f, tmp >> 8);
 970         ds3000_writereg(state, 0x5e, tmp & 0xff);
 971
 972         return 0;
 973 }
 974
 975 static int ds3000_set_frontend(struct dvb_frontend *fe,
 976                                 struct dvb_frontend_parameters *p)
 977 {
 978         struct ds3000_state *state = fe->demodulator_priv;
 979         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 980
 981         int i;
 982         fe_status_t status;
 983         u8 mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf, div4;
 984         s32 offset_khz;
 985         u16 value, ndiv;
 986         u32 f3db;
 987
 988         dprintk("%s() ", __func__);
 989
 990         if (state->config->set_ts_params)
 991                 state->config->set_ts_params(fe, 0);
 992         /* Tune */
 993         /* unknown */
 994         ds3000_tuner_writereg(state, 0x07, 0x02);
 995         ds3000_tuner_writereg(state, 0x10, 0x00);
 996         ds3000_tuner_writereg(state, 0x60, 0x79);
 997         ds3000_tuner_writereg(state, 0x08, 0x01);
 998         ds3000_tuner_writereg(state, 0x00, 0x01);
 999         div4 = 0;
1000
1001         /* calculate and set freq divider */
1002         if (p->frequency < 1146000) {
1003                 ds3000_tuner_writereg(state, 0x10, 0x11);
1004                 div4 = 1;
1005                 ndiv = ((p->frequency * (6 + 8) * 4) +
1006                                 (DS3000_XTAL_FREQ / 2)) /
1007                                 DS3000_XTAL_FREQ - 1024;
1008         } else {
1009                 ds3000_tuner_writereg(state, 0x10, 0x01);
1010                 ndiv = ((p->frequency * (6 + 8) * 2) +
1011                                 (DS3000_XTAL_FREQ / 2)) /
1012                                 DS3000_XTAL_FREQ - 1024;
1013         }
1014
1015         ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
1016         ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
1017
1018         /* set pll */
1019         ds3000_tuner_writereg(state, 0x03, 0x06);
1020         ds3000_tuner_writereg(state, 0x51, 0x0f);
1021         ds3000_tuner_writereg(state, 0x51, 0x1f);
1022         ds3000_tuner_writereg(state, 0x50, 0x10);
1023         ds3000_tuner_writereg(state, 0x50, 0x00);
1024         msleep(5);
1025
1026         /* unknown */
1027         ds3000_tuner_writereg(state, 0x51, 0x17);
1028         ds3000_tuner_writereg(state, 0x51, 0x1f);
1029         ds3000_tuner_writereg(state, 0x50, 0x08);
1030         ds3000_tuner_writereg(state, 0x50, 0x00);
1031         msleep(5);
1032
1033         value = ds3000_tuner_readreg(state, 0x3d);
1034         value &= 0x0f;
1035         if ((value > 4) && (value < 15)) {
1036                 value -= 3;
1037                 if (value < 4)
1038                         value = 4;
1039                 value = ((value << 3) | 0x01) & 0x79;
1040         }
1041
1042         ds3000_tuner_writereg(state, 0x60, value);
1043         ds3000_tuner_writereg(state, 0x51, 0x17);
1044         ds3000_tuner_writereg(state, 0x51, 0x1f);
1045         ds3000_tuner_writereg(state, 0x50, 0x08);
1046         ds3000_tuner_writereg(state, 0x50, 0x00);
1047
1048         /* set low-pass filter period */
1049         ds3000_tuner_writereg(state, 0x04, 0x2e);
1050         ds3000_tuner_writereg(state, 0x51, 0x1b);
1051         ds3000_tuner_writereg(state, 0x51, 0x1f);
1052         ds3000_tuner_writereg(state, 0x50, 0x04);
1053         ds3000_tuner_writereg(state, 0x50, 0x00);
1054         msleep(5);
1055
1056         f3db = ((c->symbol_rate / 1000) << 2) / 5 + 2000;
1057         if ((c->symbol_rate / 1000) < 5000)
1058                 f3db += 3000;
1059         if (f3db < 7000)
1060                 f3db = 7000;
1061         if (f3db > 40000)
1062                 f3db = 40000;
1063
1064         /* set low-pass filter baseband */
1065         value = ds3000_tuner_readreg(state, 0x26);
1066         mlpf = 0x2e * 207 / ((value << 1) + 151);
1067         mlpf_max = mlpf * 135 / 100;
1068         mlpf_min = mlpf * 78 / 100;
1069         if (mlpf_max > 63)
1070                 mlpf_max = 63;
1071
1072         /* rounded to the closest integer */
1073         nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
1074                         / (2766 * DS3000_XTAL_FREQ);
1075         if (nlpf > 23)
1076                 nlpf = 23;
1077         if (nlpf < 1)
1078                 nlpf = 1;
1079
1080         /* rounded to the closest integer */
1081         mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1082                         (1000 * f3db / 2)) / (1000 * f3db);
1083
1084         if (mlpf_new < mlpf_min) {
1085                 nlpf++;
1086                 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1087                                 (1000 * f3db / 2)) / (1000 * f3db);
1088         }
1089
1090         if (mlpf_new > mlpf_max)
1091                 mlpf_new = mlpf_max;
1092
1093         ds3000_tuner_writereg(state, 0x04, mlpf_new);
1094         ds3000_tuner_writereg(state, 0x06, nlpf);
1095         ds3000_tuner_writereg(state, 0x51, 0x1b);
1096         ds3000_tuner_writereg(state, 0x51, 0x1f);
1097         ds3000_tuner_writereg(state, 0x50, 0x04);
1098         ds3000_tuner_writereg(state, 0x50, 0x00);
1099         msleep(5);
1100
1101         /* unknown */
1102         ds3000_tuner_writereg(state, 0x51, 0x1e);
1103         ds3000_tuner_writereg(state, 0x51, 0x1f);
1104         ds3000_tuner_writereg(state, 0x50, 0x01);
1105         ds3000_tuner_writereg(state, 0x50, 0x00);
1106         msleep(60);
1107
1108         offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ
1109                 / (6 + 8) / (div4 + 1) / 2 - p->frequency;
1110
1111         /* ds3000 global reset */
1112         ds3000_writereg(state, 0x07, 0x80);
1113         ds3000_writereg(state, 0x07, 0x00);
1114         /* ds3000 build-in uC reset */
1115         ds3000_writereg(state, 0xb2, 0x01);
1116         /* ds3000 software reset */
1117         ds3000_writereg(state, 0x00, 0x01);
1118
1119         switch (c->delivery_system) {
1120         case SYS_DVBS:
1121                 /* initialise the demod in DVB-S mode */
1122                 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
1123                         ds3000_writereg(state,
1124                                 ds3000_dvbs_init_tab[i],
1125                                 ds3000_dvbs_init_tab[i + 1]);
1126                 value = ds3000_readreg(state, 0xfe);
1127                 value &= 0xc0;
1128                 value |= 0x1b;
1129                 ds3000_writereg(state, 0xfe, value);
1130                 break;
1131         case SYS_DVBS2:
1132                 /* initialise the demod in DVB-S2 mode */
1133                 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
1134                         ds3000_writereg(state,
1135                                 ds3000_dvbs2_init_tab[i],
1136                                 ds3000_dvbs2_init_tab[i + 1]);
1137                 ds3000_writereg(state, 0xfe, 0x98);
1138                 break;
1139         default:
1140                 return 1;
1141         }
1142
1143         /* enable 27MHz clock output */
1144         ds3000_writereg(state, 0x29, 0x80);
1145         /* enable ac coupling */
1146         ds3000_writereg(state, 0x25, 0x8a);
1147
1148         /* enhance symbol rate performance */
1149         if ((c->symbol_rate / 1000) <= 5000) {
1150                 value = 29777 / (c->symbol_rate / 1000) + 1;
1151                 if (value % 2 != 0)
1152                         value++;
1153                 ds3000_writereg(state, 0xc3, 0x0d);
1154                 ds3000_writereg(state, 0xc8, value);
1155                 ds3000_writereg(state, 0xc4, 0x10);
1156                 ds3000_writereg(state, 0xc7, 0x0e);
1157         } else if ((c->symbol_rate / 1000) <= 10000) {
1158                 value = 92166 / (c->symbol_rate / 1000) + 1;
1159                 if (value % 2 != 0)
1160                         value++;
1161                 ds3000_writereg(state, 0xc3, 0x07);
1162                 ds3000_writereg(state, 0xc8, value);
1163                 ds3000_writereg(state, 0xc4, 0x09);
1164                 ds3000_writereg(state, 0xc7, 0x12);
1165         } else if ((c->symbol_rate / 1000) <= 20000) {
1166                 value = 64516 / (c->symbol_rate / 1000) + 1;
1167                 ds3000_writereg(state, 0xc3, value);
1168                 ds3000_writereg(state, 0xc8, 0x0e);
1169                 ds3000_writereg(state, 0xc4, 0x07);
1170                 ds3000_writereg(state, 0xc7, 0x18);
1171         } else {
1172                 value = 129032 / (c->symbol_rate / 1000) + 1;
1173                 ds3000_writereg(state, 0xc3, value);
1174                 ds3000_writereg(state, 0xc8, 0x0a);
1175                 ds3000_writereg(state, 0xc4, 0x05);
1176                 ds3000_writereg(state, 0xc7, 0x24);
1177         }
1178
1179         /* normalized symbol rate rounded to the closest integer */
1180         value = (((c->symbol_rate / 1000) << 16) +
1181                         (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
1182         ds3000_writereg(state, 0x61, value & 0x00ff);
1183         ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
1184
1185         /* co-channel interference cancellation disabled */
1186         ds3000_writereg(state, 0x56, 0x00);
1187
1188         /* equalizer disabled */
1189         ds3000_writereg(state, 0x76, 0x00);
1190
1191         /*ds3000_writereg(state, 0x08, 0x03);
1192         ds3000_writereg(state, 0xfd, 0x22);
1193         ds3000_writereg(state, 0x08, 0x07);
1194         ds3000_writereg(state, 0xfd, 0x42);
1195         ds3000_writereg(state, 0x08, 0x07);*/
1196
1197         if (state->config->ci_mode) {
1198                 switch (c->delivery_system) {
1199                 case SYS_DVBS:
1200                 default:
1201                         ds3000_writereg(state, 0xfd, 0x80);
1202                 break;
1203                 case SYS_DVBS2:
1204                         ds3000_writereg(state, 0xfd, 0x01);
1205                         break;
1206                 }
1207         }
1208
1209         /* ds3000 out of software reset */
1210         ds3000_writereg(state, 0x00, 0x00);
1211         /* start ds3000 build-in uC */
1212         ds3000_writereg(state, 0xb2, 0x00);
1213
1214         ds3000_set_carrier_offset(fe, offset_khz);
1215
1216         for (i = 0; i < 30 ; i++) {
1217                 ds3000_read_status(fe, &status);
1218                 if (status && FE_HAS_LOCK)
1219                         break;
1220
1221                 msleep(10);
1222         }
1223
1224         return 0;
1225 }
1226
1227 static int ds3000_tune(struct dvb_frontend *fe,
1228                         struct dvb_frontend_parameters *p,
1229                         unsigned int mode_flags,
1230                         unsigned int *delay,
1231                         fe_status_t *status)
1232 {
1233         if (p) {
1234                 int ret = ds3000_set_frontend(fe, p);
1235                 if (ret)
1236                         return ret;
1237         }
1238
1239         *delay = HZ / 5;
1240
1241         return ds3000_read_status(fe, status);
1242 }
1243
1244 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1245 {
1246         dprintk("%s()\n", __func__);
1247         return DVBFE_ALGO_HW;
1248 }
1249
1250 /*
1251  * Initialise or wake up device
1252  *
1253  * Power config will reset and load initial firmware if required
1254  */
1255 static int ds3000_initfe(struct dvb_frontend *fe)
1256 {
1257         struct ds3000_state *state = fe->demodulator_priv;
1258         int ret;
1259
1260         dprintk("%s()\n", __func__);
1261         /* hard reset */
1262         ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1263         msleep(1);
1264
1265         /* TS2020 init */
1266         ds3000_tuner_writereg(state, 0x42, 0x73);
1267         ds3000_tuner_writereg(state, 0x05, 0x01);
1268         ds3000_tuner_writereg(state, 0x62, 0xf5);
1269         /* Load the firmware if required */
1270         ret = ds3000_firmware_ondemand(fe);
1271         if (ret != 0) {
1272                 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1273                 return ret;
1274         }
1275
1276         return 0;
1277 }
1278
1279 /* Put device to sleep */
1280 static int ds3000_sleep(struct dvb_frontend *fe)
1281 {
1282         dprintk("%s()\n", __func__);
1283         return 0;
1284 }
1285
1286 static struct dvb_frontend_ops ds3000_ops = {
1287
1288         .info = {
1289                 .name = "Montage Technology DS3000/TS2020",
1290                 .type = FE_QPSK,
1291                 .frequency_min = 950000,
1292                 .frequency_max = 2150000,
1293                 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1294                 .frequency_tolerance = 5000,
1295                 .symbol_rate_min = 1000000,
1296                 .symbol_rate_max = 45000000,
1297                 .caps = FE_CAN_INVERSION_AUTO |
1298                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1299                         FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1300                         FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1301                         FE_CAN_2G_MODULATION |
1302                         FE_CAN_QPSK | FE_CAN_RECOVER
1303         },
1304
1305         .release = ds3000_release,
1306
1307         .init = ds3000_initfe,
1308         .sleep = ds3000_sleep,
1309         .read_status = ds3000_read_status,
1310         .read_ber = ds3000_read_ber,
1311         .read_signal_strength = ds3000_read_signal_strength,
1312         .read_snr = ds3000_read_snr,
1313         .read_ucblocks = ds3000_read_ucblocks,
1314         .set_voltage = ds3000_set_voltage,
1315         .set_tone = ds3000_set_tone,
1316         .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1317         .diseqc_send_burst = ds3000_diseqc_send_burst,
1318         .get_frontend_algo = ds3000_get_algo,
1319
1320         .set_property = ds3000_set_property,
1321         .get_property = ds3000_get_property,
1322         .set_frontend = ds3000_set_frontend,
1323         .tune = ds3000_tune,
1324 };
1325
1326 module_param(debug, int, 0644);
1327 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1328
1329 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
1330                         "DS3000/TS2020 hardware");
1331 MODULE_AUTHOR("Konstantin Dimitrov");
1332 MODULE_LICENSE("GPL");