1 /* Frontend part of the Linux driver for the Afatech 9005
2 * USB1.1 DVB-T receiver.
4 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
6 * Thanks to Afatech who kindly provided information.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 * see Documentation/dvb/README.dvb-usb for more information
28 #include <asm/div64.h>
30 struct af9005_fe_state {
31 struct dvb_usb_device *d;
34 /* retraining parameters */
39 u16 original_aci0_if_top;
40 u16 original_aci1_if_top;
41 u16 original_aci0_if_min;
42 u8 original_if_unplug_th;
43 u8 original_rf_unplug_th;
44 u8 original_dtop_if_unplug_th;
45 u8 original_dtop_rf_unplug_th;
48 u32 pre_vit_error_count;
49 u32 pre_vit_bit_count;
51 u32 post_vit_error_count;
52 u32 post_vit_bit_count;
58 unsigned long next_status_check;
59 struct dvb_frontend frontend;
62 static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi,
63 u16 reglo, u8 pos, u8 len, u16 value)
67 if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff))))
69 return af9005_write_register_bits(d, reghi, pos, len,
70 (u8) ((value & 0x300) >> 8));
73 static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi,
74 u16 reglo, u8 pos, u8 len, u16 * value)
79 if ((ret = af9005_read_ofdm_register(d, reglo, &temp0)))
81 if ((ret = af9005_read_ofdm_register(d, reghi, &temp1)))
85 *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0;
88 *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0;
91 *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0;
94 *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0;
97 err("invalid pos in read word agc");
104 static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available)
106 struct af9005_fe_state *state = fe->demodulator_priv;
112 ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
113 fec_vtb_rsd_mon_en_pos,
114 fec_vtb_rsd_mon_en_len, &temp);
119 af9005_read_register_bits(state->d,
120 xd_p_reg_ofsm_read_rbc_en,
121 reg_ofsm_read_rbc_en_pos,
122 reg_ofsm_read_rbc_en_len, &temp);
132 static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe,
133 u32 * post_err_count,
137 struct af9005_fe_state *state = fe->demodulator_priv;
141 u8 temp, temp0, temp1, temp2;
147 /* check if error bit count is ready */
149 af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy,
150 fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len,
155 deb_info("rsd counter not ready\n");
158 /* get abort count */
160 af9005_read_ofdm_register(state->d,
161 xd_r_fec_rsd_abort_packet_cnt_7_0,
166 af9005_read_ofdm_register(state->d,
167 xd_r_fec_rsd_abort_packet_cnt_15_8,
171 loc_abort_count = ((u16) temp1 << 8) + temp0;
173 /* get error count */
175 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0,
180 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8,
185 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16,
189 err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
190 *post_err_count = err_count - (u32) loc_abort_count *8 * 8;
192 /* get RSD packet number */
194 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
199 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
203 cw_count = ((u32) temp1 << 8) + temp0;
205 err("wrong RSD packet count");
208 deb_info("POST abort count %d err count %d rsd packets %d\n",
209 loc_abort_count, err_count, cw_count);
210 *post_cw_count = cw_count - (u32) loc_abort_count;
211 *abort_count = loc_abort_count;
216 static int af9005_get_post_vit_ber(struct dvb_frontend *fe,
217 u32 * post_err_count, u32 * post_cw_count,
220 u32 loc_cw_count = 0, loc_err_count;
221 u16 loc_abort_count = 0;
225 af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count,
229 *post_err_count = loc_err_count;
230 *post_cw_count = loc_cw_count * 204 * 8;
231 *abort_count = loc_abort_count;
236 static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe,
240 struct af9005_fe_state *state = fe->demodulator_priv;
241 u8 temp, temp0, temp1, temp2;
242 u32 super_frame_count, x, bits;
246 af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy,
247 fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len,
252 deb_info("viterbi counter not ready\n");
253 return 101; /* ERR_APO_VTB_COUNTER_NOT_READY; */
256 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0,
261 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8,
266 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16,
270 *pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
273 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
278 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
282 super_frame_count = ((u32) temp1 << 8) + temp0;
283 if (super_frame_count == 0) {
284 deb_info("super frame count 0\n");
290 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
291 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
298 } else if (temp == 1) {
302 err("Invalid fft mode");
306 /* read constellation mode */
308 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
309 reg_tpsd_const_pos, reg_tpsd_const_len,
324 err("invalid constellation mode");
327 *pre_bit_count = super_frame_count * 68 * 4 * x * bits;
328 deb_info("PRE err count %d frame count %d bit count %d\n",
329 *pre_err_count, super_frame_count, *pre_bit_count);
333 static int af9005_reset_pre_viterbi(struct dvb_frontend *fe)
335 struct af9005_fe_state *state = fe->demodulator_priv;
338 /* set super frame count to 1 */
340 af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
344 ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
348 /* reset pre viterbi error count */
350 af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst,
351 fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len,
357 static int af9005_reset_post_viterbi(struct dvb_frontend *fe)
359 struct af9005_fe_state *state = fe->demodulator_priv;
362 /* set packet unit */
364 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
369 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
373 /* reset post viterbi error count */
375 af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst,
376 fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len,
382 static int af9005_get_statistic(struct dvb_frontend *fe)
384 struct af9005_fe_state *state = fe->demodulator_priv;
385 int ret, fecavailable;
386 u64 numerator, denominator;
388 deb_info("GET STATISTIC\n");
389 ret = af9005_is_fecmon_available(fe, &fecavailable);
393 deb_info("fecmon not available\n");
397 ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count,
398 &state->pre_vit_bit_count);
400 af9005_reset_pre_viterbi(fe);
401 if (state->pre_vit_bit_count > 0) {
402 /* according to v 0.0.4 of the dvb api ber should be a multiple
403 of 10E-9 so we have to multiply the error count by
406 (u64) state->pre_vit_error_count * (u64) 1000000000;
407 denominator = (u64) state->pre_vit_bit_count;
408 state->ber = do_div(numerator, denominator);
410 state->ber = 0xffffffff;
414 ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count,
415 &state->post_vit_bit_count,
416 &state->abort_count);
418 ret = af9005_reset_post_viterbi(fe);
419 state->unc += state->abort_count;
426 static int af9005_fe_refresh_state(struct dvb_frontend *fe)
428 struct af9005_fe_state *state = fe->demodulator_priv;
429 if (time_after(jiffies, state->next_status_check)) {
430 deb_info("REFRESH STATE\n");
433 if (af9005_get_statistic(fe))
434 err("get_statistic_failed");
435 state->next_status_check = jiffies + 250 * HZ / 1000;
440 static int af9005_fe_read_status(struct dvb_frontend *fe, fe_status_t * stat)
442 struct af9005_fe_state *state = fe->demodulator_priv;
446 if (fe->ops.tuner_ops.release == NULL)
450 ret = af9005_read_register_bits(state->d, xd_p_agc_lock,
451 agc_lock_pos, agc_lock_len, &temp);
455 *stat |= FE_HAS_SIGNAL;
457 ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock,
458 fd_tpsd_lock_pos, fd_tpsd_lock_len,
463 *stat |= FE_HAS_CARRIER;
465 ret = af9005_read_register_bits(state->d,
466 xd_r_mp2if_sync_byte_locked,
467 mp2if_sync_byte_locked_pos,
468 mp2if_sync_byte_locked_pos, &temp);
472 *stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK;
474 af9005_led_control(state->d, *stat & FE_HAS_LOCK);
477 af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected,
478 reg_strong_sginal_detected_pos,
479 reg_strong_sginal_detected_len, &temp);
482 if (temp != state->strong) {
483 deb_info("adjust for strong signal %d\n", temp);
484 state->strong = temp;
489 static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber)
491 struct af9005_fe_state *state = fe->demodulator_priv;
492 if (fe->ops.tuner_ops.release == NULL)
494 af9005_fe_refresh_state(fe);
499 static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
501 struct af9005_fe_state *state = fe->demodulator_priv;
502 if (fe->ops.tuner_ops.release == NULL)
504 af9005_fe_refresh_state(fe);
509 static int af9005_fe_read_signal_strength(struct dvb_frontend *fe,
512 struct af9005_fe_state *state = fe->demodulator_priv;
516 if (fe->ops.tuner_ops.release == NULL)
519 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain,
524 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
528 /* this value has no real meaning, but i don't have the tables that relate
529 the rf and if gain with the dbm, so I just scale the value */
530 *strength = (512 - rf_gain - if_gain) << 7;
534 static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
536 /* the snr can be derived from the ber and the constellation
537 but I don't think this kind of complex calculations belong
538 in the driver. I may be wrong.... */
542 static int af9005_fe_program_cfoe(struct dvb_usb_device *d, fe_bandwidth_t bw)
544 u8 temp0, temp1, temp2, temp3, buf[4];
546 u32 NS_coeff1_2048Nu;
547 u32 NS_coeff1_8191Nu;
548 u32 NS_coeff1_8192Nu;
549 u32 NS_coeff1_8193Nu;
554 case BANDWIDTH_6_MHZ:
555 NS_coeff1_2048Nu = 0x2ADB6DC;
556 NS_coeff1_8191Nu = 0xAB7313;
557 NS_coeff1_8192Nu = 0xAB6DB7;
558 NS_coeff1_8193Nu = 0xAB685C;
559 NS_coeff2_2k = 0x156DB6E;
560 NS_coeff2_8k = 0x55B6DC;
563 case BANDWIDTH_7_MHZ:
564 NS_coeff1_2048Nu = 0x3200001;
565 NS_coeff1_8191Nu = 0xC80640;
566 NS_coeff1_8192Nu = 0xC80000;
567 NS_coeff1_8193Nu = 0xC7F9C0;
568 NS_coeff2_2k = 0x1900000;
569 NS_coeff2_8k = 0x640000;
572 case BANDWIDTH_8_MHZ:
573 NS_coeff1_2048Nu = 0x3924926;
574 NS_coeff1_8191Nu = 0xE4996E;
575 NS_coeff1_8192Nu = 0xE49249;
576 NS_coeff1_8193Nu = 0xE48B25;
577 NS_coeff2_2k = 0x1C92493;
578 NS_coeff2_8k = 0x724925;
581 err("Invalid bandwidth %d.", bw);
586 * write NS_coeff1_2048Nu
589 temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
590 temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
591 temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
592 temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);
594 /* big endian to make 8051 happy */
600 /* cfoe_NS_2k_coeff1_25_24 */
601 ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
605 /* cfoe_NS_2k_coeff1_23_16 */
606 ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
610 /* cfoe_NS_2k_coeff1_15_8 */
611 ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
615 /* cfoe_NS_2k_coeff1_7_0 */
616 ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
624 temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
625 temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
626 temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
627 temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);
629 /* big endian to make 8051 happy */
635 ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
639 ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
643 ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
647 ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
652 * write NS_coeff1_8191Nu
655 temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
656 temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
657 temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
658 temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);
660 /* big endian to make 8051 happy */
666 ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
670 ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
674 ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
678 ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
683 * write NS_coeff1_8192Nu
686 temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
687 temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
688 temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
689 temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);
691 /* big endian to make 8051 happy */
697 ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
701 ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
705 ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
709 ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
714 * write NS_coeff1_8193Nu
717 temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
718 temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
719 temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
720 temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);
722 /* big endian to make 8051 happy */
728 ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
732 ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
736 ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
740 ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
748 temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
749 temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
750 temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
751 temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);
753 /* big endian to make 8051 happy */
759 ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
763 ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
767 ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
771 ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
776 static int af9005_fe_select_bw(struct dvb_usb_device *d, fe_bandwidth_t bw)
780 case BANDWIDTH_6_MHZ:
783 case BANDWIDTH_7_MHZ:
786 case BANDWIDTH_8_MHZ:
790 err("Invalid bandwidth %d.", bw);
793 return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
797 static int af9005_fe_power(struct dvb_frontend *fe, int on)
799 struct af9005_fe_state *state = fe->demodulator_priv;
802 deb_info("power %s tuner\n", on ? "on" : "off");
803 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
807 static struct mt2060_config af9005_mt2060_config = {
811 static struct qt1010_config af9005_qt1010_config = {
815 static int af9005_fe_init(struct dvb_frontend *fe)
817 struct af9005_fe_state *state = fe->demodulator_priv;
818 struct dvb_usb_adapter *adap = fe->dvb->priv;
819 int ret, i, scriptlen;
820 u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
824 deb_info("in af9005_fe_init\n");
829 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
832 if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
834 /* clear ofdm reset */
835 deb_info("clear ofdm reset\n");
836 for (i = 0; i < 150; i++) {
838 af9005_read_ofdm_register(state->d,
839 xd_I2C_reg_ofdm_rst, &temp)))
841 if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
850 write xd_g_reg_ofsm_clk 7
855 write xd_g_reg_ofsm_clk 0
858 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
861 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
865 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
868 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
871 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
875 temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
877 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
878 reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
880 ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
881 reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);
885 /* don't know what register aefc is, but this is what the windows driver does */
886 ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
890 /* set stand alone chip */
891 deb_info("set stand alone chip\n");
893 af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
894 reg_dca_stand_alone_pos,
895 reg_dca_stand_alone_len, 1)))
898 /* set dca upper & lower chip */
899 deb_info("set dca upper & lower chip\n");
901 af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
902 reg_dca_upper_chip_pos,
903 reg_dca_upper_chip_len, 0)))
906 af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
907 reg_dca_lower_chip_pos,
908 reg_dca_lower_chip_len, 0)))
911 /* set 2wire master clock to 0x14 (for 60KHz) */
912 deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
914 af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
917 /* clear dca enable chip */
918 deb_info("clear dca enable chip\n");
920 af9005_write_register_bits(state->d, xd_p_reg_dca_en,
921 reg_dca_en_pos, reg_dca_en_len, 0)))
923 /* FIXME these are register bits, but I don't know which ones */
924 ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
927 ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
931 /* init other parameters: program cfoe and select bandwidth */
932 deb_info("program cfoe\n");
933 if ((ret = af9005_fe_program_cfoe(state->d, BANDWIDTH_6_MHZ)))
935 /* set read-update bit for constellation */
936 deb_info("set read-update bit for constellation\n");
938 af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
939 reg_feq_read_update_pos,
940 reg_feq_read_update_len, 1)))
943 /* sample code has a set MPEG TS code here
944 but sniffing reveals that it doesn't do it */
946 /* set read-update bit to 1 for DCA constellation */
947 deb_info("set read-update bit 1 for DCA constellation\n");
949 af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
950 reg_dca_read_update_pos,
951 reg_dca_read_update_len, 1)))
954 /* enable fec monitor */
955 deb_info("enable fec monitor\n");
957 af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
958 fec_vtb_rsd_mon_en_pos,
959 fec_vtb_rsd_mon_en_len, 1)))
962 /* FIXME should be register bits, I don't know which ones */
963 ret = af9005_write_ofdm_register(state->d, 0xa601, 0);
965 /* set api_retrain_never_freeze */
966 deb_info("set api_retrain_never_freeze\n");
967 if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
970 /* load init script */
972 err("Missing Free init script\n");
973 return scriptlen = ret = -EINVAL;
977 state->original_fcw =
978 ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;
981 /* save original TOPs */
982 deb_info("save original TOPs\n");
986 af9005_read_word_agc(state->d,
987 xd_p_reg_aagc_rf_top_numerator_9_8,
988 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
989 &state->original_rf_top);
995 af9005_read_word_agc(state->d,
996 xd_p_reg_aagc_if_top_numerator_9_8,
997 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
998 &state->original_if_top);
1004 af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1005 &state->original_aci0_if_top);
1011 af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1012 &state->original_aci1_if_top);
1016 /* attach tuner and init */
1017 if (fe->ops.tuner_ops.release == NULL) {
1018 /* read tuner and board id from eeprom */
1019 ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2);
1021 err("Impossible to read EEPROM\n");
1024 deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]);
1026 case 2: /* MT2060 */
1027 /* read if1 from eeprom */
1028 ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2);
1030 err("Impossible to read EEPROM\n");
1033 if1 = (u16) (buf[0] << 8) + buf[1];
1034 if (dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap,
1035 &af9005_mt2060_config, if1) == NULL) {
1036 deb_info("MT2060 attach failed\n");
1040 case 3: /* QT1010 */
1041 case 9: /* QT1010B */
1042 if (dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap,
1043 &af9005_qt1010_config) ==NULL) {
1044 deb_info("QT1010 attach failed\n");
1049 err("Unsupported tuner type %d", buf[0]);
1052 ret = fe->ops.tuner_ops.init(fe);
1057 deb_info("profit!\n");
1061 static int af9005_fe_sleep(struct dvb_frontend *fe)
1063 return af9005_fe_power(fe, 0);
1066 static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
1068 struct af9005_fe_state *state = fe->demodulator_priv;
1076 af9005_led_control(state->d, 0);
1081 static int af9005_fe_set_frontend(struct dvb_frontend *fe,
1082 struct dvb_frontend_parameters *fep)
1084 struct af9005_fe_state *state = fe->demodulator_priv;
1086 u8 temp, temp0, temp1, temp2;
1088 deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
1089 fep->u.ofdm.bandwidth);
1090 if (fe->ops.tuner_ops.release == NULL) {
1091 err("Tuner not attached");
1095 deb_info("turn off led\n");
1096 /* not in the log */
1097 ret = af9005_led_control(state->d, 0);
1100 /* not sure about the bits */
1101 ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0);
1105 /* set FCW to default value */
1106 deb_info("set FCW to default value\n");
1107 temp0 = (u8) (state->original_fcw & 0x000000ff);
1108 temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8);
1109 temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16);
1110 ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0);
1113 ret = af9005_write_ofdm_register(state->d, 0xae19, temp1);
1116 ret = af9005_write_ofdm_register(state->d, 0xae18, temp2);
1120 /* restore original TOPs */
1121 deb_info("restore original TOPs\n");
1123 af9005_write_word_agc(state->d,
1124 xd_p_reg_aagc_rf_top_numerator_9_8,
1125 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1126 state->original_rf_top);
1130 af9005_write_word_agc(state->d,
1131 xd_p_reg_aagc_if_top_numerator_9_8,
1132 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1133 state->original_if_top);
1137 af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1138 state->original_aci0_if_top);
1142 af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1143 state->original_aci1_if_top);
1147 /* select bandwidth */
1148 deb_info("select bandwidth");
1149 ret = af9005_fe_select_bw(state->d, fep->u.ofdm.bandwidth);
1152 ret = af9005_fe_program_cfoe(state->d, fep->u.ofdm.bandwidth);
1156 /* clear easy mode flag */
1157 deb_info("clear easy mode flag\n");
1158 ret = af9005_write_ofdm_register(state->d, 0xaefd, 0);
1162 /* set unplug threshold to original value */
1163 deb_info("set unplug threshold to original value\n");
1165 af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th,
1166 state->original_if_unplug_th);
1170 deb_info("set tuner\n");
1171 ret = fe->ops.tuner_ops.set_params(fe, fep);
1176 deb_info("trigger ofsm\n");
1178 ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1);
1182 /* clear retrain and freeze flag */
1183 deb_info("clear retrain and freeze flag\n");
1185 af9005_write_register_bits(state->d,
1186 xd_p_reg_api_retrain_request,
1187 reg_api_retrain_request_pos, 2, 0);
1191 /* reset pre viterbi and post viterbi registers and statistics */
1192 af9005_reset_pre_viterbi(fe);
1193 af9005_reset_post_viterbi(fe);
1194 state->pre_vit_error_count = 0;
1195 state->pre_vit_bit_count = 0;
1197 state->post_vit_error_count = 0;
1198 /* state->unc = 0; commented out since it should be ever increasing */
1199 state->abort_count = 0;
1201 state->next_status_check = jiffies;
1207 static int af9005_fe_get_frontend(struct dvb_frontend *fe,
1208 struct dvb_frontend_parameters *fep)
1210 struct af9005_fe_state *state = fe->demodulator_priv;
1216 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
1217 reg_tpsd_const_pos, reg_tpsd_const_len,
1221 deb_info("===== fe_get_frontend ==============\n");
1222 deb_info("CONSTELLATION ");
1225 fep->u.ofdm.constellation = QPSK;
1229 fep->u.ofdm.constellation = QAM_16;
1230 deb_info("QAM_16\n");
1233 fep->u.ofdm.constellation = QAM_64;
1234 deb_info("QAM_64\n");
1238 /* tps hierarchy and alpha value */
1240 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier,
1241 reg_tpsd_hier_pos, reg_tpsd_hier_len,
1245 deb_info("HIERARCHY ");
1248 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1252 fep->u.ofdm.hierarchy_information = HIERARCHY_1;
1256 fep->u.ofdm.hierarchy_information = HIERARCHY_2;
1260 fep->u.ofdm.hierarchy_information = HIERARCHY_4;
1265 /* high/low priority */
1267 af9005_read_register_bits(state->d, xd_g_reg_dec_pri,
1268 reg_dec_pri_pos, reg_dec_pri_len, &temp);
1271 /* if temp is set = high priority */
1272 deb_info("PRIORITY %s\n", temp ? "high" : "low");
1276 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr,
1277 reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len,
1281 deb_info("CODERATE HP ");
1284 fep->u.ofdm.code_rate_HP = FEC_1_2;
1285 deb_info("FEC_1_2\n");
1288 fep->u.ofdm.code_rate_HP = FEC_2_3;
1289 deb_info("FEC_2_3\n");
1292 fep->u.ofdm.code_rate_HP = FEC_3_4;
1293 deb_info("FEC_3_4\n");
1296 fep->u.ofdm.code_rate_HP = FEC_5_6;
1297 deb_info("FEC_5_6\n");
1300 fep->u.ofdm.code_rate_HP = FEC_7_8;
1301 deb_info("FEC_7_8\n");
1307 af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr,
1308 reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len,
1312 deb_info("CODERATE LP ");
1315 fep->u.ofdm.code_rate_LP = FEC_1_2;
1316 deb_info("FEC_1_2\n");
1319 fep->u.ofdm.code_rate_LP = FEC_2_3;
1320 deb_info("FEC_2_3\n");
1323 fep->u.ofdm.code_rate_LP = FEC_3_4;
1324 deb_info("FEC_3_4\n");
1327 fep->u.ofdm.code_rate_LP = FEC_5_6;
1328 deb_info("FEC_5_6\n");
1331 fep->u.ofdm.code_rate_LP = FEC_7_8;
1332 deb_info("FEC_7_8\n");
1336 /* guard interval */
1338 af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi,
1339 reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
1342 deb_info("GUARD INTERVAL ");
1345 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1349 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1353 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1357 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1364 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
1365 reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
1369 deb_info("TRANSMISSION MODE ");
1372 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1376 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1383 af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos,
1385 deb_info("BANDWIDTH ");
1388 fep->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1392 fep->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1396 fep->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1403 static void af9005_fe_release(struct dvb_frontend *fe)
1405 struct af9005_fe_state *state =
1406 (struct af9005_fe_state *)fe->demodulator_priv;
1410 static struct dvb_frontend_ops af9005_fe_ops;
1412 struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d)
1414 struct af9005_fe_state *state = NULL;
1416 /* allocate memory for the internal state */
1417 state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL);
1421 deb_info("attaching frontend af9005\n");
1426 memcpy(&state->frontend.ops, &af9005_fe_ops,
1427 sizeof(struct dvb_frontend_ops));
1428 state->frontend.demodulator_priv = state;
1430 return &state->frontend;
1435 static struct dvb_frontend_ops af9005_fe_ops = {
1437 .name = "AF9005 USB DVB-T",
1439 .frequency_min = 44250000,
1440 .frequency_max = 867250000,
1441 .frequency_stepsize = 250000,
1442 .caps = FE_CAN_INVERSION_AUTO |
1443 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1444 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1445 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1446 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
1447 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
1448 FE_CAN_HIERARCHY_AUTO,
1451 .release = af9005_fe_release,
1453 .init = af9005_fe_init,
1454 .sleep = af9005_fe_sleep,
1455 .ts_bus_ctrl = af9005_ts_bus_ctrl,
1457 .set_frontend = af9005_fe_set_frontend,
1458 .get_frontend = af9005_fe_get_frontend,
1460 .read_status = af9005_fe_read_status,
1461 .read_ber = af9005_fe_read_ber,
1462 .read_signal_strength = af9005_fe_read_signal_strength,
1463 .read_snr = af9005_fe_read_snr,
1464 .read_ucblocks = af9005_fe_read_unc_blocks,