drivers/media/dvb-frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*(DEBLOBBED)*/
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/device.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/string.h>
  29 #include <linux/slab.h>
  30
  31 #include "dvb_frontend.h"
  32 #include "tda1004x.h"
  33
  34 static int debug;
  35 #define dprintk(args...) \
  36         do { \
  37                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  38         } while (0)
  39
  40 #define TDA1004X_CHIPID          0x00
  41 #define TDA1004X_AUTO            0x01
  42 #define TDA1004X_IN_CONF1        0x02
  43 #define TDA1004X_IN_CONF2        0x03
  44 #define TDA1004X_OUT_CONF1       0x04
  45 #define TDA1004X_OUT_CONF2       0x05
  46 #define TDA1004X_STATUS_CD       0x06
  47 #define TDA1004X_CONFC4          0x07
  48 #define TDA1004X_DSSPARE2        0x0C
  49 #define TDA10045H_CODE_IN        0x0D
  50 #define TDA10045H_FWPAGE         0x0E
  51 #define TDA1004X_SCAN_CPT        0x10
  52 #define TDA1004X_DSP_CMD         0x11
  53 #define TDA1004X_DSP_ARG         0x12
  54 #define TDA1004X_DSP_DATA1       0x13
  55 #define TDA1004X_DSP_DATA2       0x14
  56 #define TDA1004X_CONFADC1        0x15
  57 #define TDA1004X_CONFC1          0x16
  58 #define TDA10045H_S_AGC          0x1a
  59 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  60 #define TDA1004X_SNR             0x1c
  61 #define TDA1004X_CONF_TS1        0x1e
  62 #define TDA1004X_CONF_TS2        0x1f
  63 #define TDA1004X_CBER_RESET      0x20
  64 #define TDA1004X_CBER_MSB        0x21
  65 #define TDA1004X_CBER_LSB        0x22
  66 #define TDA1004X_CVBER_LUT       0x23
  67 #define TDA1004X_VBER_MSB        0x24
  68 #define TDA1004X_VBER_MID        0x25
  69 #define TDA1004X_VBER_LSB        0x26
  70 #define TDA1004X_UNCOR           0x27
  71
  72 #define TDA10045H_CONFPLL_P      0x2D
  73 #define TDA10045H_CONFPLL_M_MSB  0x2E
  74 #define TDA10045H_CONFPLL_M_LSB  0x2F
  75 #define TDA10045H_CONFPLL_N      0x30
  76
  77 #define TDA10046H_CONFPLL1       0x2D
  78 #define TDA10046H_CONFPLL2       0x2F
  79 #define TDA10046H_CONFPLL3       0x30
  80 #define TDA10046H_TIME_WREF1     0x31
  81 #define TDA10046H_TIME_WREF2     0x32
  82 #define TDA10046H_TIME_WREF3     0x33
  83 #define TDA10046H_TIME_WREF4     0x34
  84 #define TDA10046H_TIME_WREF5     0x35
  85
  86 #define TDA10045H_UNSURW_MSB     0x31
  87 #define TDA10045H_UNSURW_LSB     0x32
  88 #define TDA10045H_WREF_MSB       0x33
  89 #define TDA10045H_WREF_MID       0x34
  90 #define TDA10045H_WREF_LSB       0x35
  91 #define TDA10045H_MUXOUT         0x36
  92 #define TDA1004X_CONFADC2        0x37
  93
  94 #define TDA10045H_IOFFSET        0x38
  95
  96 #define TDA10046H_CONF_TRISTATE1 0x3B
  97 #define TDA10046H_CONF_TRISTATE2 0x3C
  98 #define TDA10046H_CONF_POLARITY  0x3D
  99 #define TDA10046H_FREQ_OFFSET    0x3E
 100 #define TDA10046H_GPIO_OUT_SEL   0x41
 101 #define TDA10046H_GPIO_SELECT    0x42
 102 #define TDA10046H_AGC_CONF       0x43
 103 #define TDA10046H_AGC_THR        0x44
 104 #define TDA10046H_AGC_RENORM     0x45
 105 #define TDA10046H_AGC_GAINS      0x46
 106 #define TDA10046H_AGC_TUN_MIN    0x47
 107 #define TDA10046H_AGC_TUN_MAX    0x48
 108 #define TDA10046H_AGC_IF_MIN     0x49
 109 #define TDA10046H_AGC_IF_MAX     0x4A
 110
 111 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 112 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 113
 114 #define TDA10046H_CVBER_CTRL     0x4F
 115 #define TDA10046H_AGC_IF_LEVEL   0x52
 116 #define TDA10046H_CODE_CPT       0x57
 117 #define TDA10046H_CODE_IN        0x58
 118
 119
 120 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 121 {
 122         int ret;
 123         u8 buf[] = { reg, data };
 124         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 125
 126         dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data);
 127
 128         msg.addr = state->config->demod_address;
 129         ret = i2c_transfer(state->i2c, &msg, 1);
 130
 131         if (ret != 1)
 132                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 133                         __func__, reg, data, ret);
 134
 135         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
 136                 reg, data, ret);
 137         return (ret != 1) ? -1 : 0;
 138 }
 139
 140 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 141 {
 142         int ret;
 143         u8 b0[] = { reg };
 144         u8 b1[] = { 0 };
 145         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 146                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 147
 148         dprintk("%s: reg=0x%x\n", __func__, reg);
 149
 150         msg[0].addr = state->config->demod_address;
 151         msg[1].addr = state->config->demod_address;
 152         ret = i2c_transfer(state->i2c, msg, 2);
 153
 154         if (ret != 2) {
 155                 dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
 156                         ret);
 157                 return -EINVAL;
 158         }
 159
 160         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
 161                 reg, b1[0], ret);
 162         return b1[0];
 163 }
 164
 165 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 166 {
 167         int val;
 168         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg,
 169                 mask, data);
 170
 171         // read a byte and check
 172         val = tda1004x_read_byte(state, reg);
 173         if (val < 0)
 174                 return val;
 175
 176         // mask if off
 177         val = val & ~mask;
 178         val |= data & 0xff;
 179
 180         // write it out again
 181         return tda1004x_write_byteI(state, reg, val);
 182 }
 183
 184 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 185 {
 186         int i;
 187         int result;
 188
 189         dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len);
 190
 191         result = 0;
 192         for (i = 0; i < len; i++) {
 193                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 194                 if (result != 0)
 195                         break;
 196         }
 197
 198         return result;
 199 }
 200
 201 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 202 {
 203         int result;
 204         dprintk("%s\n", __func__);
 205
 206         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 207         msleep(20);
 208         return result;
 209 }
 210
 211 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 212 {
 213         dprintk("%s\n", __func__);
 214
 215         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 216 }
 217
 218 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 219                                    u32 bandwidth)
 220 {
 221         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 222         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 223         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 224
 225         switch (bandwidth) {
 226         case 6000000:
 227                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 228                 break;
 229
 230         case 7000000:
 231                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 232                 break;
 233
 234         case 8000000:
 235                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 236                 break;
 237
 238         default:
 239                 return -EINVAL;
 240         }
 241
 242         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 243
 244         return 0;
 245 }
 246
 247 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 248                                    u32 bandwidth)
 249 {
 250         static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
 251         static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
 252         static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
 253
 254         static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
 255         static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
 256         static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
 257         int tda10046_clk53m;
 258
 259         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 260             (state->config->if_freq == TDA10046_FREQ_052))
 261                 tda10046_clk53m = 0;
 262         else
 263                 tda10046_clk53m = 1;
 264         switch (bandwidth) {
 265         case 6000000:
 266                 if (tda10046_clk53m)
 267                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
 268                                                   sizeof(bandwidth_6mhz_53M));
 269                 else
 270                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
 271                                                   sizeof(bandwidth_6mhz_48M));
 272                 if (state->config->if_freq == TDA10046_FREQ_045) {
 273                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
 274                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
 275                 }
 276                 break;
 277
 278         case 7000000:
 279                 if (tda10046_clk53m)
 280                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
 281                                                   sizeof(bandwidth_7mhz_53M));
 282                 else
 283                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
 284                                                   sizeof(bandwidth_7mhz_48M));
 285                 if (state->config->if_freq == TDA10046_FREQ_045) {
 286                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 287                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 288                 }
 289                 break;
 290
 291         case 8000000:
 292                 if (tda10046_clk53m)
 293                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
 294                                                   sizeof(bandwidth_8mhz_53M));
 295                 else
 296                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
 297                                                   sizeof(bandwidth_8mhz_48M));
 298                 if (state->config->if_freq == TDA10046_FREQ_045) {
 299                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 300                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
 301                 }
 302                 break;
 303
 304         default:
 305                 return -EINVAL;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static int tda1004x_do_upload(struct tda1004x_state *state,
 312                               const unsigned char *mem, unsigned int len,
 313                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 314 {
 315         u8 buf[65];
 316         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 317         int tx_size;
 318         int pos = 0;
 319
 320         /* clear code counter */
 321         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 322         fw_msg.addr = state->config->demod_address;
 323
 324         i2c_lock_adapter(state->i2c);
 325         buf[0] = dspCodeInReg;
 326         while (pos != len) {
 327                 // work out how much to send this time
 328                 tx_size = len - pos;
 329                 if (tx_size > 0x10)
 330                         tx_size = 0x10;
 331
 332                 // send the chunk
 333                 memcpy(buf + 1, mem + pos, tx_size);
 334                 fw_msg.len = tx_size + 1;
 335                 if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 336                         printk(KERN_ERR "tda1004x: Error during firmware upload\n");
 337                         i2c_unlock_adapter(state->i2c);
 338                         return -EIO;
 339                 }
 340                 pos += tx_size;
 341
 342                 dprintk("%s: fw_pos=0x%x\n", __func__, pos);
 343         }
 344         i2c_unlock_adapter(state->i2c);
 345
 346         /* give the DSP a chance to settle 03/10/05 Hac */
 347         msleep(100);
 348
 349         return 0;
 350 }
 351
 352 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
 353 {
 354         u8 data1, data2;
 355         unsigned long timeout;
 356
 357         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 358                 timeout = jiffies + 2 * HZ;
 359                 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 360                         if (time_after(jiffies, timeout)) {
 361                                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
 362                                 break;
 363                         }
 364                         msleep(1);
 365                 }
 366         } else
 367                 msleep(100);
 368
 369         // check upload was OK
 370         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 371         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 372
 373         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 374         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 375         if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
 376                 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
 377                 return -EIO;
 378         }
 379         printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
 380         return 0;
 381 }
 382
 383 static int tda10045_fwupload(struct dvb_frontend* fe)
 384 {
 385         struct tda1004x_state* state = fe->demodulator_priv;
 386         int ret;
 387         const struct firmware *fw;
 388
 389         /* don't re-upload unless necessary */
 390         if (tda1004x_check_upload_ok(state) == 0)
 391                 return 0;
 392
 393         /* request the firmware, this will block until someone uploads it */
 394         printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", "/*(DEBLOBBED)*/");
 395         ret = state->config->reject_firmware(fe, &fw, "/*(DEBLOBBED)*/");
 396         if (ret) {
 397                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 398                 return ret;
 399         }
 400
 401         /* reset chip */
 402         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 403         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 404         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 405         msleep(10);
 406
 407         /* set parameters */
 408         tda10045h_set_bandwidth(state, 8000000);
 409
 410         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 411         release_firmware(fw);
 412         if (ret)
 413                 return ret;
 414         printk(KERN_INFO "tda1004x: firmware upload complete\n");
 415
 416         /* wait for DSP to initialise */
 417         /* DSPREADY doesn't seem to work on the TDA10045H */
 418         msleep(100);
 419
 420         return tda1004x_check_upload_ok(state);
 421 }
 422
 423 static void tda10046_init_plls(struct dvb_frontend* fe)
 424 {
 425         struct tda1004x_state* state = fe->demodulator_priv;
 426         int tda10046_clk53m;
 427
 428         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 429             (state->config->if_freq == TDA10046_FREQ_052))
 430                 tda10046_clk53m = 0;
 431         else
 432                 tda10046_clk53m = 1;
 433
 434         tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
 435         if(tda10046_clk53m) {
 436                 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
 437                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
 438         } else {
 439                 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
 440                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
 441         }
 442         if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
 443                 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__);
 444                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 445         } else {
 446                 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__);
 447                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
 448         }
 449         if(tda10046_clk53m)
 450                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
 451         else
 452                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
 453         /* Note clock frequency is handled implicitly */
 454         switch (state->config->if_freq) {
 455         case TDA10046_FREQ_045:
 456                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 457                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 458                 break;
 459         case TDA10046_FREQ_052:
 460                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 461                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
 462                 break;
 463         case TDA10046_FREQ_3617:
 464                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 465                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
 466                 break;
 467         case TDA10046_FREQ_3613:
 468                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 469                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
 470                 break;
 471         }
 472         tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */
 473         /* let the PLLs settle */
 474         msleep(120);
 475 }
 476
 477 static int tda10046_fwupload(struct dvb_frontend* fe)
 478 {
 479         struct tda1004x_state* state = fe->demodulator_priv;
 480         int ret, confc4;
 481         const struct firmware *fw;
 482
 483         /* reset + wake up chip */
 484         if (state->config->xtal_freq == TDA10046_XTAL_4M) {
 485                 confc4 = 0;
 486         } else {
 487                 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__);
 488                 confc4 = 0x80;
 489         }
 490         tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
 491
 492         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 493         /* set GPIO 1 and 3 */
 494         if (state->config->gpio_config != TDA10046_GPTRI) {
 495                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
 496                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
 497         }
 498         /* let the clocks recover from sleep */
 499         msleep(10);
 500
 501         /* The PLLs need to be reprogrammed after sleep */
 502         tda10046_init_plls(fe);
 503         tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
 504
 505         /* don't re-upload unless necessary */
 506         if (tda1004x_check_upload_ok(state) == 0)
 507                 return 0;
 508
 509         /*
 510            For i2c normal work, we need to slow down the bus speed.
 511            However, the slow down breaks the eeprom firmware load.
 512            So, use normal speed for eeprom booting and then restore the
 513            i2c speed after that. Tested with MSI TV @nyware A/D board,
 514            that comes with firmware version 29 inside their eeprom.
 515
 516            It should also be noticed that no other I2C transfer should
 517            be in course while booting from eeprom, otherwise, tda10046
 518            goes into an instable state. So, proper locking are needed
 519            at the i2c bus master.
 520          */
 521         printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
 522         tda1004x_write_byteI(state, TDA1004X_CONFC4, 4);
 523         msleep(300);
 524         tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
 525
 526         /* Checks if eeprom firmware went without troubles */
 527         if (tda1004x_check_upload_ok(state) == 0)
 528                 return 0;
 529
 530         /* eeprom firmware didn't work. Load one manually. */
 531
 532         if (state->config->reject_firmware != NULL) {
 533                 /* request the firmware, this will block until someone uploads it */
 534                 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
 535                 ret = state->config->reject_firmware(fe, &fw, "/*(DEBLOBBED)*/");
 536                 if (ret) {
 537                         /* remain compatible to old bug: try to load with tda10045 image name */
 538                         ret = state->config->reject_firmware(fe, &fw, "/*(DEBLOBBED)*/");
 539                         if (ret) {
 540                                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 541                                 return ret;
 542                         } else {
 543                                 printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
 544                                                   "/*(DEBLOBBED)*/");
 545                         }
 546                 }
 547         } else {
 548                 printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
 549                 return -EIO;
 550         }
 551         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 552         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 553         release_firmware(fw);
 554         return tda1004x_check_upload_ok(state);
 555 }
 556
 557 static int tda1004x_encode_fec(int fec)
 558 {
 559         // convert known FEC values
 560         switch (fec) {
 561         case FEC_1_2:
 562                 return 0;
 563         case FEC_2_3:
 564                 return 1;
 565         case FEC_3_4:
 566                 return 2;
 567         case FEC_5_6:
 568                 return 3;
 569         case FEC_7_8:
 570                 return 4;
 571         }
 572
 573         // unsupported
 574         return -EINVAL;
 575 }
 576
 577 static int tda1004x_decode_fec(int tdafec)
 578 {
 579         // convert known FEC values
 580         switch (tdafec) {
 581         case 0:
 582                 return FEC_1_2;
 583         case 1:
 584                 return FEC_2_3;
 585         case 2:
 586                 return FEC_3_4;
 587         case 3:
 588                 return FEC_5_6;
 589         case 4:
 590                 return FEC_7_8;
 591         }
 592
 593         // unsupported
 594         return -1;
 595 }
 596
 597 static int tda1004x_write(struct dvb_frontend* fe, const u8 buf[], int len)
 598 {
 599         struct tda1004x_state* state = fe->demodulator_priv;
 600
 601         if (len != 2)
 602                 return -EINVAL;
 603
 604         return tda1004x_write_byteI(state, buf[0], buf[1]);
 605 }
 606
 607 static int tda10045_init(struct dvb_frontend* fe)
 608 {
 609         struct tda1004x_state* state = fe->demodulator_priv;
 610
 611         dprintk("%s\n", __func__);
 612
 613         if (tda10045_fwupload(fe)) {
 614                 printk("tda1004x: firmware upload failed\n");
 615                 return -EIO;
 616         }
 617
 618         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 619
 620         // tda setup
 621         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 622         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 623         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 624         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 625         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 626         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 627         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 628         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 629         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 630         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 631         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 632
 633         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 634
 635         return 0;
 636 }
 637
 638 static int tda10046_init(struct dvb_frontend* fe)
 639 {
 640         struct tda1004x_state* state = fe->demodulator_priv;
 641         dprintk("%s\n", __func__);
 642
 643         if (tda10046_fwupload(fe)) {
 644                 printk("tda1004x: firmware upload failed\n");
 645                         return -EIO;
 646         }
 647
 648         // tda setup
 649         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 650         tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87);    // 100 ppm crystal, select HP stream
 651         tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88);      // enable pulse killer
 652
 653         switch (state->config->agc_config) {
 654         case TDA10046_AGC_DEFAULT:
 655                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
 656                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 657                 break;
 658         case TDA10046_AGC_IFO_AUTO_NEG:
 659                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 660                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 661                 break;
 662         case TDA10046_AGC_IFO_AUTO_POS:
 663                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 664                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00);  // set AGC polarities
 665                 break;
 666         case TDA10046_AGC_TDA827X:
 667                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 668                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 669                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 670                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 671                 break;
 672         }
 673         if (state->config->ts_mode == 0) {
 674                 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
 675                 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 676         } else {
 677                 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
 678                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
 679                                                         state->config->invert_oclk << 4);
 680         }
 681         tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
 682         tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
 683         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 684         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 685         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 686         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 687         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
 688         tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
 689         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 690         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
 691         // tda1004x_write_mask(state, 0x50, 0x80, 0x80);         // handle out of guard echoes
 692
 693         return 0;
 694 }
 695
 696 static int tda1004x_set_fe(struct dvb_frontend *fe)
 697 {
 698         struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
 699         struct tda1004x_state* state = fe->demodulator_priv;
 700         int tmp;
 701         int inversion;
 702
 703         dprintk("%s\n", __func__);
 704
 705         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 706                 // setup auto offset
 707                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 708                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 709                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 710
 711                 // disable agc_conf[2]
 712                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 713         }
 714
 715         // set frequency
 716         if (fe->ops.tuner_ops.set_params) {
 717                 fe->ops.tuner_ops.set_params(fe);
 718                 if (fe->ops.i2c_gate_ctrl)
 719                         fe->ops.i2c_gate_ctrl(fe, 0);
 720         }
 721
 722         // Hardcoded to use auto as much as possible on the TDA10045 as it
 723         // is very unreliable if AUTO mode is _not_ used.
 724         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 725                 fe_params->code_rate_HP = FEC_AUTO;
 726                 fe_params->guard_interval = GUARD_INTERVAL_AUTO;
 727                 fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
 728         }
 729
 730         // Set standard params.. or put them to auto
 731         if ((fe_params->code_rate_HP == FEC_AUTO) ||
 732                 (fe_params->code_rate_LP == FEC_AUTO) ||
 733                 (fe_params->modulation == QAM_AUTO) ||
 734                 (fe_params->hierarchy == HIERARCHY_AUTO)) {
 735                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 736                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */
 737                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 738                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 739         } else {
 740                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 741
 742                 // set HP FEC
 743                 tmp = tda1004x_encode_fec(fe_params->code_rate_HP);
 744                 if (tmp < 0)
 745                         return tmp;
 746                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 747
 748                 // set LP FEC
 749                 tmp = tda1004x_encode_fec(fe_params->code_rate_LP);
 750                 if (tmp < 0)
 751                         return tmp;
 752                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 753
 754                 /* set modulation */
 755                 switch (fe_params->modulation) {
 756                 case QPSK:
 757                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 758                         break;
 759
 760                 case QAM_16:
 761                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 762                         break;
 763
 764                 case QAM_64:
 765                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 766                         break;
 767
 768                 default:
 769                         return -EINVAL;
 770                 }
 771
 772                 // set hierarchy
 773                 switch (fe_params->hierarchy) {
 774                 case HIERARCHY_NONE:
 775                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 776                         break;
 777
 778                 case HIERARCHY_1:
 779                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 780                         break;
 781
 782                 case HIERARCHY_2:
 783                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 784                         break;
 785
 786                 case HIERARCHY_4:
 787                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 788                         break;
 789
 790                 default:
 791                         return -EINVAL;
 792                 }
 793         }
 794
 795         // set bandwidth
 796         switch (state->demod_type) {
 797         case TDA1004X_DEMOD_TDA10045:
 798                 tda10045h_set_bandwidth(state, fe_params->bandwidth_hz);
 799                 break;
 800
 801         case TDA1004X_DEMOD_TDA10046:
 802                 tda10046h_set_bandwidth(state, fe_params->bandwidth_hz);
 803                 break;
 804         }
 805
 806         // set inversion
 807         inversion = fe_params->inversion;
 808         if (state->config->invert)
 809                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 810         switch (inversion) {
 811         case INVERSION_OFF:
 812                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 813                 break;
 814
 815         case INVERSION_ON:
 816                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 817                 break;
 818
 819         default:
 820                 return -EINVAL;
 821         }
 822
 823         // set guard interval
 824         switch (fe_params->guard_interval) {
 825         case GUARD_INTERVAL_1_32:
 826                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 827                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 828                 break;
 829
 830         case GUARD_INTERVAL_1_16:
 831                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 832                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 833                 break;
 834
 835         case GUARD_INTERVAL_1_8:
 836                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 837                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 838                 break;
 839
 840         case GUARD_INTERVAL_1_4:
 841                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 842                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 843                 break;
 844
 845         case GUARD_INTERVAL_AUTO:
 846                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 847                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 848                 break;
 849
 850         default:
 851                 return -EINVAL;
 852         }
 853
 854         // set transmission mode
 855         switch (fe_params->transmission_mode) {
 856         case TRANSMISSION_MODE_2K:
 857                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 858                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 859                 break;
 860
 861         case TRANSMISSION_MODE_8K:
 862                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 863                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 864                 break;
 865
 866         case TRANSMISSION_MODE_AUTO:
 867                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 868                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 869                 break;
 870
 871         default:
 872                 return -EINVAL;
 873         }
 874
 875         // start the lock
 876         switch (state->demod_type) {
 877         case TDA1004X_DEMOD_TDA10045:
 878                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 879                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 880                 break;
 881
 882         case TDA1004X_DEMOD_TDA10046:
 883                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 884                 msleep(1);
 885                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
 886                 break;
 887         }
 888
 889         msleep(10);
 890
 891         return 0;
 892 }
 893
 894 static int tda1004x_get_fe(struct dvb_frontend *fe)
 895 {
 896         struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
 897         struct tda1004x_state* state = fe->demodulator_priv;
 898
 899         dprintk("%s\n", __func__);
 900
 901         // inversion status
 902         fe_params->inversion = INVERSION_OFF;
 903         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 904                 fe_params->inversion = INVERSION_ON;
 905         if (state->config->invert)
 906                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 907
 908         // bandwidth
 909         switch (state->demod_type) {
 910         case TDA1004X_DEMOD_TDA10045:
 911                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 912                 case 0x14:
 913                         fe_params->bandwidth_hz = 8000000;
 914                         break;
 915                 case 0xdb:
 916                         fe_params->bandwidth_hz = 7000000;
 917                         break;
 918                 case 0x4f:
 919                         fe_params->bandwidth_hz = 6000000;
 920                         break;
 921                 }
 922                 break;
 923         case TDA1004X_DEMOD_TDA10046:
 924                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 925                 case 0x5c:
 926                 case 0x54:
 927                         fe_params->bandwidth_hz = 8000000;
 928                         break;
 929                 case 0x6a:
 930                 case 0x60:
 931                         fe_params->bandwidth_hz = 7000000;
 932                         break;
 933                 case 0x7b:
 934                 case 0x70:
 935                         fe_params->bandwidth_hz = 6000000;
 936                         break;
 937                 }
 938                 break;
 939         }
 940
 941         // FEC
 942         fe_params->code_rate_HP =
 943             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 944         fe_params->code_rate_LP =
 945             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 946
 947         /* modulation */
 948         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 949         case 0:
 950                 fe_params->modulation = QPSK;
 951                 break;
 952         case 1:
 953                 fe_params->modulation = QAM_16;
 954                 break;
 955         case 2:
 956                 fe_params->modulation = QAM_64;
 957                 break;
 958         }
 959
 960         // transmission mode
 961         fe_params->transmission_mode = TRANSMISSION_MODE_2K;
 962         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 963                 fe_params->transmission_mode = TRANSMISSION_MODE_8K;
 964
 965         // guard interval
 966         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 967         case 0:
 968                 fe_params->guard_interval = GUARD_INTERVAL_1_32;
 969                 break;
 970         case 1:
 971                 fe_params->guard_interval = GUARD_INTERVAL_1_16;
 972                 break;
 973         case 2:
 974                 fe_params->guard_interval = GUARD_INTERVAL_1_8;
 975                 break;
 976         case 3:
 977                 fe_params->guard_interval = GUARD_INTERVAL_1_4;
 978                 break;
 979         }
 980
 981         // hierarchy
 982         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 983         case 0:
 984                 fe_params->hierarchy = HIERARCHY_NONE;
 985                 break;
 986         case 1:
 987                 fe_params->hierarchy = HIERARCHY_1;
 988                 break;
 989         case 2:
 990                 fe_params->hierarchy = HIERARCHY_2;
 991                 break;
 992         case 3:
 993                 fe_params->hierarchy = HIERARCHY_4;
 994                 break;
 995         }
 996
 997         return 0;
 998 }
 999
1000 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
1001 {
1002         struct tda1004x_state* state = fe->demodulator_priv;
1003         int status;
1004         int cber;
1005         int vber;
1006
1007         dprintk("%s\n", __func__);
1008
1009         // read status
1010         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
1011         if (status == -1)
1012                 return -EIO;
1013
1014         // decode
1015         *fe_status = 0;
1016         if (status & 4)
1017                 *fe_status |= FE_HAS_SIGNAL;
1018         if (status & 2)
1019                 *fe_status |= FE_HAS_CARRIER;
1020         if (status & 8)
1021                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1022
1023         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1024         // is getting anything valid
1025         if (!(*fe_status & FE_HAS_VITERBI)) {
1026                 // read the CBER
1027                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1028                 if (cber == -1)
1029                         return -EIO;
1030                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1031                 if (status == -1)
1032                         return -EIO;
1033                 cber |= (status << 8);
1034                 // The address 0x20 should be read to cope with a TDA10046 bug
1035                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1036
1037                 if (cber != 65535)
1038                         *fe_status |= FE_HAS_VITERBI;
1039         }
1040
1041         // if we DO have some valid VITERBI output, but don't already have SYNC
1042         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1043         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1044                 // read the VBER
1045                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1046                 if (vber == -1)
1047                         return -EIO;
1048                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1049                 if (status == -1)
1050                         return -EIO;
1051                 vber |= (status << 8);
1052                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1053                 if (status == -1)
1054                         return -EIO;
1055                 vber |= (status & 0x0f) << 16;
1056                 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1057                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1058
1059                 // if RS has passed some valid TS packets, then we must be
1060                 // getting some SYNC bytes
1061                 if (vber < 16632)
1062                         *fe_status |= FE_HAS_SYNC;
1063         }
1064
1065         // success
1066         dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
1067         return 0;
1068 }
1069
1070 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1071 {
1072         struct tda1004x_state* state = fe->demodulator_priv;
1073         int tmp;
1074         int reg = 0;
1075
1076         dprintk("%s\n", __func__);
1077
1078         // determine the register to use
1079         switch (state->demod_type) {
1080         case TDA1004X_DEMOD_TDA10045:
1081                 reg = TDA10045H_S_AGC;
1082                 break;
1083
1084         case TDA1004X_DEMOD_TDA10046:
1085                 reg = TDA10046H_AGC_IF_LEVEL;
1086                 break;
1087         }
1088
1089         // read it
1090         tmp = tda1004x_read_byte(state, reg);
1091         if (tmp < 0)
1092                 return -EIO;
1093
1094         *signal = (tmp << 8) | tmp;
1095         dprintk("%s: signal=0x%x\n", __func__, *signal);
1096         return 0;
1097 }
1098
1099 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1100 {
1101         struct tda1004x_state* state = fe->demodulator_priv;
1102         int tmp;
1103
1104         dprintk("%s\n", __func__);
1105
1106         // read it
1107         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1108         if (tmp < 0)
1109                 return -EIO;
1110         tmp = 255 - tmp;
1111
1112         *snr = ((tmp << 8) | tmp);
1113         dprintk("%s: snr=0x%x\n", __func__, *snr);
1114         return 0;
1115 }
1116
1117 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1118 {
1119         struct tda1004x_state* state = fe->demodulator_priv;
1120         int tmp;
1121         int tmp2;
1122         int counter;
1123
1124         dprintk("%s\n", __func__);
1125
1126         // read the UCBLOCKS and reset
1127         counter = 0;
1128         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1129         if (tmp < 0)
1130                 return -EIO;
1131         tmp &= 0x7f;
1132         while (counter++ < 5) {
1133                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1134                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1135                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1136
1137                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1138                 if (tmp2 < 0)
1139                         return -EIO;
1140                 tmp2 &= 0x7f;
1141                 if ((tmp2 < tmp) || (tmp2 == 0))
1142                         break;
1143         }
1144
1145         if (tmp != 0x7f)
1146                 *ucblocks = tmp;
1147         else
1148                 *ucblocks = 0xffffffff;
1149
1150         dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks);
1151         return 0;
1152 }
1153
1154 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1155 {
1156         struct tda1004x_state* state = fe->demodulator_priv;
1157         int tmp;
1158
1159         dprintk("%s\n", __func__);
1160
1161         // read it in
1162         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1163         if (tmp < 0)
1164                 return -EIO;
1165         *ber = tmp << 1;
1166         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1167         if (tmp < 0)
1168                 return -EIO;
1169         *ber |= (tmp << 9);
1170         // The address 0x20 should be read to cope with a TDA10046 bug
1171         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1172
1173         dprintk("%s: ber=0x%x\n", __func__, *ber);
1174         return 0;
1175 }
1176
1177 static int tda1004x_sleep(struct dvb_frontend* fe)
1178 {
1179         struct tda1004x_state* state = fe->demodulator_priv;
1180         int gpio_conf;
1181
1182         switch (state->demod_type) {
1183         case TDA1004X_DEMOD_TDA10045:
1184                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1185                 break;
1186
1187         case TDA1004X_DEMOD_TDA10046:
1188                 /* set outputs to tristate */
1189                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1190                 /* invert GPIO 1 and 3 if desired*/
1191                 gpio_conf = state->config->gpio_config;
1192                 if (gpio_conf >= TDA10046_GP00_I)
1193                         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
1194                                                         (gpio_conf & 0x0f) ^ 0x0a);
1195
1196                 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
1197                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1198                 break;
1199         }
1200
1201         return 0;
1202 }
1203
1204 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1205 {
1206         struct tda1004x_state* state = fe->demodulator_priv;
1207
1208         if (enable) {
1209                 return tda1004x_enable_tuner_i2c(state);
1210         } else {
1211                 return tda1004x_disable_tuner_i2c(state);
1212         }
1213 }
1214
1215 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1216 {
1217         fesettings->min_delay_ms = 800;
1218         /* Drift compensation makes no sense for DVB-T */
1219         fesettings->step_size = 0;
1220         fesettings->max_drift = 0;
1221         return 0;
1222 }
1223
1224 static void tda1004x_release(struct dvb_frontend* fe)
1225 {
1226         struct tda1004x_state *state = fe->demodulator_priv;
1227         kfree(state);
1228 }
1229
1230 static struct dvb_frontend_ops tda10045_ops = {
1231         .delsys = { SYS_DVBT },
1232         .info = {
1233                 .name = "Philips TDA10045H DVB-T",
1234                 .frequency_min = 51000000,
1235                 .frequency_max = 858000000,
1236                 .frequency_stepsize = 166667,
1237                 .caps =
1238                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1239                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1240                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1241                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1242         },
1243
1244         .release = tda1004x_release,
1245
1246         .init = tda10045_init,
1247         .sleep = tda1004x_sleep,
1248         .write = tda1004x_write,
1249         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1250
1251         .set_frontend = tda1004x_set_fe,
1252         .get_frontend = tda1004x_get_fe,
1253         .get_tune_settings = tda1004x_get_tune_settings,
1254
1255         .read_status = tda1004x_read_status,
1256         .read_ber = tda1004x_read_ber,
1257         .read_signal_strength = tda1004x_read_signal_strength,
1258         .read_snr = tda1004x_read_snr,
1259         .read_ucblocks = tda1004x_read_ucblocks,
1260 };
1261
1262 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1263                                      struct i2c_adapter* i2c)
1264 {
1265         struct tda1004x_state *state;
1266         int id;
1267
1268         /* allocate memory for the internal state */
1269         state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1270         if (!state) {
1271                 printk(KERN_ERR "Can't allocate memory for tda10045 state\n");
1272                 return NULL;
1273         }
1274
1275         /* setup the state */
1276         state->config = config;
1277         state->i2c = i2c;
1278         state->demod_type = TDA1004X_DEMOD_TDA10045;
1279
1280         /* check if the demod is there */
1281         id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1282         if (id < 0) {
1283                 printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n");
1284                 kfree(state);
1285                 return NULL;
1286         }
1287
1288         if (id != 0x25) {
1289                 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1290                 kfree(state);
1291                 return NULL;
1292         }
1293
1294         /* create dvb_frontend */
1295         memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1296         state->frontend.demodulator_priv = state;
1297         return &state->frontend;
1298 }
1299
1300 static struct dvb_frontend_ops tda10046_ops = {
1301         .delsys = { SYS_DVBT },
1302         .info = {
1303                 .name = "Philips TDA10046H DVB-T",
1304                 .frequency_min = 51000000,
1305                 .frequency_max = 858000000,
1306                 .frequency_stepsize = 166667,
1307                 .caps =
1308                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1309                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1310                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1311                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1312         },
1313
1314         .release = tda1004x_release,
1315
1316         .init = tda10046_init,
1317         .sleep = tda1004x_sleep,
1318         .write = tda1004x_write,
1319         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1320
1321         .set_frontend = tda1004x_set_fe,
1322         .get_frontend = tda1004x_get_fe,
1323         .get_tune_settings = tda1004x_get_tune_settings,
1324
1325         .read_status = tda1004x_read_status,
1326         .read_ber = tda1004x_read_ber,
1327         .read_signal_strength = tda1004x_read_signal_strength,
1328         .read_snr = tda1004x_read_snr,
1329         .read_ucblocks = tda1004x_read_ucblocks,
1330 };
1331
1332 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1333                                      struct i2c_adapter* i2c)
1334 {
1335         struct tda1004x_state *state;
1336         int id;
1337
1338         /* allocate memory for the internal state */
1339         state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1340         if (!state) {
1341                 printk(KERN_ERR "Can't allocate memory for tda10046 state\n");
1342                 return NULL;
1343         }
1344
1345         /* setup the state */
1346         state->config = config;
1347         state->i2c = i2c;
1348         state->demod_type = TDA1004X_DEMOD_TDA10046;
1349
1350         /* check if the demod is there */
1351         id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1352         if (id < 0) {
1353                 printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n");
1354                 kfree(state);
1355                 return NULL;
1356         }
1357         if (id != 0x46) {
1358                 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1359                 kfree(state);
1360                 return NULL;
1361         }
1362
1363         /* create dvb_frontend */
1364         memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1365         state->frontend.demodulator_priv = state;
1366         return &state->frontend;
1367 }
1368
1369 module_param(debug, int, 0644);
1370 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1371
1372 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1373 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1374 MODULE_LICENSE("GPL");
1375
1376 EXPORT_SYMBOL(tda10045_attach);
1377 EXPORT_SYMBOL(tda10046_attach);