drivers/media/dvb-frontends/ds3000.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Montage Technology DS3000 - DVBS/S2 Demodulator driver
   4     Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
   5
   6     Copyright (C) 2009-2012 TurboSight.com
   7
   8  */
   9
  10 #include <linux/slab.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/firmware.h>
  16
  17 #include <media/dvb_frontend.h>
  18 #include "ts2020.h"
  19 #include "ds3000.h"
  20
  21 static int debug;
  22
  23 #define dprintk(args...) \
  24         do { \
  25                 if (debug) \
  26                         printk(args); \
  27         } while (0)
  28
  29 /*(DEBLOBBED)*/
  30
  31 #define DS3000_SAMPLE_RATE 96000 /* in kHz */
  32
  33 /* Register values to initialise the demod in DVB-S mode */
  34 static u8 ds3000_dvbs_init_tab[] = {
  35         0x23, 0x05,
  36         0x08, 0x03,
  37         0x0c, 0x00,
  38         0x21, 0x54,
  39         0x25, 0x82,
  40         0x27, 0x31,
  41         0x30, 0x08,
  42         0x31, 0x40,
  43         0x32, 0x32,
  44         0x33, 0x35,
  45         0x35, 0xff,
  46         0x3a, 0x00,
  47         0x37, 0x10,
  48         0x38, 0x10,
  49         0x39, 0x02,
  50         0x42, 0x60,
  51         0x4a, 0x40,
  52         0x4b, 0x04,
  53         0x4d, 0x91,
  54         0x5d, 0xc8,
  55         0x50, 0x77,
  56         0x51, 0x77,
  57         0x52, 0x36,
  58         0x53, 0x36,
  59         0x56, 0x01,
  60         0x63, 0x43,
  61         0x64, 0x30,
  62         0x65, 0x40,
  63         0x68, 0x26,
  64         0x69, 0x4c,
  65         0x70, 0x20,
  66         0x71, 0x70,
  67         0x72, 0x04,
  68         0x73, 0x00,
  69         0x70, 0x40,
  70         0x71, 0x70,
  71         0x72, 0x04,
  72         0x73, 0x00,
  73         0x70, 0x60,
  74         0x71, 0x70,
  75         0x72, 0x04,
  76         0x73, 0x00,
  77         0x70, 0x80,
  78         0x71, 0x70,
  79         0x72, 0x04,
  80         0x73, 0x00,
  81         0x70, 0xa0,
  82         0x71, 0x70,
  83         0x72, 0x04,
  84         0x73, 0x00,
  85         0x70, 0x1f,
  86         0x76, 0x00,
  87         0x77, 0xd1,
  88         0x78, 0x0c,
  89         0x79, 0x80,
  90         0x7f, 0x04,
  91         0x7c, 0x00,
  92         0x80, 0x86,
  93         0x81, 0xa6,
  94         0x85, 0x04,
  95         0xcd, 0xf4,
  96         0x90, 0x33,
  97         0xa0, 0x44,
  98         0xc0, 0x18,
  99         0xc3, 0x10,
 100         0xc4, 0x08,
 101         0xc5, 0x80,
 102         0xc6, 0x80,
 103         0xc7, 0x0a,
 104         0xc8, 0x1a,
 105         0xc9, 0x80,
 106         0xfe, 0x92,
 107         0xe0, 0xf8,
 108         0xe6, 0x8b,
 109         0xd0, 0x40,
 110         0xf8, 0x20,
 111         0xfa, 0x0f,
 112         0xfd, 0x20,
 113         0xad, 0x20,
 114         0xae, 0x07,
 115         0xb8, 0x00,
 116 };
 117
 118 /* Register values to initialise the demod in DVB-S2 mode */
 119 static u8 ds3000_dvbs2_init_tab[] = {
 120         0x23, 0x0f,
 121         0x08, 0x07,
 122         0x0c, 0x00,
 123         0x21, 0x54,
 124         0x25, 0x82,
 125         0x27, 0x31,
 126         0x30, 0x08,
 127         0x31, 0x32,
 128         0x32, 0x32,
 129         0x33, 0x35,
 130         0x35, 0xff,
 131         0x3a, 0x00,
 132         0x37, 0x10,
 133         0x38, 0x10,
 134         0x39, 0x02,
 135         0x42, 0x60,
 136         0x4a, 0x80,
 137         0x4b, 0x04,
 138         0x4d, 0x81,
 139         0x5d, 0x88,
 140         0x50, 0x36,
 141         0x51, 0x36,
 142         0x52, 0x36,
 143         0x53, 0x36,
 144         0x63, 0x60,
 145         0x64, 0x10,
 146         0x65, 0x10,
 147         0x68, 0x04,
 148         0x69, 0x29,
 149         0x70, 0x20,
 150         0x71, 0x70,
 151         0x72, 0x04,
 152         0x73, 0x00,
 153         0x70, 0x40,
 154         0x71, 0x70,
 155         0x72, 0x04,
 156         0x73, 0x00,
 157         0x70, 0x60,
 158         0x71, 0x70,
 159         0x72, 0x04,
 160         0x73, 0x00,
 161         0x70, 0x80,
 162         0x71, 0x70,
 163         0x72, 0x04,
 164         0x73, 0x00,
 165         0x70, 0xa0,
 166         0x71, 0x70,
 167         0x72, 0x04,
 168         0x73, 0x00,
 169         0x70, 0x1f,
 170         0xa0, 0x44,
 171         0xc0, 0x08,
 172         0xc1, 0x10,
 173         0xc2, 0x08,
 174         0xc3, 0x10,
 175         0xc4, 0x08,
 176         0xc5, 0xf0,
 177         0xc6, 0xf0,
 178         0xc7, 0x0a,
 179         0xc8, 0x1a,
 180         0xc9, 0x80,
 181         0xca, 0x23,
 182         0xcb, 0x24,
 183         0xce, 0x74,
 184         0x90, 0x03,
 185         0x76, 0x80,
 186         0x77, 0x42,
 187         0x78, 0x0a,
 188         0x79, 0x80,
 189         0xad, 0x40,
 190         0xae, 0x07,
 191         0x7f, 0xd4,
 192         0x7c, 0x00,
 193         0x80, 0xa8,
 194         0x81, 0xda,
 195         0x7c, 0x01,
 196         0x80, 0xda,
 197         0x81, 0xec,
 198         0x7c, 0x02,
 199         0x80, 0xca,
 200         0x81, 0xeb,
 201         0x7c, 0x03,
 202         0x80, 0xba,
 203         0x81, 0xdb,
 204         0x85, 0x08,
 205         0x86, 0x00,
 206         0x87, 0x02,
 207         0x89, 0x80,
 208         0x8b, 0x44,
 209         0x8c, 0xaa,
 210         0x8a, 0x10,
 211         0xba, 0x00,
 212         0xf5, 0x04,
 213         0xfe, 0x44,
 214         0xd2, 0x32,
 215         0xb8, 0x00,
 216 };
 217
 218 struct ds3000_state {
 219         struct i2c_adapter *i2c;
 220         const struct ds3000_config *config;
 221         struct dvb_frontend frontend;
 222         /* previous uncorrected block counter for DVB-S2 */
 223         u16 prevUCBS2;
 224 };
 225
 226 static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
 227 {
 228         u8 buf[] = { reg, data };
 229         struct i2c_msg msg = { .addr = state->config->demod_address,
 230                 .flags = 0, .buf = buf, .len = 2 };
 231         int err;
 232
 233         dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
 234
 235         err = i2c_transfer(state->i2c, &msg, 1);
 236         if (err != 1) {
 237                 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
 238                        __func__, err, reg, data);
 239                 return -EREMOTEIO;
 240         }
 241
 242         return 0;
 243 }
 244
 245 static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 246 {
 247         struct ds3000_state *state = fe->demodulator_priv;
 248
 249         if (enable)
 250                 ds3000_writereg(state, 0x03, 0x12);
 251         else
 252                 ds3000_writereg(state, 0x03, 0x02);
 253
 254         return 0;
 255 }
 256
 257 /* I2C write for 8k firmware load */
 258 static int ds3000_writeFW(struct ds3000_state *state, int reg,
 259                                 const u8 *data, u16 len)
 260 {
 261         int i, ret = 0;
 262         struct i2c_msg msg;
 263         u8 *buf;
 264
 265         buf = kmalloc(33, GFP_KERNEL);
 266         if (!buf)
 267                 return -ENOMEM;
 268
 269         *(buf) = reg;
 270
 271         msg.addr = state->config->demod_address;
 272         msg.flags = 0;
 273         msg.buf = buf;
 274         msg.len = 33;
 275
 276         for (i = 0; i < len; i += 32) {
 277                 memcpy(buf + 1, data + i, 32);
 278
 279                 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
 280
 281                 ret = i2c_transfer(state->i2c, &msg, 1);
 282                 if (ret != 1) {
 283                         printk(KERN_ERR "%s: write error(err == %i, reg == 0x%02x\n",
 284                                __func__, ret, reg);
 285                         ret = -EREMOTEIO;
 286                         goto error;
 287                 }
 288         }
 289         ret = 0;
 290
 291 error:
 292         kfree(buf);
 293
 294         return ret;
 295 }
 296
 297 static int ds3000_readreg(struct ds3000_state *state, u8 reg)
 298 {
 299         int ret;
 300         u8 b0[] = { reg };
 301         u8 b1[] = { 0 };
 302         struct i2c_msg msg[] = {
 303                 {
 304                         .addr = state->config->demod_address,
 305                         .flags = 0,
 306                         .buf = b0,
 307                         .len = 1
 308                 }, {
 309                         .addr = state->config->demod_address,
 310                         .flags = I2C_M_RD,
 311                         .buf = b1,
 312                         .len = 1
 313                 }
 314         };
 315
 316         ret = i2c_transfer(state->i2c, msg, 2);
 317
 318         if (ret != 2) {
 319                 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
 320                 return ret;
 321         }
 322
 323         dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
 324
 325         return b1[0];
 326 }
 327
 328 static int ds3000_load_firmware(struct dvb_frontend *fe,
 329                                         const struct firmware *fw);
 330
 331 static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
 332 {
 333         struct ds3000_state *state = fe->demodulator_priv;
 334         const struct firmware *fw;
 335         int ret = 0;
 336
 337         dprintk("%s()\n", __func__);
 338
 339         ret = ds3000_readreg(state, 0xb2);
 340         if (ret < 0)
 341                 return ret;
 342
 343         /* Load firmware */
 344         /* request the firmware, this will block until someone uploads it */
 345         printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
 346                                 "/*(DEBLOBBED)*/");
 347         ret = reject_firmware(&fw, "/*(DEBLOBBED)*/",
 348                                 state->i2c->dev.parent);
 349         printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
 350         if (ret) {
 351                 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not found?)\n",
 352                        __func__);
 353                 return ret;
 354         }
 355
 356         ret = ds3000_load_firmware(fe, fw);
 357         if (ret)
 358                 printk("%s: Writing firmware to device failed\n", __func__);
 359
 360         release_firmware(fw);
 361
 362         dprintk("%s: Firmware upload %s\n", __func__,
 363                         ret == 0 ? "complete" : "failed");
 364
 365         return ret;
 366 }
 367
 368 static int ds3000_load_firmware(struct dvb_frontend *fe,
 369                                         const struct firmware *fw)
 370 {
 371         struct ds3000_state *state = fe->demodulator_priv;
 372         int ret = 0;
 373
 374         dprintk("%s\n", __func__);
 375         dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
 376                         fw->size,
 377                         fw->data[0],
 378                         fw->data[1],
 379                         fw->data[fw->size - 2],
 380                         fw->data[fw->size - 1]);
 381
 382         /* Begin the firmware load process */
 383         ds3000_writereg(state, 0xb2, 0x01);
 384         /* write the entire firmware */
 385         ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size);
 386         ds3000_writereg(state, 0xb2, 0x00);
 387
 388         return ret;
 389 }
 390
 391 static int ds3000_set_voltage(struct dvb_frontend *fe,
 392                               enum fe_sec_voltage voltage)
 393 {
 394         struct ds3000_state *state = fe->demodulator_priv;
 395         u8 data;
 396
 397         dprintk("%s(%d)\n", __func__, voltage);
 398
 399         data = ds3000_readreg(state, 0xa2);
 400         data |= 0x03; /* bit0 V/H, bit1 off/on */
 401
 402         switch (voltage) {
 403         case SEC_VOLTAGE_18:
 404                 data &= ~0x03;
 405                 break;
 406         case SEC_VOLTAGE_13:
 407                 data &= ~0x03;
 408                 data |= 0x01;
 409                 break;
 410         case SEC_VOLTAGE_OFF:
 411                 break;
 412         }
 413
 414         ds3000_writereg(state, 0xa2, data);
 415
 416         return 0;
 417 }
 418
 419 static int ds3000_read_status(struct dvb_frontend *fe, enum fe_status *status)
 420 {
 421         struct ds3000_state *state = fe->demodulator_priv;
 422         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 423         int lock;
 424
 425         *status = 0;
 426
 427         switch (c->delivery_system) {
 428         case SYS_DVBS:
 429                 lock = ds3000_readreg(state, 0xd1);
 430                 if ((lock & 0x07) == 0x07)
 431                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 432                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 433                                 FE_HAS_LOCK;
 434
 435                 break;
 436         case SYS_DVBS2:
 437                 lock = ds3000_readreg(state, 0x0d);
 438                 if ((lock & 0x8f) == 0x8f)
 439                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 440                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 441                                 FE_HAS_LOCK;
 442
 443                 break;
 444         default:
 445                 return -EINVAL;
 446         }
 447
 448         if (state->config->set_lock_led)
 449                 state->config->set_lock_led(fe, *status == 0 ? 0 : 1);
 450
 451         dprintk("%s: status = 0x%02x\n", __func__, lock);
 452
 453         return 0;
 454 }
 455
 456 /* read DS3000 BER value */
 457 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
 458 {
 459         struct ds3000_state *state = fe->demodulator_priv;
 460         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 461         u8 data;
 462         u32 ber_reading, lpdc_frames;
 463
 464         dprintk("%s()\n", __func__);
 465
 466         switch (c->delivery_system) {
 467         case SYS_DVBS:
 468                 /* set the number of bytes checked during
 469                 BER estimation */
 470                 ds3000_writereg(state, 0xf9, 0x04);
 471                 /* read BER estimation status */
 472                 data = ds3000_readreg(state, 0xf8);
 473                 /* check if BER estimation is ready */
 474                 if ((data & 0x10) == 0) {
 475                         /* this is the number of error bits,
 476                         to calculate the bit error rate
 477                         divide to 8388608 */
 478                         *ber = (ds3000_readreg(state, 0xf7) << 8) |
 479                                 ds3000_readreg(state, 0xf6);
 480                         /* start counting error bits */
 481                         /* need to be set twice
 482                         otherwise it fails sometimes */
 483                         data |= 0x10;
 484                         ds3000_writereg(state, 0xf8, data);
 485                         ds3000_writereg(state, 0xf8, data);
 486                 } else
 487                         /* used to indicate that BER estimation
 488                         is not ready, i.e. BER is unknown */
 489                         *ber = 0xffffffff;
 490                 break;
 491         case SYS_DVBS2:
 492                 /* read the number of LPDC decoded frames */
 493                 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
 494                                 (ds3000_readreg(state, 0xd6) << 8) |
 495                                 ds3000_readreg(state, 0xd5);
 496                 /* read the number of packets with bad CRC */
 497                 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
 498                                 ds3000_readreg(state, 0xf7);
 499                 if (lpdc_frames > 750) {
 500                         /* clear LPDC frame counters */
 501                         ds3000_writereg(state, 0xd1, 0x01);
 502                         /* clear bad packets counter */
 503                         ds3000_writereg(state, 0xf9, 0x01);
 504                         /* enable bad packets counter */
 505                         ds3000_writereg(state, 0xf9, 0x00);
 506                         /* enable LPDC frame counters */
 507                         ds3000_writereg(state, 0xd1, 0x00);
 508                         *ber = ber_reading;
 509                 } else
 510                         /* used to indicate that BER estimation is not ready,
 511                         i.e. BER is unknown */
 512                         *ber = 0xffffffff;
 513                 break;
 514         default:
 515                 return -EINVAL;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static int ds3000_read_signal_strength(struct dvb_frontend *fe,
 522                                                 u16 *signal_strength)
 523 {
 524         if (fe->ops.tuner_ops.get_rf_strength)
 525                 fe->ops.tuner_ops.get_rf_strength(fe, signal_strength);
 526
 527         return 0;
 528 }
 529
 530 /* calculate DS3000 snr value in dB */
 531 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
 532 {
 533         struct ds3000_state *state = fe->demodulator_priv;
 534         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 535         u8 snr_reading, snr_value;
 536         u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
 537         static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
 538                 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
 539                 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
 540                 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
 541         };
 542         static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
 543                 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
 544                 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
 545                 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
 546                 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
 547                 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
 548                 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
 549                 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
 550                 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
 551                 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
 552                 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
 553                 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
 554                 0x49e9, 0x4a20, 0x4a57
 555         };
 556
 557         dprintk("%s()\n", __func__);
 558
 559         switch (c->delivery_system) {
 560         case SYS_DVBS:
 561                 snr_reading = ds3000_readreg(state, 0xff);
 562                 snr_reading /= 8;
 563                 if (snr_reading == 0)
 564                         *snr = 0x0000;
 565                 else {
 566                         if (snr_reading > 20)
 567                                 snr_reading = 20;
 568                         snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
 569                         /* cook the value to be suitable for szap-s2
 570                         human readable output */
 571                         *snr = snr_value * 8 * 655;
 572                 }
 573                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 574                                 snr_reading, *snr);
 575                 break;
 576         case SYS_DVBS2:
 577                 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
 578                                 (ds3000_readreg(state, 0x8d) << 4);
 579                 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
 580                 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
 581                 if (tmp == 0) {
 582                         *snr = 0x0000;
 583                         return 0;
 584                 }
 585                 if (dvbs2_noise_reading == 0) {
 586                         snr_value = 0x0013;
 587                         /* cook the value to be suitable for szap-s2
 588                         human readable output */
 589                         *snr = 0xffff;
 590                         return 0;
 591                 }
 592                 if (tmp > dvbs2_noise_reading) {
 593                         snr_reading = tmp / dvbs2_noise_reading;
 594                         if (snr_reading > 80)
 595                                 snr_reading = 80;
 596                         snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
 597                         /* cook the value to be suitable for szap-s2
 598                         human readable output */
 599                         *snr = snr_value * 5 * 655;
 600                 } else {
 601                         snr_reading = dvbs2_noise_reading / tmp;
 602                         if (snr_reading > 80)
 603                                 snr_reading = 80;
 604                         *snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000);
 605                 }
 606                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 607                                 snr_reading, *snr);
 608                 break;
 609         default:
 610                 return -EINVAL;
 611         }
 612
 613         return 0;
 614 }
 615
 616 /* read DS3000 uncorrected blocks */
 617 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 618 {
 619         struct ds3000_state *state = fe->demodulator_priv;
 620         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 621         u8 data;
 622         u16 _ucblocks;
 623
 624         dprintk("%s()\n", __func__);
 625
 626         switch (c->delivery_system) {
 627         case SYS_DVBS:
 628                 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
 629                                 ds3000_readreg(state, 0xf4);
 630                 data = ds3000_readreg(state, 0xf8);
 631                 /* clear packet counters */
 632                 data &= ~0x20;
 633                 ds3000_writereg(state, 0xf8, data);
 634                 /* enable packet counters */
 635                 data |= 0x20;
 636                 ds3000_writereg(state, 0xf8, data);
 637                 break;
 638         case SYS_DVBS2:
 639                 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
 640                                 ds3000_readreg(state, 0xe1);
 641                 if (_ucblocks > state->prevUCBS2)
 642                         *ucblocks = _ucblocks - state->prevUCBS2;
 643                 else
 644                         *ucblocks = state->prevUCBS2 - _ucblocks;
 645                 state->prevUCBS2 = _ucblocks;
 646                 break;
 647         default:
 648                 return -EINVAL;
 649         }
 650
 651         return 0;
 652 }
 653
 654 static int ds3000_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
 655 {
 656         struct ds3000_state *state = fe->demodulator_priv;
 657         u8 data;
 658
 659         dprintk("%s(%d)\n", __func__, tone);
 660         if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
 661                 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
 662                 return -EINVAL;
 663         }
 664
 665         data = ds3000_readreg(state, 0xa2);
 666         data &= ~0xc0;
 667         ds3000_writereg(state, 0xa2, data);
 668
 669         switch (tone) {
 670         case SEC_TONE_ON:
 671                 dprintk("%s: setting tone on\n", __func__);
 672                 data = ds3000_readreg(state, 0xa1);
 673                 data &= ~0x43;
 674                 data |= 0x04;
 675                 ds3000_writereg(state, 0xa1, data);
 676                 break;
 677         case SEC_TONE_OFF:
 678                 dprintk("%s: setting tone off\n", __func__);
 679                 data = ds3000_readreg(state, 0xa2);
 680                 data |= 0x80;
 681                 ds3000_writereg(state, 0xa2, data);
 682                 break;
 683         }
 684
 685         return 0;
 686 }
 687
 688 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
 689                                 struct dvb_diseqc_master_cmd *d)
 690 {
 691         struct ds3000_state *state = fe->demodulator_priv;
 692         int i;
 693         u8 data;
 694
 695         /* Dump DiSEqC message */
 696         dprintk("%s(", __func__);
 697         for (i = 0 ; i < d->msg_len;) {
 698                 dprintk("0x%02x", d->msg[i]);
 699                 if (++i < d->msg_len)
 700                         dprintk(", ");
 701         }
 702
 703         /* enable DiSEqC message send pin */
 704         data = ds3000_readreg(state, 0xa2);
 705         data &= ~0xc0;
 706         ds3000_writereg(state, 0xa2, data);
 707
 708         /* DiSEqC message */
 709         for (i = 0; i < d->msg_len; i++)
 710                 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
 711
 712         data = ds3000_readreg(state, 0xa1);
 713         /* clear DiSEqC message length and status,
 714         enable DiSEqC message send */
 715         data &= ~0xf8;
 716         /* set DiSEqC mode, modulation active during 33 pulses,
 717         set DiSEqC message length */
 718         data |= ((d->msg_len - 1) << 3) | 0x07;
 719         ds3000_writereg(state, 0xa1, data);
 720
 721         /* wait up to 150ms for DiSEqC transmission to complete */
 722         for (i = 0; i < 15; i++) {
 723                 data = ds3000_readreg(state, 0xa1);
 724                 if ((data & 0x40) == 0)
 725                         break;
 726                 msleep(10);
 727         }
 728
 729         /* DiSEqC timeout after 150ms */
 730         if (i == 15) {
 731                 data = ds3000_readreg(state, 0xa1);
 732                 data &= ~0x80;
 733                 data |= 0x40;
 734                 ds3000_writereg(state, 0xa1, data);
 735
 736                 data = ds3000_readreg(state, 0xa2);
 737                 data &= ~0xc0;
 738                 data |= 0x80;
 739                 ds3000_writereg(state, 0xa2, data);
 740
 741                 return -ETIMEDOUT;
 742         }
 743
 744         data = ds3000_readreg(state, 0xa2);
 745         data &= ~0xc0;
 746         data |= 0x80;
 747         ds3000_writereg(state, 0xa2, data);
 748
 749         return 0;
 750 }
 751
 752 /* Send DiSEqC burst */
 753 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
 754                                     enum fe_sec_mini_cmd burst)
 755 {
 756         struct ds3000_state *state = fe->demodulator_priv;
 757         int i;
 758         u8 data;
 759
 760         dprintk("%s()\n", __func__);
 761
 762         data = ds3000_readreg(state, 0xa2);
 763         data &= ~0xc0;
 764         ds3000_writereg(state, 0xa2, data);
 765
 766         /* DiSEqC burst */
 767         if (burst == SEC_MINI_A)
 768                 /* Unmodulated tone burst */
 769                 ds3000_writereg(state, 0xa1, 0x02);
 770         else if (burst == SEC_MINI_B)
 771                 /* Modulated tone burst */
 772                 ds3000_writereg(state, 0xa1, 0x01);
 773         else
 774                 return -EINVAL;
 775
 776         msleep(13);
 777         for (i = 0; i < 5; i++) {
 778                 data = ds3000_readreg(state, 0xa1);
 779                 if ((data & 0x40) == 0)
 780                         break;
 781                 msleep(1);
 782         }
 783
 784         if (i == 5) {
 785                 data = ds3000_readreg(state, 0xa1);
 786                 data &= ~0x80;
 787                 data |= 0x40;
 788                 ds3000_writereg(state, 0xa1, data);
 789
 790                 data = ds3000_readreg(state, 0xa2);
 791                 data &= ~0xc0;
 792                 data |= 0x80;
 793                 ds3000_writereg(state, 0xa2, data);
 794
 795                 return -ETIMEDOUT;
 796         }
 797
 798         data = ds3000_readreg(state, 0xa2);
 799         data &= ~0xc0;
 800         data |= 0x80;
 801         ds3000_writereg(state, 0xa2, data);
 802
 803         return 0;
 804 }
 805
 806 static void ds3000_release(struct dvb_frontend *fe)
 807 {
 808         struct ds3000_state *state = fe->demodulator_priv;
 809
 810         if (state->config->set_lock_led)
 811                 state->config->set_lock_led(fe, 0);
 812
 813         dprintk("%s\n", __func__);
 814         kfree(state);
 815 }
 816
 817 static const struct dvb_frontend_ops ds3000_ops;
 818
 819 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
 820                                     struct i2c_adapter *i2c)
 821 {
 822         struct ds3000_state *state;
 823         int ret;
 824
 825         dprintk("%s\n", __func__);
 826
 827         /* allocate memory for the internal state */
 828         state = kzalloc(sizeof(*state), GFP_KERNEL);
 829         if (!state)
 830                 return NULL;
 831
 832         state->config = config;
 833         state->i2c = i2c;
 834         state->prevUCBS2 = 0;
 835
 836         /* check if the demod is present */
 837         ret = ds3000_readreg(state, 0x00) & 0xfe;
 838         if (ret != 0xe0) {
 839                 kfree(state);
 840                 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
 841                 return NULL;
 842         }
 843
 844         printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
 845                         ds3000_readreg(state, 0x02),
 846                         ds3000_readreg(state, 0x01));
 847
 848         memcpy(&state->frontend.ops, &ds3000_ops,
 849                         sizeof(struct dvb_frontend_ops));
 850         state->frontend.demodulator_priv = state;
 851
 852         /*
 853          * Some devices like T480 starts with voltage on. Be sure
 854          * to turn voltage off during init, as this can otherwise
 855          * interfere with Unicable SCR systems.
 856          */
 857         ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF);
 858         return &state->frontend;
 859 }
 860 EXPORT_SYMBOL(ds3000_attach);
 861
 862 static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
 863                                         s32 carrier_offset_khz)
 864 {
 865         struct ds3000_state *state = fe->demodulator_priv;
 866         s32 tmp;
 867
 868         tmp = carrier_offset_khz;
 869         tmp *= 65536;
 870         tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
 871
 872         if (tmp < 0)
 873                 tmp += 65536;
 874
 875         ds3000_writereg(state, 0x5f, tmp >> 8);
 876         ds3000_writereg(state, 0x5e, tmp & 0xff);
 877
 878         return 0;
 879 }
 880
 881 static int ds3000_set_frontend(struct dvb_frontend *fe)
 882 {
 883         struct ds3000_state *state = fe->demodulator_priv;
 884         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 885
 886         int i;
 887         enum fe_status status;
 888         s32 offset_khz;
 889         u32 frequency;
 890         u16 value;
 891
 892         dprintk("%s() ", __func__);
 893
 894         if (state->config->set_ts_params)
 895                 state->config->set_ts_params(fe, 0);
 896         /* Tune */
 897         if (fe->ops.tuner_ops.set_params)
 898                 fe->ops.tuner_ops.set_params(fe);
 899
 900         /* ds3000 global reset */
 901         ds3000_writereg(state, 0x07, 0x80);
 902         ds3000_writereg(state, 0x07, 0x00);
 903         /* ds3000 built-in uC reset */
 904         ds3000_writereg(state, 0xb2, 0x01);
 905         /* ds3000 software reset */
 906         ds3000_writereg(state, 0x00, 0x01);
 907
 908         switch (c->delivery_system) {
 909         case SYS_DVBS:
 910                 /* initialise the demod in DVB-S mode */
 911                 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
 912                         ds3000_writereg(state,
 913                                 ds3000_dvbs_init_tab[i],
 914                                 ds3000_dvbs_init_tab[i + 1]);
 915                 value = ds3000_readreg(state, 0xfe);
 916                 value &= 0xc0;
 917                 value |= 0x1b;
 918                 ds3000_writereg(state, 0xfe, value);
 919                 break;
 920         case SYS_DVBS2:
 921                 /* initialise the demod in DVB-S2 mode */
 922                 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
 923                         ds3000_writereg(state,
 924                                 ds3000_dvbs2_init_tab[i],
 925                                 ds3000_dvbs2_init_tab[i + 1]);
 926                 if (c->symbol_rate >= 30000000)
 927                         ds3000_writereg(state, 0xfe, 0x54);
 928                 else
 929                         ds3000_writereg(state, 0xfe, 0x98);
 930                 break;
 931         default:
 932                 return -EINVAL;
 933         }
 934
 935         /* enable 27MHz clock output */
 936         ds3000_writereg(state, 0x29, 0x80);
 937         /* enable ac coupling */
 938         ds3000_writereg(state, 0x25, 0x8a);
 939
 940         if ((c->symbol_rate < ds3000_ops.info.symbol_rate_min) ||
 941                         (c->symbol_rate > ds3000_ops.info.symbol_rate_max)) {
 942                 dprintk("%s() symbol_rate %u out of range (%u ... %u)\n",
 943                                 __func__, c->symbol_rate,
 944                                 ds3000_ops.info.symbol_rate_min,
 945                                 ds3000_ops.info.symbol_rate_max);
 946                 return -EINVAL;
 947         }
 948
 949         /* enhance symbol rate performance */
 950         if ((c->symbol_rate / 1000) <= 5000) {
 951                 value = 29777 / (c->symbol_rate / 1000) + 1;
 952                 if (value % 2 != 0)
 953                         value++;
 954                 ds3000_writereg(state, 0xc3, 0x0d);
 955                 ds3000_writereg(state, 0xc8, value);
 956                 ds3000_writereg(state, 0xc4, 0x10);
 957                 ds3000_writereg(state, 0xc7, 0x0e);
 958         } else if ((c->symbol_rate / 1000) <= 10000) {
 959                 value = 92166 / (c->symbol_rate / 1000) + 1;
 960                 if (value % 2 != 0)
 961                         value++;
 962                 ds3000_writereg(state, 0xc3, 0x07);
 963                 ds3000_writereg(state, 0xc8, value);
 964                 ds3000_writereg(state, 0xc4, 0x09);
 965                 ds3000_writereg(state, 0xc7, 0x12);
 966         } else if ((c->symbol_rate / 1000) <= 20000) {
 967                 value = 64516 / (c->symbol_rate / 1000) + 1;
 968                 ds3000_writereg(state, 0xc3, value);
 969                 ds3000_writereg(state, 0xc8, 0x0e);
 970                 ds3000_writereg(state, 0xc4, 0x07);
 971                 ds3000_writereg(state, 0xc7, 0x18);
 972         } else {
 973                 value = 129032 / (c->symbol_rate / 1000) + 1;
 974                 ds3000_writereg(state, 0xc3, value);
 975                 ds3000_writereg(state, 0xc8, 0x0a);
 976                 ds3000_writereg(state, 0xc4, 0x05);
 977                 ds3000_writereg(state, 0xc7, 0x24);
 978         }
 979
 980         /* normalized symbol rate rounded to the closest integer */
 981         value = (((c->symbol_rate / 1000) << 16) +
 982                         (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
 983         ds3000_writereg(state, 0x61, value & 0x00ff);
 984         ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
 985
 986         /* co-channel interference cancellation disabled */
 987         ds3000_writereg(state, 0x56, 0x00);
 988
 989         /* equalizer disabled */
 990         ds3000_writereg(state, 0x76, 0x00);
 991
 992         /*ds3000_writereg(state, 0x08, 0x03);
 993         ds3000_writereg(state, 0xfd, 0x22);
 994         ds3000_writereg(state, 0x08, 0x07);
 995         ds3000_writereg(state, 0xfd, 0x42);
 996         ds3000_writereg(state, 0x08, 0x07);*/
 997
 998         if (state->config->ci_mode) {
 999                 switch (c->delivery_system) {
1000                 case SYS_DVBS:
1001                 default:
1002                         ds3000_writereg(state, 0xfd, 0x80);
1003                 break;
1004                 case SYS_DVBS2:
1005                         ds3000_writereg(state, 0xfd, 0x01);
1006                         break;
1007                 }
1008         }
1009
1010         /* ds3000 out of software reset */
1011         ds3000_writereg(state, 0x00, 0x00);
1012         /* start ds3000 built-in uC */
1013         ds3000_writereg(state, 0xb2, 0x00);
1014
1015         if (fe->ops.tuner_ops.get_frequency) {
1016                 fe->ops.tuner_ops.get_frequency(fe, &frequency);
1017                 offset_khz = frequency - c->frequency;
1018                 ds3000_set_carrier_offset(fe, offset_khz);
1019         }
1020
1021         for (i = 0; i < 30 ; i++) {
1022                 ds3000_read_status(fe, &status);
1023                 if (status & FE_HAS_LOCK)
1024                         break;
1025
1026                 msleep(10);
1027         }
1028
1029         return 0;
1030 }
1031
1032 static int ds3000_tune(struct dvb_frontend *fe,
1033                         bool re_tune,
1034                         unsigned int mode_flags,
1035                         unsigned int *delay,
1036                         enum fe_status *status)
1037 {
1038         if (re_tune) {
1039                 int ret = ds3000_set_frontend(fe);
1040                 if (ret)
1041                         return ret;
1042         }
1043
1044         *delay = HZ / 5;
1045
1046         return ds3000_read_status(fe, status);
1047 }
1048
1049 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1050 {
1051         struct ds3000_state *state = fe->demodulator_priv;
1052
1053         if (state->config->set_lock_led)
1054                 state->config->set_lock_led(fe, 0);
1055
1056         dprintk("%s()\n", __func__);
1057         return DVBFE_ALGO_HW;
1058 }
1059
1060 /*
1061  * Initialise or wake up device
1062  *
1063  * Power config will reset and load initial firmware if required
1064  */
1065 static int ds3000_initfe(struct dvb_frontend *fe)
1066 {
1067         struct ds3000_state *state = fe->demodulator_priv;
1068         int ret;
1069
1070         dprintk("%s()\n", __func__);
1071         /* hard reset */
1072         ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1073         msleep(1);
1074
1075         /* Load the firmware if required */
1076         ret = ds3000_firmware_ondemand(fe);
1077         if (ret != 0) {
1078                 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1079                 return ret;
1080         }
1081
1082         return 0;
1083 }
1084
1085 static const struct dvb_frontend_ops ds3000_ops = {
1086         .delsys = { SYS_DVBS, SYS_DVBS2 },
1087         .info = {
1088                 .name = "Montage Technology DS3000",
1089                 .frequency_min_hz =  950 * MHz,
1090                 .frequency_max_hz = 2150 * MHz,
1091                 .frequency_stepsize_hz = 1011 * kHz,
1092                 .frequency_tolerance_hz = 5 * MHz,
1093                 .symbol_rate_min = 1000000,
1094                 .symbol_rate_max = 45000000,
1095                 .caps = FE_CAN_INVERSION_AUTO |
1096                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1097                         FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1098                         FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1099                         FE_CAN_2G_MODULATION |
1100                         FE_CAN_QPSK | FE_CAN_RECOVER
1101         },
1102
1103         .release = ds3000_release,
1104
1105         .init = ds3000_initfe,
1106         .i2c_gate_ctrl = ds3000_i2c_gate_ctrl,
1107         .read_status = ds3000_read_status,
1108         .read_ber = ds3000_read_ber,
1109         .read_signal_strength = ds3000_read_signal_strength,
1110         .read_snr = ds3000_read_snr,
1111         .read_ucblocks = ds3000_read_ucblocks,
1112         .set_voltage = ds3000_set_voltage,
1113         .set_tone = ds3000_set_tone,
1114         .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1115         .diseqc_send_burst = ds3000_diseqc_send_burst,
1116         .get_frontend_algo = ds3000_get_algo,
1117
1118         .set_frontend = ds3000_set_frontend,
1119         .tune = ds3000_tune,
1120 };
1121
1122 module_param(debug, int, 0644);
1123 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1124
1125 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology DS3000 hardware");
1126 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
1127 MODULE_LICENSE("GPL");
1128 /*(DEBLOBBED)*/