drivers/media/dvb-frontends/ds3000.c

   1 /*
   2     Montage Technology DS3000 - DVBS/S2 Demodulator driver
   3     Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
   4
   5     Copyright (C) 2009-2012 TurboSight.com
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/slab.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/firmware.h>
  28
  29 #include "dvb_frontend.h"
  30 #include "ts2020.h"
  31 #include "ds3000.h"
  32
  33 static int debug;
  34
  35 #define dprintk(args...) \
  36         do { \
  37                 if (debug) \
  38                         printk(args); \
  39         } while (0)
  40
  41 /*(DEBLOBBED)*/
  42
  43 #define DS3000_SAMPLE_RATE 96000 /* in kHz */
  44
  45 /* Register values to initialise the demod in DVB-S mode */
  46 static u8 ds3000_dvbs_init_tab[] = {
  47         0x23, 0x05,
  48         0x08, 0x03,
  49         0x0c, 0x00,
  50         0x21, 0x54,
  51         0x25, 0x82,
  52         0x27, 0x31,
  53         0x30, 0x08,
  54         0x31, 0x40,
  55         0x32, 0x32,
  56         0x33, 0x35,
  57         0x35, 0xff,
  58         0x3a, 0x00,
  59         0x37, 0x10,
  60         0x38, 0x10,
  61         0x39, 0x02,
  62         0x42, 0x60,
  63         0x4a, 0x40,
  64         0x4b, 0x04,
  65         0x4d, 0x91,
  66         0x5d, 0xc8,
  67         0x50, 0x77,
  68         0x51, 0x77,
  69         0x52, 0x36,
  70         0x53, 0x36,
  71         0x56, 0x01,
  72         0x63, 0x43,
  73         0x64, 0x30,
  74         0x65, 0x40,
  75         0x68, 0x26,
  76         0x69, 0x4c,
  77         0x70, 0x20,
  78         0x71, 0x70,
  79         0x72, 0x04,
  80         0x73, 0x00,
  81         0x70, 0x40,
  82         0x71, 0x70,
  83         0x72, 0x04,
  84         0x73, 0x00,
  85         0x70, 0x60,
  86         0x71, 0x70,
  87         0x72, 0x04,
  88         0x73, 0x00,
  89         0x70, 0x80,
  90         0x71, 0x70,
  91         0x72, 0x04,
  92         0x73, 0x00,
  93         0x70, 0xa0,
  94         0x71, 0x70,
  95         0x72, 0x04,
  96         0x73, 0x00,
  97         0x70, 0x1f,
  98         0x76, 0x00,
  99         0x77, 0xd1,
 100         0x78, 0x0c,
 101         0x79, 0x80,
 102         0x7f, 0x04,
 103         0x7c, 0x00,
 104         0x80, 0x86,
 105         0x81, 0xa6,
 106         0x85, 0x04,
 107         0xcd, 0xf4,
 108         0x90, 0x33,
 109         0xa0, 0x44,
 110         0xc0, 0x18,
 111         0xc3, 0x10,
 112         0xc4, 0x08,
 113         0xc5, 0x80,
 114         0xc6, 0x80,
 115         0xc7, 0x0a,
 116         0xc8, 0x1a,
 117         0xc9, 0x80,
 118         0xfe, 0x92,
 119         0xe0, 0xf8,
 120         0xe6, 0x8b,
 121         0xd0, 0x40,
 122         0xf8, 0x20,
 123         0xfa, 0x0f,
 124         0xfd, 0x20,
 125         0xad, 0x20,
 126         0xae, 0x07,
 127         0xb8, 0x00,
 128 };
 129
 130 /* Register values to initialise the demod in DVB-S2 mode */
 131 static u8 ds3000_dvbs2_init_tab[] = {
 132         0x23, 0x0f,
 133         0x08, 0x07,
 134         0x0c, 0x00,
 135         0x21, 0x54,
 136         0x25, 0x82,
 137         0x27, 0x31,
 138         0x30, 0x08,
 139         0x31, 0x32,
 140         0x32, 0x32,
 141         0x33, 0x35,
 142         0x35, 0xff,
 143         0x3a, 0x00,
 144         0x37, 0x10,
 145         0x38, 0x10,
 146         0x39, 0x02,
 147         0x42, 0x60,
 148         0x4a, 0x80,
 149         0x4b, 0x04,
 150         0x4d, 0x81,
 151         0x5d, 0x88,
 152         0x50, 0x36,
 153         0x51, 0x36,
 154         0x52, 0x36,
 155         0x53, 0x36,
 156         0x63, 0x60,
 157         0x64, 0x10,
 158         0x65, 0x10,
 159         0x68, 0x04,
 160         0x69, 0x29,
 161         0x70, 0x20,
 162         0x71, 0x70,
 163         0x72, 0x04,
 164         0x73, 0x00,
 165         0x70, 0x40,
 166         0x71, 0x70,
 167         0x72, 0x04,
 168         0x73, 0x00,
 169         0x70, 0x60,
 170         0x71, 0x70,
 171         0x72, 0x04,
 172         0x73, 0x00,
 173         0x70, 0x80,
 174         0x71, 0x70,
 175         0x72, 0x04,
 176         0x73, 0x00,
 177         0x70, 0xa0,
 178         0x71, 0x70,
 179         0x72, 0x04,
 180         0x73, 0x00,
 181         0x70, 0x1f,
 182         0xa0, 0x44,
 183         0xc0, 0x08,
 184         0xc1, 0x10,
 185         0xc2, 0x08,
 186         0xc3, 0x10,
 187         0xc4, 0x08,
 188         0xc5, 0xf0,
 189         0xc6, 0xf0,
 190         0xc7, 0x0a,
 191         0xc8, 0x1a,
 192         0xc9, 0x80,
 193         0xca, 0x23,
 194         0xcb, 0x24,
 195         0xce, 0x74,
 196         0x90, 0x03,
 197         0x76, 0x80,
 198         0x77, 0x42,
 199         0x78, 0x0a,
 200         0x79, 0x80,
 201         0xad, 0x40,
 202         0xae, 0x07,
 203         0x7f, 0xd4,
 204         0x7c, 0x00,
 205         0x80, 0xa8,
 206         0x81, 0xda,
 207         0x7c, 0x01,
 208         0x80, 0xda,
 209         0x81, 0xec,
 210         0x7c, 0x02,
 211         0x80, 0xca,
 212         0x81, 0xeb,
 213         0x7c, 0x03,
 214         0x80, 0xba,
 215         0x81, 0xdb,
 216         0x85, 0x08,
 217         0x86, 0x00,
 218         0x87, 0x02,
 219         0x89, 0x80,
 220         0x8b, 0x44,
 221         0x8c, 0xaa,
 222         0x8a, 0x10,
 223         0xba, 0x00,
 224         0xf5, 0x04,
 225         0xfe, 0x44,
 226         0xd2, 0x32,
 227         0xb8, 0x00,
 228 };
 229
 230 struct ds3000_state {
 231         struct i2c_adapter *i2c;
 232         const struct ds3000_config *config;
 233         struct dvb_frontend frontend;
 234         /* previous uncorrected block counter for DVB-S2 */
 235         u16 prevUCBS2;
 236 };
 237
 238 static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
 239 {
 240         u8 buf[] = { reg, data };
 241         struct i2c_msg msg = { .addr = state->config->demod_address,
 242                 .flags = 0, .buf = buf, .len = 2 };
 243         int err;
 244
 245         dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
 246
 247         err = i2c_transfer(state->i2c, &msg, 1);
 248         if (err != 1) {
 249                 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
 250                          " value == 0x%02x)\n", __func__, err, reg, data);
 251                 return -EREMOTEIO;
 252         }
 253
 254         return 0;
 255 }
 256
 257 static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 258 {
 259         struct ds3000_state *state = fe->demodulator_priv;
 260
 261         if (enable)
 262                 ds3000_writereg(state, 0x03, 0x12);
 263         else
 264                 ds3000_writereg(state, 0x03, 0x02);
 265
 266         return 0;
 267 }
 268
 269 /* I2C write for 8k firmware load */
 270 static int ds3000_writeFW(struct ds3000_state *state, int reg,
 271                                 const u8 *data, u16 len)
 272 {
 273         int i, ret = 0;
 274         struct i2c_msg msg;
 275         u8 *buf;
 276
 277         buf = kmalloc(33, GFP_KERNEL);
 278         if (buf == NULL) {
 279                 printk(KERN_ERR "Unable to kmalloc\n");
 280                 return -ENOMEM;
 281         }
 282
 283         *(buf) = reg;
 284
 285         msg.addr = state->config->demod_address;
 286         msg.flags = 0;
 287         msg.buf = buf;
 288         msg.len = 33;
 289
 290         for (i = 0; i < len; i += 32) {
 291                 memcpy(buf + 1, data + i, 32);
 292
 293                 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
 294
 295                 ret = i2c_transfer(state->i2c, &msg, 1);
 296                 if (ret != 1) {
 297                         printk(KERN_ERR "%s: write error(err == %i, "
 298                                 "reg == 0x%02x\n", __func__, ret, reg);
 299                         ret = -EREMOTEIO;
 300                         goto error;
 301                 }
 302         }
 303         ret = 0;
 304
 305 error:
 306         kfree(buf);
 307
 308         return ret;
 309 }
 310
 311 static int ds3000_readreg(struct ds3000_state *state, u8 reg)
 312 {
 313         int ret;
 314         u8 b0[] = { reg };
 315         u8 b1[] = { 0 };
 316         struct i2c_msg msg[] = {
 317                 {
 318                         .addr = state->config->demod_address,
 319                         .flags = 0,
 320                         .buf = b0,
 321                         .len = 1
 322                 }, {
 323                         .addr = state->config->demod_address,
 324                         .flags = I2C_M_RD,
 325                         .buf = b1,
 326                         .len = 1
 327                 }
 328         };
 329
 330         ret = i2c_transfer(state->i2c, msg, 2);
 331
 332         if (ret != 2) {
 333                 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
 334                 return ret;
 335         }
 336
 337         dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
 338
 339         return b1[0];
 340 }
 341
 342 static int ds3000_load_firmware(struct dvb_frontend *fe,
 343                                         const struct firmware *fw);
 344
 345 static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
 346 {
 347         struct ds3000_state *state = fe->demodulator_priv;
 348         const struct firmware *fw;
 349         int ret = 0;
 350
 351         dprintk("%s()\n", __func__);
 352
 353         ret = ds3000_readreg(state, 0xb2);
 354         if (ret < 0)
 355                 return ret;
 356
 357         /* Load firmware */
 358         /* request the firmware, this will block until someone uploads it */
 359         printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
 360                                 "/*(DEBLOBBED)*/");
 361         ret = reject_firmware(&fw, "/*(DEBLOBBED)*/",
 362                                 state->i2c->dev.parent);
 363         printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
 364         if (ret) {
 365                 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
 366                                 "found?)\n", __func__);
 367                 return ret;
 368         }
 369
 370         ret = ds3000_load_firmware(fe, fw);
 371         if (ret)
 372                 printk("%s: Writing firmware to device failed\n", __func__);
 373
 374         release_firmware(fw);
 375
 376         dprintk("%s: Firmware upload %s\n", __func__,
 377                         ret == 0 ? "complete" : "failed");
 378
 379         return ret;
 380 }
 381
 382 static int ds3000_load_firmware(struct dvb_frontend *fe,
 383                                         const struct firmware *fw)
 384 {
 385         struct ds3000_state *state = fe->demodulator_priv;
 386         int ret = 0;
 387
 388         dprintk("%s\n", __func__);
 389         dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
 390                         fw->size,
 391                         fw->data[0],
 392                         fw->data[1],
 393                         fw->data[fw->size - 2],
 394                         fw->data[fw->size - 1]);
 395
 396         /* Begin the firmware load process */
 397         ds3000_writereg(state, 0xb2, 0x01);
 398         /* write the entire firmware */
 399         ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size);
 400         ds3000_writereg(state, 0xb2, 0x00);
 401
 402         return ret;
 403 }
 404
 405 static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
 406 {
 407         struct ds3000_state *state = fe->demodulator_priv;
 408         u8 data;
 409
 410         dprintk("%s(%d)\n", __func__, voltage);
 411
 412         data = ds3000_readreg(state, 0xa2);
 413         data |= 0x03; /* bit0 V/H, bit1 off/on */
 414
 415         switch (voltage) {
 416         case SEC_VOLTAGE_18:
 417                 data &= ~0x03;
 418                 break;
 419         case SEC_VOLTAGE_13:
 420                 data &= ~0x03;
 421                 data |= 0x01;
 422                 break;
 423         case SEC_VOLTAGE_OFF:
 424                 break;
 425         }
 426
 427         ds3000_writereg(state, 0xa2, data);
 428
 429         return 0;
 430 }
 431
 432 static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
 433 {
 434         struct ds3000_state *state = fe->demodulator_priv;
 435         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 436         int lock;
 437
 438         *status = 0;
 439
 440         switch (c->delivery_system) {
 441         case SYS_DVBS:
 442                 lock = ds3000_readreg(state, 0xd1);
 443                 if ((lock & 0x07) == 0x07)
 444                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 445                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 446                                 FE_HAS_LOCK;
 447
 448                 break;
 449         case SYS_DVBS2:
 450                 lock = ds3000_readreg(state, 0x0d);
 451                 if ((lock & 0x8f) == 0x8f)
 452                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 453                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 454                                 FE_HAS_LOCK;
 455
 456                 break;
 457         default:
 458                 return 1;
 459         }
 460
 461         if (state->config->set_lock_led)
 462                 state->config->set_lock_led(fe, *status == 0 ? 0 : 1);
 463
 464         dprintk("%s: status = 0x%02x\n", __func__, lock);
 465
 466         return 0;
 467 }
 468
 469 /* read DS3000 BER value */
 470 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
 471 {
 472         struct ds3000_state *state = fe->demodulator_priv;
 473         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 474         u8 data;
 475         u32 ber_reading, lpdc_frames;
 476
 477         dprintk("%s()\n", __func__);
 478
 479         switch (c->delivery_system) {
 480         case SYS_DVBS:
 481                 /* set the number of bytes checked during
 482                 BER estimation */
 483                 ds3000_writereg(state, 0xf9, 0x04);
 484                 /* read BER estimation status */
 485                 data = ds3000_readreg(state, 0xf8);
 486                 /* check if BER estimation is ready */
 487                 if ((data & 0x10) == 0) {
 488                         /* this is the number of error bits,
 489                         to calculate the bit error rate
 490                         divide to 8388608 */
 491                         *ber = (ds3000_readreg(state, 0xf7) << 8) |
 492                                 ds3000_readreg(state, 0xf6);
 493                         /* start counting error bits */
 494                         /* need to be set twice
 495                         otherwise it fails sometimes */
 496                         data |= 0x10;
 497                         ds3000_writereg(state, 0xf8, data);
 498                         ds3000_writereg(state, 0xf8, data);
 499                 } else
 500                         /* used to indicate that BER estimation
 501                         is not ready, i.e. BER is unknown */
 502                         *ber = 0xffffffff;
 503                 break;
 504         case SYS_DVBS2:
 505                 /* read the number of LPDC decoded frames */
 506                 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
 507                                 (ds3000_readreg(state, 0xd6) << 8) |
 508                                 ds3000_readreg(state, 0xd5);
 509                 /* read the number of packets with bad CRC */
 510                 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
 511                                 ds3000_readreg(state, 0xf7);
 512                 if (lpdc_frames > 750) {
 513                         /* clear LPDC frame counters */
 514                         ds3000_writereg(state, 0xd1, 0x01);
 515                         /* clear bad packets counter */
 516                         ds3000_writereg(state, 0xf9, 0x01);
 517                         /* enable bad packets counter */
 518                         ds3000_writereg(state, 0xf9, 0x00);
 519                         /* enable LPDC frame counters */
 520                         ds3000_writereg(state, 0xd1, 0x00);
 521                         *ber = ber_reading;
 522                 } else
 523                         /* used to indicate that BER estimation is not ready,
 524                         i.e. BER is unknown */
 525                         *ber = 0xffffffff;
 526                 break;
 527         default:
 528                 return 1;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int ds3000_read_signal_strength(struct dvb_frontend *fe,
 535                                                 u16 *signal_strength)
 536 {
 537         if (fe->ops.tuner_ops.get_rf_strength)
 538                 fe->ops.tuner_ops.get_rf_strength(fe, signal_strength);
 539
 540         return 0;
 541 }
 542
 543 /* calculate DS3000 snr value in dB */
 544 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
 545 {
 546         struct ds3000_state *state = fe->demodulator_priv;
 547         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 548         u8 snr_reading, snr_value;
 549         u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
 550         static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
 551                 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
 552                 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
 553                 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
 554         };
 555         static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
 556                 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
 557                 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
 558                 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
 559                 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
 560                 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
 561                 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
 562                 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
 563                 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
 564                 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
 565                 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
 566                 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
 567                 0x49e9, 0x4a20, 0x4a57
 568         };
 569
 570         dprintk("%s()\n", __func__);
 571
 572         switch (c->delivery_system) {
 573         case SYS_DVBS:
 574                 snr_reading = ds3000_readreg(state, 0xff);
 575                 snr_reading /= 8;
 576                 if (snr_reading == 0)
 577                         *snr = 0x0000;
 578                 else {
 579                         if (snr_reading > 20)
 580                                 snr_reading = 20;
 581                         snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
 582                         /* cook the value to be suitable for szap-s2
 583                         human readable output */
 584                         *snr = snr_value * 8 * 655;
 585                 }
 586                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 587                                 snr_reading, *snr);
 588                 break;
 589         case SYS_DVBS2:
 590                 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
 591                                 (ds3000_readreg(state, 0x8d) << 4);
 592                 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
 593                 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
 594                 if (tmp == 0) {
 595                         *snr = 0x0000;
 596                         return 0;
 597                 }
 598                 if (dvbs2_noise_reading == 0) {
 599                         snr_value = 0x0013;
 600                         /* cook the value to be suitable for szap-s2
 601                         human readable output */
 602                         *snr = 0xffff;
 603                         return 0;
 604                 }
 605                 if (tmp > dvbs2_noise_reading) {
 606                         snr_reading = tmp / dvbs2_noise_reading;
 607                         if (snr_reading > 80)
 608                                 snr_reading = 80;
 609                         snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
 610                         /* cook the value to be suitable for szap-s2
 611                         human readable output */
 612                         *snr = snr_value * 5 * 655;
 613                 } else {
 614                         snr_reading = dvbs2_noise_reading / tmp;
 615                         if (snr_reading > 80)
 616                                 snr_reading = 80;
 617                         *snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000);
 618                 }
 619                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 620                                 snr_reading, *snr);
 621                 break;
 622         default:
 623                 return 1;
 624         }
 625
 626         return 0;
 627 }
 628
 629 /* read DS3000 uncorrected blocks */
 630 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 631 {
 632         struct ds3000_state *state = fe->demodulator_priv;
 633         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 634         u8 data;
 635         u16 _ucblocks;
 636
 637         dprintk("%s()\n", __func__);
 638
 639         switch (c->delivery_system) {
 640         case SYS_DVBS:
 641                 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
 642                                 ds3000_readreg(state, 0xf4);
 643                 data = ds3000_readreg(state, 0xf8);
 644                 /* clear packet counters */
 645                 data &= ~0x20;
 646                 ds3000_writereg(state, 0xf8, data);
 647                 /* enable packet counters */
 648                 data |= 0x20;
 649                 ds3000_writereg(state, 0xf8, data);
 650                 break;
 651         case SYS_DVBS2:
 652                 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
 653                                 ds3000_readreg(state, 0xe1);
 654                 if (_ucblocks > state->prevUCBS2)
 655                         *ucblocks = _ucblocks - state->prevUCBS2;
 656                 else
 657                         *ucblocks = state->prevUCBS2 - _ucblocks;
 658                 state->prevUCBS2 = _ucblocks;
 659                 break;
 660         default:
 661                 return 1;
 662         }
 663
 664         return 0;
 665 }
 666
 667 static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
 668 {
 669         struct ds3000_state *state = fe->demodulator_priv;
 670         u8 data;
 671
 672         dprintk("%s(%d)\n", __func__, tone);
 673         if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
 674                 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
 675                 return -EINVAL;
 676         }
 677
 678         data = ds3000_readreg(state, 0xa2);
 679         data &= ~0xc0;
 680         ds3000_writereg(state, 0xa2, data);
 681
 682         switch (tone) {
 683         case SEC_TONE_ON:
 684                 dprintk("%s: setting tone on\n", __func__);
 685                 data = ds3000_readreg(state, 0xa1);
 686                 data &= ~0x43;
 687                 data |= 0x04;
 688                 ds3000_writereg(state, 0xa1, data);
 689                 break;
 690         case SEC_TONE_OFF:
 691                 dprintk("%s: setting tone off\n", __func__);
 692                 data = ds3000_readreg(state, 0xa2);
 693                 data |= 0x80;
 694                 ds3000_writereg(state, 0xa2, data);
 695                 break;
 696         }
 697
 698         return 0;
 699 }
 700
 701 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
 702                                 struct dvb_diseqc_master_cmd *d)
 703 {
 704         struct ds3000_state *state = fe->demodulator_priv;
 705         int i;
 706         u8 data;
 707
 708         /* Dump DiSEqC message */
 709         dprintk("%s(", __func__);
 710         for (i = 0 ; i < d->msg_len;) {
 711                 dprintk("0x%02x", d->msg[i]);
 712                 if (++i < d->msg_len)
 713                         dprintk(", ");
 714         }
 715
 716         /* enable DiSEqC message send pin */
 717         data = ds3000_readreg(state, 0xa2);
 718         data &= ~0xc0;
 719         ds3000_writereg(state, 0xa2, data);
 720
 721         /* DiSEqC message */
 722         for (i = 0; i < d->msg_len; i++)
 723                 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
 724
 725         data = ds3000_readreg(state, 0xa1);
 726         /* clear DiSEqC message length and status,
 727         enable DiSEqC message send */
 728         data &= ~0xf8;
 729         /* set DiSEqC mode, modulation active during 33 pulses,
 730         set DiSEqC message length */
 731         data |= ((d->msg_len - 1) << 3) | 0x07;
 732         ds3000_writereg(state, 0xa1, data);
 733
 734         /* wait up to 150ms for DiSEqC transmission to complete */
 735         for (i = 0; i < 15; i++) {
 736                 data = ds3000_readreg(state, 0xa1);
 737                 if ((data & 0x40) == 0)
 738                         break;
 739                 msleep(10);
 740         }
 741
 742         /* DiSEqC timeout after 150ms */
 743         if (i == 15) {
 744                 data = ds3000_readreg(state, 0xa1);
 745                 data &= ~0x80;
 746                 data |= 0x40;
 747                 ds3000_writereg(state, 0xa1, data);
 748
 749                 data = ds3000_readreg(state, 0xa2);
 750                 data &= ~0xc0;
 751                 data |= 0x80;
 752                 ds3000_writereg(state, 0xa2, data);
 753
 754                 return 1;
 755         }
 756
 757         data = ds3000_readreg(state, 0xa2);
 758         data &= ~0xc0;
 759         data |= 0x80;
 760         ds3000_writereg(state, 0xa2, data);
 761
 762         return 0;
 763 }
 764
 765 /* Send DiSEqC burst */
 766 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
 767                                         fe_sec_mini_cmd_t burst)
 768 {
 769         struct ds3000_state *state = fe->demodulator_priv;
 770         int i;
 771         u8 data;
 772
 773         dprintk("%s()\n", __func__);
 774
 775         data = ds3000_readreg(state, 0xa2);
 776         data &= ~0xc0;
 777         ds3000_writereg(state, 0xa2, data);
 778
 779         /* DiSEqC burst */
 780         if (burst == SEC_MINI_A)
 781                 /* Unmodulated tone burst */
 782                 ds3000_writereg(state, 0xa1, 0x02);
 783         else if (burst == SEC_MINI_B)
 784                 /* Modulated tone burst */
 785                 ds3000_writereg(state, 0xa1, 0x01);
 786         else
 787                 return -EINVAL;
 788
 789         msleep(13);
 790         for (i = 0; i < 5; i++) {
 791                 data = ds3000_readreg(state, 0xa1);
 792                 if ((data & 0x40) == 0)
 793                         break;
 794                 msleep(1);
 795         }
 796
 797         if (i == 5) {
 798                 data = ds3000_readreg(state, 0xa1);
 799                 data &= ~0x80;
 800                 data |= 0x40;
 801                 ds3000_writereg(state, 0xa1, data);
 802
 803                 data = ds3000_readreg(state, 0xa2);
 804                 data &= ~0xc0;
 805                 data |= 0x80;
 806                 ds3000_writereg(state, 0xa2, data);
 807
 808                 return 1;
 809         }
 810
 811         data = ds3000_readreg(state, 0xa2);
 812         data &= ~0xc0;
 813         data |= 0x80;
 814         ds3000_writereg(state, 0xa2, data);
 815
 816         return 0;
 817 }
 818
 819 static void ds3000_release(struct dvb_frontend *fe)
 820 {
 821         struct ds3000_state *state = fe->demodulator_priv;
 822
 823         if (state->config->set_lock_led)
 824                 state->config->set_lock_led(fe, 0);
 825
 826         dprintk("%s\n", __func__);
 827         kfree(state);
 828 }
 829
 830 static struct dvb_frontend_ops ds3000_ops;
 831
 832 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
 833                                     struct i2c_adapter *i2c)
 834 {
 835         struct ds3000_state *state = NULL;
 836         int ret;
 837
 838         dprintk("%s\n", __func__);
 839
 840         /* allocate memory for the internal state */
 841         state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL);
 842         if (state == NULL) {
 843                 printk(KERN_ERR "Unable to kmalloc\n");
 844                 goto error2;
 845         }
 846
 847         state->config = config;
 848         state->i2c = i2c;
 849         state->prevUCBS2 = 0;
 850
 851         /* check if the demod is present */
 852         ret = ds3000_readreg(state, 0x00) & 0xfe;
 853         if (ret != 0xe0) {
 854                 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
 855                 goto error3;
 856         }
 857
 858         printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
 859                         ds3000_readreg(state, 0x02),
 860                         ds3000_readreg(state, 0x01));
 861
 862         memcpy(&state->frontend.ops, &ds3000_ops,
 863                         sizeof(struct dvb_frontend_ops));
 864         state->frontend.demodulator_priv = state;
 865
 866         /*
 867          * Some devices like T480 starts with voltage on. Be sure
 868          * to turn voltage off during init, as this can otherwise
 869          * interfere with Unicable SCR systems.
 870          */
 871         ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF);
 872         return &state->frontend;
 873
 874 error3:
 875         kfree(state);
 876 error2:
 877         return NULL;
 878 }
 879 EXPORT_SYMBOL(ds3000_attach);
 880
 881 static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
 882                                         s32 carrier_offset_khz)
 883 {
 884         struct ds3000_state *state = fe->demodulator_priv;
 885         s32 tmp;
 886
 887         tmp = carrier_offset_khz;
 888         tmp *= 65536;
 889         tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
 890
 891         if (tmp < 0)
 892                 tmp += 65536;
 893
 894         ds3000_writereg(state, 0x5f, tmp >> 8);
 895         ds3000_writereg(state, 0x5e, tmp & 0xff);
 896
 897         return 0;
 898 }
 899
 900 static int ds3000_set_frontend(struct dvb_frontend *fe)
 901 {
 902         struct ds3000_state *state = fe->demodulator_priv;
 903         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 904
 905         int i;
 906         fe_status_t status;
 907         s32 offset_khz;
 908         u32 frequency;
 909         u16 value;
 910
 911         dprintk("%s() ", __func__);
 912
 913         if (state->config->set_ts_params)
 914                 state->config->set_ts_params(fe, 0);
 915         /* Tune */
 916         if (fe->ops.tuner_ops.set_params)
 917                 fe->ops.tuner_ops.set_params(fe);
 918
 919         /* ds3000 global reset */
 920         ds3000_writereg(state, 0x07, 0x80);
 921         ds3000_writereg(state, 0x07, 0x00);
 922         /* ds3000 build-in uC reset */
 923         ds3000_writereg(state, 0xb2, 0x01);
 924         /* ds3000 software reset */
 925         ds3000_writereg(state, 0x00, 0x01);
 926
 927         switch (c->delivery_system) {
 928         case SYS_DVBS:
 929                 /* initialise the demod in DVB-S mode */
 930                 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
 931                         ds3000_writereg(state,
 932                                 ds3000_dvbs_init_tab[i],
 933                                 ds3000_dvbs_init_tab[i + 1]);
 934                 value = ds3000_readreg(state, 0xfe);
 935                 value &= 0xc0;
 936                 value |= 0x1b;
 937                 ds3000_writereg(state, 0xfe, value);
 938                 break;
 939         case SYS_DVBS2:
 940                 /* initialise the demod in DVB-S2 mode */
 941                 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
 942                         ds3000_writereg(state,
 943                                 ds3000_dvbs2_init_tab[i],
 944                                 ds3000_dvbs2_init_tab[i + 1]);
 945                 if (c->symbol_rate >= 30000000)
 946                         ds3000_writereg(state, 0xfe, 0x54);
 947                 else
 948                         ds3000_writereg(state, 0xfe, 0x98);
 949                 break;
 950         default:
 951                 return 1;
 952         }
 953
 954         /* enable 27MHz clock output */
 955         ds3000_writereg(state, 0x29, 0x80);
 956         /* enable ac coupling */
 957         ds3000_writereg(state, 0x25, 0x8a);
 958
 959         /* enhance symbol rate performance */
 960         if ((c->symbol_rate / 1000) <= 5000) {
 961                 value = 29777 / (c->symbol_rate / 1000) + 1;
 962                 if (value % 2 != 0)
 963                         value++;
 964                 ds3000_writereg(state, 0xc3, 0x0d);
 965                 ds3000_writereg(state, 0xc8, value);
 966                 ds3000_writereg(state, 0xc4, 0x10);
 967                 ds3000_writereg(state, 0xc7, 0x0e);
 968         } else if ((c->symbol_rate / 1000) <= 10000) {
 969                 value = 92166 / (c->symbol_rate / 1000) + 1;
 970                 if (value % 2 != 0)
 971                         value++;
 972                 ds3000_writereg(state, 0xc3, 0x07);
 973                 ds3000_writereg(state, 0xc8, value);
 974                 ds3000_writereg(state, 0xc4, 0x09);
 975                 ds3000_writereg(state, 0xc7, 0x12);
 976         } else if ((c->symbol_rate / 1000) <= 20000) {
 977                 value = 64516 / (c->symbol_rate / 1000) + 1;
 978                 ds3000_writereg(state, 0xc3, value);
 979                 ds3000_writereg(state, 0xc8, 0x0e);
 980                 ds3000_writereg(state, 0xc4, 0x07);
 981                 ds3000_writereg(state, 0xc7, 0x18);
 982         } else {
 983                 value = 129032 / (c->symbol_rate / 1000) + 1;
 984                 ds3000_writereg(state, 0xc3, value);
 985                 ds3000_writereg(state, 0xc8, 0x0a);
 986                 ds3000_writereg(state, 0xc4, 0x05);
 987                 ds3000_writereg(state, 0xc7, 0x24);
 988         }
 989
 990         /* normalized symbol rate rounded to the closest integer */
 991         value = (((c->symbol_rate / 1000) << 16) +
 992                         (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
 993         ds3000_writereg(state, 0x61, value & 0x00ff);
 994         ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
 995
 996         /* co-channel interference cancellation disabled */
 997         ds3000_writereg(state, 0x56, 0x00);
 998
 999         /* equalizer disabled */
1000         ds3000_writereg(state, 0x76, 0x00);
1001
1002         /*ds3000_writereg(state, 0x08, 0x03);
1003         ds3000_writereg(state, 0xfd, 0x22);
1004         ds3000_writereg(state, 0x08, 0x07);
1005         ds3000_writereg(state, 0xfd, 0x42);
1006         ds3000_writereg(state, 0x08, 0x07);*/
1007
1008         if (state->config->ci_mode) {
1009                 switch (c->delivery_system) {
1010                 case SYS_DVBS:
1011                 default:
1012                         ds3000_writereg(state, 0xfd, 0x80);
1013                 break;
1014                 case SYS_DVBS2:
1015                         ds3000_writereg(state, 0xfd, 0x01);
1016                         break;
1017                 }
1018         }
1019
1020         /* ds3000 out of software reset */
1021         ds3000_writereg(state, 0x00, 0x00);
1022         /* start ds3000 build-in uC */
1023         ds3000_writereg(state, 0xb2, 0x00);
1024
1025         if (fe->ops.tuner_ops.get_frequency) {
1026                 fe->ops.tuner_ops.get_frequency(fe, &frequency);
1027                 offset_khz = frequency - c->frequency;
1028                 ds3000_set_carrier_offset(fe, offset_khz);
1029         }
1030
1031         for (i = 0; i < 30 ; i++) {
1032                 ds3000_read_status(fe, &status);
1033                 if (status & FE_HAS_LOCK)
1034                         break;
1035
1036                 msleep(10);
1037         }
1038
1039         return 0;
1040 }
1041
1042 static int ds3000_tune(struct dvb_frontend *fe,
1043                         bool re_tune,
1044                         unsigned int mode_flags,
1045                         unsigned int *delay,
1046                         fe_status_t *status)
1047 {
1048         if (re_tune) {
1049                 int ret = ds3000_set_frontend(fe);
1050                 if (ret)
1051                         return ret;
1052         }
1053
1054         *delay = HZ / 5;
1055
1056         return ds3000_read_status(fe, status);
1057 }
1058
1059 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1060 {
1061         struct ds3000_state *state = fe->demodulator_priv;
1062
1063         if (state->config->set_lock_led)
1064                 state->config->set_lock_led(fe, 0);
1065
1066         dprintk("%s()\n", __func__);
1067         return DVBFE_ALGO_HW;
1068 }
1069
1070 /*
1071  * Initialise or wake up device
1072  *
1073  * Power config will reset and load initial firmware if required
1074  */
1075 static int ds3000_initfe(struct dvb_frontend *fe)
1076 {
1077         struct ds3000_state *state = fe->demodulator_priv;
1078         int ret;
1079
1080         dprintk("%s()\n", __func__);
1081         /* hard reset */
1082         ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1083         msleep(1);
1084
1085         /* Load the firmware if required */
1086         ret = ds3000_firmware_ondemand(fe);
1087         if (ret != 0) {
1088                 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1089                 return ret;
1090         }
1091
1092         return 0;
1093 }
1094
1095 static struct dvb_frontend_ops ds3000_ops = {
1096         .delsys = { SYS_DVBS, SYS_DVBS2 },
1097         .info = {
1098                 .name = "Montage Technology DS3000",
1099                 .frequency_min = 950000,
1100                 .frequency_max = 2150000,
1101                 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1102                 .frequency_tolerance = 5000,
1103                 .symbol_rate_min = 1000000,
1104                 .symbol_rate_max = 45000000,
1105                 .caps = FE_CAN_INVERSION_AUTO |
1106                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1107                         FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1108                         FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1109                         FE_CAN_2G_MODULATION |
1110                         FE_CAN_QPSK | FE_CAN_RECOVER
1111         },
1112
1113         .release = ds3000_release,
1114
1115         .init = ds3000_initfe,
1116         .i2c_gate_ctrl = ds3000_i2c_gate_ctrl,
1117         .read_status = ds3000_read_status,
1118         .read_ber = ds3000_read_ber,
1119         .read_signal_strength = ds3000_read_signal_strength,
1120         .read_snr = ds3000_read_snr,
1121         .read_ucblocks = ds3000_read_ucblocks,
1122         .set_voltage = ds3000_set_voltage,
1123         .set_tone = ds3000_set_tone,
1124         .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1125         .diseqc_send_burst = ds3000_diseqc_send_burst,
1126         .get_frontend_algo = ds3000_get_algo,
1127
1128         .set_frontend = ds3000_set_frontend,
1129         .tune = ds3000_tune,
1130 };
1131
1132 module_param(debug, int, 0644);
1133 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1134
1135 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
1136                         "DS3000 hardware");
1137 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
1138 MODULE_LICENSE("GPL");
1139 /*(DEBLOBBED)*/