drivers/media/dvb-frontends/drxd_hard.c

   1 /*
   2  * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
   3  *
   4  * Copyright (C) 2003-2007 Micronas
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/firmware.h>
  30 #include <linux/i2c.h>
  31 #include <asm/div64.h>
  32
  33 #include "dvb_frontend.h"
  34 #include "drxd.h"
  35 #include "drxd_firm.h"
  36
  37 #define DRX_FW_FILENAME_A2 "/*(DEBLOBBED)*/"
  38 #define DRX_FW_FILENAME_B1 "/*(DEBLOBBED)*/"
  39
  40 #define CHUNK_SIZE 48
  41
  42 #define DRX_I2C_RMW           0x10
  43 #define DRX_I2C_BROADCAST     0x20
  44 #define DRX_I2C_CLEARCRC      0x80
  45 #define DRX_I2C_SINGLE_MASTER 0xC0
  46 #define DRX_I2C_MODEFLAGS     0xC0
  47 #define DRX_I2C_FLAGS         0xF0
  48
  49 #ifndef SIZEOF_ARRAY
  50 #define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
  51 #endif
  52
  53 #define DEFAULT_LOCK_TIMEOUT    1100
  54
  55 #define DRX_CHANNEL_AUTO 0
  56 #define DRX_CHANNEL_HIGH 1
  57 #define DRX_CHANNEL_LOW  2
  58
  59 #define DRX_LOCK_MPEG  1
  60 #define DRX_LOCK_FEC   2
  61 #define DRX_LOCK_DEMOD 4
  62
  63 /****************************************************************************/
  64
  65 enum CSCDState {
  66         CSCD_INIT = 0,
  67         CSCD_SET,
  68         CSCD_SAVED
  69 };
  70
  71 enum CDrxdState {
  72         DRXD_UNINITIALIZED = 0,
  73         DRXD_STOPPED,
  74         DRXD_STARTED
  75 };
  76
  77 enum AGC_CTRL_MODE {
  78         AGC_CTRL_AUTO = 0,
  79         AGC_CTRL_USER,
  80         AGC_CTRL_OFF
  81 };
  82
  83 enum OperationMode {
  84         OM_Default,
  85         OM_DVBT_Diversity_Front,
  86         OM_DVBT_Diversity_End
  87 };
  88
  89 struct SCfgAgc {
  90         enum AGC_CTRL_MODE ctrlMode;
  91         u16 outputLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  92         u16 settleLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  93         u16 minOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  94         u16 maxOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  95         u16 speed;              /* range [0, ... , 1023], 1/n of fullscale range */
  96
  97         u16 R1;
  98         u16 R2;
  99         u16 R3;
 100 };
 101
 102 struct SNoiseCal {
 103         int cpOpt;
 104         short cpNexpOfs;
 105         short tdCal2k;
 106         short tdCal8k;
 107 };
 108
 109 enum app_env {
 110         APPENV_STATIC = 0,
 111         APPENV_PORTABLE = 1,
 112         APPENV_MOBILE = 2
 113 };
 114
 115 enum EIFFilter {
 116         IFFILTER_SAW = 0,
 117         IFFILTER_DISCRETE = 1
 118 };
 119
 120 struct drxd_state {
 121         struct dvb_frontend frontend;
 122         struct dvb_frontend_ops ops;
 123         struct dtv_frontend_properties props;
 124
 125         const struct firmware *fw;
 126         struct device *dev;
 127
 128         struct i2c_adapter *i2c;
 129         void *priv;
 130         struct drxd_config config;
 131
 132         int i2c_access;
 133         int init_done;
 134         struct mutex mutex;
 135
 136         u8 chip_adr;
 137         u16 hi_cfg_timing_div;
 138         u16 hi_cfg_bridge_delay;
 139         u16 hi_cfg_wakeup_key;
 140         u16 hi_cfg_ctrl;
 141
 142         u16 intermediate_freq;
 143         u16 osc_clock_freq;
 144
 145         enum CSCDState cscd_state;
 146         enum CDrxdState drxd_state;
 147
 148         u16 sys_clock_freq;
 149         s16 osc_clock_deviation;
 150         u16 expected_sys_clock_freq;
 151
 152         u16 insert_rs_byte;
 153         u16 enable_parallel;
 154
 155         int operation_mode;
 156
 157         struct SCfgAgc if_agc_cfg;
 158         struct SCfgAgc rf_agc_cfg;
 159
 160         struct SNoiseCal noise_cal;
 161
 162         u32 fe_fs_add_incr;
 163         u32 org_fe_fs_add_incr;
 164         u16 current_fe_if_incr;
 165
 166         u16 m_FeAgRegAgPwd;
 167         u16 m_FeAgRegAgAgcSio;
 168
 169         u16 m_EcOcRegOcModeLop;
 170         u16 m_EcOcRegSncSncLvl;
 171         u8 *m_InitAtomicRead;
 172         u8 *m_HiI2cPatch;
 173
 174         u8 *m_ResetCEFR;
 175         u8 *m_InitFE_1;
 176         u8 *m_InitFE_2;
 177         u8 *m_InitCP;
 178         u8 *m_InitCE;
 179         u8 *m_InitEQ;
 180         u8 *m_InitSC;
 181         u8 *m_InitEC;
 182         u8 *m_ResetECRAM;
 183         u8 *m_InitDiversityFront;
 184         u8 *m_InitDiversityEnd;
 185         u8 *m_DisableDiversity;
 186         u8 *m_StartDiversityFront;
 187         u8 *m_StartDiversityEnd;
 188
 189         u8 *m_DiversityDelay8MHZ;
 190         u8 *m_DiversityDelay6MHZ;
 191
 192         u8 *microcode;
 193         u32 microcode_length;
 194
 195         int type_A;
 196         int PGA;
 197         int diversity;
 198         int tuner_mirrors;
 199
 200         enum app_env app_env_default;
 201         enum app_env app_env_diversity;
 202
 203 };
 204
 205 /****************************************************************************/
 206 /* I2C **********************************************************************/
 207 /****************************************************************************/
 208
 209 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
 210 {
 211         struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
 212
 213         if (i2c_transfer(adap, &msg, 1) != 1)
 214                 return -1;
 215         return 0;
 216 }
 217
 218 static int i2c_read(struct i2c_adapter *adap,
 219                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 220 {
 221         struct i2c_msg msgs[2] = {
 222                 {
 223                         .addr = adr, .flags = 0,
 224                         .buf = msg, .len = len
 225                 }, {
 226                         .addr = adr, .flags = I2C_M_RD,
 227                         .buf = answ, .len = alen
 228                 }
 229         };
 230         if (i2c_transfer(adap, msgs, 2) != 2)
 231                 return -1;
 232         return 0;
 233 }
 234
 235 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
 236 {
 237         u64 tmp64;
 238
 239         tmp64 = (u64)a * (u64)b;
 240         do_div(tmp64, c);
 241
 242         return (u32) tmp64;
 243 }
 244
 245 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
 246 {
 247         u8 adr = state->config.demod_address;
 248         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 249                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 250         };
 251         u8 mm2[2];
 252         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
 253                 return -1;
 254         if (data)
 255                 *data = mm2[0] | (mm2[1] << 8);
 256         return mm2[0] | (mm2[1] << 8);
 257 }
 258
 259 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
 260 {
 261         u8 adr = state->config.demod_address;
 262         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 263                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 264         };
 265         u8 mm2[4];
 266
 267         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
 268                 return -1;
 269         if (data)
 270                 *data =
 271                     mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
 272         return 0;
 273 }
 274
 275 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
 276 {
 277         u8 adr = state->config.demod_address;
 278         u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
 279                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 280                 data & 0xff, (data >> 8) & 0xff
 281         };
 282
 283         if (i2c_write(state->i2c, adr, mm, 6) < 0)
 284                 return -1;
 285         return 0;
 286 }
 287
 288 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
 289 {
 290         u8 adr = state->config.demod_address;
 291         u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
 292                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 293                 data & 0xff, (data >> 8) & 0xff,
 294                 (data >> 16) & 0xff, (data >> 24) & 0xff
 295         };
 296
 297         if (i2c_write(state->i2c, adr, mm, 8) < 0)
 298                 return -1;
 299         return 0;
 300 }
 301
 302 static int write_chunk(struct drxd_state *state,
 303                        u32 reg, u8 *data, u32 len, u8 flags)
 304 {
 305         u8 adr = state->config.demod_address;
 306         u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
 307                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 308         };
 309         int i;
 310
 311         for (i = 0; i < len; i++)
 312                 mm[4 + i] = data[i];
 313         if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
 314                 printk(KERN_ERR "error in write_chunk\n");
 315                 return -1;
 316         }
 317         return 0;
 318 }
 319
 320 static int WriteBlock(struct drxd_state *state,
 321                       u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
 322 {
 323         while (BlockSize > 0) {
 324                 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
 325
 326                 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
 327                         return -1;
 328                 pBlock += Chunk;
 329                 Address += (Chunk >> 1);
 330                 BlockSize -= Chunk;
 331         }
 332         return 0;
 333 }
 334
 335 static int WriteTable(struct drxd_state *state, u8 * pTable)
 336 {
 337         int status = 0;
 338
 339         if (pTable == NULL)
 340                 return 0;
 341
 342         while (!status) {
 343                 u16 Length;
 344                 u32 Address = pTable[0] | (pTable[1] << 8) |
 345                     (pTable[2] << 16) | (pTable[3] << 24);
 346
 347                 if (Address == 0xFFFFFFFF)
 348                         break;
 349                 pTable += sizeof(u32);
 350
 351                 Length = pTable[0] | (pTable[1] << 8);
 352                 pTable += sizeof(u16);
 353                 if (!Length)
 354                         break;
 355                 status = WriteBlock(state, Address, Length * 2, pTable, 0);
 356                 pTable += (Length * 2);
 357         }
 358         return status;
 359 }
 360
 361 /****************************************************************************/
 362 /****************************************************************************/
 363 /****************************************************************************/
 364
 365 static int ResetCEFR(struct drxd_state *state)
 366 {
 367         return WriteTable(state, state->m_ResetCEFR);
 368 }
 369
 370 static int InitCP(struct drxd_state *state)
 371 {
 372         return WriteTable(state, state->m_InitCP);
 373 }
 374
 375 static int InitCE(struct drxd_state *state)
 376 {
 377         int status;
 378         enum app_env AppEnv = state->app_env_default;
 379
 380         do {
 381                 status = WriteTable(state, state->m_InitCE);
 382                 if (status < 0)
 383                         break;
 384
 385                 if (state->operation_mode == OM_DVBT_Diversity_Front ||
 386                     state->operation_mode == OM_DVBT_Diversity_End) {
 387                         AppEnv = state->app_env_diversity;
 388                 }
 389                 if (AppEnv == APPENV_STATIC) {
 390                         status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
 391                         if (status < 0)
 392                                 break;
 393                 } else if (AppEnv == APPENV_PORTABLE) {
 394                         status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
 395                         if (status < 0)
 396                                 break;
 397                 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
 398                         status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
 399                         if (status < 0)
 400                                 break;
 401                 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
 402                         status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
 403                         if (status < 0)
 404                                 break;
 405                 }
 406
 407                 /* start ce */
 408                 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
 409                 if (status < 0)
 410                         break;
 411         } while (0);
 412         return status;
 413 }
 414
 415 static int StopOC(struct drxd_state *state)
 416 {
 417         int status = 0;
 418         u16 ocSyncLvl = 0;
 419         u16 ocModeLop = state->m_EcOcRegOcModeLop;
 420         u16 dtoIncLop = 0;
 421         u16 dtoIncHip = 0;
 422
 423         do {
 424                 /* Store output configuration */
 425                 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
 426                 if (status < 0)
 427                         break;
 428                 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
 429                 state->m_EcOcRegSncSncLvl = ocSyncLvl;
 430                 /* m_EcOcRegOcModeLop = ocModeLop; */
 431
 432                 /* Flush FIFO (byte-boundary) at fixed rate */
 433                 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
 434                 if (status < 0)
 435                         break;
 436                 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
 437                 if (status < 0)
 438                         break;
 439                 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
 440                 if (status < 0)
 441                         break;
 442                 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
 443                 if (status < 0)
 444                         break;
 445                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
 446                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
 447                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 448                 if (status < 0)
 449                         break;
 450                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 451                 if (status < 0)
 452                         break;
 453
 454                 msleep(1);
 455                 /* Output pins to '0' */
 456                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
 457                 if (status < 0)
 458                         break;
 459
 460                 /* Force the OC out of sync */
 461                 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
 462                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
 463                 if (status < 0)
 464                         break;
 465                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
 466                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
 467                 ocModeLop |= 0x2;       /* Magically-out-of-sync */
 468                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 469                 if (status < 0)
 470                         break;
 471                 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
 472                 if (status < 0)
 473                         break;
 474                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 475                 if (status < 0)
 476                         break;
 477         } while (0);
 478
 479         return status;
 480 }
 481
 482 static int StartOC(struct drxd_state *state)
 483 {
 484         int status = 0;
 485
 486         do {
 487                 /* Stop OC */
 488                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 489                 if (status < 0)
 490                         break;
 491
 492                 /* Restore output configuration */
 493                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
 494                 if (status < 0)
 495                         break;
 496                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
 497                 if (status < 0)
 498                         break;
 499
 500                 /* Output pins active again */
 501                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
 502                 if (status < 0)
 503                         break;
 504
 505                 /* Start OC */
 506                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 507                 if (status < 0)
 508                         break;
 509         } while (0);
 510         return status;
 511 }
 512
 513 static int InitEQ(struct drxd_state *state)
 514 {
 515         return WriteTable(state, state->m_InitEQ);
 516 }
 517
 518 static int InitEC(struct drxd_state *state)
 519 {
 520         return WriteTable(state, state->m_InitEC);
 521 }
 522
 523 static int InitSC(struct drxd_state *state)
 524 {
 525         return WriteTable(state, state->m_InitSC);
 526 }
 527
 528 static int InitAtomicRead(struct drxd_state *state)
 529 {
 530         return WriteTable(state, state->m_InitAtomicRead);
 531 }
 532
 533 static int CorrectSysClockDeviation(struct drxd_state *state);
 534
 535 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
 536 {
 537         u16 ScRaRamLock = 0;
 538         const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
 539                                     SC_RA_RAM_LOCK_FEC__M |
 540                                     SC_RA_RAM_LOCK_DEMOD__M);
 541         const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
 542                                    SC_RA_RAM_LOCK_DEMOD__M);
 543         const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
 544
 545         int status;
 546
 547         *pLockStatus = 0;
 548
 549         status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
 550         if (status < 0) {
 551                 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
 552                 return status;
 553         }
 554
 555         if (state->drxd_state != DRXD_STARTED)
 556                 return 0;
 557
 558         if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
 559                 *pLockStatus |= DRX_LOCK_MPEG;
 560                 CorrectSysClockDeviation(state);
 561         }
 562
 563         if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
 564                 *pLockStatus |= DRX_LOCK_FEC;
 565
 566         if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
 567                 *pLockStatus |= DRX_LOCK_DEMOD;
 568         return 0;
 569 }
 570
 571 /****************************************************************************/
 572
 573 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 574 {
 575         int status;
 576
 577         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 578                 return -1;
 579
 580         if (cfg->ctrlMode == AGC_CTRL_USER) {
 581                 do {
 582                         u16 FeAgRegPm1AgcWri;
 583                         u16 FeAgRegAgModeLop;
 584
 585                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 586                         if (status < 0)
 587                                 break;
 588                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 589                         FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
 590                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 591                         if (status < 0)
 592                                 break;
 593
 594                         FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
 595                                                   FE_AG_REG_PM1_AGC_WRI__M);
 596                         status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
 597                         if (status < 0)
 598                                 break;
 599                 } while (0);
 600         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 601                 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
 602                     ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
 603                     ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
 604                     ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
 605                     )
 606                         return -1;
 607                 do {
 608                         u16 FeAgRegAgModeLop;
 609                         u16 FeAgRegEgcSetLvl;
 610                         u16 slope, offset;
 611
 612                         /* == Mode == */
 613
 614                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 615                         if (status < 0)
 616                                 break;
 617                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 618                         FeAgRegAgModeLop |=
 619                             FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
 620                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 621                         if (status < 0)
 622                                 break;
 623
 624                         /* == Settle level == */
 625
 626                         FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
 627                                                   FE_AG_REG_EGC_SET_LVL__M);
 628                         status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
 629                         if (status < 0)
 630                                 break;
 631
 632                         /* == Min/Max == */
 633
 634                         slope = (u16) ((cfg->maxOutputLevel -
 635                                         cfg->minOutputLevel) / 2);
 636                         offset = (u16) ((cfg->maxOutputLevel +
 637                                          cfg->minOutputLevel) / 2 - 511);
 638
 639                         status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
 640                         if (status < 0)
 641                                 break;
 642                         status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
 643                         if (status < 0)
 644                                 break;
 645
 646                         /* == Speed == */
 647                         {
 648                                 const u16 maxRur = 8;
 649                                 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
 650                                 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
 651                                         17, 18, 18, 19,
 652                                         20, 21, 22, 23,
 653                                         24, 26, 27, 28,
 654                                         29, 31
 655                                 };
 656
 657                                 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
 658                                     (maxRur + 1);
 659                                 u16 fineSpeed = (u16) (cfg->speed -
 660                                                        ((cfg->speed /
 661                                                          fineSteps) *
 662                                                         fineSteps));
 663                                 u16 invRurCount = (u16) (cfg->speed /
 664                                                          fineSteps);
 665                                 u16 rurCount;
 666                                 if (invRurCount > maxRur) {
 667                                         rurCount = 0;
 668                                         fineSpeed += fineSteps;
 669                                 } else {
 670                                         rurCount = maxRur - invRurCount;
 671                                 }
 672
 673                                 /*
 674                                    fastInc = default *
 675                                    (2^(fineSpeed/fineSteps))
 676                                    => range[default...2*default>
 677                                    slowInc = default *
 678                                    (2^(fineSpeed/fineSteps))
 679                                  */
 680                                 {
 681                                         u16 fastIncrDec =
 682                                             fastIncrDecLUT[fineSpeed /
 683                                                            ((fineSteps /
 684                                                              (14 + 1)) + 1)];
 685                                         u16 slowIncrDec =
 686                                             slowIncrDecLUT[fineSpeed /
 687                                                            (fineSteps /
 688                                                             (3 + 1))];
 689
 690                                         status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
 691                                         if (status < 0)
 692                                                 break;
 693                                         status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
 694                                         if (status < 0)
 695                                                 break;
 696                                         status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
 697                                         if (status < 0)
 698                                                 break;
 699                                         status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
 700                                         if (status < 0)
 701                                                 break;
 702                                         status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
 703                                         if (status < 0)
 704                                                 break;
 705                                 }
 706                         }
 707                 } while (0);
 708
 709         } else {
 710                 /* No OFF mode for IF control */
 711                 return -1;
 712         }
 713         return status;
 714 }
 715
 716 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 717 {
 718         int status = 0;
 719
 720         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 721                 return -1;
 722
 723         if (cfg->ctrlMode == AGC_CTRL_USER) {
 724                 do {
 725                         u16 AgModeLop = 0;
 726                         u16 level = (cfg->outputLevel);
 727
 728                         if (level == DRXD_FE_CTRL_MAX)
 729                                 level++;
 730
 731                         status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
 732                         if (status < 0)
 733                                 break;
 734
 735                         /*==== Mode ====*/
 736
 737                         /* Powerdown PD2, WRI source */
 738                         state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 739                         state->m_FeAgRegAgPwd |=
 740                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 741                         status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
 742                         if (status < 0)
 743                                 break;
 744
 745                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 746                         if (status < 0)
 747                                 break;
 748                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 749                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 750                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 751                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 752                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 753                         if (status < 0)
 754                                 break;
 755
 756                         /* enable AGC2 pin */
 757                         {
 758                                 u16 FeAgRegAgAgcSio = 0;
 759                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 760                                 if (status < 0)
 761                                         break;
 762                                 FeAgRegAgAgcSio &=
 763                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 764                                 FeAgRegAgAgcSio |=
 765                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 766                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 767                                 if (status < 0)
 768                                         break;
 769                         }
 770
 771                 } while (0);
 772         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 773                 u16 AgModeLop = 0;
 774
 775                 do {
 776                         u16 level;
 777                         /* Automatic control */
 778                         /* Powerup PD2, AGC2 as output, TGC source */
 779                         (state->m_FeAgRegAgPwd) &=
 780                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 781                         (state->m_FeAgRegAgPwd) |=
 782                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 783                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 784                         if (status < 0)
 785                                 break;
 786
 787                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 788                         if (status < 0)
 789                                 break;
 790                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 791                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 792                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 793                                       FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
 794                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 795                         if (status < 0)
 796                                 break;
 797                         /* Settle level */
 798                         level = (((cfg->settleLevel) >> 4) &
 799                                  FE_AG_REG_TGC_SET_LVL__M);
 800                         status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
 801                         if (status < 0)
 802                                 break;
 803
 804                         /* Min/max: don't care */
 805
 806                         /* Speed: TODO */
 807
 808                         /* enable AGC2 pin */
 809                         {
 810                                 u16 FeAgRegAgAgcSio = 0;
 811                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 812                                 if (status < 0)
 813                                         break;
 814                                 FeAgRegAgAgcSio &=
 815                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 816                                 FeAgRegAgAgcSio |=
 817                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 818                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 819                                 if (status < 0)
 820                                         break;
 821                         }
 822
 823                 } while (0);
 824         } else {
 825                 u16 AgModeLop = 0;
 826
 827                 do {
 828                         /* No RF AGC control */
 829                         /* Powerdown PD2, AGC2 as output, WRI source */
 830                         (state->m_FeAgRegAgPwd) &=
 831                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 832                         (state->m_FeAgRegAgPwd) |=
 833                             FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
 834                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 835                         if (status < 0)
 836                                 break;
 837
 838                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 839                         if (status < 0)
 840                                 break;
 841                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 842                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 843                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 844                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 845                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 846                         if (status < 0)
 847                                 break;
 848
 849                         /* set FeAgRegAgAgcSio AGC2 (RF) as input */
 850                         {
 851                                 u16 FeAgRegAgAgcSio = 0;
 852                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 853                                 if (status < 0)
 854                                         break;
 855                                 FeAgRegAgAgcSio &=
 856                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 857                                 FeAgRegAgAgcSio |=
 858                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
 859                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 860                                 if (status < 0)
 861                                         break;
 862                         }
 863                 } while (0);
 864         }
 865         return status;
 866 }
 867
 868 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
 869 {
 870         int status = 0;
 871
 872         *pValue = 0;
 873         if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
 874                 u16 Value;
 875                 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
 876                 Value &= FE_AG_REG_GC1_AGC_DAT__M;
 877                 if (status >= 0) {
 878                         /*           3.3V
 879                            |
 880                            R1
 881                            |
 882                            Vin - R3 - * -- Vout
 883                            |
 884                            R2
 885                            |
 886                            GND
 887                          */
 888                         u32 R1 = state->if_agc_cfg.R1;
 889                         u32 R2 = state->if_agc_cfg.R2;
 890                         u32 R3 = state->if_agc_cfg.R3;
 891
 892                         u32 Vmax, Rpar, Vmin, Vout;
 893
 894                         if (R2 == 0 && (R1 == 0 || R3 == 0))
 895                                 return 0;
 896
 897                         Vmax = (3300 * R2) / (R1 + R2);
 898                         Rpar = (R2 * R3) / (R3 + R2);
 899                         Vmin = (3300 * Rpar) / (R1 + Rpar);
 900                         Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
 901
 902                         *pValue = Vout;
 903                 }
 904         }
 905         return status;
 906 }
 907
 908 static int load_firmware(struct drxd_state *state, const char *fw_name)
 909 {
 910         const struct firmware *fw;
 911
 912         if (reject_firmware(&fw, fw_name, state->dev) < 0) {
 913                 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
 914                 return -EIO;
 915         }
 916
 917         state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
 918         if (state->microcode == NULL) {
 919                 release_firmware(fw);
 920                 printk(KERN_ERR "drxd: firmware load failure: no memory\n");
 921                 return -ENOMEM;
 922         }
 923
 924         state->microcode_length = fw->size;
 925         release_firmware(fw);
 926         return 0;
 927 }
 928
 929 static int DownloadMicrocode(struct drxd_state *state,
 930                              const u8 *pMCImage, u32 Length)
 931 {
 932         u8 *pSrc;
 933         u32 Address;
 934         u16 nBlocks;
 935         u16 BlockSize;
 936         u32 offset = 0;
 937         int i, status = 0;
 938
 939         pSrc = (u8 *) pMCImage;
 940         /* We're not using Flags */
 941         /* Flags = (pSrc[0] << 8) | pSrc[1]; */
 942         pSrc += sizeof(u16);
 943         offset += sizeof(u16);
 944         nBlocks = (pSrc[0] << 8) | pSrc[1];
 945         pSrc += sizeof(u16);
 946         offset += sizeof(u16);
 947
 948         for (i = 0; i < nBlocks; i++) {
 949                 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
 950                     (pSrc[2] << 8) | pSrc[3];
 951                 pSrc += sizeof(u32);
 952                 offset += sizeof(u32);
 953
 954                 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
 955                 pSrc += sizeof(u16);
 956                 offset += sizeof(u16);
 957
 958                 /* We're not using Flags */
 959                 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
 960                 pSrc += sizeof(u16);
 961                 offset += sizeof(u16);
 962
 963                 /* We're not using BlockCRC */
 964                 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
 965                 pSrc += sizeof(u16);
 966                 offset += sizeof(u16);
 967
 968                 status = WriteBlock(state, Address, BlockSize,
 969                                     pSrc, DRX_I2C_CLEARCRC);
 970                 if (status < 0)
 971                         break;
 972                 pSrc += BlockSize;
 973                 offset += BlockSize;
 974         }
 975
 976         return status;
 977 }
 978
 979 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
 980 {
 981         u32 nrRetries = 0;
 982         u16 waitCmd;
 983         int status;
 984
 985         status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
 986         if (status < 0)
 987                 return status;
 988
 989         do {
 990                 nrRetries += 1;
 991                 if (nrRetries > DRXD_MAX_RETRIES) {
 992                         status = -1;
 993                         break;
 994                 }
 995                 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
 996         } while (waitCmd != 0);
 997
 998         if (status >= 0)
 999                 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
1000         return status;
1001 }
1002
1003 static int HI_CfgCommand(struct drxd_state *state)
1004 {
1005         int status = 0;
1006
1007         mutex_lock(&state->mutex);
1008         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1009         Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
1010         Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
1011         Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1012         Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1013
1014         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1015
1016         if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
1017             HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
1018                 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1019                                  HI_RA_RAM_SRV_CMD_CONFIG, 0);
1020         else
1021                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
1022         mutex_unlock(&state->mutex);
1023         return status;
1024 }
1025
1026 static int InitHI(struct drxd_state *state)
1027 {
1028         state->hi_cfg_wakeup_key = (state->chip_adr);
1029         /* port/bridge/power down ctrl */
1030         state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1031         return HI_CfgCommand(state);
1032 }
1033
1034 static int HI_ResetCommand(struct drxd_state *state)
1035 {
1036         int status;
1037
1038         mutex_lock(&state->mutex);
1039         status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1040                          HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1041         if (status == 0)
1042                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
1043         mutex_unlock(&state->mutex);
1044         msleep(1);
1045         return status;
1046 }
1047
1048 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1049 {
1050         state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1051         if (bEnableBridge)
1052                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1053         else
1054                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1055
1056         return HI_CfgCommand(state);
1057 }
1058
1059 #define HI_TR_WRITE      0x9
1060 #define HI_TR_READ       0xA
1061 #define HI_TR_READ_WRITE 0xB
1062 #define HI_TR_BROADCAST  0x4
1063
1064 #if 0
1065 static int AtomicReadBlock(struct drxd_state *state,
1066                            u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1067 {
1068         int status;
1069         int i = 0;
1070
1071         /* Parameter check */
1072         if ((!pData) || ((DataSize & 1) != 0))
1073                 return -1;
1074
1075         mutex_lock(&state->mutex);
1076
1077         do {
1078                 /* Instruct HI to read n bytes */
1079                 /* TODO use proper names forthese egisters */
1080                 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1081                 if (status < 0)
1082                         break;
1083                 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1084                 if (status < 0)
1085                         break;
1086                 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1087                 if (status < 0)
1088                         break;
1089                 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1090                 if (status < 0)
1091                         break;
1092                 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1093                 if (status < 0)
1094                         break;
1095
1096                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1097                 if (status < 0)
1098                         break;
1099
1100         } while (0);
1101
1102         if (status >= 0) {
1103                 for (i = 0; i < (DataSize / 2); i += 1) {
1104                         u16 word;
1105
1106                         status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1107                                         &word, 0);
1108                         if (status < 0)
1109                                 break;
1110                         pData[2 * i] = (u8) (word & 0xFF);
1111                         pData[(2 * i) + 1] = (u8) (word >> 8);
1112                 }
1113         }
1114         mutex_unlock(&state->mutex);
1115         return status;
1116 }
1117
1118 static int AtomicReadReg32(struct drxd_state *state,
1119                            u32 Addr, u32 *pData, u8 Flags)
1120 {
1121         u8 buf[sizeof(u32)];
1122         int status;
1123
1124         if (!pData)
1125                 return -1;
1126         status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1127         *pData = (((u32) buf[0]) << 0) +
1128             (((u32) buf[1]) << 8) +
1129             (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1130         return status;
1131 }
1132 #endif
1133
1134 static int StopAllProcessors(struct drxd_state *state)
1135 {
1136         return Write16(state, HI_COMM_EXEC__A,
1137                        SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1138 }
1139
1140 static int EnableAndResetMB(struct drxd_state *state)
1141 {
1142         if (state->type_A) {
1143                 /* disable? monitor bus observe @ EC_OC */
1144                 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1145         }
1146
1147         /* do inverse broadcast, followed by explicit write to HI */
1148         Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1149         Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1150         return 0;
1151 }
1152
1153 static int InitCC(struct drxd_state *state)
1154 {
1155         if (state->osc_clock_freq == 0 ||
1156             state->osc_clock_freq > 20000 ||
1157             (state->osc_clock_freq % 4000) != 0) {
1158                 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1159                 return -1;
1160         }
1161
1162         Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1163         Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1164                 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1165         Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1166         Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1167         Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1168
1169         return 0;
1170 }
1171
1172 static int ResetECOD(struct drxd_state *state)
1173 {
1174         int status = 0;
1175
1176         if (state->type_A)
1177                 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1178         else
1179                 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1180
1181         if (!(status < 0))
1182                 status = WriteTable(state, state->m_ResetECRAM);
1183         if (!(status < 0))
1184                 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1185         return status;
1186 }
1187
1188 /* Configure PGA switch */
1189
1190 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1191 {
1192         int status;
1193         u16 AgModeLop = 0;
1194         u16 AgModeHip = 0;
1195         do {
1196                 if (pgaSwitch) {
1197                         /* PGA on */
1198                         /* fine gain */
1199                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1200                         if (status < 0)
1201                                 break;
1202                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1203                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1204                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1205                         if (status < 0)
1206                                 break;
1207
1208                         /* coarse gain */
1209                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1210                         if (status < 0)
1211                                 break;
1212                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1213                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1214                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1215                         if (status < 0)
1216                                 break;
1217
1218                         /* enable fine and coarse gain, enable AAF,
1219                            no ext resistor */
1220                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1221                         if (status < 0)
1222                                 break;
1223                 } else {
1224                         /* PGA off, bypass */
1225
1226                         /* fine gain */
1227                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1228                         if (status < 0)
1229                                 break;
1230                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1231                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1232                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1233                         if (status < 0)
1234                                 break;
1235
1236                         /* coarse gain */
1237                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1238                         if (status < 0)
1239                                 break;
1240                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1241                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1242                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1243                         if (status < 0)
1244                                 break;
1245
1246                         /* disable fine and coarse gain, enable AAF,
1247                            no ext resistor */
1248                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1249                         if (status < 0)
1250                                 break;
1251                 }
1252         } while (0);
1253         return status;
1254 }
1255
1256 static int InitFE(struct drxd_state *state)
1257 {
1258         int status;
1259
1260         do {
1261                 status = WriteTable(state, state->m_InitFE_1);
1262                 if (status < 0)
1263                         break;
1264
1265                 if (state->type_A) {
1266                         status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1267                                          FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1268                                          0);
1269                 } else {
1270                         if (state->PGA)
1271                                 status = SetCfgPga(state, 0);
1272                         else
1273                                 status =
1274                                     Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1275                                             B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1276                                             0);
1277                 }
1278
1279                 if (status < 0)
1280                         break;
1281                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1282                 if (status < 0)
1283                         break;
1284                 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1285                 if (status < 0)
1286                         break;
1287
1288                 status = WriteTable(state, state->m_InitFE_2);
1289                 if (status < 0)
1290                         break;
1291
1292         } while (0);
1293
1294         return status;
1295 }
1296
1297 static int InitFT(struct drxd_state *state)
1298 {
1299         /*
1300            norm OFFSET,  MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1301            SC stuff
1302          */
1303         return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1304 }
1305
1306 static int SC_WaitForReady(struct drxd_state *state)
1307 {
1308         u16 curCmd;
1309         int i;
1310
1311         for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1312                 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1313                 if (status == 0 || curCmd == 0)
1314                         return status;
1315         }
1316         return -1;
1317 }
1318
1319 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1320 {
1321         int status = 0;
1322         u16 errCode;
1323
1324         Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1325         SC_WaitForReady(state);
1326
1327         Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1328
1329         if (errCode == 0xFFFF) {
1330                 printk(KERN_ERR "Command Error\n");
1331                 status = -1;
1332         }
1333
1334         return status;
1335 }
1336
1337 static int SC_ProcStartCommand(struct drxd_state *state,
1338                                u16 subCmd, u16 param0, u16 param1)
1339 {
1340         int status = 0;
1341         u16 scExec;
1342
1343         mutex_lock(&state->mutex);
1344         do {
1345                 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1346                 if (scExec != 1) {
1347                         status = -1;
1348                         break;
1349                 }
1350                 SC_WaitForReady(state);
1351                 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1352                 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1353                 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1354
1355                 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1356         } while (0);
1357         mutex_unlock(&state->mutex);
1358         return status;
1359 }
1360
1361 static int SC_SetPrefParamCommand(struct drxd_state *state,
1362                                   u16 subCmd, u16 param0, u16 param1)
1363 {
1364         int status;
1365
1366         mutex_lock(&state->mutex);
1367         do {
1368                 status = SC_WaitForReady(state);
1369                 if (status < 0)
1370                         break;
1371                 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1372                 if (status < 0)
1373                         break;
1374                 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1375                 if (status < 0)
1376                         break;
1377                 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1378                 if (status < 0)
1379                         break;
1380
1381                 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1382                 if (status < 0)
1383                         break;
1384         } while (0);
1385         mutex_unlock(&state->mutex);
1386         return status;
1387 }
1388
1389 #if 0
1390 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1391 {
1392         int status = 0;
1393
1394         mutex_lock(&state->mutex);
1395         do {
1396                 status = SC_WaitForReady(state);
1397                 if (status < 0)
1398                         break;
1399                 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1400                 if (status < 0)
1401                         break;
1402                 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1403                 if (status < 0)
1404                         break;
1405         } while (0);
1406         mutex_unlock(&state->mutex);
1407         return status;
1408 }
1409 #endif
1410
1411 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1412 {
1413         int status;
1414
1415         do {
1416                 u16 EcOcRegIprInvMpg = 0;
1417                 u16 EcOcRegOcModeLop = 0;
1418                 u16 EcOcRegOcModeHip = 0;
1419                 u16 EcOcRegOcMpgSio = 0;
1420
1421                 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1422
1423                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1424                         if (bEnableOutput) {
1425                                 EcOcRegOcModeHip |=
1426                                     B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1427                         } else
1428                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1429                         EcOcRegOcModeLop |=
1430                             EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1431                 } else {
1432                         EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1433
1434                         if (bEnableOutput)
1435                                 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1436                         else
1437                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1438
1439                         /* Don't Insert RS Byte */
1440                         if (state->insert_rs_byte) {
1441                                 EcOcRegOcModeLop &=
1442                                     (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1443                                 EcOcRegOcModeHip &=
1444                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1445                                 EcOcRegOcModeHip |=
1446                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1447                         } else {
1448                                 EcOcRegOcModeLop |=
1449                                     EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1450                                 EcOcRegOcModeHip &=
1451                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1452                                 EcOcRegOcModeHip |=
1453                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1454                         }
1455
1456                         /* Mode = Parallel */
1457                         if (state->enable_parallel)
1458                                 EcOcRegOcModeLop &=
1459                                     (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1460                         else
1461                                 EcOcRegOcModeLop |=
1462                                     EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1463                 }
1464                 /* Invert Data */
1465                 /* EcOcRegIprInvMpg |= 0x00FF; */
1466                 EcOcRegIprInvMpg &= (~(0x00FF));
1467
1468                 /* Invert Error ( we don't use the pin ) */
1469                 /*  EcOcRegIprInvMpg |= 0x0100; */
1470                 EcOcRegIprInvMpg &= (~(0x0100));
1471
1472                 /* Invert Start ( we don't use the pin ) */
1473                 /* EcOcRegIprInvMpg |= 0x0200; */
1474                 EcOcRegIprInvMpg &= (~(0x0200));
1475
1476                 /* Invert Valid ( we don't use the pin ) */
1477                 /* EcOcRegIprInvMpg |= 0x0400; */
1478                 EcOcRegIprInvMpg &= (~(0x0400));
1479
1480                 /* Invert Clock */
1481                 /* EcOcRegIprInvMpg |= 0x0800; */
1482                 EcOcRegIprInvMpg &= (~(0x0800));
1483
1484                 /* EcOcRegOcModeLop =0x05; */
1485                 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1486                 if (status < 0)
1487                         break;
1488                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1489                 if (status < 0)
1490                         break;
1491                 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1492                 if (status < 0)
1493                         break;
1494                 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1495                 if (status < 0)
1496                         break;
1497         } while (0);
1498         return status;
1499 }
1500
1501 static int SetDeviceTypeId(struct drxd_state *state)
1502 {
1503         int status = 0;
1504         u16 deviceId = 0;
1505
1506         do {
1507                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1508                 if (status < 0)
1509                         break;
1510                 /* TODO: why twice? */
1511                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1512                 if (status < 0)
1513                         break;
1514                 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1515
1516                 state->type_A = 0;
1517                 state->PGA = 0;
1518                 state->diversity = 0;
1519                 if (deviceId == 0) {    /* on A2 only 3975 available */
1520                         state->type_A = 1;
1521                         printk(KERN_INFO "DRX3975D-A2\n");
1522                 } else {
1523                         deviceId >>= 12;
1524                         printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1525                         switch (deviceId) {
1526                         case 4:
1527                                 state->diversity = 1;
1528                         case 3:
1529                         case 7:
1530                                 state->PGA = 1;
1531                                 break;
1532                         case 6:
1533                                 state->diversity = 1;
1534                         case 5:
1535                         case 8:
1536                                 break;
1537                         default:
1538                                 status = -1;
1539                                 break;
1540                         }
1541                 }
1542         } while (0);
1543
1544         if (status < 0)
1545                 return status;
1546
1547         /* Init Table selection */
1548         state->m_InitAtomicRead = DRXD_InitAtomicRead;
1549         state->m_InitSC = DRXD_InitSC;
1550         state->m_ResetECRAM = DRXD_ResetECRAM;
1551         if (state->type_A) {
1552                 state->m_ResetCEFR = DRXD_ResetCEFR;
1553                 state->m_InitFE_1 = DRXD_InitFEA2_1;
1554                 state->m_InitFE_2 = DRXD_InitFEA2_2;
1555                 state->m_InitCP = DRXD_InitCPA2;
1556                 state->m_InitCE = DRXD_InitCEA2;
1557                 state->m_InitEQ = DRXD_InitEQA2;
1558                 state->m_InitEC = DRXD_InitECA2;
1559                 if (load_firmware(state, DRX_FW_FILENAME_A2))
1560                         return -EIO;
1561         } else {
1562                 state->m_ResetCEFR = NULL;
1563                 state->m_InitFE_1 = DRXD_InitFEB1_1;
1564                 state->m_InitFE_2 = DRXD_InitFEB1_2;
1565                 state->m_InitCP = DRXD_InitCPB1;
1566                 state->m_InitCE = DRXD_InitCEB1;
1567                 state->m_InitEQ = DRXD_InitEQB1;
1568                 state->m_InitEC = DRXD_InitECB1;
1569                 if (load_firmware(state, DRX_FW_FILENAME_B1))
1570                         return -EIO;
1571         }
1572         if (state->diversity) {
1573                 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1574                 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1575                 state->m_DisableDiversity = DRXD_DisableDiversity;
1576                 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1577                 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1578                 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1579                 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1580         } else {
1581                 state->m_InitDiversityFront = NULL;
1582                 state->m_InitDiversityEnd = NULL;
1583                 state->m_DisableDiversity = NULL;
1584                 state->m_StartDiversityFront = NULL;
1585                 state->m_StartDiversityEnd = NULL;
1586                 state->m_DiversityDelay8MHZ = NULL;
1587                 state->m_DiversityDelay6MHZ = NULL;
1588         }
1589
1590         return status;
1591 }
1592
1593 static int CorrectSysClockDeviation(struct drxd_state *state)
1594 {
1595         int status;
1596         s32 incr = 0;
1597         s32 nomincr = 0;
1598         u32 bandwidth = 0;
1599         u32 sysClockInHz = 0;
1600         u32 sysClockFreq = 0;   /* in kHz */
1601         s16 oscClockDeviation;
1602         s16 Diff;
1603
1604         do {
1605                 /* Retrieve bandwidth and incr, sanity check */
1606
1607                 /* These accesses should be AtomicReadReg32, but that
1608                    causes trouble (at least for diversity */
1609                 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1610                 if (status < 0)
1611                         break;
1612                 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1613                 if (status < 0)
1614                         break;
1615
1616                 if (state->type_A) {
1617                         if ((nomincr - incr < -500) || (nomincr - incr > 500))
1618                                 break;
1619                 } else {
1620                         if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1621                                 break;
1622                 }
1623
1624                 switch (state->props.bandwidth_hz) {
1625                 case 8000000:
1626                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1627                         break;
1628                 case 7000000:
1629                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1630                         break;
1631                 case 6000000:
1632                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1633                         break;
1634                 default:
1635                         return -1;
1636                         break;
1637                 }
1638
1639                 /* Compute new sysclock value
1640                    sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1641                 incr += (1 << 23);
1642                 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1643                 sysClockFreq = (u32) (sysClockInHz / 1000);
1644                 /* rounding */
1645                 if ((sysClockInHz % 1000) > 500)
1646                         sysClockFreq++;
1647
1648                 /* Compute clock deviation in ppm */
1649                 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1650                                              (s32)
1651                                              (state->expected_sys_clock_freq)) *
1652                                             1000000L) /
1653                                            (s32)
1654                                            (state->expected_sys_clock_freq));
1655
1656                 Diff = oscClockDeviation - state->osc_clock_deviation;
1657                 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1658                 if (Diff >= -200 && Diff <= 200) {
1659                         state->sys_clock_freq = (u16) sysClockFreq;
1660                         if (oscClockDeviation != state->osc_clock_deviation) {
1661                                 if (state->config.osc_deviation) {
1662                                         state->config.osc_deviation(state->priv,
1663                                                                     oscClockDeviation,
1664                                                                     1);
1665                                         state->osc_clock_deviation =
1666                                             oscClockDeviation;
1667                                 }
1668                         }
1669                         /* switch OFF SRMM scan in SC */
1670                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1671                         if (status < 0)
1672                                 break;
1673                         /* overrule FE_IF internal value for
1674                            proper re-locking */
1675                         status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1676                         if (status < 0)
1677                                 break;
1678                         state->cscd_state = CSCD_SAVED;
1679                 }
1680         } while (0);
1681
1682         return status;
1683 }
1684
1685 static int DRX_Stop(struct drxd_state *state)
1686 {
1687         int status;
1688
1689         if (state->drxd_state != DRXD_STARTED)
1690                 return 0;
1691
1692         do {
1693                 if (state->cscd_state != CSCD_SAVED) {
1694                         u32 lock;
1695                         status = DRX_GetLockStatus(state, &lock);
1696                         if (status < 0)
1697                                 break;
1698                 }
1699
1700                 status = StopOC(state);
1701                 if (status < 0)
1702                         break;
1703
1704                 state->drxd_state = DRXD_STOPPED;
1705
1706                 status = ConfigureMPEGOutput(state, 0);
1707                 if (status < 0)
1708                         break;
1709
1710                 if (state->type_A) {
1711                         /* Stop relevant processors off the device */
1712                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1713                         if (status < 0)
1714                                 break;
1715
1716                         status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1717                         if (status < 0)
1718                                 break;
1719                         status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1720                         if (status < 0)
1721                                 break;
1722                 } else {
1723                         /* Stop all processors except HI & CC & FE */
1724                         status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1725                         if (status < 0)
1726                                 break;
1727                         status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1728                         if (status < 0)
1729                                 break;
1730                         status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1731                         if (status < 0)
1732                                 break;
1733                         status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1734                         if (status < 0)
1735                                 break;
1736                         status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1737                         if (status < 0)
1738                                 break;
1739                         status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1740                         if (status < 0)
1741                                 break;
1742                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1743                         if (status < 0)
1744                                 break;
1745                 }
1746
1747         } while (0);
1748         return status;
1749 }
1750
1751 #if 0   /* Currently unused */
1752 static int SetOperationMode(struct drxd_state *state, int oMode)
1753 {
1754         int status;
1755
1756         do {
1757                 if (state->drxd_state != DRXD_STOPPED) {
1758                         status = -1;
1759                         break;
1760                 }
1761
1762                 if (oMode == state->operation_mode) {
1763                         status = 0;
1764                         break;
1765                 }
1766
1767                 if (oMode != OM_Default && !state->diversity) {
1768                         status = -1;
1769                         break;
1770                 }
1771
1772                 switch (oMode) {
1773                 case OM_DVBT_Diversity_Front:
1774                         status = WriteTable(state, state->m_InitDiversityFront);
1775                         break;
1776                 case OM_DVBT_Diversity_End:
1777                         status = WriteTable(state, state->m_InitDiversityEnd);
1778                         break;
1779                 case OM_Default:
1780                         /* We need to check how to
1781                            get DRXD out of diversity */
1782                 default:
1783                         status = WriteTable(state, state->m_DisableDiversity);
1784                         break;
1785                 }
1786         } while (0);
1787
1788         if (!status)
1789                 state->operation_mode = oMode;
1790         return status;
1791 }
1792 #endif
1793
1794 static int StartDiversity(struct drxd_state *state)
1795 {
1796         int status = 0;
1797         u16 rcControl;
1798
1799         do {
1800                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1801                         status = WriteTable(state, state->m_StartDiversityFront);
1802                         if (status < 0)
1803                                 break;
1804                 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1805                         status = WriteTable(state, state->m_StartDiversityEnd);
1806                         if (status < 0)
1807                                 break;
1808                         if (state->props.bandwidth_hz == 8000000) {
1809                                 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1810                                 if (status < 0)
1811                                         break;
1812                         } else {
1813                                 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1814                                 if (status < 0)
1815                                         break;
1816                         }
1817
1818                         status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1819                         if (status < 0)
1820                                 break;
1821                         rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1822                         rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1823                             /*  combining enabled */
1824                             B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1825                             B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1826                             B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1827                         status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1828                         if (status < 0)
1829                                 break;
1830                 }
1831         } while (0);
1832         return status;
1833 }
1834
1835 static int SetFrequencyShift(struct drxd_state *state,
1836                              u32 offsetFreq, int channelMirrored)
1837 {
1838         int negativeShift = (state->tuner_mirrors == channelMirrored);
1839
1840         /* Handle all mirroring
1841          *
1842          * Note: ADC mirroring (aliasing) is implictly handled by limiting
1843          * feFsRegAddInc to 28 bits below
1844          * (if the result before masking is more than 28 bits, this means
1845          *  that the ADC is mirroring.
1846          * The masking is in fact the aliasing of the ADC)
1847          *
1848          */
1849
1850         /* Compute register value, unsigned computation */
1851         state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1852                                          offsetFreq,
1853                                          1 << 28, state->sys_clock_freq);
1854         /* Remove integer part */
1855         state->fe_fs_add_incr &= 0x0FFFFFFFL;
1856         if (negativeShift)
1857                 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1858
1859         /* Save the frequency shift without tunerOffset compensation
1860            for CtrlGetChannel. */
1861         state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1862                                              1 << 28, state->sys_clock_freq);
1863         /* Remove integer part */
1864         state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1865         if (negativeShift)
1866                 state->org_fe_fs_add_incr = ((1L << 28) -
1867                                              state->org_fe_fs_add_incr);
1868
1869         return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1870                        state->fe_fs_add_incr, 0);
1871 }
1872
1873 static int SetCfgNoiseCalibration(struct drxd_state *state,
1874                                   struct SNoiseCal *noiseCal)
1875 {
1876         u16 beOptEna;
1877         int status = 0;
1878
1879         do {
1880                 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1881                 if (status < 0)
1882                         break;
1883                 if (noiseCal->cpOpt) {
1884                         beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1885                 } else {
1886                         beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1887                         status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1888                         if (status < 0)
1889                                 break;
1890                 }
1891                 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1892                 if (status < 0)
1893                         break;
1894
1895                 if (!state->type_A) {
1896                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1897                         if (status < 0)
1898                                 break;
1899                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1900                         if (status < 0)
1901                                 break;
1902                 }
1903         } while (0);
1904
1905         return status;
1906 }
1907
1908 static int DRX_Start(struct drxd_state *state, s32 off)
1909 {
1910         struct dtv_frontend_properties *p = &state->props;
1911         int status;
1912
1913         u16 transmissionParams = 0;
1914         u16 operationMode = 0;
1915         u16 qpskTdTpsPwr = 0;
1916         u16 qam16TdTpsPwr = 0;
1917         u16 qam64TdTpsPwr = 0;
1918         u32 feIfIncr = 0;
1919         u32 bandwidth = 0;
1920         int mirrorFreqSpect;
1921
1922         u16 qpskSnCeGain = 0;
1923         u16 qam16SnCeGain = 0;
1924         u16 qam64SnCeGain = 0;
1925         u16 qpskIsGainMan = 0;
1926         u16 qam16IsGainMan = 0;
1927         u16 qam64IsGainMan = 0;
1928         u16 qpskIsGainExp = 0;
1929         u16 qam16IsGainExp = 0;
1930         u16 qam64IsGainExp = 0;
1931         u16 bandwidthParam = 0;
1932
1933         if (off < 0)
1934                 off = (off - 500) / 1000;
1935         else
1936                 off = (off + 500) / 1000;
1937
1938         do {
1939                 if (state->drxd_state != DRXD_STOPPED)
1940                         return -1;
1941                 status = ResetECOD(state);
1942                 if (status < 0)
1943                         break;
1944                 if (state->type_A) {
1945                         status = InitSC(state);
1946                         if (status < 0)
1947                                 break;
1948                 } else {
1949                         status = InitFT(state);
1950                         if (status < 0)
1951                                 break;
1952                         status = InitCP(state);
1953                         if (status < 0)
1954                                 break;
1955                         status = InitCE(state);
1956                         if (status < 0)
1957                                 break;
1958                         status = InitEQ(state);
1959                         if (status < 0)
1960                                 break;
1961                         status = InitSC(state);
1962                         if (status < 0)
1963                                 break;
1964                 }
1965
1966                 /* Restore current IF & RF AGC settings */
1967
1968                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1969                 if (status < 0)
1970                         break;
1971                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1972                 if (status < 0)
1973                         break;
1974
1975                 mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1976
1977                 switch (p->transmission_mode) {
1978                 default:        /* Not set, detect it automatically */
1979                         operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1980                         /* fall through , try first guess DRX_FFTMODE_8K */
1981                 case TRANSMISSION_MODE_8K:
1982                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1983                         if (state->type_A) {
1984                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1985                                 if (status < 0)
1986                                         break;
1987                                 qpskSnCeGain = 99;
1988                                 qam16SnCeGain = 83;
1989                                 qam64SnCeGain = 67;
1990                         }
1991                         break;
1992                 case TRANSMISSION_MODE_2K:
1993                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1994                         if (state->type_A) {
1995                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1996                                 if (status < 0)
1997                                         break;
1998                                 qpskSnCeGain = 97;
1999                                 qam16SnCeGain = 71;
2000                                 qam64SnCeGain = 65;
2001                         }
2002                         break;
2003                 }
2004
2005                 switch (p->guard_interval) {
2006                 case GUARD_INTERVAL_1_4:
2007                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2008                         break;
2009                 case GUARD_INTERVAL_1_8:
2010                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2011                         break;
2012                 case GUARD_INTERVAL_1_16:
2013                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2014                         break;
2015                 case GUARD_INTERVAL_1_32:
2016                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2017                         break;
2018                 default:        /* Not set, detect it automatically */
2019                         operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2020                         /* try first guess 1/4 */
2021                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2022                         break;
2023                 }
2024
2025                 switch (p->hierarchy) {
2026                 case HIERARCHY_1:
2027                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2028                         if (state->type_A) {
2029                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2030                                 if (status < 0)
2031                                         break;
2032                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2033                                 if (status < 0)
2034                                         break;
2035
2036                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2037                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2038                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2039
2040                                 qpskIsGainMan =
2041                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2042                                 qam16IsGainMan =
2043                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2044                                 qam64IsGainMan =
2045                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2046
2047                                 qpskIsGainExp =
2048                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2049                                 qam16IsGainExp =
2050                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2051                                 qam64IsGainExp =
2052                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2053                         }
2054                         break;
2055
2056                 case HIERARCHY_2:
2057                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2058                         if (state->type_A) {
2059                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2060                                 if (status < 0)
2061                                         break;
2062                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2063                                 if (status < 0)
2064                                         break;
2065
2066                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2067                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2068                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2069
2070                                 qpskIsGainMan =
2071                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2072                                 qam16IsGainMan =
2073                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2074                                 qam64IsGainMan =
2075                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2076
2077                                 qpskIsGainExp =
2078                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2079                                 qam16IsGainExp =
2080                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2081                                 qam64IsGainExp =
2082                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2083                         }
2084                         break;
2085                 case HIERARCHY_4:
2086                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2087                         if (state->type_A) {
2088                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2089                                 if (status < 0)
2090                                         break;
2091                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2092                                 if (status < 0)
2093                                         break;
2094
2095                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2096                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2097                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2098
2099                                 qpskIsGainMan =
2100                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2101                                 qam16IsGainMan =
2102                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2103                                 qam64IsGainMan =
2104                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2105
2106                                 qpskIsGainExp =
2107                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2108                                 qam16IsGainExp =
2109                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2110                                 qam64IsGainExp =
2111                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2112                         }
2113                         break;
2114                 case HIERARCHY_AUTO:
2115                 default:
2116                         /* Not set, detect it automatically, start with none */
2117                         operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2118                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2119                         if (state->type_A) {
2120                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2121                                 if (status < 0)
2122                                         break;
2123                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2124                                 if (status < 0)
2125                                         break;
2126
2127                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2128                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2129                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2130
2131                                 qpskIsGainMan =
2132                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2133                                 qam16IsGainMan =
2134                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2135                                 qam64IsGainMan =
2136                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2137
2138                                 qpskIsGainExp =
2139                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2140                                 qam16IsGainExp =
2141                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2142                                 qam64IsGainExp =
2143                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2144                         }
2145                         break;
2146                 }
2147                 status = status;
2148                 if (status < 0)
2149                         break;
2150
2151                 switch (p->modulation) {
2152                 default:
2153                         operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2154                         /* fall through , try first guess
2155                            DRX_CONSTELLATION_QAM64 */
2156                 case QAM_64:
2157                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2158                         if (state->type_A) {
2159                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2160                                 if (status < 0)
2161                                         break;
2162                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2163                                 if (status < 0)
2164                                         break;
2165                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2166                                 if (status < 0)
2167                                         break;
2168                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2169                                 if (status < 0)
2170                                         break;
2171                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2172                                 if (status < 0)
2173                                         break;
2174
2175                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2176                                 if (status < 0)
2177                                         break;
2178                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2179                                 if (status < 0)
2180                                         break;
2181                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2182                                 if (status < 0)
2183                                         break;
2184                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2185                                 if (status < 0)
2186                                         break;
2187                         }
2188                         break;
2189                 case QPSK:
2190                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2191                         if (state->type_A) {
2192                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2193                                 if (status < 0)
2194                                         break;
2195                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2196                                 if (status < 0)
2197                                         break;
2198                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2199                                 if (status < 0)
2200                                         break;
2201                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2202                                 if (status < 0)
2203                                         break;
2204                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2205                                 if (status < 0)
2206                                         break;
2207
2208                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2209                                 if (status < 0)
2210                                         break;
2211                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2212                                 if (status < 0)
2213                                         break;
2214                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2215                                 if (status < 0)
2216                                         break;
2217                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2218                                 if (status < 0)
2219                                         break;
2220                         }
2221                         break;
2222
2223                 case QAM_16:
2224                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2225                         if (state->type_A) {
2226                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2227                                 if (status < 0)
2228                                         break;
2229                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2230                                 if (status < 0)
2231                                         break;
2232                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2233                                 if (status < 0)
2234                                         break;
2235                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2236                                 if (status < 0)
2237                                         break;
2238                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2239                                 if (status < 0)
2240                                         break;
2241
2242                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2243                                 if (status < 0)
2244                                         break;
2245                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2246                                 if (status < 0)
2247                                         break;
2248                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2249                                 if (status < 0)
2250                                         break;
2251                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2252                                 if (status < 0)
2253                                         break;
2254                         }
2255                         break;
2256
2257                 }
2258                 status = status;
2259                 if (status < 0)
2260                         break;
2261
2262                 switch (DRX_CHANNEL_HIGH) {
2263                 default:
2264                 case DRX_CHANNEL_AUTO:
2265                 case DRX_CHANNEL_LOW:
2266                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2267                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2268                         if (status < 0)
2269                                 break;
2270                         break;
2271                 case DRX_CHANNEL_HIGH:
2272                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2273                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2274                         if (status < 0)
2275                                 break;
2276                         break;
2277
2278                 }
2279
2280                 switch (p->code_rate_HP) {
2281                 case FEC_1_2:
2282                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2283                         if (state->type_A) {
2284                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2285                                 if (status < 0)
2286                                         break;
2287                         }
2288                         break;
2289                 default:
2290                         operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2291                 case FEC_2_3:
2292                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2293                         if (state->type_A) {
2294                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2295                                 if (status < 0)
2296                                         break;
2297                         }
2298                         break;
2299                 case FEC_3_4:
2300                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2301                         if (state->type_A) {
2302                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2303                                 if (status < 0)
2304                                         break;
2305                         }
2306                         break;
2307                 case FEC_5_6:
2308                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2309                         if (state->type_A) {
2310                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2311                                 if (status < 0)
2312                                         break;
2313                         }
2314                         break;
2315                 case FEC_7_8:
2316                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2317                         if (state->type_A) {
2318                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2319                                 if (status < 0)
2320                                         break;
2321                         }
2322                         break;
2323                 }
2324                 status = status;
2325                 if (status < 0)
2326                         break;
2327
2328                 /* First determine real bandwidth (Hz) */
2329                 /* Also set delay for impulse noise cruncher (only A2) */
2330                 /* Also set parameters for EC_OC fix, note
2331                    EC_OC_REG_TMD_HIL_MAR is changed
2332                    by SC for fix for some 8K,1/8 guard but is restored by
2333                    InitEC and ResetEC
2334                    functions */
2335                 switch (p->bandwidth_hz) {
2336                 case 0:
2337                         p->bandwidth_hz = 8000000;
2338                         /* fall through */
2339                 case 8000000:
2340                         /* (64/7)*(8/8)*1000000 */
2341                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2342
2343                         bandwidthParam = 0;
2344                         status = Write16(state,
2345                                          FE_AG_REG_IND_DEL__A, 50, 0x0000);
2346                         break;
2347                 case 7000000:
2348                         /* (64/7)*(7/8)*1000000 */
2349                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2350                         bandwidthParam = 0x4807;        /*binary:0100 1000 0000 0111 */
2351                         status = Write16(state,
2352                                          FE_AG_REG_IND_DEL__A, 59, 0x0000);
2353                         break;
2354                 case 6000000:
2355                         /* (64/7)*(6/8)*1000000 */
2356                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2357                         bandwidthParam = 0x0F07;        /*binary: 0000 1111 0000 0111 */
2358                         status = Write16(state,
2359                                          FE_AG_REG_IND_DEL__A, 71, 0x0000);
2360                         break;
2361                 default:
2362                         status = -EINVAL;
2363                 }
2364                 if (status < 0)
2365                         break;
2366
2367                 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2368                 if (status < 0)
2369                         break;
2370
2371                 {
2372                         u16 sc_config;
2373                         status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2374                         if (status < 0)
2375                                 break;
2376
2377                         /* enable SLAVE mode in 2k 1/32 to
2378                            prevent timing change glitches */
2379                         if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2380                             (p->guard_interval == GUARD_INTERVAL_1_32)) {
2381                                 /* enable slave */
2382                                 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2383                         } else {
2384                                 /* disable slave */
2385                                 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2386                         }
2387                         status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2388                         if (status < 0)
2389                                 break;
2390                 }
2391
2392                 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2393                 if (status < 0)
2394                         break;
2395
2396                 if (state->cscd_state == CSCD_INIT) {
2397                         /* switch on SRMM scan in SC */
2398                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2399                         if (status < 0)
2400                                 break;
2401 /*            CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2402                         state->cscd_state = CSCD_SET;
2403                 }
2404
2405                 /* Now compute FE_IF_REG_INCR */
2406                 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2407                    ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2408                 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2409                                     (1ULL << 21), bandwidth) - (1 << 23);
2410                 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2411                 if (status < 0)
2412                         break;
2413                 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2414                 if (status < 0)
2415                         break;
2416                 /* Bandwidth setting done */
2417
2418                 /* Mirror & frequency offset */
2419                 SetFrequencyShift(state, off, mirrorFreqSpect);
2420
2421                 /* Start SC, write channel settings to SC */
2422
2423                 /* Enable SC after setting all other parameters */
2424                 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2425                 if (status < 0)
2426                         break;
2427                 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2428                 if (status < 0)
2429                         break;
2430
2431                 /* Write SC parameter registers, operation mode */
2432 #if 1
2433                 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2434                                  SC_RA_RAM_OP_AUTO_GUARD__M |
2435                                  SC_RA_RAM_OP_AUTO_CONST__M |
2436                                  SC_RA_RAM_OP_AUTO_HIER__M |
2437                                  SC_RA_RAM_OP_AUTO_RATE__M);
2438 #endif
2439                 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2440                 if (status < 0)
2441                         break;
2442
2443                 /* Start correct processes to get in lock */
2444                 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2445                 if (status < 0)
2446                         break;
2447
2448                 status = StartOC(state);
2449                 if (status < 0)
2450                         break;
2451
2452                 if (state->operation_mode != OM_Default) {
2453                         status = StartDiversity(state);
2454                         if (status < 0)
2455                                 break;
2456                 }
2457
2458                 state->drxd_state = DRXD_STARTED;
2459         } while (0);
2460
2461         return status;
2462 }
2463
2464 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2465 {
2466         u32 ulRfAgcOutputLevel = 0xffffffff;
2467         u32 ulRfAgcSettleLevel = 528;   /* Optimum value for MT2060 */
2468         u32 ulRfAgcMinLevel = 0;        /* Currently unused */
2469         u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2470         u32 ulRfAgcSpeed = 0;   /* Currently unused */
2471         u32 ulRfAgcMode = 0;    /*2;   Off */
2472         u32 ulRfAgcR1 = 820;
2473         u32 ulRfAgcR2 = 2200;
2474         u32 ulRfAgcR3 = 150;
2475         u32 ulIfAgcMode = 0;    /* Auto */
2476         u32 ulIfAgcOutputLevel = 0xffffffff;
2477         u32 ulIfAgcSettleLevel = 0xffffffff;
2478         u32 ulIfAgcMinLevel = 0xffffffff;
2479         u32 ulIfAgcMaxLevel = 0xffffffff;
2480         u32 ulIfAgcSpeed = 0xffffffff;
2481         u32 ulIfAgcR1 = 820;
2482         u32 ulIfAgcR2 = 2200;
2483         u32 ulIfAgcR3 = 150;
2484         u32 ulClock = state->config.clock;
2485         u32 ulSerialMode = 0;
2486         u32 ulEcOcRegOcModeLop = 4;     /* Dynamic DTO source */
2487         u32 ulHiI2cDelay = HI_I2C_DELAY;
2488         u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2489         u32 ulHiI2cPatch = 0;
2490         u32 ulEnvironment = APPENV_PORTABLE;
2491         u32 ulEnvironmentDiversity = APPENV_MOBILE;
2492         u32 ulIFFilter = IFFILTER_SAW;
2493
2494         state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2495         state->if_agc_cfg.outputLevel = 0;
2496         state->if_agc_cfg.settleLevel = 140;
2497         state->if_agc_cfg.minOutputLevel = 0;
2498         state->if_agc_cfg.maxOutputLevel = 1023;
2499         state->if_agc_cfg.speed = 904;
2500
2501         if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2502                 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2503                 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2504         }
2505
2506         if (ulIfAgcMode == 0 &&
2507             ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2508             ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2509             ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2510             ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2511                 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2512                 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2513                 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2514                 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2515                 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2516         }
2517
2518         state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2519         state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2520         state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2521
2522         state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2523         state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2524         state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2525
2526         state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2527         /* rest of the RFAgcCfg structure currently unused */
2528         if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2529                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2530                 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2531         }
2532
2533         if (ulRfAgcMode == 0 &&
2534             ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2535             ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2536             ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2537             ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2538                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2539                 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2540                 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2541                 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2542                 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2543         }
2544
2545         if (ulRfAgcMode == 2)
2546                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2547
2548         if (ulEnvironment <= 2)
2549                 state->app_env_default = (enum app_env)
2550                     (ulEnvironment);
2551         if (ulEnvironmentDiversity <= 2)
2552                 state->app_env_diversity = (enum app_env)
2553                     (ulEnvironmentDiversity);
2554
2555         if (ulIFFilter == IFFILTER_DISCRETE) {
2556                 /* discrete filter */
2557                 state->noise_cal.cpOpt = 0;
2558                 state->noise_cal.cpNexpOfs = 40;
2559                 state->noise_cal.tdCal2k = -40;
2560                 state->noise_cal.tdCal8k = -24;
2561         } else {
2562                 /* SAW filter */
2563                 state->noise_cal.cpOpt = 1;
2564                 state->noise_cal.cpNexpOfs = 0;
2565                 state->noise_cal.tdCal2k = -21;
2566                 state->noise_cal.tdCal8k = -24;
2567         }
2568         state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2569
2570         state->chip_adr = (state->config.demod_address << 1) | 1;
2571         switch (ulHiI2cPatch) {
2572         case 1:
2573                 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2574                 break;
2575         case 3:
2576                 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2577                 break;
2578         default:
2579                 state->m_HiI2cPatch = NULL;
2580         }
2581
2582         /* modify tuner and clock attributes */
2583         state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2584         /* expected system clock frequency in kHz */
2585         state->expected_sys_clock_freq = 48000;
2586         /* real system clock frequency in kHz */
2587         state->sys_clock_freq = 48000;
2588         state->osc_clock_freq = (u16) ulClock;
2589         state->osc_clock_deviation = 0;
2590         state->cscd_state = CSCD_INIT;
2591         state->drxd_state = DRXD_UNINITIALIZED;
2592
2593         state->PGA = 0;
2594         state->type_A = 0;
2595         state->tuner_mirrors = 0;
2596
2597         /* modify MPEG output attributes */
2598         state->insert_rs_byte = state->config.insert_rs_byte;
2599         state->enable_parallel = (ulSerialMode != 1);
2600
2601         /* Timing div, 250ns/Psys */
2602         /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2603
2604         state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2605                                           ulHiI2cDelay) / 1000;
2606         /* Bridge delay, uses oscilator clock */
2607         /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2608         state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2609                                             ulHiI2cBridgeDelay) / 1000;
2610
2611         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2612         /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2613         state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2614         return 0;
2615 }
2616
2617 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2618 {
2619         int status = 0;
2620         u32 driverVersion;
2621
2622         if (state->init_done)
2623                 return 0;
2624
2625         CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2626
2627         do {
2628                 state->operation_mode = OM_Default;
2629
2630                 status = SetDeviceTypeId(state);
2631                 if (status < 0)
2632                         break;
2633
2634                 /* Apply I2c address patch to B1 */
2635                 if (!state->type_A && state->m_HiI2cPatch != NULL)
2636                         status = WriteTable(state, state->m_HiI2cPatch);
2637                         if (status < 0)
2638                                 break;
2639
2640                 if (state->type_A) {
2641                         /* HI firmware patch for UIO readout,
2642                            avoid clearing of result register */
2643                         status = Write16(state, 0x43012D, 0x047f, 0);
2644                         if (status < 0)
2645                                 break;
2646                 }
2647
2648                 status = HI_ResetCommand(state);
2649                 if (status < 0)
2650                         break;
2651
2652                 status = StopAllProcessors(state);
2653                 if (status < 0)
2654                         break;
2655                 status = InitCC(state);
2656                 if (status < 0)
2657                         break;
2658
2659                 state->osc_clock_deviation = 0;
2660
2661                 if (state->config.osc_deviation)
2662                         state->osc_clock_deviation =
2663                             state->config.osc_deviation(state->priv, 0, 0);
2664                 {
2665                         /* Handle clock deviation */
2666                         s32 devB;
2667                         s32 devA = (s32) (state->osc_clock_deviation) *
2668                             (s32) (state->expected_sys_clock_freq);
2669                         /* deviation in kHz */
2670                         s32 deviation = (devA / (1000000L));
2671                         /* rounding, signed */
2672                         if (devA > 0)
2673                                 devB = (2);
2674                         else
2675                                 devB = (-2);
2676                         if ((devB * (devA % 1000000L) > 1000000L)) {
2677                                 /* add +1 or -1 */
2678                                 deviation += (devB / 2);
2679                         }
2680
2681                         state->sys_clock_freq =
2682                             (u16) ((state->expected_sys_clock_freq) +
2683                                    deviation);
2684                 }
2685                 status = InitHI(state);
2686                 if (status < 0)
2687                         break;
2688                 status = InitAtomicRead(state);
2689                 if (status < 0)
2690                         break;
2691
2692                 status = EnableAndResetMB(state);
2693                 if (status < 0)
2694                         break;
2695                 if (state->type_A)
2696                         status = ResetCEFR(state);
2697                         if (status < 0)
2698                                 break;
2699
2700                 if (fw) {
2701                         status = DownloadMicrocode(state, fw, fw_size);
2702                         if (status < 0)
2703                                 break;
2704                 } else {
2705                         status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2706                         if (status < 0)
2707                                 break;
2708                 }
2709
2710                 if (state->PGA) {
2711                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2712                         SetCfgPga(state, 0);    /* PGA = 0 dB */
2713                 } else {
2714                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2715                 }
2716
2717                 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2718
2719                 status = InitFE(state);
2720                 if (status < 0)
2721                         break;
2722                 status = InitFT(state);
2723                 if (status < 0)
2724                         break;
2725                 status = InitCP(state);
2726                 if (status < 0)
2727                         break;
2728                 status = InitCE(state);
2729                 if (status < 0)
2730                         break;
2731                 status = InitEQ(state);
2732                 if (status < 0)
2733                         break;
2734                 status = InitEC(state);
2735                 if (status < 0)
2736                         break;
2737                 status = InitSC(state);
2738                 if (status < 0)
2739                         break;
2740
2741                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2742                 if (status < 0)
2743                         break;
2744                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2745                 if (status < 0)
2746                         break;
2747
2748                 state->cscd_state = CSCD_INIT;
2749                 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2750                 if (status < 0)
2751                         break;
2752                 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2753                 if (status < 0)
2754                         break;
2755
2756                 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2757                                  (VERSION_MAJOR % 10)) << 24;
2758                 driverVersion += (((VERSION_MINOR / 10) << 4) +
2759                                   (VERSION_MINOR % 10)) << 16;
2760                 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2761                     ((VERSION_PATCH / 100) << 8) +
2762                     ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2763
2764                 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2765                 if (status < 0)
2766                         break;
2767
2768                 status = StopOC(state);
2769                 if (status < 0)
2770                         break;
2771
2772                 state->drxd_state = DRXD_STOPPED;
2773                 state->init_done = 1;
2774                 status = 0;
2775         } while (0);
2776         return status;
2777 }
2778
2779 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
2780 {
2781         DRX_GetLockStatus(state, pLockStatus);
2782
2783         /*if (*pLockStatus&DRX_LOCK_MPEG) */
2784         if (*pLockStatus & DRX_LOCK_FEC) {
2785                 ConfigureMPEGOutput(state, 1);
2786                 /* Get status again, in case we have MPEG lock now */
2787                 /*DRX_GetLockStatus(state, pLockStatus); */
2788         }
2789
2790         return 0;
2791 }
2792
2793 /****************************************************************************/
2794 /****************************************************************************/
2795 /****************************************************************************/
2796
2797 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2798 {
2799         struct drxd_state *state = fe->demodulator_priv;
2800         u32 value;
2801         int res;
2802
2803         res = ReadIFAgc(state, &value);
2804         if (res < 0)
2805                 *strength = 0;
2806         else
2807                 *strength = 0xffff - (value << 4);
2808         return 0;
2809 }
2810
2811 static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2812 {
2813         struct drxd_state *state = fe->demodulator_priv;
2814         u32 lock;
2815
2816         DRXD_status(state, &lock);
2817         *status = 0;
2818         /* No MPEG lock in V255 firmware, bug ? */
2819 #if 1
2820         if (lock & DRX_LOCK_MPEG)
2821                 *status |= FE_HAS_LOCK;
2822 #else
2823         if (lock & DRX_LOCK_FEC)
2824                 *status |= FE_HAS_LOCK;
2825 #endif
2826         if (lock & DRX_LOCK_FEC)
2827                 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2828         if (lock & DRX_LOCK_DEMOD)
2829                 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2830
2831         return 0;
2832 }
2833
2834 static int drxd_init(struct dvb_frontend *fe)
2835 {
2836         struct drxd_state *state = fe->demodulator_priv;
2837         int err = 0;
2838
2839 /*(DEBLOBBED)*/
2840         return DRXD_init(state, 0, 0);
2841
2842         err = DRXD_init(state, state->fw->data, state->fw->size);
2843         release_firmware(state->fw);
2844         return err;
2845 }
2846
2847 int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2848 {
2849         struct drxd_state *state = fe->demodulator_priv;
2850
2851         if (state->config.disable_i2c_gate_ctrl == 1)
2852                 return 0;
2853
2854         return DRX_ConfigureI2CBridge(state, onoff);
2855 }
2856 EXPORT_SYMBOL(drxd_config_i2c);
2857
2858 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2859                                   struct dvb_frontend_tune_settings *sets)
2860 {
2861         sets->min_delay_ms = 10000;
2862         sets->max_drift = 0;
2863         sets->step_size = 0;
2864         return 0;
2865 }
2866
2867 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2868 {
2869         *ber = 0;
2870         return 0;
2871 }
2872
2873 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2874 {
2875         *snr = 0;
2876         return 0;
2877 }
2878
2879 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2880 {
2881         *ucblocks = 0;
2882         return 0;
2883 }
2884
2885 static int drxd_sleep(struct dvb_frontend *fe)
2886 {
2887         struct drxd_state *state = fe->demodulator_priv;
2888
2889         ConfigureMPEGOutput(state, 0);
2890         return 0;
2891 }
2892
2893 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2894 {
2895         return drxd_config_i2c(fe, enable);
2896 }
2897
2898 static int drxd_set_frontend(struct dvb_frontend *fe)
2899 {
2900         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2901         struct drxd_state *state = fe->demodulator_priv;
2902         s32 off = 0;
2903
2904         state->props = *p;
2905         DRX_Stop(state);
2906
2907         if (fe->ops.tuner_ops.set_params) {
2908                 fe->ops.tuner_ops.set_params(fe);
2909                 if (fe->ops.i2c_gate_ctrl)
2910                         fe->ops.i2c_gate_ctrl(fe, 0);
2911         }
2912
2913         msleep(200);
2914
2915         return DRX_Start(state, off);
2916 }
2917
2918 static void drxd_release(struct dvb_frontend *fe)
2919 {
2920         struct drxd_state *state = fe->demodulator_priv;
2921
2922         kfree(state);
2923 }
2924
2925 static struct dvb_frontend_ops drxd_ops = {
2926         .delsys = { SYS_DVBT},
2927         .info = {
2928                  .name = "Micronas DRXD DVB-T",
2929                  .frequency_min = 47125000,
2930                  .frequency_max = 855250000,
2931                  .frequency_stepsize = 166667,
2932                  .frequency_tolerance = 0,
2933                  .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2934                  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2935                  FE_CAN_FEC_AUTO |
2936                  FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2937                  FE_CAN_QAM_AUTO |
2938                  FE_CAN_TRANSMISSION_MODE_AUTO |
2939                  FE_CAN_GUARD_INTERVAL_AUTO |
2940                  FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2941
2942         .release = drxd_release,
2943         .init = drxd_init,
2944         .sleep = drxd_sleep,
2945         .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2946
2947         .set_frontend = drxd_set_frontend,
2948         .get_tune_settings = drxd_get_tune_settings,
2949
2950         .read_status = drxd_read_status,
2951         .read_ber = drxd_read_ber,
2952         .read_signal_strength = drxd_read_signal_strength,
2953         .read_snr = drxd_read_snr,
2954         .read_ucblocks = drxd_read_ucblocks,
2955 };
2956
2957 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2958                                  void *priv, struct i2c_adapter *i2c,
2959                                  struct device *dev)
2960 {
2961         struct drxd_state *state = NULL;
2962
2963         state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2964         if (!state)
2965                 return NULL;
2966         memset(state, 0, sizeof(*state));
2967
2968         state->ops = drxd_ops;
2969         state->dev = dev;
2970         state->config = *config;
2971         state->i2c = i2c;
2972         state->priv = priv;
2973
2974         mutex_init(&state->mutex);
2975
2976         if (Read16(state, 0, 0, 0) < 0)
2977                 goto error;
2978
2979         state->frontend.ops = drxd_ops;
2980         state->frontend.demodulator_priv = state;
2981         ConfigureMPEGOutput(state, 0);
2982         /* add few initialization to allow gate control */
2983         CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2984         InitHI(state);
2985
2986         return &state->frontend;
2987
2988 error:
2989         printk(KERN_ERR "drxd: not found\n");
2990         kfree(state);
2991         return NULL;
2992 }
2993 EXPORT_SYMBOL(drxd_attach);
2994
2995 MODULE_DESCRIPTION("DRXD driver");
2996 MODULE_AUTHOR("Micronas");
2997 MODULE_LICENSE("GPL");