drivers/media/dvb-frontends/dib9000.c

   1 /*
   2  * Linux-DVB Driver for DiBcom's DiB9000 and demodulator-family.
   3  *
   4  * Copyright (C) 2005-10 DiBcom (http://www.dibcom.fr/)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License as
   8  *      published by the Free Software Foundation, version 2.
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/i2c.h>
  12 #include <linux/mutex.h>
  13
  14 #include "dvb_math.h"
  15 #include "dvb_frontend.h"
  16
  17 #include "dib9000.h"
  18 #include "dibx000_common.h"
  19
  20 static int debug;
  21 module_param(debug, int, 0644);
  22 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
  23
  24 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB9000: "); printk(args); printk("\n"); } } while (0)
  25 #define MAX_NUMBER_OF_FRONTENDS 6
  26
  27 struct i2c_device {
  28         struct i2c_adapter *i2c_adap;
  29         u8 i2c_addr;
  30         u8 *i2c_read_buffer;
  31         u8 *i2c_write_buffer;
  32 };
  33
  34 struct dib9000_pid_ctrl {
  35 #define DIB9000_PID_FILTER_CTRL 0
  36 #define DIB9000_PID_FILTER      1
  37         u8 cmd;
  38         u8 id;
  39         u16 pid;
  40         u8 onoff;
  41 };
  42
  43 struct dib9000_state {
  44         struct i2c_device i2c;
  45
  46         struct dibx000_i2c_master i2c_master;
  47         struct i2c_adapter tuner_adap;
  48         struct i2c_adapter component_bus;
  49
  50         u16 revision;
  51         u8 reg_offs;
  52
  53         enum frontend_tune_state tune_state;
  54         u32 status;
  55         struct dvb_frontend_parametersContext channel_status;
  56
  57         u8 fe_id;
  58
  59 #define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff
  60         u16 gpio_dir;
  61 #define DIB9000_GPIO_DEFAULT_VALUES     0x0000
  62         u16 gpio_val;
  63 #define DIB9000_GPIO_DEFAULT_PWM_POS    0xffff
  64         u16 gpio_pwm_pos;
  65
  66         union {                 /* common for all chips */
  67                 struct {
  68                         u8 mobile_mode:1;
  69                 } host;
  70
  71                 struct {
  72                         struct dib9000_fe_memory_map {
  73                                 u16 addr;
  74                                 u16 size;
  75                         } fe_mm[18];
  76                         u8 memcmd;
  77
  78                         struct mutex mbx_if_lock;       /* to protect read/write operations */
  79                         struct mutex mbx_lock;  /* to protect the whole mailbox handling */
  80
  81                         struct mutex mem_lock;  /* to protect the memory accesses */
  82                         struct mutex mem_mbx_lock;      /* to protect the memory-based mailbox */
  83
  84 #define MBX_MAX_WORDS (256 - 200 - 2)
  85 #define DIB9000_MSG_CACHE_SIZE 2
  86                         u16 message_cache[DIB9000_MSG_CACHE_SIZE][MBX_MAX_WORDS];
  87                         u8 fw_is_running;
  88                 } risc;
  89         } platform;
  90
  91         union {                 /* common for all platforms */
  92                 struct {
  93                         struct dib9000_config cfg;
  94                 } d9;
  95         } chip;
  96
  97         struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
  98         u16 component_bus_speed;
  99
 100         /* for the I2C transfer */
 101         struct i2c_msg msg[2];
 102         u8 i2c_write_buffer[255];
 103         u8 i2c_read_buffer[255];
 104         struct mutex demod_lock;
 105         u8 get_frontend_internal;
 106         struct dib9000_pid_ctrl pid_ctrl[10];
 107         s8 pid_ctrl_index; /* -1: empty list; -2: do not use the list */
 108 };
 109
 110 static const u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 111         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 112         0, 0, 0, 0, 0, 0, 0, 0
 113 };
 114
 115 enum dib9000_power_mode {
 116         DIB9000_POWER_ALL = 0,
 117
 118         DIB9000_POWER_NO,
 119         DIB9000_POWER_INTERF_ANALOG_AGC,
 120         DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
 121         DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD,
 122         DIB9000_POWER_INTERFACE_ONLY,
 123 };
 124
 125 enum dib9000_out_messages {
 126         OUT_MSG_HBM_ACK,
 127         OUT_MSG_HOST_BUF_FAIL,
 128         OUT_MSG_REQ_VERSION,
 129         OUT_MSG_BRIDGE_I2C_W,
 130         OUT_MSG_BRIDGE_I2C_R,
 131         OUT_MSG_BRIDGE_APB_W,
 132         OUT_MSG_BRIDGE_APB_R,
 133         OUT_MSG_SCAN_CHANNEL,
 134         OUT_MSG_MONIT_DEMOD,
 135         OUT_MSG_CONF_GPIO,
 136         OUT_MSG_DEBUG_HELP,
 137         OUT_MSG_SUBBAND_SEL,
 138         OUT_MSG_ENABLE_TIME_SLICE,
 139         OUT_MSG_FE_FW_DL,
 140         OUT_MSG_FE_CHANNEL_SEARCH,
 141         OUT_MSG_FE_CHANNEL_TUNE,
 142         OUT_MSG_FE_SLEEP,
 143         OUT_MSG_FE_SYNC,
 144         OUT_MSG_CTL_MONIT,
 145
 146         OUT_MSG_CONF_SVC,
 147         OUT_MSG_SET_HBM,
 148         OUT_MSG_INIT_DEMOD,
 149         OUT_MSG_ENABLE_DIVERSITY,
 150         OUT_MSG_SET_OUTPUT_MODE,
 151         OUT_MSG_SET_PRIORITARY_CHANNEL,
 152         OUT_MSG_ACK_FRG,
 153         OUT_MSG_INIT_PMU,
 154 };
 155
 156 enum dib9000_in_messages {
 157         IN_MSG_DATA,
 158         IN_MSG_FRAME_INFO,
 159         IN_MSG_CTL_MONIT,
 160         IN_MSG_ACK_FREE_ITEM,
 161         IN_MSG_DEBUG_BUF,
 162         IN_MSG_MPE_MONITOR,
 163         IN_MSG_RAWTS_MONITOR,
 164         IN_MSG_END_BRIDGE_I2C_RW,
 165         IN_MSG_END_BRIDGE_APB_RW,
 166         IN_MSG_VERSION,
 167         IN_MSG_END_OF_SCAN,
 168         IN_MSG_MONIT_DEMOD,
 169         IN_MSG_ERROR,
 170         IN_MSG_FE_FW_DL_DONE,
 171         IN_MSG_EVENT,
 172         IN_MSG_ACK_CHANGE_SVC,
 173         IN_MSG_HBM_PROF,
 174 };
 175
 176 /* memory_access requests */
 177 #define FE_MM_W_CHANNEL                   0
 178 #define FE_MM_W_FE_INFO                   1
 179 #define FE_MM_RW_SYNC                     2
 180
 181 #define FE_SYNC_CHANNEL          1
 182 #define FE_SYNC_W_GENERIC_MONIT  2
 183 #define FE_SYNC_COMPONENT_ACCESS 3
 184
 185 #define FE_MM_R_CHANNEL_SEARCH_STATE      3
 186 #define FE_MM_R_CHANNEL_UNION_CONTEXT     4
 187 #define FE_MM_R_FE_INFO                   5
 188 #define FE_MM_R_FE_MONITOR                6
 189
 190 #define FE_MM_W_CHANNEL_HEAD              7
 191 #define FE_MM_W_CHANNEL_UNION             8
 192 #define FE_MM_W_CHANNEL_CONTEXT           9
 193 #define FE_MM_R_CHANNEL_UNION            10
 194 #define FE_MM_R_CHANNEL_CONTEXT          11
 195 #define FE_MM_R_CHANNEL_TUNE_STATE       12
 196
 197 #define FE_MM_R_GENERIC_MONITORING_SIZE  13
 198 #define FE_MM_W_GENERIC_MONITORING           14
 199 #define FE_MM_R_GENERIC_MONITORING           15
 200
 201 #define FE_MM_W_COMPONENT_ACCESS         16
 202 #define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
 203 static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len);
 204 static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
 205
 206 static u16 to_fw_output_mode(u16 mode)
 207 {
 208         switch (mode) {
 209         case OUTMODE_HIGH_Z:
 210                 return 0;
 211         case OUTMODE_MPEG2_PAR_GATED_CLK:
 212                 return 4;
 213         case OUTMODE_MPEG2_PAR_CONT_CLK:
 214                 return 8;
 215         case OUTMODE_MPEG2_SERIAL:
 216                 return 16;
 217         case OUTMODE_DIVERSITY:
 218                 return 128;
 219         case OUTMODE_MPEG2_FIFO:
 220                 return 2;
 221         case OUTMODE_ANALOG_ADC:
 222                 return 1;
 223         default:
 224                 return 0;
 225         }
 226 }
 227
 228 static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 len, u16 attribute)
 229 {
 230         u32 chunk_size = 126;
 231         u32 l;
 232         int ret;
 233
 234         if (state->platform.risc.fw_is_running && (reg < 1024))
 235                 return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len);
 236
 237         memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
 238         state->msg[0].addr = state->i2c.i2c_addr >> 1;
 239         state->msg[0].flags = 0;
 240         state->msg[0].buf = state->i2c_write_buffer;
 241         state->msg[0].len = 2;
 242         state->msg[1].addr = state->i2c.i2c_addr >> 1;
 243         state->msg[1].flags = I2C_M_RD;
 244         state->msg[1].buf = b;
 245         state->msg[1].len = len;
 246
 247         state->i2c_write_buffer[0] = reg >> 8;
 248         state->i2c_write_buffer[1] = reg & 0xff;
 249
 250         if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
 251                 state->i2c_write_buffer[0] |= (1 << 5);
 252         if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
 253                 state->i2c_write_buffer[0] |= (1 << 4);
 254
 255         do {
 256                 l = len < chunk_size ? len : chunk_size;
 257                 state->msg[1].len = l;
 258                 state->msg[1].buf = b;
 259                 ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 2) != 2 ? -EREMOTEIO : 0;
 260                 if (ret != 0) {
 261                         dprintk("i2c read error on %d", reg);
 262                         return -EREMOTEIO;
 263                 }
 264
 265                 b += l;
 266                 len -= l;
 267
 268                 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
 269                         reg += l / 2;
 270         } while ((ret == 0) && len);
 271
 272         return 0;
 273 }
 274
 275 static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg)
 276 {
 277         struct i2c_msg msg[2] = {
 278                 {.addr = i2c->i2c_addr >> 1, .flags = 0,
 279                         .buf = i2c->i2c_write_buffer, .len = 2},
 280                 {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD,
 281                         .buf = i2c->i2c_read_buffer, .len = 2},
 282         };
 283
 284         i2c->i2c_write_buffer[0] = reg >> 8;
 285         i2c->i2c_write_buffer[1] = reg & 0xff;
 286
 287         if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
 288                 dprintk("read register %x error", reg);
 289                 return 0;
 290         }
 291
 292         return (i2c->i2c_read_buffer[0] << 8) | i2c->i2c_read_buffer[1];
 293 }
 294
 295 static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg)
 296 {
 297         if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, 0) != 0)
 298                 return 0;
 299         return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
 300 }
 301
 302 static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute)
 303 {
 304         if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2,
 305                                 attribute) != 0)
 306                 return 0;
 307         return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
 308 }
 309
 310 #define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
 311
 312 static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute)
 313 {
 314         u32 chunk_size = 126;
 315         u32 l;
 316         int ret;
 317
 318         if (state->platform.risc.fw_is_running && (reg < 1024)) {
 319                 if (dib9000_risc_apb_access_write
 320                     (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
 321                         return -EINVAL;
 322                 return 0;
 323         }
 324
 325         memset(&state->msg[0], 0, sizeof(struct i2c_msg));
 326         state->msg[0].addr = state->i2c.i2c_addr >> 1;
 327         state->msg[0].flags = 0;
 328         state->msg[0].buf = state->i2c_write_buffer;
 329         state->msg[0].len = len + 2;
 330
 331         state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
 332         state->i2c_write_buffer[1] = (reg) & 0xff;
 333
 334         if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
 335                 state->i2c_write_buffer[0] |= (1 << 5);
 336         if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
 337                 state->i2c_write_buffer[0] |= (1 << 4);
 338
 339         do {
 340                 l = len < chunk_size ? len : chunk_size;
 341                 state->msg[0].len = l + 2;
 342                 memcpy(&state->i2c_write_buffer[2], buf, l);
 343
 344                 ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0;
 345
 346                 buf += l;
 347                 len -= l;
 348
 349                 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
 350                         reg += l / 2;
 351         } while ((ret == 0) && len);
 352
 353         return ret;
 354 }
 355
 356 static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
 357 {
 358         struct i2c_msg msg = {
 359                 .addr = i2c->i2c_addr >> 1, .flags = 0,
 360                 .buf = i2c->i2c_write_buffer, .len = 4
 361         };
 362
 363         i2c->i2c_write_buffer[0] = (reg >> 8) & 0xff;
 364         i2c->i2c_write_buffer[1] = reg & 0xff;
 365         i2c->i2c_write_buffer[2] = (val >> 8) & 0xff;
 366         i2c->i2c_write_buffer[3] = val & 0xff;
 367
 368         return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
 369 }
 370
 371 static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val)
 372 {
 373         u8 b[2] = { val >> 8, val & 0xff };
 374         return dib9000_write16_attr(state, reg, b, 2, 0);
 375 }
 376
 377 static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute)
 378 {
 379         u8 b[2] = { val >> 8, val & 0xff };
 380         return dib9000_write16_attr(state, reg, b, 2, attribute);
 381 }
 382
 383 #define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
 384 #define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
 385 #define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
 386
 387 #define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
 388 #define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
 389
 390 #define MAC_IRQ      (1 << 1)
 391 #define IRQ_POL_MSK  (1 << 4)
 392
 393 #define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
 394 #define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
 395
 396 static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading)
 397 {
 398         u8 b[14] = { 0 };
 399
 400 /*      dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */
 401 /*      b[0] = 0 << 7; */
 402         b[1] = 1;
 403
 404 /*      b[2] = 0; */
 405 /*      b[3] = 0; */
 406         b[4] = (u8) (addr >> 8);
 407         b[5] = (u8) (addr & 0xff);
 408
 409 /*      b[10] = 0; */
 410 /*      b[11] = 0; */
 411         b[12] = (u8) (addr >> 8);
 412         b[13] = (u8) (addr & 0xff);
 413
 414         addr += len;
 415 /*      b[6] = 0; */
 416 /*      b[7] = 0; */
 417         b[8] = (u8) (addr >> 8);
 418         b[9] = (u8) (addr & 0xff);
 419
 420         dib9000_write(state, 1056, b, 14);
 421         if (reading)
 422                 dib9000_write_word(state, 1056, (1 << 15) | 1);
 423         state->platform.risc.memcmd = -1;       /* if it was called directly reset it - to force a future setup-call to set it */
 424 }
 425
 426 static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd)
 427 {
 428         struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f];
 429         /* decide whether we need to "refresh" the memory controller */
 430         if (state->platform.risc.memcmd == cmd &&       /* same command */
 431             !(cmd & 0x80 && m->size < 67))      /* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
 432                 return;
 433         dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80);
 434         state->platform.risc.memcmd = cmd;
 435 }
 436
 437 static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len)
 438 {
 439         if (!state->platform.risc.fw_is_running)
 440                 return -EIO;
 441
 442         if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) {
 443                 dprintk("could not get the lock");
 444                 return -EINTR;
 445         }
 446         dib9000_risc_mem_setup(state, cmd | 0x80);
 447         dib9000_risc_mem_read_chunks(state, b, len);
 448         mutex_unlock(&state->platform.risc.mem_lock);
 449         return 0;
 450 }
 451
 452 static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b)
 453 {
 454         struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd];
 455         if (!state->platform.risc.fw_is_running)
 456                 return -EIO;
 457
 458         if (mutex_lock_interruptible(&state->platform.risc.mem_lock) < 0) {
 459                 dprintk("could not get the lock");
 460                 return -EINTR;
 461         }
 462         dib9000_risc_mem_setup(state, cmd);
 463         dib9000_risc_mem_write_chunks(state, b, m->size);
 464         mutex_unlock(&state->platform.risc.mem_lock);
 465         return 0;
 466 }
 467
 468 static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len)
 469 {
 470         u16 offs;
 471
 472         if (risc_id == 1)
 473                 offs = 16;
 474         else
 475                 offs = 0;
 476
 477         /* config crtl reg */
 478         dib9000_write_word(state, 1024 + offs, 0x000f);
 479         dib9000_write_word(state, 1025 + offs, 0);
 480         dib9000_write_word(state, 1031 + offs, key);
 481
 482         dprintk("going to download %dB of microcode", len);
 483         if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) {
 484                 dprintk("error while downloading microcode for RISC %c", 'A' + risc_id);
 485                 return -EIO;
 486         }
 487
 488         dprintk("Microcode for RISC %c loaded", 'A' + risc_id);
 489
 490         return 0;
 491 }
 492
 493 static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id)
 494 {
 495         u16 mbox_offs;
 496         u16 reset_reg;
 497         u16 tries = 1000;
 498
 499         if (risc_id == 1)
 500                 mbox_offs = 16;
 501         else
 502                 mbox_offs = 0;
 503
 504         /* Reset mailbox  */
 505         dib9000_write_word(state, 1027 + mbox_offs, 0x8000);
 506
 507         /* Read reset status */
 508         do {
 509                 reset_reg = dib9000_read_word(state, 1027 + mbox_offs);
 510                 msleep(100);
 511         } while ((reset_reg & 0x8000) && --tries);
 512
 513         if (reset_reg & 0x8000) {
 514                 dprintk("MBX: init ERROR, no response from RISC %c", 'A' + risc_id);
 515                 return -EIO;
 516         }
 517         dprintk("MBX: initialized");
 518         return 0;
 519 }
 520
 521 #define MAX_MAILBOX_TRY 100
 522 static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr)
 523 {
 524         u8 *d, b[2];
 525         u16 tmp;
 526         u16 size;
 527         u32 i;
 528         int ret = 0;
 529
 530         if (!state->platform.risc.fw_is_running)
 531                 return -EINVAL;
 532
 533         if (mutex_lock_interruptible(&state->platform.risc.mbx_if_lock) < 0) {
 534                 dprintk("could not get the lock");
 535                 return -EINTR;
 536         }
 537         tmp = MAX_MAILBOX_TRY;
 538         do {
 539                 size = dib9000_read_word_attr(state, 1043, attr) & 0xff;
 540                 if ((size + len + 1) > MBX_MAX_WORDS && --tmp) {
 541                         dprintk("MBX: RISC mbx full, retrying");
 542                         msleep(100);
 543                 } else
 544                         break;
 545         } while (1);
 546
 547         /*dprintk( "MBX: size: %d", size); */
 548
 549         if (tmp == 0) {
 550                 ret = -EINVAL;
 551                 goto out;
 552         }
 553 #ifdef DUMP_MSG
 554         dprintk("--> %02x %d ", id, len + 1);
 555         for (i = 0; i < len; i++)
 556                 dprintk("%04x ", data[i]);
 557         dprintk("\n");
 558 #endif
 559
 560         /* byte-order conversion - works on big (where it is not necessary) or little endian */
 561         d = (u8 *) data;
 562         for (i = 0; i < len; i++) {
 563                 tmp = data[i];
 564                 *d++ = tmp >> 8;
 565                 *d++ = tmp & 0xff;
 566         }
 567
 568         /* write msg */
 569         b[0] = id;
 570         b[1] = len + 1;
 571         if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) {
 572                 ret = -EIO;
 573                 goto out;
 574         }
 575
 576         /* update register nb_mes_in_RX */
 577         ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr);
 578
 579 out:
 580         mutex_unlock(&state->platform.risc.mbx_if_lock);
 581
 582         return ret;
 583 }
 584
 585 static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr)
 586 {
 587 #ifdef DUMP_MSG
 588         u16 *d = data;
 589 #endif
 590
 591         u16 tmp, i;
 592         u8 size;
 593         u8 mc_base;
 594
 595         if (!state->platform.risc.fw_is_running)
 596                 return 0;
 597
 598         if (mutex_lock_interruptible(&state->platform.risc.mbx_if_lock) < 0) {
 599                 dprintk("could not get the lock");
 600                 return 0;
 601         }
 602         if (risc_id == 1)
 603                 mc_base = 16;
 604         else
 605                 mc_base = 0;
 606
 607         /* Length and type in the first word */
 608         *data = dib9000_read_word_attr(state, 1029 + mc_base, attr);
 609
 610         size = *data & 0xff;
 611         if (size <= MBX_MAX_WORDS) {
 612                 data++;
 613                 size--;         /* Initial word already read */
 614
 615                 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr);
 616
 617                 /* to word conversion */
 618                 for (i = 0; i < size; i++) {
 619                         tmp = *data;
 620                         *data = (tmp >> 8) | (tmp << 8);
 621                         data++;
 622                 }
 623
 624 #ifdef DUMP_MSG
 625                 dprintk("<-- ");
 626                 for (i = 0; i < size + 1; i++)
 627                         dprintk("%04x ", d[i]);
 628                 dprintk("\n");
 629 #endif
 630         } else {
 631                 dprintk("MBX: message is too big for message cache (%d), flushing message", size);
 632                 size--;         /* Initial word already read */
 633                 while (size--)
 634                         dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr);
 635         }
 636         /* Update register nb_mes_in_TX */
 637         dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr);
 638
 639         mutex_unlock(&state->platform.risc.mbx_if_lock);
 640
 641         return size + 1;
 642 }
 643
 644 static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size)
 645 {
 646         u32 ts = data[1] << 16 | data[0];
 647         char *b = (char *)&data[2];
 648
 649         b[2 * (size - 2) - 1] = '\0';   /* Bullet proof the buffer */
 650         if (*b == '~') {
 651                 b++;
 652                 dprintk("%s", b);
 653         } else
 654                 dprintk("RISC%d: %d.%04d %s", state->fe_id, ts / 10000, ts % 10000, *b ? b : "<empty>");
 655         return 1;
 656 }
 657
 658 static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr)
 659 {
 660         int i;
 661         u8 size;
 662         u16 *block;
 663         /* find a free slot */
 664         for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
 665                 block = state->platform.risc.message_cache[i];
 666                 if (*block == 0) {
 667                         size = dib9000_mbx_read(state, block, 1, attr);
 668
 669 /*                      dprintk( "MBX: fetched %04x message to cache", *block); */
 670
 671                         switch (*block >> 8) {
 672                         case IN_MSG_DEBUG_BUF:
 673                                 dib9000_risc_debug_buf(state, block + 1, size); /* debug-messages are going to be printed right away */
 674                                 *block = 0;     /* free the block */
 675                                 break;
 676 #if 0
 677                         case IN_MSG_DATA:       /* FE-TRACE */
 678                                 dib9000_risc_data_process(state, block + 1, size);
 679                                 *block = 0;
 680                                 break;
 681 #endif
 682                         default:
 683                                 break;
 684                         }
 685
 686                         return 1;
 687                 }
 688         }
 689         dprintk("MBX: no free cache-slot found for new message...");
 690         return -1;
 691 }
 692
 693 static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr)
 694 {
 695         if (risc_id == 0)
 696                 return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f;   /* 5 bit field */
 697         else
 698                 return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f;    /* 7 bit field */
 699 }
 700
 701 static int dib9000_mbx_process(struct dib9000_state *state, u16 attr)
 702 {
 703         int ret = 0;
 704
 705         if (!state->platform.risc.fw_is_running)
 706                 return -1;
 707
 708         if (mutex_lock_interruptible(&state->platform.risc.mbx_lock) < 0) {
 709                 dprintk("could not get the lock");
 710                 return -1;
 711         }
 712
 713         if (dib9000_mbx_count(state, 1, attr))  /* 1=RiscB */
 714                 ret = dib9000_mbx_fetch_to_cache(state, attr);
 715
 716         dib9000_read_word_attr(state, 1229, attr);      /* Clear the IRQ */
 717 /*      if (tmp) */
 718 /*              dprintk( "cleared IRQ: %x", tmp); */
 719         mutex_unlock(&state->platform.risc.mbx_lock);
 720
 721         return ret;
 722 }
 723
 724 static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr)
 725 {
 726         u8 i;
 727         u16 *block;
 728         u16 timeout = 30;
 729
 730         *msg = 0;
 731         do {
 732                 /* dib9000_mbx_get_from_cache(); */
 733                 for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
 734                         block = state->platform.risc.message_cache[i];
 735                         if ((*block >> 8) == id) {
 736                                 *size = (*block & 0xff) - 1;
 737                                 memcpy(msg, block + 1, (*size) * 2);
 738                                 *block = 0;     /* free the block */
 739                                 i = 0;  /* signal that we found a message */
 740                                 break;
 741                         }
 742                 }
 743
 744                 if (i == 0)
 745                         break;
 746
 747                 if (dib9000_mbx_process(state, attr) == -1)     /* try to fetch one message - if any */
 748                         return -1;
 749
 750         } while (--timeout);
 751
 752         if (timeout == 0) {
 753                 dprintk("waiting for message %d timed out", id);
 754                 return -1;
 755         }
 756
 757         return i == 0;
 758 }
 759
 760 static int dib9000_risc_check_version(struct dib9000_state *state)
 761 {
 762         u8 r[4];
 763         u8 size;
 764         u16 fw_version = 0;
 765
 766         if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0)
 767                 return -EIO;
 768
 769         if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0)
 770                 return -EIO;
 771
 772         fw_version = (r[0] << 8) | r[1];
 773         dprintk("RISC: ver: %d.%02d (IC: %d)", fw_version >> 10, fw_version & 0x3ff, (r[2] << 8) | r[3]);
 774
 775         if ((fw_version >> 10) != 7)
 776                 return -EINVAL;
 777
 778         switch (fw_version & 0x3ff) {
 779         case 11:
 780         case 12:
 781         case 14:
 782         case 15:
 783         case 16:
 784         case 17:
 785                 break;
 786         default:
 787                 dprintk("RISC: invalid firmware version");
 788                 return -EINVAL;
 789         }
 790
 791         dprintk("RISC: valid firmware version");
 792         return 0;
 793 }
 794
 795 static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)
 796 {
 797         /* Reconfig pool mac ram */
 798         dib9000_write_word(state, 1225, 0x02);  /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */
 799         dib9000_write_word(state, 1226, 0x05);
 800
 801         /* Toggles IP crypto to Host APB interface. */
 802         dib9000_write_word(state, 1542, 1);
 803
 804         /* Set jump and no jump in the dma box */
 805         dib9000_write_word(state, 1074, 0);
 806         dib9000_write_word(state, 1075, 0);
 807
 808         /* Set MAC as APB Master. */
 809         dib9000_write_word(state, 1237, 0);
 810
 811         /* Reset the RISCs */
 812         if (codeA != NULL)
 813                 dib9000_write_word(state, 1024, 2);
 814         else
 815                 dib9000_write_word(state, 1024, 15);
 816         if (codeB != NULL)
 817                 dib9000_write_word(state, 1040, 2);
 818
 819         if (codeA != NULL)
 820                 dib9000_firmware_download(state, 0, 0x1234, codeA, lenA);
 821         if (codeB != NULL)
 822                 dib9000_firmware_download(state, 1, 0x1234, codeB, lenB);
 823
 824         /* Run the RISCs */
 825         if (codeA != NULL)
 826                 dib9000_write_word(state, 1024, 0);
 827         if (codeB != NULL)
 828                 dib9000_write_word(state, 1040, 0);
 829
 830         if (codeA != NULL)
 831                 if (dib9000_mbx_host_init(state, 0) != 0)
 832                         return -EIO;
 833         if (codeB != NULL)
 834                 if (dib9000_mbx_host_init(state, 1) != 0)
 835                         return -EIO;
 836
 837         msleep(100);
 838         state->platform.risc.fw_is_running = 1;
 839
 840         if (dib9000_risc_check_version(state) != 0)
 841                 return -EINVAL;
 842
 843         state->platform.risc.memcmd = 0xff;
 844         return 0;
 845 }
 846
 847 static u16 dib9000_identify(struct i2c_device *client)
 848 {
 849         u16 value;
 850
 851         value = dib9000_i2c_read16(client, 896);
 852         if (value != 0x01b3) {
 853                 dprintk("wrong Vendor ID (0x%x)", value);
 854                 return 0;
 855         }
 856
 857         value = dib9000_i2c_read16(client, 897);
 858         if (value != 0x4000 && value != 0x4001 && value != 0x4002 && value != 0x4003 && value != 0x4004 && value != 0x4005) {
 859                 dprintk("wrong Device ID (0x%x)", value);
 860                 return 0;
 861         }
 862
 863         /* protect this driver to be used with 7000PC */
 864         if (value == 0x4000 && dib9000_i2c_read16(client, 769) == 0x4000) {
 865                 dprintk("this driver does not work with DiB7000PC");
 866                 return 0;
 867         }
 868
 869         switch (value) {
 870         case 0x4000:
 871                 dprintk("found DiB7000MA/PA/MB/PB");
 872                 break;
 873         case 0x4001:
 874                 dprintk("found DiB7000HC");
 875                 break;
 876         case 0x4002:
 877                 dprintk("found DiB7000MC");
 878                 break;
 879         case 0x4003:
 880                 dprintk("found DiB9000A");
 881                 break;
 882         case 0x4004:
 883                 dprintk("found DiB9000H");
 884                 break;
 885         case 0x4005:
 886                 dprintk("found DiB9000M");
 887                 break;
 888         }
 889
 890         return value;
 891 }
 892
 893 static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode)
 894 {
 895         /* by default everything is going to be powered off */
 896         u16 reg_903 = 0x3fff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906;
 897         u8 offset;
 898
 899         if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005)
 900                 offset = 1;
 901         else
 902                 offset = 0;
 903
 904         reg_906 = dib9000_read_word(state, 906 + offset) | 0x3; /* keep settings for RISC */
 905
 906         /* now, depending on the requested mode, we power on */
 907         switch (mode) {
 908                 /* power up everything in the demod */
 909         case DIB9000_POWER_ALL:
 910                 reg_903 = 0x0000;
 911                 reg_904 = 0x0000;
 912                 reg_905 = 0x0000;
 913                 reg_906 = 0x0000;
 914                 break;
 915
 916                 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
 917         case DIB9000_POWER_INTERFACE_ONLY:      /* TODO power up either SDIO or I2C or SRAM */
 918                 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
 919                 break;
 920
 921         case DIB9000_POWER_INTERF_ANALOG_AGC:
 922                 reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
 923                 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
 924                 reg_906 &= ~((1 << 0));
 925                 break;
 926
 927         case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
 928                 reg_903 = 0x0000;
 929                 reg_904 = 0x801f;
 930                 reg_905 = 0x0000;
 931                 reg_906 &= ~((1 << 0));
 932                 break;
 933
 934         case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD:
 935                 reg_903 = 0x0000;
 936                 reg_904 = 0x8000;
 937                 reg_905 = 0x010b;
 938                 reg_906 &= ~((1 << 0));
 939                 break;
 940         default:
 941         case DIB9000_POWER_NO:
 942                 break;
 943         }
 944
 945         /* always power down unused parts */
 946         if (!state->platform.host.mobile_mode)
 947                 reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
 948
 949         /* P_sdio_select_clk = 0 on MC and after */
 950         if (state->revision != 0x4000)
 951                 reg_906 <<= 1;
 952
 953         dib9000_write_word(state, 903 + offset, reg_903);
 954         dib9000_write_word(state, 904 + offset, reg_904);
 955         dib9000_write_word(state, 905 + offset, reg_905);
 956         dib9000_write_word(state, 906 + offset, reg_906);
 957 }
 958
 959 static int dib9000_fw_reset(struct dvb_frontend *fe)
 960 {
 961         struct dib9000_state *state = fe->demodulator_priv;
 962
 963         dib9000_write_word(state, 1817, 0x0003);
 964
 965         dib9000_write_word(state, 1227, 1);
 966         dib9000_write_word(state, 1227, 0);
 967
 968         switch ((state->revision = dib9000_identify(&state->i2c))) {
 969         case 0x4003:
 970         case 0x4004:
 971         case 0x4005:
 972                 state->reg_offs = 1;
 973                 break;
 974         default:
 975                 return -EINVAL;
 976         }
 977
 978         /* reset the i2c-master to use the host interface */
 979         dibx000_reset_i2c_master(&state->i2c_master);
 980
 981         dib9000_set_power_mode(state, DIB9000_POWER_ALL);
 982
 983         /* unforce divstr regardless whether i2c enumeration was done or not */
 984         dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1));
 985         dib9000_write_word(state, 1796, 0);
 986         dib9000_write_word(state, 1805, 0x805);
 987
 988         /* restart all parts */
 989         dib9000_write_word(state, 898, 0xffff);
 990         dib9000_write_word(state, 899, 0xffff);
 991         dib9000_write_word(state, 900, 0x0001);
 992         dib9000_write_word(state, 901, 0xff19);
 993         dib9000_write_word(state, 902, 0x003c);
 994
 995         dib9000_write_word(state, 898, 0);
 996         dib9000_write_word(state, 899, 0);
 997         dib9000_write_word(state, 900, 0);
 998         dib9000_write_word(state, 901, 0);
 999         dib9000_write_word(state, 902, 0);
1000
1001         dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives);
1002
1003         dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY);
1004
1005         return 0;
1006 }
1007
1008 static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len)
1009 {
1010         u16 mb[10];
1011         u8 i, s;
1012
1013         if (address >= 1024 || !state->platform.risc.fw_is_running)
1014                 return -EINVAL;
1015
1016         /* dprintk( "APB access thru rd fw %d %x", address, attribute); */
1017
1018         mb[0] = (u16) address;
1019         mb[1] = len / 2;
1020         dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute);
1021         switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) {
1022         case 1:
1023                 s--;
1024                 for (i = 0; i < s; i++) {
1025                         b[i * 2] = (mb[i + 1] >> 8) & 0xff;
1026                         b[i * 2 + 1] = (mb[i + 1]) & 0xff;
1027                 }
1028                 return 0;
1029         default:
1030                 return -EIO;
1031         }
1032         return -EIO;
1033 }
1034
1035 static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len)
1036 {
1037         u16 mb[10];
1038         u8 s, i;
1039
1040         if (address >= 1024 || !state->platform.risc.fw_is_running)
1041                 return -EINVAL;
1042
1043         /* dprintk( "APB access thru wr fw %d %x", address, attribute); */
1044
1045         mb[0] = (unsigned short)address;
1046         for (i = 0; i < len && i < 20; i += 2)
1047                 mb[1 + (i / 2)] = (b[i] << 8 | b[i + 1]);
1048
1049         dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, 1 + len / 2, attribute);
1050         return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL;
1051 }
1052
1053 static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i)
1054 {
1055         u8 index_loop = 10;
1056
1057         if (!state->platform.risc.fw_is_running)
1058                 return 0;
1059         dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i);
1060         do {
1061                 dib9000_risc_mem_read(state, FE_MM_RW_SYNC, state->i2c_read_buffer, 1);
1062         } while (state->i2c_read_buffer[0] && index_loop--);
1063
1064         if (index_loop > 0)
1065                 return 0;
1066         return -EIO;
1067 }
1068
1069 static int dib9000_fw_init(struct dib9000_state *state)
1070 {
1071         struct dibGPIOFunction *f;
1072         u16 b[40] = { 0 };
1073         u8 i;
1074         u8 size;
1075
1076         if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
1077                 return -EIO;
1078
1079         /* initialize the firmware */
1080         for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) {
1081                 f = &state->chip.d9.cfg.gpio_function[i];
1082                 if (f->mask) {
1083                         switch (f->function) {
1084                         case BOARD_GPIO_FUNCTION_COMPONENT_ON:
1085                                 b[0] = (u16) f->mask;
1086                                 b[1] = (u16) f->direction;
1087                                 b[2] = (u16) f->value;
1088                                 break;
1089                         case BOARD_GPIO_FUNCTION_COMPONENT_OFF:
1090                                 b[3] = (u16) f->mask;
1091                                 b[4] = (u16) f->direction;
1092                                 b[5] = (u16) f->value;
1093                                 break;
1094                         }
1095                 }
1096         }
1097         if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0)
1098                 return -EIO;
1099
1100         /* subband */
1101         b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */
1102         for (i = 0; i < state->chip.d9.cfg.subband.size; i++) {
1103                 b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz;
1104                 b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
1105                 b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
1106                 b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
1107         }
1108         b[1 + i * 4] = 0;       /* fe_id */
1109         if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0)
1110                 return -EIO;
1111
1112         /* 0 - id, 1 - no_of_frontends */
1113         b[0] = (0 << 8) | 1;
1114         /* 0 = i2c-address demod, 0 = tuner */
1115         b[1] = (0 << 8) | (0);
1116         b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
1117         b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
1118         b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
1119         b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff);
1120         b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff);
1121         b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff);
1122         b[29] = state->chip.d9.cfg.if_drives;
1123         if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0)
1124                 return -EIO;
1125
1126         if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0)
1127                 return -EIO;
1128
1129         if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0)
1130                 return -EIO;
1131
1132         if (size > ARRAY_SIZE(b)) {
1133                 dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size,
1134                         (int)ARRAY_SIZE(b));
1135                 return -EINVAL;
1136         }
1137
1138         for (i = 0; i < size; i += 2) {
1139                 state->platform.risc.fe_mm[i / 2].addr = b[i + 0];
1140                 state->platform.risc.fe_mm[i / 2].size = b[i + 1];
1141         }
1142
1143         return 0;
1144 }
1145
1146 static void dib9000_fw_set_channel_head(struct dib9000_state *state)
1147 {
1148         u8 b[9];
1149         u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000;
1150         if (state->fe_id % 2)
1151                 freq += 101;
1152
1153         b[0] = (u8) ((freq >> 0) & 0xff);
1154         b[1] = (u8) ((freq >> 8) & 0xff);
1155         b[2] = (u8) ((freq >> 16) & 0xff);
1156         b[3] = (u8) ((freq >> 24) & 0xff);
1157         b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff);
1158         b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff);
1159         b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff);
1160         b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff);
1161         b[8] = 0x80;            /* do not wait for CELL ID when doing autosearch */
1162         if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT)
1163                 b[8] |= 1;
1164         dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b);
1165 }
1166
1167 static int dib9000_fw_get_channel(struct dvb_frontend *fe)
1168 {
1169         struct dib9000_state *state = fe->demodulator_priv;
1170         struct dibDVBTChannel {
1171                 s8 spectrum_inversion;
1172
1173                 s8 nfft;
1174                 s8 guard;
1175                 s8 constellation;
1176
1177                 s8 hrch;
1178                 s8 alpha;
1179                 s8 code_rate_hp;
1180                 s8 code_rate_lp;
1181                 s8 select_hp;
1182
1183                 s8 intlv_native;
1184         };
1185         struct dibDVBTChannel *ch;
1186         int ret = 0;
1187
1188         if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
1189                 dprintk("could not get the lock");
1190                 return -EINTR;
1191         }
1192         if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
1193                 ret = -EIO;
1194                 goto error;
1195         }
1196
1197         dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION,
1198                         state->i2c_read_buffer, sizeof(struct dibDVBTChannel));
1199         ch = (struct dibDVBTChannel *)state->i2c_read_buffer;
1200
1201
1202         switch (ch->spectrum_inversion & 0x7) {
1203         case 1:
1204                 state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
1205                 break;
1206         case 0:
1207                 state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF;
1208                 break;
1209         default:
1210         case -1:
1211                 state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO;
1212                 break;
1213         }
1214         switch (ch->nfft) {
1215         case 0:
1216                 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
1217                 break;
1218         case 2:
1219                 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K;
1220                 break;
1221         case 1:
1222                 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1223                 break;
1224         default:
1225         case -1:
1226                 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
1227                 break;
1228         }
1229         switch (ch->guard) {
1230         case 0:
1231                 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
1232                 break;
1233         case 1:
1234                 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
1235                 break;
1236         case 2:
1237                 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1238                 break;
1239         case 3:
1240                 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
1241                 break;
1242         default:
1243         case -1:
1244                 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
1245                 break;
1246         }
1247         switch (ch->constellation) {
1248         case 2:
1249                 state->fe[0]->dtv_property_cache.modulation = QAM_64;
1250                 break;
1251         case 1:
1252                 state->fe[0]->dtv_property_cache.modulation = QAM_16;
1253                 break;
1254         case 0:
1255                 state->fe[0]->dtv_property_cache.modulation = QPSK;
1256                 break;
1257         default:
1258         case -1:
1259                 state->fe[0]->dtv_property_cache.modulation = QAM_AUTO;
1260                 break;
1261         }
1262         switch (ch->hrch) {
1263         case 0:
1264                 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE;
1265                 break;
1266         case 1:
1267                 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1;
1268                 break;
1269         default:
1270         case -1:
1271                 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
1272                 break;
1273         }
1274         switch (ch->code_rate_hp) {
1275         case 1:
1276                 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2;
1277                 break;
1278         case 2:
1279                 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3;
1280                 break;
1281         case 3:
1282                 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4;
1283                 break;
1284         case 5:
1285                 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6;
1286                 break;
1287         case 7:
1288                 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8;
1289                 break;
1290         default:
1291         case -1:
1292                 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO;
1293                 break;
1294         }
1295         switch (ch->code_rate_lp) {
1296         case 1:
1297                 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2;
1298                 break;
1299         case 2:
1300                 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3;
1301                 break;
1302         case 3:
1303                 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4;
1304                 break;
1305         case 5:
1306                 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6;
1307                 break;
1308         case 7:
1309                 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8;
1310                 break;
1311         default:
1312         case -1:
1313                 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO;
1314                 break;
1315         }
1316
1317 error:
1318         mutex_unlock(&state->platform.risc.mem_mbx_lock);
1319         return ret;
1320 }
1321
1322 static int dib9000_fw_set_channel_union(struct dvb_frontend *fe)
1323 {
1324         struct dib9000_state *state = fe->demodulator_priv;
1325         struct dibDVBTChannel {
1326                 s8 spectrum_inversion;
1327
1328                 s8 nfft;
1329                 s8 guard;
1330                 s8 constellation;
1331
1332                 s8 hrch;
1333                 s8 alpha;
1334                 s8 code_rate_hp;
1335                 s8 code_rate_lp;
1336                 s8 select_hp;
1337
1338                 s8 intlv_native;
1339         };
1340         struct dibDVBTChannel ch;
1341
1342         switch (state->fe[0]->dtv_property_cache.inversion) {
1343         case INVERSION_ON:
1344                 ch.spectrum_inversion = 1;
1345                 break;
1346         case INVERSION_OFF:
1347                 ch.spectrum_inversion = 0;
1348                 break;
1349         default:
1350         case INVERSION_AUTO:
1351                 ch.spectrum_inversion = -1;
1352                 break;
1353         }
1354         switch (state->fe[0]->dtv_property_cache.transmission_mode) {
1355         case TRANSMISSION_MODE_2K:
1356                 ch.nfft = 0;
1357                 break;
1358         case TRANSMISSION_MODE_4K:
1359                 ch.nfft = 2;
1360                 break;
1361         case TRANSMISSION_MODE_8K:
1362                 ch.nfft = 1;
1363                 break;
1364         default:
1365         case TRANSMISSION_MODE_AUTO:
1366                 ch.nfft = 1;
1367                 break;
1368         }
1369         switch (state->fe[0]->dtv_property_cache.guard_interval) {
1370         case GUARD_INTERVAL_1_32:
1371                 ch.guard = 0;
1372                 break;
1373         case GUARD_INTERVAL_1_16:
1374                 ch.guard = 1;
1375                 break;
1376         case GUARD_INTERVAL_1_8:
1377                 ch.guard = 2;
1378                 break;
1379         case GUARD_INTERVAL_1_4:
1380                 ch.guard = 3;
1381                 break;
1382         default:
1383         case GUARD_INTERVAL_AUTO:
1384                 ch.guard = -1;
1385                 break;
1386         }
1387         switch (state->fe[0]->dtv_property_cache.modulation) {
1388         case QAM_64:
1389                 ch.constellation = 2;
1390                 break;
1391         case QAM_16:
1392                 ch.constellation = 1;
1393                 break;
1394         case QPSK:
1395                 ch.constellation = 0;
1396                 break;
1397         default:
1398         case QAM_AUTO:
1399                 ch.constellation = -1;
1400                 break;
1401         }
1402         switch (state->fe[0]->dtv_property_cache.hierarchy) {
1403         case HIERARCHY_NONE:
1404                 ch.hrch = 0;
1405                 break;
1406         case HIERARCHY_1:
1407         case HIERARCHY_2:
1408         case HIERARCHY_4:
1409                 ch.hrch = 1;
1410                 break;
1411         default:
1412         case HIERARCHY_AUTO:
1413                 ch.hrch = -1;
1414                 break;
1415         }
1416         ch.alpha = 1;
1417         switch (state->fe[0]->dtv_property_cache.code_rate_HP) {
1418         case FEC_1_2:
1419                 ch.code_rate_hp = 1;
1420                 break;
1421         case FEC_2_3:
1422                 ch.code_rate_hp = 2;
1423                 break;
1424         case FEC_3_4:
1425                 ch.code_rate_hp = 3;
1426                 break;
1427         case FEC_5_6:
1428                 ch.code_rate_hp = 5;
1429                 break;
1430         case FEC_7_8:
1431                 ch.code_rate_hp = 7;
1432                 break;
1433         default:
1434         case FEC_AUTO:
1435                 ch.code_rate_hp = -1;
1436                 break;
1437         }
1438         switch (state->fe[0]->dtv_property_cache.code_rate_LP) {
1439         case FEC_1_2:
1440                 ch.code_rate_lp = 1;
1441                 break;
1442         case FEC_2_3:
1443                 ch.code_rate_lp = 2;
1444                 break;
1445         case FEC_3_4:
1446                 ch.code_rate_lp = 3;
1447                 break;
1448         case FEC_5_6:
1449                 ch.code_rate_lp = 5;
1450                 break;
1451         case FEC_7_8:
1452                 ch.code_rate_lp = 7;
1453                 break;
1454         default:
1455         case FEC_AUTO:
1456                 ch.code_rate_lp = -1;
1457                 break;
1458         }
1459         ch.select_hp = 1;
1460         ch.intlv_native = 1;
1461
1462         dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch);
1463
1464         return 0;
1465 }
1466
1467 static int dib9000_fw_tune(struct dvb_frontend *fe)
1468 {
1469         struct dib9000_state *state = fe->demodulator_priv;
1470         int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1471         s8 i;
1472
1473         switch (state->tune_state) {
1474         case CT_DEMOD_START:
1475                 dib9000_fw_set_channel_head(state);
1476
1477                 /* write the channel context - a channel is initialized to 0, so it is OK */
1478                 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info);
1479                 dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info);
1480
1481                 if (search)
1482                         dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0);
1483                 else {
1484                         dib9000_fw_set_channel_union(fe);
1485                         dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0);
1486                 }
1487                 state->tune_state = CT_DEMOD_STEP_1;
1488                 break;
1489         case CT_DEMOD_STEP_1:
1490                 if (search)
1491                         dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, state->i2c_read_buffer, 1);
1492                 else
1493                         dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, state->i2c_read_buffer, 1);
1494                 i = (s8)state->i2c_read_buffer[0];
1495                 switch (i) {    /* something happened */
1496                 case 0:
1497                         break;
1498                 case -2:        /* tps locks are "slower" than MPEG locks -> even in autosearch data is OK here */
1499                         if (search)
1500                                 state->status = FE_STATUS_DEMOD_SUCCESS;
1501                         else {
1502                                 state->tune_state = CT_DEMOD_STOP;
1503                                 state->status = FE_STATUS_LOCKED;
1504                         }
1505                         break;
1506                 default:
1507                         state->status = FE_STATUS_TUNE_FAILED;
1508                         state->tune_state = CT_DEMOD_STOP;
1509                         break;
1510                 }
1511                 break;
1512         default:
1513                 ret = FE_CALLBACK_TIME_NEVER;
1514                 break;
1515         }
1516
1517         return ret;
1518 }
1519
1520 static int dib9000_fw_set_diversity_in(struct dvb_frontend *fe, int onoff)
1521 {
1522         struct dib9000_state *state = fe->demodulator_priv;
1523         u16 mode = (u16) onoff;
1524         return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1);
1525 }
1526
1527 static int dib9000_fw_set_output_mode(struct dvb_frontend *fe, int mode)
1528 {
1529         struct dib9000_state *state = fe->demodulator_priv;
1530         u16 outreg, smo_mode;
1531
1532         dprintk("setting output mode for demod %p to %d", fe, mode);
1533
1534         switch (mode) {
1535         case OUTMODE_MPEG2_PAR_GATED_CLK:
1536                 outreg = (1 << 10);     /* 0x0400 */
1537                 break;
1538         case OUTMODE_MPEG2_PAR_CONT_CLK:
1539                 outreg = (1 << 10) | (1 << 6);  /* 0x0440 */
1540                 break;
1541         case OUTMODE_MPEG2_SERIAL:
1542                 outreg = (1 << 10) | (2 << 6) | (0 << 1);       /* 0x0482 */
1543                 break;
1544         case OUTMODE_DIVERSITY:
1545                 outreg = (1 << 10) | (4 << 6);  /* 0x0500 */
1546                 break;
1547         case OUTMODE_MPEG2_FIFO:
1548                 outreg = (1 << 10) | (5 << 6);
1549                 break;
1550         case OUTMODE_HIGH_Z:
1551                 outreg = 0;
1552                 break;
1553         default:
1554                 dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]);
1555                 return -EINVAL;
1556         }
1557
1558         dib9000_write_word(state, 1795, outreg);
1559
1560         switch (mode) {
1561         case OUTMODE_MPEG2_PAR_GATED_CLK:
1562         case OUTMODE_MPEG2_PAR_CONT_CLK:
1563         case OUTMODE_MPEG2_SERIAL:
1564         case OUTMODE_MPEG2_FIFO:
1565                 smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1);
1566                 if (state->chip.d9.cfg.output_mpeg2_in_188_bytes)
1567                         smo_mode |= (1 << 5);
1568                 dib9000_write_word(state, 295, smo_mode);
1569                 break;
1570         }
1571
1572         outreg = to_fw_output_mode(mode);
1573         return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1);
1574 }
1575
1576 static int dib9000_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1577 {
1578         struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1579         u16 i, len, t, index_msg;
1580
1581         for (index_msg = 0; index_msg < num; index_msg++) {
1582                 if (msg[index_msg].flags & I2C_M_RD) {  /* read */
1583                         len = msg[index_msg].len;
1584                         if (len > 16)
1585                                 len = 16;
1586
1587                         if (dib9000_read_word(state, 790) != 0)
1588                                 dprintk("TunerITF: read busy");
1589
1590                         dib9000_write_word(state, 784, (u16) (msg[index_msg].addr));
1591                         dib9000_write_word(state, 787, (len / 2) - 1);
1592                         dib9000_write_word(state, 786, 1);      /* start read */
1593
1594                         i = 1000;
1595                         while (dib9000_read_word(state, 790) != (len / 2) && i)
1596                                 i--;
1597
1598                         if (i == 0)
1599                                 dprintk("TunerITF: read failed");
1600
1601                         for (i = 0; i < len; i += 2) {
1602                                 t = dib9000_read_word(state, 785);
1603                                 msg[index_msg].buf[i] = (t >> 8) & 0xff;
1604                                 msg[index_msg].buf[i + 1] = (t) & 0xff;
1605                         }
1606                         if (dib9000_read_word(state, 790) != 0)
1607                                 dprintk("TunerITF: read more data than expected");
1608                 } else {
1609                         i = 1000;
1610                         while (dib9000_read_word(state, 789) && i)
1611                                 i--;
1612                         if (i == 0)
1613                                 dprintk("TunerITF: write busy");
1614
1615                         len = msg[index_msg].len;
1616                         if (len > 16)
1617                                 len = 16;
1618
1619                         for (i = 0; i < len; i += 2)
1620                                 dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]);
1621                         dib9000_write_word(state, 784, (u16) msg[index_msg].addr);
1622                         dib9000_write_word(state, 787, (len / 2) - 1);
1623                         dib9000_write_word(state, 786, 0);      /* start write */
1624
1625                         i = 1000;
1626                         while (dib9000_read_word(state, 791) > 0 && i)
1627                                 i--;
1628                         if (i == 0)
1629                                 dprintk("TunerITF: write failed");
1630                 }
1631         }
1632         return num;
1633 }
1634
1635 int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
1636 {
1637         struct dib9000_state *state = fe->demodulator_priv;
1638
1639         state->component_bus_speed = speed;
1640         return 0;
1641 }
1642 EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed);
1643
1644 static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1645 {
1646         struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1647         u8 type = 0;            /* I2C */
1648         u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4;
1649         u16 scl = state->component_bus_speed;   /* SCL frequency */
1650         struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER];
1651         u8 p[13] = { 0 };
1652
1653         p[0] = type;
1654         p[1] = port;
1655         p[2] = msg[0].addr << 1;
1656
1657         p[3] = (u8) scl & 0xff; /* scl */
1658         p[4] = (u8) (scl >> 8);
1659
1660         p[7] = 0;
1661         p[8] = 0;
1662
1663         p[9] = (u8) (msg[0].len);
1664         p[10] = (u8) (msg[0].len >> 8);
1665         if ((num > 1) && (msg[1].flags & I2C_M_RD)) {
1666                 p[11] = (u8) (msg[1].len);
1667                 p[12] = (u8) (msg[1].len >> 8);
1668         } else {
1669                 p[11] = 0;
1670                 p[12] = 0;
1671         }
1672
1673         if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
1674                 dprintk("could not get the lock");
1675                 return 0;
1676         }
1677
1678         dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p);
1679
1680         {                       /* write-part */
1681                 dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0);
1682                 dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len);
1683         }
1684
1685         /* do the transaction */
1686         if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) {
1687                 mutex_unlock(&state->platform.risc.mem_mbx_lock);
1688                 return 0;
1689         }
1690
1691         /* read back any possible result */
1692         if ((num > 1) && (msg[1].flags & I2C_M_RD))
1693                 dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len);
1694
1695         mutex_unlock(&state->platform.risc.mem_mbx_lock);
1696
1697         return num;
1698 }
1699
1700 static u32 dib9000_i2c_func(struct i2c_adapter *adapter)
1701 {
1702         return I2C_FUNC_I2C;
1703 }
1704
1705 static struct i2c_algorithm dib9000_tuner_algo = {
1706         .master_xfer = dib9000_tuner_xfer,
1707         .functionality = dib9000_i2c_func,
1708 };
1709
1710 static struct i2c_algorithm dib9000_component_bus_algo = {
1711         .master_xfer = dib9000_fw_component_bus_xfer,
1712         .functionality = dib9000_i2c_func,
1713 };
1714
1715 struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
1716 {
1717         struct dib9000_state *st = fe->demodulator_priv;
1718         return &st->tuner_adap;
1719 }
1720 EXPORT_SYMBOL(dib9000_get_tuner_interface);
1721
1722 struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
1723 {
1724         struct dib9000_state *st = fe->demodulator_priv;
1725         return &st->component_bus;
1726 }
1727 EXPORT_SYMBOL(dib9000_get_component_bus_interface);
1728
1729 struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
1730 {
1731         struct dib9000_state *st = fe->demodulator_priv;
1732         return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
1733 }
1734 EXPORT_SYMBOL(dib9000_get_i2c_master);
1735
1736 int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
1737 {
1738         struct dib9000_state *st = fe->demodulator_priv;
1739
1740         st->i2c.i2c_adap = i2c;
1741         return 0;
1742 }
1743 EXPORT_SYMBOL(dib9000_set_i2c_adapter);
1744
1745 static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val)
1746 {
1747         st->gpio_dir = dib9000_read_word(st, 773);
1748         st->gpio_dir &= ~(1 << num);    /* reset the direction bit */
1749         st->gpio_dir |= (dir & 0x1) << num;     /* set the new direction */
1750         dib9000_write_word(st, 773, st->gpio_dir);
1751
1752         st->gpio_val = dib9000_read_word(st, 774);
1753         st->gpio_val &= ~(1 << num);    /* reset the direction bit */
1754         st->gpio_val |= (val & 0x01) << num;    /* set the new value */
1755         dib9000_write_word(st, 774, st->gpio_val);
1756
1757         dprintk("gpio dir: %04x: gpio val: %04x", st->gpio_dir, st->gpio_val);
1758
1759         return 0;
1760 }
1761
1762 int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
1763 {
1764         struct dib9000_state *state = fe->demodulator_priv;
1765         return dib9000_cfg_gpio(state, num, dir, val);
1766 }
1767 EXPORT_SYMBOL(dib9000_set_gpio);
1768
1769 int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1770 {
1771         struct dib9000_state *state = fe->demodulator_priv;
1772         u16 val;
1773         int ret;
1774
1775         if ((state->pid_ctrl_index != -2) && (state->pid_ctrl_index < 9)) {
1776                 /* postpone the pid filtering cmd */
1777                 dprintk("pid filter cmd postpone");
1778                 state->pid_ctrl_index++;
1779                 state->pid_ctrl[state->pid_ctrl_index].cmd = DIB9000_PID_FILTER_CTRL;
1780                 state->pid_ctrl[state->pid_ctrl_index].onoff = onoff;
1781                 return 0;
1782         }
1783
1784         if (mutex_lock_interruptible(&state->demod_lock) < 0) {
1785                 dprintk("could not get the lock");
1786                 return -EINTR;
1787         }
1788
1789         val = dib9000_read_word(state, 294 + 1) & 0xffef;
1790         val |= (onoff & 0x1) << 4;
1791
1792         dprintk("PID filter enabled %d", onoff);
1793         ret = dib9000_write_word(state, 294 + 1, val);
1794         mutex_unlock(&state->demod_lock);
1795         return ret;
1796
1797 }
1798 EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl);
1799
1800 int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1801 {
1802         struct dib9000_state *state = fe->demodulator_priv;
1803         int ret;
1804
1805         if (state->pid_ctrl_index != -2) {
1806                 /* postpone the pid filtering cmd */
1807                 dprintk("pid filter postpone");
1808                 if (state->pid_ctrl_index < 9) {
1809                         state->pid_ctrl_index++;
1810                         state->pid_ctrl[state->pid_ctrl_index].cmd = DIB9000_PID_FILTER;
1811                         state->pid_ctrl[state->pid_ctrl_index].id = id;
1812                         state->pid_ctrl[state->pid_ctrl_index].pid = pid;
1813                         state->pid_ctrl[state->pid_ctrl_index].onoff = onoff;
1814                 } else
1815                         dprintk("can not add any more pid ctrl cmd");
1816                 return 0;
1817         }
1818
1819         if (mutex_lock_interruptible(&state->demod_lock) < 0) {
1820                 dprintk("could not get the lock");
1821                 return -EINTR;
1822         }
1823         dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
1824         ret = dib9000_write_word(state, 300 + 1 + id,
1825                         onoff ? (1 << 13) | pid : 0);
1826         mutex_unlock(&state->demod_lock);
1827         return ret;
1828 }
1829 EXPORT_SYMBOL(dib9000_fw_pid_filter);
1830
1831 int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
1832 {
1833         struct dib9000_state *state = fe->demodulator_priv;
1834         return dib9000_fw_init(state);
1835 }
1836 EXPORT_SYMBOL(dib9000_firmware_post_pll_init);
1837
1838 static void dib9000_release(struct dvb_frontend *demod)
1839 {
1840         struct dib9000_state *st = demod->demodulator_priv;
1841         u8 index_frontend;
1842
1843         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
1844                 dvb_frontend_detach(st->fe[index_frontend]);
1845
1846         dibx000_exit_i2c_master(&st->i2c_master);
1847
1848         i2c_del_adapter(&st->tuner_adap);
1849         i2c_del_adapter(&st->component_bus);
1850         kfree(st->fe[0]);
1851         kfree(st);
1852 }
1853
1854 static int dib9000_wakeup(struct dvb_frontend *fe)
1855 {
1856         return 0;
1857 }
1858
1859 static int dib9000_sleep(struct dvb_frontend *fe)
1860 {
1861         struct dib9000_state *state = fe->demodulator_priv;
1862         u8 index_frontend;
1863         int ret = 0;
1864
1865         if (mutex_lock_interruptible(&state->demod_lock) < 0) {
1866                 dprintk("could not get the lock");
1867                 return -EINTR;
1868         }
1869         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1870                 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
1871                 if (ret < 0)
1872                         goto error;
1873         }
1874         ret = dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0);
1875
1876 error:
1877         mutex_unlock(&state->demod_lock);
1878         return ret;
1879 }
1880
1881 static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
1882 {
1883         tune->min_delay_ms = 1000;
1884         return 0;
1885 }
1886
1887 static int dib9000_get_frontend(struct dvb_frontend *fe)
1888 {
1889         struct dib9000_state *state = fe->demodulator_priv;
1890         u8 index_frontend, sub_index_frontend;
1891         fe_status_t stat;
1892         int ret = 0;
1893
1894         if (state->get_frontend_internal == 0) {
1895                 if (mutex_lock_interruptible(&state->demod_lock) < 0) {
1896                         dprintk("could not get the lock");
1897                         return -EINTR;
1898                 }
1899         }
1900
1901         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1902                 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
1903                 if (stat & FE_HAS_SYNC) {
1904                         dprintk("TPS lock on the slave%i", index_frontend);
1905
1906                         /* synchronize the cache with the other frontends */
1907                         state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]);
1908                         for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL);
1909                              sub_index_frontend++) {
1910                                 if (sub_index_frontend != index_frontend) {
1911                                         state->fe[sub_index_frontend]->dtv_property_cache.modulation =
1912                                             state->fe[index_frontend]->dtv_property_cache.modulation;
1913                                         state->fe[sub_index_frontend]->dtv_property_cache.inversion =
1914                                             state->fe[index_frontend]->dtv_property_cache.inversion;
1915                                         state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode =
1916                                             state->fe[index_frontend]->dtv_property_cache.transmission_mode;
1917                                         state->fe[sub_index_frontend]->dtv_property_cache.guard_interval =
1918                                             state->fe[index_frontend]->dtv_property_cache.guard_interval;
1919                                         state->fe[sub_index_frontend]->dtv_property_cache.hierarchy =
1920                                             state->fe[index_frontend]->dtv_property_cache.hierarchy;
1921                                         state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP =
1922                                             state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
1923                                         state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP =
1924                                             state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
1925                                         state->fe[sub_index_frontend]->dtv_property_cache.rolloff =
1926                                             state->fe[index_frontend]->dtv_property_cache.rolloff;
1927                                 }
1928                         }
1929                         ret = 0;
1930                         goto return_value;
1931                 }
1932         }
1933
1934         /* get the channel from master chip */
1935         ret = dib9000_fw_get_channel(fe);
1936         if (ret != 0)
1937                 goto return_value;
1938
1939         /* synchronize the cache with the other frontends */
1940         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1941                 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
1942                 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
1943                 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
1944                 state->fe[index_frontend]->dtv_property_cache.modulation = fe->dtv_property_cache.modulation;
1945                 state->fe[index_frontend]->dtv_property_cache.hierarchy = fe->dtv_property_cache.hierarchy;
1946                 state->fe[index_frontend]->dtv_property_cache.code_rate_HP = fe->dtv_property_cache.code_rate_HP;
1947                 state->fe[index_frontend]->dtv_property_cache.code_rate_LP = fe->dtv_property_cache.code_rate_LP;
1948                 state->fe[index_frontend]->dtv_property_cache.rolloff = fe->dtv_property_cache.rolloff;
1949         }
1950         ret = 0;
1951
1952 return_value:
1953         if (state->get_frontend_internal == 0)
1954                 mutex_unlock(&state->demod_lock);
1955         return ret;
1956 }
1957
1958 static int dib9000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
1959 {
1960         struct dib9000_state *state = fe->demodulator_priv;
1961         state->tune_state = tune_state;
1962         if (tune_state == CT_DEMOD_START)
1963                 state->status = FE_STATUS_TUNE_PENDING;
1964
1965         return 0;
1966 }
1967
1968 static u32 dib9000_get_status(struct dvb_frontend *fe)
1969 {
1970         struct dib9000_state *state = fe->demodulator_priv;
1971         return state->status;
1972 }
1973
1974 static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_frontend_parametersContext *channel_status)
1975 {
1976         struct dib9000_state *state = fe->demodulator_priv;
1977
1978         memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext));
1979         return 0;
1980 }
1981
1982 static int dib9000_set_frontend(struct dvb_frontend *fe)
1983 {
1984         struct dib9000_state *state = fe->demodulator_priv;
1985         int sleep_time, sleep_time_slave;
1986         u32 frontend_status;
1987         u8 nbr_pending, exit_condition, index_frontend, index_frontend_success;
1988         struct dvb_frontend_parametersContext channel_status;
1989
1990         /* check that the correct parameters are set */
1991         if (state->fe[0]->dtv_property_cache.frequency == 0) {
1992                 dprintk("dib9000: must specify frequency ");
1993                 return 0;
1994         }
1995
1996         if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
1997                 dprintk("dib9000: must specify bandwidth ");
1998                 return 0;
1999         }
2000
2001         state->pid_ctrl_index = -1; /* postpone the pid filtering cmd */
2002         if (mutex_lock_interruptible(&state->demod_lock) < 0) {
2003                 dprintk("could not get the lock");
2004                 return 0;
2005         }
2006
2007         fe->dtv_property_cache.delivery_system = SYS_DVBT;
2008
2009         /* set the master status */
2010         if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO ||
2011             state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO ||
2012             state->fe[0]->dtv_property_cache.modulation == QAM_AUTO ||
2013             state->fe[0]->dtv_property_cache.code_rate_HP == FEC_AUTO) {
2014                 /* no channel specified, autosearch the channel */
2015                 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
2016         } else
2017                 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
2018
2019         /* set mode and status for the different frontends */
2020         for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2021                 dib9000_fw_set_diversity_in(state->fe[index_frontend], 1);
2022
2023                 /* synchronization of the cache */
2024                 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
2025
2026                 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT;
2027                 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
2028
2029                 dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status);
2030                 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
2031         }
2032
2033         /* actual tune */
2034         exit_condition = 0;     /* 0: tune pending; 1: tune failed; 2:tune success */
2035         index_frontend_success = 0;
2036         do {
2037                 sleep_time = dib9000_fw_tune(state->fe[0]);
2038                 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2039                         sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]);
2040                         if (sleep_time == FE_CALLBACK_TIME_NEVER)
2041                                 sleep_time = sleep_time_slave;
2042                         else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
2043                                 sleep_time = sleep_time_slave;
2044                 }
2045                 if (sleep_time != FE_CALLBACK_TIME_NEVER)
2046                         msleep(sleep_time / 10);
2047                 else
2048                         break;
2049
2050                 nbr_pending = 0;
2051                 exit_condition = 0;
2052                 index_frontend_success = 0;
2053                 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2054                         frontend_status = -dib9000_get_status(state->fe[index_frontend]);
2055                         if (frontend_status > -FE_STATUS_TUNE_PENDING) {
2056                                 exit_condition = 2;     /* tune success */
2057                                 index_frontend_success = index_frontend;
2058                                 break;
2059                         }
2060                         if (frontend_status == -FE_STATUS_TUNE_PENDING)
2061                                 nbr_pending++;  /* some frontends are still tuning */
2062                 }
2063                 if ((exit_condition != 2) && (nbr_pending == 0))
2064                         exit_condition = 1;     /* if all tune are done and no success, exit: tune failed */
2065
2066         } while (exit_condition == 0);
2067
2068         /* check the tune result */
2069         if (exit_condition == 1) {      /* tune failed */
2070                 dprintk("tune failed");
2071                 mutex_unlock(&state->demod_lock);
2072                 /* tune failed; put all the pid filtering cmd to junk */
2073                 state->pid_ctrl_index = -1;
2074                 return 0;
2075         }
2076
2077         dprintk("tune success on frontend%i", index_frontend_success);
2078
2079         /* synchronize all the channel cache */
2080         state->get_frontend_internal = 1;
2081         dib9000_get_frontend(state->fe[0]);
2082         state->get_frontend_internal = 0;
2083
2084         /* retune the other frontends with the found channel */
2085         channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
2086         for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2087                 /* only retune the frontends which was not tuned success */
2088                 if (index_frontend != index_frontend_success) {
2089                         dib9000_set_channel_status(state->fe[index_frontend], &channel_status);
2090                         dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
2091                 }
2092         }
2093         do {
2094                 sleep_time = FE_CALLBACK_TIME_NEVER;
2095                 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2096                         if (index_frontend != index_frontend_success) {
2097                                 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend]);
2098                                 if (sleep_time == FE_CALLBACK_TIME_NEVER)
2099                                         sleep_time = sleep_time_slave;
2100                                 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
2101                                         sleep_time = sleep_time_slave;
2102                         }
2103                 }
2104                 if (sleep_time != FE_CALLBACK_TIME_NEVER)
2105                         msleep(sleep_time / 10);
2106                 else
2107                         break;
2108
2109                 nbr_pending = 0;
2110                 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2111                         if (index_frontend != index_frontend_success) {
2112                                 frontend_status = -dib9000_get_status(state->fe[index_frontend]);
2113                                 if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING))
2114                                         nbr_pending++;  /* some frontends are still tuning */
2115                         }
2116                 }
2117         } while (nbr_pending != 0);
2118
2119         /* set the output mode */
2120         dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
2121         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2122                 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
2123
2124         /* turn off the diversity for the last frontend */
2125         dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0);
2126
2127         mutex_unlock(&state->demod_lock);
2128         if (state->pid_ctrl_index >= 0) {
2129                 u8 index_pid_filter_cmd;
2130                 u8 pid_ctrl_index = state->pid_ctrl_index;
2131
2132                 state->pid_ctrl_index = -2;
2133                 for (index_pid_filter_cmd = 0;
2134                                 index_pid_filter_cmd <= pid_ctrl_index;
2135                                 index_pid_filter_cmd++) {
2136                         if (state->pid_ctrl[index_pid_filter_cmd].cmd == DIB9000_PID_FILTER_CTRL)
2137                                 dib9000_fw_pid_filter_ctrl(state->fe[0],
2138                                                 state->pid_ctrl[index_pid_filter_cmd].onoff);
2139                         else if (state->pid_ctrl[index_pid_filter_cmd].cmd == DIB9000_PID_FILTER)
2140                                 dib9000_fw_pid_filter(state->fe[0],
2141                                                 state->pid_ctrl[index_pid_filter_cmd].id,
2142                                                 state->pid_ctrl[index_pid_filter_cmd].pid,
2143                                                 state->pid_ctrl[index_pid_filter_cmd].onoff);
2144                 }
2145         }
2146         /* do not postpone any more the pid filtering */
2147         state->pid_ctrl_index = -2;
2148
2149         return 0;
2150 }
2151
2152 static u16 dib9000_read_lock(struct dvb_frontend *fe)
2153 {
2154         struct dib9000_state *state = fe->demodulator_priv;
2155
2156         return dib9000_read_word(state, 535);
2157 }
2158
2159 static int dib9000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
2160 {
2161         struct dib9000_state *state = fe->demodulator_priv;
2162         u8 index_frontend;
2163         u16 lock = 0, lock_slave = 0;
2164
2165         if (mutex_lock_interruptible(&state->demod_lock) < 0) {
2166                 dprintk("could not get the lock");
2167                 return -EINTR;
2168         }
2169         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2170                 lock_slave |= dib9000_read_lock(state->fe[index_frontend]);
2171
2172         lock = dib9000_read_word(state, 535);
2173
2174         *stat = 0;
2175
2176         if ((lock & 0x8000) || (lock_slave & 0x8000))
2177                 *stat |= FE_HAS_SIGNAL;
2178         if ((lock & 0x3000) || (lock_slave & 0x3000))
2179                 *stat |= FE_HAS_CARRIER;
2180         if ((lock & 0x0100) || (lock_slave & 0x0100))
2181                 *stat |= FE_HAS_VITERBI;
2182         if (((lock & 0x0038) == 0x38) || ((lock_slave & 0x0038) == 0x38))
2183                 *stat |= FE_HAS_SYNC;
2184         if ((lock & 0x0008) || (lock_slave & 0x0008))
2185                 *stat |= FE_HAS_LOCK;
2186
2187         mutex_unlock(&state->demod_lock);
2188
2189         return 0;
2190 }
2191
2192 static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber)
2193 {
2194         struct dib9000_state *state = fe->demodulator_priv;
2195         u16 *c;
2196         int ret = 0;
2197
2198         if (mutex_lock_interruptible(&state->demod_lock) < 0) {
2199                 dprintk("could not get the lock");
2200                 return -EINTR;
2201         }
2202         if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
2203                 dprintk("could not get the lock");
2204                 ret = -EINTR;
2205                 goto error;
2206         }
2207         if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
2208                 mutex_unlock(&state->platform.risc.mem_mbx_lock);
2209                 ret = -EIO;
2210                 goto error;
2211         }
2212         dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR,
2213                         state->i2c_read_buffer, 16 * 2);
2214         mutex_unlock(&state->platform.risc.mem_mbx_lock);
2215
2216         c = (u16 *)state->i2c_read_buffer;
2217
2218         *ber = c[10] << 16 | c[11];
2219
2220 error:
2221         mutex_unlock(&state->demod_lock);
2222         return ret;
2223 }
2224
2225 static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2226 {
2227         struct dib9000_state *state = fe->demodulator_priv;
2228         u8 index_frontend;
2229         u16 *c = (u16 *)state->i2c_read_buffer;
2230         u16 val;
2231         int ret = 0;
2232
2233         if (mutex_lock_interruptible(&state->demod_lock) < 0) {
2234                 dprintk("could not get the lock");
2235                 return -EINTR;
2236         }
2237         *strength = 0;
2238         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2239                 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
2240                 if (val > 65535 - *strength)
2241                         *strength = 65535;
2242                 else
2243                         *strength += val;
2244         }
2245
2246         if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
2247                 dprintk("could not get the lock");
2248                 ret = -EINTR;
2249                 goto error;
2250         }
2251         if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
2252                 mutex_unlock(&state->platform.risc.mem_mbx_lock);
2253                 ret = -EIO;
2254                 goto error;
2255         }
2256         dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
2257         mutex_unlock(&state->platform.risc.mem_mbx_lock);
2258
2259         val = 65535 - c[4];
2260         if (val > 65535 - *strength)
2261                 *strength = 65535;
2262         else
2263                 *strength += val;
2264
2265 error:
2266         mutex_unlock(&state->demod_lock);
2267         return ret;
2268 }
2269
2270 static u32 dib9000_get_snr(struct dvb_frontend *fe)
2271 {
2272         struct dib9000_state *state = fe->demodulator_priv;
2273         u16 *c = (u16 *)state->i2c_read_buffer;
2274         u32 n, s, exp;
2275         u16 val;
2276
2277         if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
2278                 dprintk("could not get the lock");
2279                 return 0;
2280         }
2281         if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
2282                 mutex_unlock(&state->platform.risc.mem_mbx_lock);
2283                 return 0;
2284         }
2285         dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
2286         mutex_unlock(&state->platform.risc.mem_mbx_lock);
2287
2288         val = c[7];
2289         n = (val >> 4) & 0xff;
2290         exp = ((val & 0xf) << 2);
2291         val = c[8];
2292         exp += ((val >> 14) & 0x3);
2293         if ((exp & 0x20) != 0)
2294                 exp -= 0x40;
2295         n <<= exp + 16;
2296
2297         s = (val >> 6) & 0xFF;
2298         exp = (val & 0x3F);
2299         if ((exp & 0x20) != 0)
2300                 exp -= 0x40;
2301         s <<= exp + 16;
2302
2303         if (n > 0) {
2304                 u32 t = (s / n) << 16;
2305                 return t + ((s << 16) - n * t) / n;
2306         }
2307         return 0xffffffff;
2308 }
2309
2310 static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr)
2311 {
2312         struct dib9000_state *state = fe->demodulator_priv;
2313         u8 index_frontend;
2314         u32 snr_master;
2315
2316         if (mutex_lock_interruptible(&state->demod_lock) < 0) {
2317                 dprintk("could not get the lock");
2318                 return -EINTR;
2319         }
2320         snr_master = dib9000_get_snr(fe);
2321         for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2322                 snr_master += dib9000_get_snr(state->fe[index_frontend]);
2323
2324         if ((snr_master >> 16) != 0) {
2325                 snr_master = 10 * intlog10(snr_master >> 16);
2326                 *snr = snr_master / ((1 << 24) / 10);
2327         } else
2328                 *snr = 0;
2329
2330         mutex_unlock(&state->demod_lock);
2331
2332         return 0;
2333 }
2334
2335 static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
2336 {
2337         struct dib9000_state *state = fe->demodulator_priv;
2338         u16 *c = (u16 *)state->i2c_read_buffer;
2339         int ret = 0;
2340
2341         if (mutex_lock_interruptible(&state->demod_lock) < 0) {
2342                 dprintk("could not get the lock");
2343                 return -EINTR;
2344         }
2345         if (mutex_lock_interruptible(&state->platform.risc.mem_mbx_lock) < 0) {
2346                 dprintk("could not get the lock");
2347                 ret = -EINTR;
2348                 goto error;
2349         }
2350         if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
2351                 mutex_unlock(&state->platform.risc.mem_mbx_lock);
2352                 ret = -EIO;
2353                 goto error;
2354         }
2355         dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
2356         mutex_unlock(&state->platform.risc.mem_mbx_lock);
2357
2358         *unc = c[12];
2359
2360 error:
2361         mutex_unlock(&state->demod_lock);
2362         return ret;
2363 }
2364
2365 int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr)
2366 {
2367         int k = 0, ret = 0;
2368         u8 new_addr = 0;
2369         struct i2c_device client = {.i2c_adap = i2c };
2370
2371         client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
2372         if (!client.i2c_write_buffer) {
2373                 dprintk("%s: not enough memory", __func__);
2374                 return -ENOMEM;
2375         }
2376         client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
2377         if (!client.i2c_read_buffer) {
2378                 dprintk("%s: not enough memory", __func__);
2379                 ret = -ENOMEM;
2380                 goto error_memory;
2381         }
2382
2383         client.i2c_addr = default_addr + 16;
2384         dib9000_i2c_write16(&client, 1796, 0x0);
2385
2386         for (k = no_of_demods - 1; k >= 0; k--) {
2387                 /* designated i2c address */
2388                 new_addr = first_addr + (k << 1);
2389                 client.i2c_addr = default_addr;
2390
2391                 dib9000_i2c_write16(&client, 1817, 3);
2392                 dib9000_i2c_write16(&client, 1796, 0);
2393                 dib9000_i2c_write16(&client, 1227, 1);
2394                 dib9000_i2c_write16(&client, 1227, 0);
2395
2396                 client.i2c_addr = new_addr;
2397                 dib9000_i2c_write16(&client, 1817, 3);
2398                 dib9000_i2c_write16(&client, 1796, 0);
2399                 dib9000_i2c_write16(&client, 1227, 1);
2400                 dib9000_i2c_write16(&client, 1227, 0);
2401
2402                 if (dib9000_identify(&client) == 0) {
2403                         client.i2c_addr = default_addr;
2404                         if (dib9000_identify(&client) == 0) {
2405                                 dprintk("DiB9000 #%d: not identified", k);
2406                                 ret = -EIO;
2407                                 goto error;
2408                         }
2409                 }
2410
2411                 dib9000_i2c_write16(&client, 1795, (1 << 10) | (4 << 6));
2412                 dib9000_i2c_write16(&client, 1794, (new_addr << 2) | 2);
2413
2414                 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
2415         }
2416
2417         for (k = 0; k < no_of_demods; k++) {
2418                 new_addr = first_addr | (k << 1);
2419                 client.i2c_addr = new_addr;
2420
2421                 dib9000_i2c_write16(&client, 1794, (new_addr << 2));
2422                 dib9000_i2c_write16(&client, 1795, 0);
2423         }
2424
2425 error:
2426         kfree(client.i2c_read_buffer);
2427 error_memory:
2428         kfree(client.i2c_write_buffer);
2429
2430         return ret;
2431 }
2432 EXPORT_SYMBOL(dib9000_i2c_enumeration);
2433
2434 int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
2435 {
2436         struct dib9000_state *state = fe->demodulator_priv;
2437         u8 index_frontend = 1;
2438
2439         while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2440                 index_frontend++;
2441         if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
2442                 dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
2443                 state->fe[index_frontend] = fe_slave;
2444                 return 0;
2445         }
2446
2447         dprintk("too many slave frontend");
2448         return -ENOMEM;
2449 }
2450 EXPORT_SYMBOL(dib9000_set_slave_frontend);
2451
2452 int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
2453 {
2454         struct dib9000_state *state = fe->demodulator_priv;
2455         u8 index_frontend = 1;
2456
2457         while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2458                 index_frontend++;
2459         if (index_frontend != 1) {
2460                 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend - 1], index_frontend - 1);
2461                 state->fe[index_frontend] = NULL;
2462                 return 0;
2463         }
2464
2465         dprintk("no frontend to be removed");
2466         return -ENODEV;
2467 }
2468 EXPORT_SYMBOL(dib9000_remove_slave_frontend);
2469
2470 struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
2471 {
2472         struct dib9000_state *state = fe->demodulator_priv;
2473
2474         if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
2475                 return NULL;
2476         return state->fe[slave_index];
2477 }
2478 EXPORT_SYMBOL(dib9000_get_slave_frontend);
2479
2480 static struct dvb_frontend_ops dib9000_ops;
2481 struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg)
2482 {
2483         struct dvb_frontend *fe;
2484         struct dib9000_state *st;
2485         st = kzalloc(sizeof(struct dib9000_state), GFP_KERNEL);
2486         if (st == NULL)
2487                 return NULL;
2488         fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
2489         if (fe == NULL) {
2490                 kfree(st);
2491                 return NULL;
2492         }
2493
2494         memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
2495         st->i2c.i2c_adap = i2c_adap;
2496         st->i2c.i2c_addr = i2c_addr;
2497         st->i2c.i2c_write_buffer = st->i2c_write_buffer;
2498         st->i2c.i2c_read_buffer = st->i2c_read_buffer;
2499
2500         st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS;
2501         st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES;
2502         st->gpio_pwm_pos = DIB9000_GPIO_DEFAULT_PWM_POS;
2503
2504         mutex_init(&st->platform.risc.mbx_if_lock);
2505         mutex_init(&st->platform.risc.mbx_lock);
2506         mutex_init(&st->platform.risc.mem_lock);
2507         mutex_init(&st->platform.risc.mem_mbx_lock);
2508         mutex_init(&st->demod_lock);
2509         st->get_frontend_internal = 0;
2510
2511         st->pid_ctrl_index = -2;
2512
2513         st->fe[0] = fe;
2514         fe->demodulator_priv = st;
2515         memcpy(&st->fe[0]->ops, &dib9000_ops, sizeof(struct dvb_frontend_ops));
2516
2517         /* Ensure the output mode remains at the previous default if it's
2518          * not specifically set by the caller.
2519          */
2520         if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2521                 st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO;
2522
2523         if (dib9000_identify(&st->i2c) == 0)
2524                 goto error;
2525
2526         dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c.i2c_adap, st->i2c.i2c_addr);
2527
2528         st->tuner_adap.dev.parent = i2c_adap->dev.parent;
2529         strncpy(st->tuner_adap.name, "DIB9000_FW TUNER ACCESS", sizeof(st->tuner_adap.name));
2530         st->tuner_adap.algo = &dib9000_tuner_algo;
2531         st->tuner_adap.algo_data = NULL;
2532         i2c_set_adapdata(&st->tuner_adap, st);
2533         if (i2c_add_adapter(&st->tuner_adap) < 0)
2534                 goto error;
2535
2536         st->component_bus.dev.parent = i2c_adap->dev.parent;
2537         strncpy(st->component_bus.name, "DIB9000_FW COMPONENT BUS ACCESS", sizeof(st->component_bus.name));
2538         st->component_bus.algo = &dib9000_component_bus_algo;
2539         st->component_bus.algo_data = NULL;
2540         st->component_bus_speed = 340;
2541         i2c_set_adapdata(&st->component_bus, st);
2542         if (i2c_add_adapter(&st->component_bus) < 0)
2543                 goto component_bus_add_error;
2544
2545         dib9000_fw_reset(fe);
2546
2547         return fe;
2548
2549 component_bus_add_error:
2550         i2c_del_adapter(&st->tuner_adap);
2551 error:
2552         kfree(st);
2553         return NULL;
2554 }
2555 EXPORT_SYMBOL(dib9000_attach);
2556
2557 static struct dvb_frontend_ops dib9000_ops = {
2558         .delsys = { SYS_DVBT },
2559         .info = {
2560                  .name = "DiBcom 9000",
2561                  .frequency_min = 44250000,
2562                  .frequency_max = 867250000,
2563                  .frequency_stepsize = 62500,
2564                  .caps = FE_CAN_INVERSION_AUTO |
2565                  FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2566                  FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2567                  FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
2568                  FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
2569                  },
2570
2571         .release = dib9000_release,
2572
2573         .init = dib9000_wakeup,
2574         .sleep = dib9000_sleep,
2575
2576         .set_frontend = dib9000_set_frontend,
2577         .get_tune_settings = dib9000_fe_get_tune_settings,
2578         .get_frontend = dib9000_get_frontend,
2579
2580         .read_status = dib9000_read_status,
2581         .read_ber = dib9000_read_ber,
2582         .read_signal_strength = dib9000_read_signal_strength,
2583         .read_snr = dib9000_read_snr,
2584         .read_ucblocks = dib9000_read_unc_blocks,
2585 };
2586
2587 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
2588 MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
2589 MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator");
2590 MODULE_LICENSE("GPL");