drivers/input/touchscreen/hideep.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012-2017 Hideep, Inc.
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/of.h>
   8 #include <linux/firmware.h>
   9 #include <linux/delay.h>
  10 #include <linux/gpio/consumer.h>
  11 #include <linux/i2c.h>
  12 #include <linux/acpi.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/regmap.h>
  15 #include <linux/sysfs.h>
  16 #include <linux/input.h>
  17 #include <linux/input/mt.h>
  18 #include <linux/input/touchscreen.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <asm/unaligned.h>
  21
  22 #define HIDEEP_TS_NAME                  "HiDeep Touchscreen"
  23 #define HIDEEP_I2C_NAME                 "hideep_ts"
  24
  25 #define HIDEEP_MT_MAX                   10
  26 #define HIDEEP_KEY_MAX                  3
  27
  28 /* count(2) + touch data(100) + key data(6) */
  29 #define HIDEEP_MAX_EVENT                108UL
  30
  31 #define HIDEEP_TOUCH_EVENT_INDEX        2
  32 #define HIDEEP_KEY_EVENT_INDEX          102
  33
  34 /* Touch & key event */
  35 #define HIDEEP_EVENT_ADDR               0x240
  36
  37 /* command list */
  38 #define HIDEEP_RESET_CMD                0x9800
  39
  40 /* event bit */
  41 #define HIDEEP_MT_RELEASED              BIT(4)
  42 #define HIDEEP_KEY_PRESSED              BIT(7)
  43 #define HIDEEP_KEY_FIRST_PRESSED        BIT(8)
  44 #define HIDEEP_KEY_PRESSED_MASK         (HIDEEP_KEY_PRESSED | \
  45                                          HIDEEP_KEY_FIRST_PRESSED)
  46
  47 #define HIDEEP_KEY_IDX_MASK             0x0f
  48
  49 /* For NVM */
  50 #define HIDEEP_YRAM_BASE                0x40000000
  51 #define HIDEEP_PERIPHERAL_BASE          0x50000000
  52 #define HIDEEP_ESI_BASE                 (HIDEEP_PERIPHERAL_BASE + 0x00000000)
  53 #define HIDEEP_FLASH_BASE               (HIDEEP_PERIPHERAL_BASE + 0x01000000)
  54 #define HIDEEP_SYSCON_BASE              (HIDEEP_PERIPHERAL_BASE + 0x02000000)
  55
  56 #define HIDEEP_SYSCON_MOD_CON           (HIDEEP_SYSCON_BASE + 0x0000)
  57 #define HIDEEP_SYSCON_SPC_CON           (HIDEEP_SYSCON_BASE + 0x0004)
  58 #define HIDEEP_SYSCON_CLK_CON           (HIDEEP_SYSCON_BASE + 0x0008)
  59 #define HIDEEP_SYSCON_CLK_ENA           (HIDEEP_SYSCON_BASE + 0x000C)
  60 #define HIDEEP_SYSCON_RST_CON           (HIDEEP_SYSCON_BASE + 0x0010)
  61 #define HIDEEP_SYSCON_WDT_CON           (HIDEEP_SYSCON_BASE + 0x0014)
  62 #define HIDEEP_SYSCON_WDT_CNT           (HIDEEP_SYSCON_BASE + 0x0018)
  63 #define HIDEEP_SYSCON_PWR_CON           (HIDEEP_SYSCON_BASE + 0x0020)
  64 #define HIDEEP_SYSCON_PGM_ID            (HIDEEP_SYSCON_BASE + 0x00F4)
  65
  66 #define HIDEEP_FLASH_CON                (HIDEEP_FLASH_BASE + 0x0000)
  67 #define HIDEEP_FLASH_STA                (HIDEEP_FLASH_BASE + 0x0004)
  68 #define HIDEEP_FLASH_CFG                (HIDEEP_FLASH_BASE + 0x0008)
  69 #define HIDEEP_FLASH_TIM                (HIDEEP_FLASH_BASE + 0x000C)
  70 #define HIDEEP_FLASH_CACHE_CFG          (HIDEEP_FLASH_BASE + 0x0010)
  71 #define HIDEEP_FLASH_PIO_SIG            (HIDEEP_FLASH_BASE + 0x400000)
  72
  73 #define HIDEEP_ESI_TX_INVALID           (HIDEEP_ESI_BASE + 0x0008)
  74
  75 #define HIDEEP_PERASE                   0x00040000
  76 #define HIDEEP_WRONLY                   0x00100000
  77
  78 #define HIDEEP_NVM_MASK_OFS             0x0000000C
  79 #define HIDEEP_NVM_DEFAULT_PAGE         0
  80 #define HIDEEP_NVM_SFR_WPAGE            1
  81 #define HIDEEP_NVM_SFR_RPAGE            2
  82
  83 #define HIDEEP_PIO_SIG                  0x00400000
  84 #define HIDEEP_PROT_MODE                0x03400000
  85
  86 #define HIDEEP_NVM_PAGE_SIZE            128
  87
  88 #define HIDEEP_DWZ_INFO                 0x000002C0
  89
  90 struct hideep_event {
  91         __le16 x;
  92         __le16 y;
  93         __le16 z;
  94         u8 w;
  95         u8 flag;
  96         u8 type;
  97         u8 index;
  98 };
  99
 100 struct dwz_info {
 101         __be32 code_start;
 102         u8 code_crc[12];
 103
 104         __be32 c_code_start;
 105         __be16 gen_ver;
 106         __be16 c_code_len;
 107
 108         __be32 vr_start;
 109         __be16 rsv0;
 110         __be16 vr_len;
 111
 112         __be32 ft_start;
 113         __be16 vr_version;
 114         __be16 ft_len;
 115
 116         __be16 core_ver;
 117         __be16 boot_ver;
 118
 119         __be16 release_ver;
 120         __be16 custom_ver;
 121
 122         u8 factory_id;
 123         u8 panel_type;
 124         u8 model_name[6];
 125
 126         __be16 extra_option;
 127         __be16 product_code;
 128
 129         __be16 vendor_id;
 130         __be16 product_id;
 131 };
 132
 133 struct pgm_packet {
 134         struct {
 135                 u8 unused[3];
 136                 u8 len;
 137                 __be32 addr;
 138         } header;
 139         __be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)];
 140 };
 141
 142 #define HIDEEP_XFER_BUF_SIZE    sizeof(struct pgm_packet)
 143
 144 struct hideep_ts {
 145         struct i2c_client *client;
 146         struct input_dev *input_dev;
 147         struct regmap *reg;
 148
 149         struct touchscreen_properties prop;
 150
 151         struct gpio_desc *reset_gpio;
 152
 153         struct regulator *vcc_vdd;
 154         struct regulator *vcc_vid;
 155
 156         struct mutex dev_mutex;
 157
 158         u32 tch_count;
 159         u32 lpm_count;
 160
 161         /*
 162          * Data buffer to read packet from the device (contacts and key
 163          * states). We align it on double-word boundary to keep word-sized
 164          * fields in contact data and double-word-sized fields in program
 165          * packet aligned.
 166          */
 167         u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4);
 168
 169         int key_num;
 170         u32 key_codes[HIDEEP_KEY_MAX];
 171
 172         struct dwz_info dwz_info;
 173
 174         unsigned int fw_size;
 175         u32 nvm_mask;
 176 };
 177
 178 static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr,
 179                             const __be32 *data, size_t count)
 180 {
 181         struct pgm_packet *packet = (void *)ts->xfer_buf;
 182         size_t len = count * sizeof(*data);
 183         struct i2c_msg msg = {
 184                 .addr   = ts->client->addr,
 185                 .len    = len + sizeof(packet->header.len) +
 186                                 sizeof(packet->header.addr),
 187                 .buf    = &packet->header.len,
 188         };
 189         int ret;
 190
 191         if (len > HIDEEP_NVM_PAGE_SIZE)
 192                 return -EINVAL;
 193
 194         packet->header.len = 0x80 | (count - 1);
 195         packet->header.addr = cpu_to_be32(addr);
 196         memcpy(packet->payload, data, len);
 197
 198         ret = i2c_transfer(ts->client->adapter, &msg, 1);
 199         if (ret != 1)
 200                 return ret < 0 ? ret : -EIO;
 201
 202         return 0;
 203 }
 204
 205 static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr,
 206                             __be32 *data, size_t count)
 207 {
 208         struct pgm_packet *packet = (void *)ts->xfer_buf;
 209         size_t len = count * sizeof(*data);
 210         struct i2c_msg msg[] = {
 211                 {
 212                         .addr   = ts->client->addr,
 213                         .len    = sizeof(packet->header.len) +
 214                                         sizeof(packet->header.addr),
 215                         .buf    = &packet->header.len,
 216                 },
 217                 {
 218                         .addr   = ts->client->addr,
 219                         .flags  = I2C_M_RD,
 220                         .len    = len,
 221                         .buf    = (u8 *)data,
 222                 },
 223         };
 224         int ret;
 225
 226         if (len > HIDEEP_NVM_PAGE_SIZE)
 227                 return -EINVAL;
 228
 229         packet->header.len = count - 1;
 230         packet->header.addr = cpu_to_be32(addr);
 231
 232         ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg));
 233         if (ret != ARRAY_SIZE(msg))
 234                 return ret < 0 ? ret : -EIO;
 235
 236         return 0;
 237 }
 238
 239 static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val)
 240 {
 241         __be32 data;
 242         int error;
 243
 244         error = hideep_pgm_r_mem(ts, addr, &data, 1);
 245         if (error) {
 246                 dev_err(&ts->client->dev,
 247                         "read of register %#08x failed: %d\n",
 248                         addr, error);
 249                 return error;
 250         }
 251
 252         *val = be32_to_cpu(data);
 253         return 0;
 254 }
 255
 256 static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val)
 257 {
 258         __be32 data = cpu_to_be32(val);
 259         int error;
 260
 261         error = hideep_pgm_w_mem(ts, addr, &data, 1);
 262         if (error) {
 263                 dev_err(&ts->client->dev,
 264                         "write to register %#08x (%#08x) failed: %d\n",
 265                         addr, val, error);
 266                 return error;
 267         }
 268
 269         return 0;
 270 }
 271
 272 #define SW_RESET_IN_PGM(clk)                                    \
 273 {                                                               \
 274         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk));     \
 275         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03);      \
 276         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x01);      \
 277 }
 278
 279 #define SET_FLASH_PIO(ce)                                       \
 280         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON,                  \
 281                          0x01 | ((ce) << 1))
 282
 283 #define SET_PIO_SIG(x, y)                                       \
 284         hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y))
 285
 286 #define SET_FLASH_HWCONTROL()                                   \
 287         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00)
 288
 289 #define NVM_W_SFR(x, y)                                         \
 290 {                                                               \
 291         SET_FLASH_PIO(1);                                       \
 292         SET_PIO_SIG(x, y);                                      \
 293         SET_FLASH_PIO(0);                                       \
 294 }
 295
 296 static void hideep_pgm_set(struct hideep_ts *ts)
 297 {
 298         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00);
 299         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00);
 300         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF);
 301         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01);
 302         hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01);
 303         hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03);
 304         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00);
 305 }
 306
 307 static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern)
 308 {
 309         u16 p1 = 0xAF39;
 310         u16 p2 = 0xDF9D;
 311         int error;
 312
 313         error = regmap_bulk_write(ts->reg, p1, &p2, 1);
 314         if (error) {
 315                 dev_err(&ts->client->dev,
 316                         "%s: regmap_bulk_write() failed with %d\n",
 317                         __func__, error);
 318                 return error;
 319         }
 320
 321         usleep_range(1000, 1100);
 322
 323         /* flush invalid Tx load register */
 324         error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01);
 325         if (error)
 326                 return error;
 327
 328         error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern);
 329         if (error)
 330                 return error;
 331
 332         return 0;
 333 }
 334
 335 static int hideep_enter_pgm(struct hideep_ts *ts)
 336 {
 337         int retry_count = 10;
 338         u32 pattern;
 339         int error;
 340
 341         while (retry_count--) {
 342                 error = hideep_pgm_get_pattern(ts, &pattern);
 343                 if (error) {
 344                         dev_err(&ts->client->dev,
 345                                 "hideep_pgm_get_pattern failed: %d\n", error);
 346                 } else if (pattern != 0x39AF9DDF) {
 347                         dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n",
 348                                 __func__, pattern);
 349                 } else {
 350                         dev_dbg(&ts->client->dev, "found magic code");
 351
 352                         hideep_pgm_set(ts);
 353                         usleep_range(1000, 1100);
 354
 355                         return 0;
 356                 }
 357         }
 358
 359         dev_err(&ts->client->dev, "failed to  enter pgm mode\n");
 360         SW_RESET_IN_PGM(1000);
 361         return -EIO;
 362 }
 363
 364 static void hideep_nvm_unlock(struct hideep_ts *ts)
 365 {
 366         u32 unmask_code;
 367
 368         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE);
 369         hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code);
 370         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
 371
 372         /* make it unprotected code */
 373         unmask_code &= ~HIDEEP_PROT_MODE;
 374
 375         /* compare unmask code */
 376         if (unmask_code != ts->nvm_mask)
 377                 dev_warn(&ts->client->dev,
 378                          "read mask code different %#08x vs %#08x",
 379                          unmask_code, ts->nvm_mask);
 380
 381         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE);
 382         SET_FLASH_PIO(0);
 383
 384         NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask);
 385         SET_FLASH_HWCONTROL();
 386         hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
 387 }
 388
 389 static int hideep_check_status(struct hideep_ts *ts)
 390 {
 391         int time_out = 100;
 392         int status;
 393         int error;
 394
 395         while (time_out--) {
 396                 error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status);
 397                 if (!error && status)
 398                         return 0;
 399
 400                 usleep_range(1000, 1100);
 401         }
 402
 403         return -ETIMEDOUT;
 404 }
 405
 406 static int hideep_program_page(struct hideep_ts *ts, u32 addr,
 407                                const __be32 *ucode, size_t xfer_count)
 408 {
 409         u32 val;
 410         int error;
 411
 412         error = hideep_check_status(ts);
 413         if (error)
 414                 return -EBUSY;
 415
 416         addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1);
 417
 418         SET_FLASH_PIO(0);
 419         SET_FLASH_PIO(1);
 420
 421         /* erase page */
 422         SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF);
 423
 424         SET_FLASH_PIO(0);
 425
 426         error = hideep_check_status(ts);
 427         if (error)
 428                 return -EBUSY;
 429
 430         /* write page */
 431         SET_FLASH_PIO(1);
 432
 433         val = be32_to_cpu(ucode[0]);
 434         SET_PIO_SIG(HIDEEP_WRONLY | addr, val);
 435
 436         hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY,
 437                          ucode, xfer_count);
 438
 439         val = be32_to_cpu(ucode[xfer_count - 1]);
 440         SET_PIO_SIG(124, val);
 441
 442         SET_FLASH_PIO(0);
 443
 444         usleep_range(1000, 1100);
 445
 446         error = hideep_check_status(ts);
 447         if (error)
 448                 return -EBUSY;
 449
 450         SET_FLASH_HWCONTROL();
 451
 452         return 0;
 453 }
 454
 455 static int hideep_program_nvm(struct hideep_ts *ts,
 456                               const __be32 *ucode, size_t ucode_len)
 457 {
 458         struct pgm_packet *packet_r = (void *)ts->xfer_buf;
 459         __be32 *current_ucode = packet_r->payload;
 460         size_t xfer_len;
 461         size_t xfer_count;
 462         u32 addr = 0;
 463         int error;
 464
 465         hideep_nvm_unlock(ts);
 466
 467         while (ucode_len > 0) {
 468                 xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
 469                 xfer_count = xfer_len / sizeof(*ucode);
 470
 471                 error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
 472                                          current_ucode, xfer_count);
 473                 if (error) {
 474                         dev_err(&ts->client->dev,
 475                                 "%s: failed to read page at offset %#08x: %d\n",
 476                                 __func__, addr, error);
 477                         return error;
 478                 }
 479
 480                 /* See if the page needs updating */
 481                 if (memcmp(ucode, current_ucode, xfer_len)) {
 482                         error = hideep_program_page(ts, addr,
 483                                                     ucode, xfer_count);
 484                         if (error) {
 485                                 dev_err(&ts->client->dev,
 486                                         "%s: iwrite failure @%#08x: %d\n",
 487                                         __func__, addr, error);
 488                                 return error;
 489                         }
 490
 491                         usleep_range(1000, 1100);
 492                 }
 493
 494                 ucode += xfer_count;
 495                 addr += xfer_len;
 496                 ucode_len -= xfer_len;
 497         }
 498
 499         return 0;
 500 }
 501
 502 static int hideep_verify_nvm(struct hideep_ts *ts,
 503                              const __be32 *ucode, size_t ucode_len)
 504 {
 505         struct pgm_packet *packet_r = (void *)ts->xfer_buf;
 506         __be32 *current_ucode = packet_r->payload;
 507         size_t xfer_len;
 508         size_t xfer_count;
 509         u32 addr = 0;
 510         int i;
 511         int error;
 512
 513         while (ucode_len > 0) {
 514                 xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
 515                 xfer_count = xfer_len / sizeof(*ucode);
 516
 517                 error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
 518                                          current_ucode, xfer_count);
 519                 if (error) {
 520                         dev_err(&ts->client->dev,
 521                                 "%s: failed to read page at offset %#08x: %d\n",
 522                                 __func__, addr, error);
 523                         return error;
 524                 }
 525
 526                 if (memcmp(ucode, current_ucode, xfer_len)) {
 527                         const u8 *ucode_bytes = (const u8 *)ucode;
 528                         const u8 *current_bytes = (const u8 *)current_ucode;
 529
 530                         for (i = 0; i < xfer_len; i++)
 531                                 if (ucode_bytes[i] != current_bytes[i])
 532                                         dev_err(&ts->client->dev,
 533                                                 "%s: mismatch @%#08x: (%#02x vs %#02x)\n",
 534                                                 __func__, addr + i,
 535                                                 ucode_bytes[i],
 536                                                 current_bytes[i]);
 537
 538                         return -EIO;
 539                 }
 540
 541                 ucode += xfer_count;
 542                 addr += xfer_len;
 543                 ucode_len -= xfer_len;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int hideep_load_dwz(struct hideep_ts *ts)
 550 {
 551         u16 product_code;
 552         int error;
 553
 554         error = hideep_enter_pgm(ts);
 555         if (error)
 556                 return error;
 557
 558         msleep(50);
 559
 560         error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO,
 561                                  (void *)&ts->dwz_info,
 562                                  sizeof(ts->dwz_info) / sizeof(__be32));
 563
 564         SW_RESET_IN_PGM(10);
 565         msleep(50);
 566
 567         if (error) {
 568                 dev_err(&ts->client->dev,
 569                         "failed to fetch DWZ data: %d\n", error);
 570                 return error;
 571         }
 572
 573         product_code = be16_to_cpu(ts->dwz_info.product_code);
 574
 575         switch (product_code & 0xF0) {
 576         case 0x40:
 577                 dev_dbg(&ts->client->dev, "used crimson IC");
 578                 ts->fw_size = 1024 * 48;
 579                 ts->nvm_mask = 0x00310000;
 580                 break;
 581         case 0x60:
 582                 dev_dbg(&ts->client->dev, "used lime IC");
 583                 ts->fw_size = 1024 * 64;
 584                 ts->nvm_mask = 0x0030027B;
 585                 break;
 586         default:
 587                 dev_err(&ts->client->dev, "product code is wrong: %#04x",
 588                         product_code);
 589                 return -EINVAL;
 590         }
 591
 592         dev_dbg(&ts->client->dev, "firmware release version: %#04x",
 593                 be16_to_cpu(ts->dwz_info.release_ver));
 594
 595         return 0;
 596 }
 597
 598 static int hideep_flash_firmware(struct hideep_ts *ts,
 599                                  const __be32 *ucode, size_t ucode_len)
 600 {
 601         int retry_cnt = 3;
 602         int error;
 603
 604         while (retry_cnt--) {
 605                 error = hideep_program_nvm(ts, ucode, ucode_len);
 606                 if (!error) {
 607                         error = hideep_verify_nvm(ts, ucode, ucode_len);
 608                         if (!error)
 609                                 return 0;
 610                 }
 611         }
 612
 613         return error;
 614 }
 615
 616 static int hideep_update_firmware(struct hideep_ts *ts,
 617                                   const __be32 *ucode, size_t ucode_len)
 618 {
 619         int error, error2;
 620
 621         dev_dbg(&ts->client->dev, "starting firmware update");
 622
 623         /* enter program mode */
 624         error = hideep_enter_pgm(ts);
 625         if (error)
 626                 return error;
 627
 628         error = hideep_flash_firmware(ts, ucode, ucode_len);
 629         if (error)
 630                 dev_err(&ts->client->dev,
 631                         "firmware update failed: %d\n", error);
 632         else
 633                 dev_dbg(&ts->client->dev, "firmware updated successfully\n");
 634
 635         SW_RESET_IN_PGM(1000);
 636
 637         error2 = hideep_load_dwz(ts);
 638         if (error2)
 639                 dev_err(&ts->client->dev,
 640                         "failed to load dwz after firmware update: %d\n",
 641                         error2);
 642
 643         return error ?: error2;
 644 }
 645
 646 static int hideep_power_on(struct hideep_ts *ts)
 647 {
 648         int error = 0;
 649
 650         error = regulator_enable(ts->vcc_vdd);
 651         if (error)
 652                 dev_err(&ts->client->dev,
 653                         "failed to enable 'vdd' regulator: %d", error);
 654
 655         usleep_range(999, 1000);
 656
 657         error = regulator_enable(ts->vcc_vid);
 658         if (error)
 659                 dev_err(&ts->client->dev,
 660                         "failed to enable 'vcc_vid' regulator: %d",
 661                         error);
 662
 663         msleep(30);
 664
 665         if (ts->reset_gpio) {
 666                 gpiod_set_value_cansleep(ts->reset_gpio, 0);
 667         } else {
 668                 error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01);
 669                 if (error)
 670                         dev_err(&ts->client->dev,
 671                                 "failed to send 'reset' command: %d\n", error);
 672         }
 673
 674         msleep(50);
 675
 676         return error;
 677 }
 678
 679 static void hideep_power_off(void *data)
 680 {
 681         struct hideep_ts *ts = data;
 682
 683         if (ts->reset_gpio)
 684                 gpiod_set_value(ts->reset_gpio, 1);
 685
 686         regulator_disable(ts->vcc_vid);
 687         regulator_disable(ts->vcc_vdd);
 688 }
 689
 690 #define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN)
 691
 692 static void hideep_report_slot(struct input_dev *input,
 693                                const struct hideep_event *event)
 694 {
 695         input_mt_slot(input, event->index & 0x0f);
 696         input_mt_report_slot_state(input,
 697                                    __GET_MT_TOOL_TYPE(event->type),
 698                                    !(event->flag & HIDEEP_MT_RELEASED));
 699         if (!(event->flag & HIDEEP_MT_RELEASED)) {
 700                 input_report_abs(input, ABS_MT_POSITION_X,
 701                                  le16_to_cpup(&event->x));
 702                 input_report_abs(input, ABS_MT_POSITION_Y,
 703                                  le16_to_cpup(&event->y));
 704                 input_report_abs(input, ABS_MT_PRESSURE,
 705                                  le16_to_cpup(&event->z));
 706                 input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w);
 707         }
 708 }
 709
 710 static void hideep_parse_and_report(struct hideep_ts *ts)
 711 {
 712         const struct hideep_event *events =
 713                         (void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX];
 714         const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX];
 715         int touch_count = ts->xfer_buf[0];
 716         int key_count = ts->xfer_buf[1] & 0x0f;
 717         int lpm_count = ts->xfer_buf[1] & 0xf0;
 718         int i;
 719
 720         /* get touch event count */
 721         dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x",
 722                 touch_count, key_count, lpm_count);
 723
 724         touch_count = min(touch_count, HIDEEP_MT_MAX);
 725         for (i = 0; i < touch_count; i++)
 726                 hideep_report_slot(ts->input_dev, events + i);
 727
 728         key_count = min(key_count, HIDEEP_KEY_MAX);
 729         for (i = 0; i < key_count; i++) {
 730                 u8 key_data = keys[i * 2];
 731
 732                 input_report_key(ts->input_dev,
 733                                  ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK],
 734                                  key_data & HIDEEP_KEY_PRESSED_MASK);
 735         }
 736
 737         input_mt_sync_frame(ts->input_dev);
 738         input_sync(ts->input_dev);
 739 }
 740
 741 static irqreturn_t hideep_irq(int irq, void *handle)
 742 {
 743         struct hideep_ts *ts = handle;
 744         int error;
 745
 746         BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE);
 747
 748         error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR,
 749                                  ts->xfer_buf, HIDEEP_MAX_EVENT / 2);
 750         if (error) {
 751                 dev_err(&ts->client->dev, "failed to read events: %d\n", error);
 752                 goto out;
 753         }
 754
 755         hideep_parse_and_report(ts);
 756
 757 out:
 758         return IRQ_HANDLED;
 759 }
 760
 761 static int hideep_get_axis_info(struct hideep_ts *ts)
 762 {
 763         __le16 val[2];
 764         int error;
 765
 766         error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val));
 767         if (error)
 768                 return error;
 769
 770         ts->prop.max_x = le16_to_cpup(val);
 771         ts->prop.max_y = le16_to_cpup(val + 1);
 772
 773         dev_dbg(&ts->client->dev, "X: %d, Y: %d",
 774                 ts->prop.max_x, ts->prop.max_y);
 775
 776         return 0;
 777 }
 778
 779 static int hideep_init_input(struct hideep_ts *ts)
 780 {
 781         struct device *dev = &ts->client->dev;
 782         int i;
 783         int error;
 784
 785         ts->input_dev = devm_input_allocate_device(dev);
 786         if (!ts->input_dev) {
 787                 dev_err(dev, "failed to allocate input device\n");
 788                 return -ENOMEM;
 789         }
 790
 791         ts->input_dev->name = HIDEEP_TS_NAME;
 792         ts->input_dev->id.bustype = BUS_I2C;
 793         input_set_drvdata(ts->input_dev, ts);
 794
 795         input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X);
 796         input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y);
 797         input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0);
 798         input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
 799         input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
 800                              0, MT_TOOL_MAX, 0, 0);
 801         touchscreen_parse_properties(ts->input_dev, true, &ts->prop);
 802
 803         if (ts->prop.max_x == 0 || ts->prop.max_y == 0) {
 804                 error = hideep_get_axis_info(ts);
 805                 if (error)
 806                         return error;
 807         }
 808
 809         error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX,
 810                                     INPUT_MT_DIRECT);
 811         if (error)
 812                 return error;
 813
 814         ts->key_num = device_property_count_u32(dev, "linux,keycodes");
 815         if (ts->key_num > HIDEEP_KEY_MAX) {
 816                 dev_err(dev, "too many keys defined: %d\n",
 817                         ts->key_num);
 818                 return -EINVAL;
 819         }
 820
 821         if (ts->key_num <= 0) {
 822                 dev_dbg(dev,
 823                         "missing or malformed 'linux,keycodes' property\n");
 824         } else {
 825                 error = device_property_read_u32_array(dev, "linux,keycodes",
 826                                                        ts->key_codes,
 827                                                        ts->key_num);
 828                 if (error) {
 829                         dev_dbg(dev, "failed to read keymap: %d", error);
 830                         return error;
 831                 }
 832
 833                 if (ts->key_num) {
 834                         ts->input_dev->keycode = ts->key_codes;
 835                         ts->input_dev->keycodesize = sizeof(ts->key_codes[0]);
 836                         ts->input_dev->keycodemax = ts->key_num;
 837
 838                         for (i = 0; i < ts->key_num; i++)
 839                                 input_set_capability(ts->input_dev, EV_KEY,
 840                                         ts->key_codes[i]);
 841                 }
 842         }
 843
 844         error = input_register_device(ts->input_dev);
 845         if (error) {
 846                 dev_err(dev, "failed to register input device: %d", error);
 847                 return error;
 848         }
 849
 850         return 0;
 851 }
 852
 853 static ssize_t hideep_update_fw(struct device *dev,
 854                                 struct device_attribute *attr,
 855                                 const char *buf, size_t count)
 856 {
 857         struct i2c_client *client = to_i2c_client(dev);
 858         struct hideep_ts *ts = i2c_get_clientdata(client);
 859         const struct firmware *fw_entry;
 860         char *fw_name;
 861         int mode;
 862         int error;
 863
 864         error = kstrtoint(buf, 0, &mode);
 865         if (error)
 866                 return error;
 867
 868         fw_name = kasprintf(GFP_KERNEL, "/*(DEBLOBBED)*/",
 869                             be16_to_cpu(ts->dwz_info.product_id));
 870         if (!fw_name)
 871                 return -ENOMEM;
 872
 873         error = reject_firmware(&fw_entry, fw_name, dev);
 874         if (error) {
 875                 dev_err(dev, "failed to request firmware %s: %d",
 876                         fw_name, error);
 877                 goto out_free_fw_name;
 878         }
 879
 880         if (fw_entry->size % sizeof(__be32)) {
 881                 dev_err(dev, "invalid firmware size %zu\n", fw_entry->size);
 882                 error = -EINVAL;
 883                 goto out_release_fw;
 884         }
 885
 886         if (fw_entry->size > ts->fw_size) {
 887                 dev_err(dev, "fw size (%zu) is too big (memory size %d)\n",
 888                         fw_entry->size, ts->fw_size);
 889                 error = -EFBIG;
 890                 goto out_release_fw;
 891         }
 892
 893         mutex_lock(&ts->dev_mutex);
 894         disable_irq(client->irq);
 895
 896         error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data,
 897                                        fw_entry->size);
 898
 899         enable_irq(client->irq);
 900         mutex_unlock(&ts->dev_mutex);
 901
 902 out_release_fw:
 903         release_firmware(fw_entry);
 904 out_free_fw_name:
 905         kfree(fw_name);
 906
 907         return error ?: count;
 908 }
 909
 910 static ssize_t hideep_fw_version_show(struct device *dev,
 911                                       struct device_attribute *attr, char *buf)
 912 {
 913         struct i2c_client *client = to_i2c_client(dev);
 914         struct hideep_ts *ts = i2c_get_clientdata(client);
 915         ssize_t len;
 916
 917         mutex_lock(&ts->dev_mutex);
 918         len = scnprintf(buf, PAGE_SIZE, "%04x\n",
 919                         be16_to_cpu(ts->dwz_info.release_ver));
 920         mutex_unlock(&ts->dev_mutex);
 921
 922         return len;
 923 }
 924
 925 static ssize_t hideep_product_id_show(struct device *dev,
 926                                       struct device_attribute *attr, char *buf)
 927 {
 928         struct i2c_client *client = to_i2c_client(dev);
 929         struct hideep_ts *ts = i2c_get_clientdata(client);
 930         ssize_t len;
 931
 932         mutex_lock(&ts->dev_mutex);
 933         len = scnprintf(buf, PAGE_SIZE, "%04x\n",
 934                         be16_to_cpu(ts->dwz_info.product_id));
 935         mutex_unlock(&ts->dev_mutex);
 936
 937         return len;
 938 }
 939
 940 static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL);
 941 static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL);
 942 static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw);
 943
 944 static struct attribute *hideep_ts_sysfs_entries[] = {
 945         &dev_attr_version.attr,
 946         &dev_attr_product_id.attr,
 947         &dev_attr_update_fw.attr,
 948         NULL,
 949 };
 950
 951 static const struct attribute_group hideep_ts_attr_group = {
 952         .attrs = hideep_ts_sysfs_entries,
 953 };
 954
 955 static int __maybe_unused hideep_suspend(struct device *dev)
 956 {
 957         struct i2c_client *client = to_i2c_client(dev);
 958         struct hideep_ts *ts = i2c_get_clientdata(client);
 959
 960         disable_irq(client->irq);
 961         hideep_power_off(ts);
 962
 963         return 0;
 964 }
 965
 966 static int __maybe_unused hideep_resume(struct device *dev)
 967 {
 968         struct i2c_client *client = to_i2c_client(dev);
 969         struct hideep_ts *ts = i2c_get_clientdata(client);
 970         int error;
 971
 972         error = hideep_power_on(ts);
 973         if (error) {
 974                 dev_err(&client->dev, "power on failed");
 975                 return error;
 976         }
 977
 978         enable_irq(client->irq);
 979
 980         return 0;
 981 }
 982
 983 static SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume);
 984
 985 static const struct regmap_config hideep_regmap_config = {
 986         .reg_bits = 16,
 987         .reg_format_endian = REGMAP_ENDIAN_LITTLE,
 988         .val_bits = 16,
 989         .val_format_endian = REGMAP_ENDIAN_LITTLE,
 990         .max_register = 0xffff,
 991 };
 992
 993 static int hideep_probe(struct i2c_client *client,
 994                         const struct i2c_device_id *id)
 995 {
 996         struct hideep_ts *ts;
 997         int error;
 998
 999         /* check i2c bus */
1000         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1001                 dev_err(&client->dev, "check i2c device error");
1002                 return -ENODEV;
1003         }
1004
1005         if (client->irq <= 0) {
1006                 dev_err(&client->dev, "missing irq: %d\n", client->irq);
1007                 return -EINVAL;
1008         }
1009
1010         ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
1011         if (!ts)
1012                 return -ENOMEM;
1013
1014         ts->client = client;
1015         i2c_set_clientdata(client, ts);
1016         mutex_init(&ts->dev_mutex);
1017
1018         ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config);
1019         if (IS_ERR(ts->reg)) {
1020                 error = PTR_ERR(ts->reg);
1021                 dev_err(&client->dev,
1022                         "failed to initialize regmap: %d\n", error);
1023                 return error;
1024         }
1025
1026         ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd");
1027         if (IS_ERR(ts->vcc_vdd))
1028                 return PTR_ERR(ts->vcc_vdd);
1029
1030         ts->vcc_vid = devm_regulator_get(&client->dev, "vid");
1031         if (IS_ERR(ts->vcc_vid))
1032                 return PTR_ERR(ts->vcc_vid);
1033
1034         ts->reset_gpio = devm_gpiod_get_optional(&client->dev,
1035                                                  "reset", GPIOD_OUT_HIGH);
1036         if (IS_ERR(ts->reset_gpio))
1037                 return PTR_ERR(ts->reset_gpio);
1038
1039         error = hideep_power_on(ts);
1040         if (error) {
1041                 dev_err(&client->dev, "power on failed: %d\n", error);
1042                 return error;
1043         }
1044
1045         error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts);
1046         if (error)
1047                 return error;
1048
1049         error = hideep_load_dwz(ts);
1050         if (error) {
1051                 dev_err(&client->dev, "failed to load dwz: %d", error);
1052                 return error;
1053         }
1054
1055         error = hideep_init_input(ts);
1056         if (error)
1057                 return error;
1058
1059         error = devm_request_threaded_irq(&client->dev, client->irq,
1060                                           NULL, hideep_irq, IRQF_ONESHOT,
1061                                           client->name, ts);
1062         if (error) {
1063                 dev_err(&client->dev, "failed to request irq %d: %d\n",
1064                         client->irq, error);
1065                 return error;
1066         }
1067
1068         error = devm_device_add_group(&client->dev, &hideep_ts_attr_group);
1069         if (error) {
1070                 dev_err(&client->dev,
1071                         "failed to add sysfs attributes: %d\n", error);
1072                 return error;
1073         }
1074
1075         return 0;
1076 }
1077
1078 static const struct i2c_device_id hideep_i2c_id[] = {
1079         { HIDEEP_I2C_NAME, 0 },
1080         { }
1081 };
1082 MODULE_DEVICE_TABLE(i2c, hideep_i2c_id);
1083
1084 #ifdef CONFIG_ACPI
1085 static const struct acpi_device_id hideep_acpi_id[] = {
1086         { "HIDP0001", 0 },
1087         { }
1088 };
1089 MODULE_DEVICE_TABLE(acpi, hideep_acpi_id);
1090 #endif
1091
1092 #ifdef CONFIG_OF
1093 static const struct of_device_id hideep_match_table[] = {
1094         { .compatible = "hideep,hideep-ts" },
1095         { }
1096 };
1097 MODULE_DEVICE_TABLE(of, hideep_match_table);
1098 #endif
1099
1100 static struct i2c_driver hideep_driver = {
1101         .driver = {
1102                 .name                   = HIDEEP_I2C_NAME,
1103                 .of_match_table         = of_match_ptr(hideep_match_table),
1104                 .acpi_match_table       = ACPI_PTR(hideep_acpi_id),
1105                 .pm                     = &hideep_pm_ops,
1106         },
1107         .id_table       = hideep_i2c_id,
1108         .probe          = hideep_probe,
1109 };
1110
1111 module_i2c_driver(hideep_driver);
1112
1113 MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller");
1114 MODULE_AUTHOR("anthony.kim@hideep.com");
1115 MODULE_LICENSE("GPL v2");