2 * Copyright (c) 2012 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 * This file contains support for diagnostic functions. It is accessed by
37 * opening the qib_diag device, normally minor number 129. Diagnostic use
38 * of the QLogic_IB chip may render the chip or board unusable until the
39 * driver is unloaded, or in some cases, until the system is rebooted.
41 * Accesses to the chip through this interface are not similar to going
42 * through the /sys/bus/pci resource mmap interface.
46 #include <linux/pci.h>
47 #include <linux/poll.h>
48 #include <linux/vmalloc.h>
49 #include <linux/export.h>
51 #include <linux/uaccess.h>
54 #include "qib_common.h"
57 #define pr_fmt(fmt) QIB_DRV_NAME ": " fmt
60 * Each client that opens the diag device must read then write
61 * offset 0, to prevent lossage from random cat or od. diag_state
62 * sequences this "handshake".
64 enum diag_state { UNUSED = 0, OPENED, INIT, READY };
66 /* State for an individual client. PID so children cannot abuse handshake */
67 static struct qib_diag_client {
68 struct qib_diag_client *next;
69 struct qib_devdata *dd;
71 enum diag_state state;
75 * Get a client struct. Recycled if possible, else kmalloc.
76 * Must be called with qib_mutex held
78 static struct qib_diag_client *get_client(struct qib_devdata *dd)
80 struct qib_diag_client *dc;
84 /* got from pool remove it and use */
85 client_pool = dc->next;
87 /* None in pool, alloc and init */
88 dc = kmalloc(sizeof *dc, GFP_KERNEL);
93 dc->pid = current->pid;
100 * Return to pool. Must be called with qib_mutex held
102 static void return_client(struct qib_diag_client *dc)
104 struct qib_devdata *dd = dc->dd;
105 struct qib_diag_client *tdc, *rdc;
108 if (dc == dd->diag_client) {
109 dd->diag_client = dc->next;
112 tdc = dc->dd->diag_client;
114 if (dc == tdc->next) {
115 tdc->next = dc->next;
126 rdc->next = client_pool;
131 static int qib_diag_open(struct inode *in, struct file *fp);
132 static int qib_diag_release(struct inode *in, struct file *fp);
133 static ssize_t qib_diag_read(struct file *fp, char __user *data,
134 size_t count, loff_t *off);
135 static ssize_t qib_diag_write(struct file *fp, const char __user *data,
136 size_t count, loff_t *off);
138 static const struct file_operations diag_file_ops = {
139 .owner = THIS_MODULE,
140 .write = qib_diag_write,
141 .read = qib_diag_read,
142 .open = qib_diag_open,
143 .release = qib_diag_release,
144 .llseek = default_llseek,
147 static atomic_t diagpkt_count = ATOMIC_INIT(0);
148 static struct cdev *diagpkt_cdev;
149 static struct device *diagpkt_device;
151 static ssize_t qib_diagpkt_write(struct file *fp, const char __user *data,
152 size_t count, loff_t *off);
154 static const struct file_operations diagpkt_file_ops = {
155 .owner = THIS_MODULE,
156 .write = qib_diagpkt_write,
157 .llseek = noop_llseek,
160 int qib_diag_add(struct qib_devdata *dd)
165 if (atomic_inc_return(&diagpkt_count) == 1) {
166 ret = qib_cdev_init(QIB_DIAGPKT_MINOR, "ipath_diagpkt",
167 &diagpkt_file_ops, &diagpkt_cdev,
173 snprintf(name, sizeof(name), "ipath_diag%d", dd->unit);
174 ret = qib_cdev_init(QIB_DIAG_MINOR_BASE + dd->unit, name,
175 &diag_file_ops, &dd->diag_cdev,
181 static void qib_unregister_observers(struct qib_devdata *dd);
183 void qib_diag_remove(struct qib_devdata *dd)
185 struct qib_diag_client *dc;
187 if (atomic_dec_and_test(&diagpkt_count))
188 qib_cdev_cleanup(&diagpkt_cdev, &diagpkt_device);
190 qib_cdev_cleanup(&dd->diag_cdev, &dd->diag_device);
193 * Return all diag_clients of this device. There should be none,
194 * as we are "guaranteed" that no clients are still open
196 while (dd->diag_client)
197 return_client(dd->diag_client);
199 /* Now clean up all unused client structs */
200 while (client_pool) {
202 client_pool = dc->next;
205 /* Clean up observer list */
206 qib_unregister_observers(dd);
209 /* qib_remap_ioaddr32 - remap an offset into chip address space to __iomem *
211 * @dd: the qlogic_ib device
212 * @offs: the offset in chip-space
213 * @cntp: Pointer to max (byte) count for transfer starting at offset
214 * This returns a u32 __iomem * so it can be used for both 64 and 32-bit
215 * mapping. It is needed because with the use of PAT for control of
216 * write-combining, the logically contiguous address-space of the chip
217 * may be split into virtually non-contiguous spaces, with different
218 * attributes, which are them mapped to contiguous physical space
219 * based from the first BAR.
221 * The code below makes the same assumptions as were made in
222 * init_chip_wc_pat() (qib_init.c), copied here:
223 * Assumes chip address space looks like:
224 * - kregs + sregs + cregs + uregs (in any order)
225 * - piobufs (2K and 4K bufs in either order)
227 * - kregs + sregs + cregs (in any order)
228 * - piobufs (2K and 4K bufs in either order)
231 * If cntp is non-NULL, returns how many bytes from offset can be accessed
232 * Returns 0 if the offset is not mapped.
234 static u32 __iomem *qib_remap_ioaddr32(struct qib_devdata *dd, u32 offset,
238 u32 snd_bottom, snd_lim = 0;
239 u32 __iomem *krb32 = (u32 __iomem *)dd->kregbase;
240 u32 __iomem *map = NULL;
244 /* First, simplest case, offset is within the first map. */
245 kreglen = (dd->kregend - dd->kregbase) * sizeof(u64);
246 if (offset < kreglen) {
247 map = krb32 + (offset / sizeof(u32));
248 cnt = kreglen - offset;
253 * Next check for user regs, the next most common case,
254 * and a cheap check because if they are not in the first map
255 * they are last in chip.
258 /* If user regs mapped, they are after send, so set limit. */
259 u32 ulim = (dd->cfgctxts * dd->ureg_align) + dd->uregbase;
260 if (!dd->piovl15base)
261 snd_lim = dd->uregbase;
262 krb32 = (u32 __iomem *)dd->userbase;
263 if (offset >= dd->uregbase && offset < ulim) {
264 map = krb32 + (offset - dd->uregbase) / sizeof(u32);
271 * Lastly, check for offset within Send Buffers.
272 * This is gnarly because struct devdata is deliberately vague
273 * about things like 7322 VL15 buffers, and we are not in
274 * chip-specific code here, so should not make many assumptions.
275 * The one we _do_ make is that the only chip that has more sndbufs
276 * than we admit is the 7322, and it has userregs above that, so
277 * we know the snd_lim.
279 /* Assume 2K buffers are first. */
280 snd_bottom = dd->pio2k_bufbase;
282 u32 tot2k = dd->piobcnt2k * ALIGN(dd->piosize2k, dd->palign);
283 snd_lim = snd_bottom + tot2k;
285 /* If 4k buffers exist, account for them by bumping
288 tot4k = dd->piobcnt4k * dd->align4k;
289 offs4k = dd->piobufbase >> 32;
291 if (snd_bottom > offs4k)
294 /* 4k above 2k. Bump snd_lim, if needed*/
295 if (!dd->userbase || dd->piovl15base)
296 snd_lim = offs4k + tot4k;
300 * Judgement call: can we ignore the space between SendBuffs and
301 * UserRegs, where we would like to see vl15 buffs, but not more?
303 if (offset >= snd_bottom && offset < snd_lim) {
304 offset -= snd_bottom;
305 map = (u32 __iomem *)dd->piobase + (offset / sizeof(u32));
306 cnt = snd_lim - offset;
309 if (!map && offs4k && dd->piovl15base) {
310 snd_lim = offs4k + tot4k + 2 * dd->align4k;
311 if (offset >= (offs4k + tot4k) && offset < snd_lim) {
312 map = (u32 __iomem *)dd->piovl15base +
313 ((offset - (offs4k + tot4k)) / sizeof(u32));
314 cnt = snd_lim - offset;
325 * qib_read_umem64 - read a 64-bit quantity from the chip into user space
326 * @dd: the qlogic_ib device
327 * @uaddr: the location to store the data in user memory
328 * @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore)
329 * @count: number of bytes to copy (multiple of 32 bits)
331 * This function also localizes all chip memory accesses.
332 * The copy should be written such that we read full cacheline packets
333 * from the chip. This is usually used for a single qword
335 * NOTE: This assumes the chip address is 64-bit aligned.
337 static int qib_read_umem64(struct qib_devdata *dd, void __user *uaddr,
338 u32 regoffs, size_t count)
340 const u64 __iomem *reg_addr;
341 const u64 __iomem *reg_end;
345 reg_addr = (const u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit);
346 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {
352 reg_end = reg_addr + (count / sizeof(u64));
354 /* not very efficient, but it works for now */
355 while (reg_addr < reg_end) {
356 u64 data = readq(reg_addr);
358 if (copy_to_user(uaddr, &data, sizeof(u64))) {
363 uaddr += sizeof(u64);
371 * qib_write_umem64 - write a 64-bit quantity to the chip from user space
372 * @dd: the qlogic_ib device
373 * @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore)
374 * @uaddr: the source of the data in user memory
375 * @count: the number of bytes to copy (multiple of 32 bits)
377 * This is usually used for a single qword
378 * NOTE: This assumes the chip address is 64-bit aligned.
381 static int qib_write_umem64(struct qib_devdata *dd, u32 regoffs,
382 const void __user *uaddr, size_t count)
384 u64 __iomem *reg_addr;
385 const u64 __iomem *reg_end;
389 reg_addr = (u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit);
390 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {
396 reg_end = reg_addr + (count / sizeof(u64));
398 /* not very efficient, but it works for now */
399 while (reg_addr < reg_end) {
401 if (copy_from_user(&data, uaddr, sizeof(data))) {
405 writeq(data, reg_addr);
408 uaddr += sizeof(u64);
416 * qib_read_umem32 - read a 32-bit quantity from the chip into user space
417 * @dd: the qlogic_ib device
418 * @uaddr: the location to store the data in user memory
419 * @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore)
420 * @count: number of bytes to copy
422 * read 32 bit values, not 64 bit; for memories that only
423 * support 32 bit reads; usually a single dword.
425 static int qib_read_umem32(struct qib_devdata *dd, void __user *uaddr,
426 u32 regoffs, size_t count)
428 const u32 __iomem *reg_addr;
429 const u32 __iomem *reg_end;
433 reg_addr = qib_remap_ioaddr32(dd, regoffs, &limit);
434 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {
440 reg_end = reg_addr + (count / sizeof(u32));
442 /* not very efficient, but it works for now */
443 while (reg_addr < reg_end) {
444 u32 data = readl(reg_addr);
446 if (copy_to_user(uaddr, &data, sizeof(data))) {
452 uaddr += sizeof(u32);
461 * qib_write_umem32 - write a 32-bit quantity to the chip from user space
462 * @dd: the qlogic_ib device
463 * @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore)
464 * @uaddr: the source of the data in user memory
465 * @count: number of bytes to copy
467 * write 32 bit values, not 64 bit; for memories that only
468 * support 32 bit write; usually a single dword.
471 static int qib_write_umem32(struct qib_devdata *dd, u32 regoffs,
472 const void __user *uaddr, size_t count)
474 u32 __iomem *reg_addr;
475 const u32 __iomem *reg_end;
479 reg_addr = qib_remap_ioaddr32(dd, regoffs, &limit);
480 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {
486 reg_end = reg_addr + (count / sizeof(u32));
488 while (reg_addr < reg_end) {
491 if (copy_from_user(&data, uaddr, sizeof(data))) {
495 writel(data, reg_addr);
498 uaddr += sizeof(u32);
505 static int qib_diag_open(struct inode *in, struct file *fp)
507 int unit = iminor(in) - QIB_DIAG_MINOR_BASE;
508 struct qib_devdata *dd;
509 struct qib_diag_client *dc;
512 mutex_lock(&qib_mutex);
514 dd = qib_lookup(unit);
516 if (dd == NULL || !(dd->flags & QIB_PRESENT) ||
527 dc->next = dd->diag_client;
528 dd->diag_client = dc;
529 fp->private_data = dc;
532 mutex_unlock(&qib_mutex);
538 * qib_diagpkt_write - write an IB packet
539 * @fp: the diag data device file pointer
540 * @data: qib_diag_pkt structure saying where to get the packet
541 * @count: size of data to write
542 * @off: unused by this code
544 static ssize_t qib_diagpkt_write(struct file *fp,
545 const char __user *data,
546 size_t count, loff_t *off)
549 u32 plen, clen, pbufn;
550 struct qib_diag_xpkt dp;
552 struct qib_devdata *dd;
553 struct qib_pportdata *ppd;
556 if (count != sizeof(dp)) {
560 if (copy_from_user(&dp, data, sizeof(dp))) {
565 dd = qib_lookup(dp.unit);
566 if (!dd || !(dd->flags & QIB_PRESENT) || !dd->kregbase) {
570 if (!(dd->flags & QIB_INITTED)) {
571 /* no hardware, freeze, etc. */
576 if (dp.version != _DIAG_XPKT_VERS) {
577 qib_dev_err(dd, "Invalid version %u for diagpkt_write\n",
582 /* send count must be an exact number of dwords */
587 if (!dp.port || dp.port > dd->num_pports) {
591 ppd = &dd->pport[dp.port - 1];
593 /* need total length before first word written */
594 /* +1 word is for the qword padding */
595 plen = sizeof(u32) + dp.len;
598 if ((plen + 4) > ppd->ibmaxlen) {
600 goto bail; /* before writing pbc */
602 tmpbuf = vmalloc(plen);
604 qib_devinfo(dd->pcidev,
605 "Unable to allocate tmp buffer, failing\n");
610 if (copy_from_user(tmpbuf,
611 (const void __user *) (unsigned long) dp.data,
617 plen >>= 2; /* in dwords */
622 piobuf = dd->f_getsendbuf(ppd, dp.pbc_wd, &pbufn);
627 /* disarm it just to be extra sure */
628 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbufn));
630 /* disable header check on pbufn for this packet */
631 dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_DIS1, NULL);
633 writeq(dp.pbc_wd, piobuf);
635 * Copy all but the trigger word, then flush, so it's written
636 * to chip before trigger word, then write trigger word, then
637 * flush again, so packet is sent.
639 if (dd->flags & QIB_PIO_FLUSH_WC) {
641 qib_pio_copy(piobuf + 2, tmpbuf, clen - 1);
643 __raw_writel(tmpbuf[clen - 1], piobuf + clen + 1);
645 qib_pio_copy(piobuf + 2, tmpbuf, clen);
647 if (dd->flags & QIB_USE_SPCL_TRIG) {
648 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
651 __raw_writel(0xaebecede, piobuf + spcl_off);
655 * Ensure buffer is written to the chip, then re-enable
656 * header checks (if supported by chip). The txchk
657 * code will ensure seen by chip before returning.
660 qib_sendbuf_done(dd, pbufn);
661 dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
670 static int qib_diag_release(struct inode *in, struct file *fp)
672 mutex_lock(&qib_mutex);
673 return_client(fp->private_data);
674 fp->private_data = NULL;
675 mutex_unlock(&qib_mutex);
680 * Chip-specific code calls to register its interest in
683 struct diag_observer_list_elt {
684 struct diag_observer_list_elt *next;
685 const struct diag_observer *op;
688 int qib_register_observer(struct qib_devdata *dd,
689 const struct diag_observer *op)
691 struct diag_observer_list_elt *olp;
697 olp = vmalloc(sizeof *olp);
699 pr_err("vmalloc for observer failed\n");
705 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
707 olp->next = dd->diag_observer_list;
708 dd->diag_observer_list = olp;
709 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
716 /* Remove all registered observers when device is closed */
717 static void qib_unregister_observers(struct qib_devdata *dd)
719 struct diag_observer_list_elt *olp;
722 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
723 olp = dd->diag_observer_list;
725 /* Pop one observer, let go of lock */
726 dd->diag_observer_list = olp->next;
727 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
730 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
731 olp = dd->diag_observer_list;
733 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
737 * Find the observer, if any, for the specified address. Initial implementation
738 * is simple stack of observers. This must be called with diag transaction
741 static const struct diag_observer *diag_get_observer(struct qib_devdata *dd,
744 struct diag_observer_list_elt *olp;
745 const struct diag_observer *op = NULL;
747 olp = dd->diag_observer_list;
750 if (addr >= op->bottom && addr <= op->top)
760 static ssize_t qib_diag_read(struct file *fp, char __user *data,
761 size_t count, loff_t *off)
763 struct qib_diag_client *dc = fp->private_data;
764 struct qib_devdata *dd = dc->dd;
765 void __iomem *kreg_base;
768 if (dc->pid != current->pid) {
773 kreg_base = dd->kregbase;
777 else if ((count % 4) || (*off % 4))
778 /* address or length is not 32-bit aligned, hence invalid */
780 else if (dc->state < READY && (*off || count != 8))
781 ret = -EINVAL; /* prevent cat /dev/qib_diag* */
786 const struct diag_observer *op;
788 use_32 = (count % 8) || (*off % 8);
790 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
792 * Check for observer on this address range.
793 * we only support a single 32 or 64-bit read
794 * via observer, currently.
796 op = diag_get_observer(dd, *off);
799 ret = op->hook(dd, op, offset, &data64, 0, use_32);
802 * We need to release lock before any copy_to_user(),
803 * whether implicit in qib_read_umem* or explicit below.
805 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
809 * Address or length is not 64-bit aligned;
812 ret = qib_read_umem32(dd, data, (u32) *off,
815 ret = qib_read_umem64(dd, data, (u32) *off,
817 } else if (ret == count) {
818 /* Below finishes case where observer existed */
819 ret = copy_to_user(data, &data64, use_32 ?
820 sizeof(u32) : sizeof(u64));
829 if (dc->state == OPENED)
836 static ssize_t qib_diag_write(struct file *fp, const char __user *data,
837 size_t count, loff_t *off)
839 struct qib_diag_client *dc = fp->private_data;
840 struct qib_devdata *dd = dc->dd;
841 void __iomem *kreg_base;
844 if (dc->pid != current->pid) {
849 kreg_base = dd->kregbase;
853 else if ((count % 4) || (*off % 4))
854 /* address or length is not 32-bit aligned, hence invalid */
856 else if (dc->state < READY &&
857 ((*off || count != 8) || dc->state != INIT))
858 /* No writes except second-step of init seq */
859 ret = -EINVAL; /* before any other write allowed */
862 const struct diag_observer *op = NULL;
863 int use_32 = (count % 8) || (*off % 8);
866 * Check for observer on this address range.
867 * We only support a single 32 or 64-bit write
868 * via observer, currently. This helps, because
869 * we would otherwise have to jump through hoops
870 * to make "diag transaction" meaningful when we
871 * cannot do a copy_from_user while holding the lock.
873 if (count == 4 || count == 8) {
876 ret = copy_from_user(&data64, data, count);
881 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
882 op = diag_get_observer(dd, *off);
884 ret = op->hook(dd, op, offset, &data64, ~0Ull,
886 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
892 * Address or length is not 64-bit aligned;
895 ret = qib_write_umem32(dd, (u32) *off, data,
898 ret = qib_write_umem64(dd, (u32) *off, data,
906 if (dc->state == INIT)
907 dc->state = READY; /* all read/write OK now */