drivers/infiniband/hw/nes/nes_hw.h

   1 /*
   2 * Copyright (c) 2006 - 2011 Intel Corporation.  All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33 #ifndef __NES_HW_H
  34 #define __NES_HW_H
  35
  36 #define NES_PHY_TYPE_CX4       1
  37 #define NES_PHY_TYPE_1G        2
  38 #define NES_PHY_TYPE_ARGUS     4
  39 #define NES_PHY_TYPE_PUMA_1G   5
  40 #define NES_PHY_TYPE_PUMA_10G  6
  41 #define NES_PHY_TYPE_GLADIUS   7
  42 #define NES_PHY_TYPE_SFP_D     8
  43 #define NES_PHY_TYPE_KR        9
  44
  45 #define NES_MULTICAST_PF_MAX 8
  46 #define NES_A0 3
  47
  48 #define NES_ENABLE_PAU 0x07000001
  49 #define NES_DISABLE_PAU 0x07000000
  50 #define NES_PAU_COUNTER 10
  51 #define NES_CQP_OPCODE_MASK 0x3f
  52
  53 enum pci_regs {
  54         NES_INT_STAT = 0x0000,
  55         NES_INT_MASK = 0x0004,
  56         NES_INT_PENDING = 0x0008,
  57         NES_INTF_INT_STAT = 0x000C,
  58         NES_INTF_INT_MASK = 0x0010,
  59         NES_TIMER_STAT = 0x0014,
  60         NES_PERIODIC_CONTROL = 0x0018,
  61         NES_ONE_SHOT_CONTROL = 0x001C,
  62         NES_EEPROM_COMMAND = 0x0020,
  63         NES_EEPROM_DATA = 0x0024,
  64         NES_FLASH_COMMAND = 0x0028,
  65         NES_FLASH_DATA  = 0x002C,
  66         NES_SOFTWARE_RESET = 0x0030,
  67         NES_CQ_ACK = 0x0034,
  68         NES_WQE_ALLOC = 0x0040,
  69         NES_CQE_ALLOC = 0x0044,
  70         NES_AEQ_ALLOC = 0x0048
  71 };
  72
  73 enum indexed_regs {
  74         NES_IDX_CREATE_CQP_LOW = 0x0000,
  75         NES_IDX_CREATE_CQP_HIGH = 0x0004,
  76         NES_IDX_QP_CONTROL = 0x0040,
  77         NES_IDX_FLM_CONTROL = 0x0080,
  78         NES_IDX_INT_CPU_STATUS = 0x00a0,
  79         NES_IDX_GPR_TRIGGER = 0x00bc,
  80         NES_IDX_GPIO_CONTROL = 0x00f0,
  81         NES_IDX_GPIO_DATA = 0x00f4,
  82         NES_IDX_GPR2 = 0x010c,
  83         NES_IDX_TCP_CONFIG0 = 0x01e4,
  84         NES_IDX_TCP_TIMER_CONFIG = 0x01ec,
  85         NES_IDX_TCP_NOW = 0x01f0,
  86         NES_IDX_QP_MAX_CFG_SIZES = 0x0200,
  87         NES_IDX_QP_CTX_SIZE = 0x0218,
  88         NES_IDX_TCP_TIMER_SIZE0 = 0x0238,
  89         NES_IDX_TCP_TIMER_SIZE1 = 0x0240,
  90         NES_IDX_ARP_CACHE_SIZE = 0x0258,
  91         NES_IDX_CQ_CTX_SIZE = 0x0260,
  92         NES_IDX_MRT_SIZE = 0x0278,
  93         NES_IDX_PBL_REGION_SIZE = 0x0280,
  94         NES_IDX_IRRQ_COUNT = 0x02b0,
  95         NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0,
  96         NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300,
  97         NES_IDX_DST_IP_ADDR = 0x0400,
  98         NES_IDX_PCIX_DIAG = 0x08e8,
  99         NES_IDX_MPP_DEBUG = 0x0a00,
 100         NES_IDX_PORT_RX_DISCARDS = 0x0a30,
 101         NES_IDX_PORT_TX_DISCARDS = 0x0a34,
 102         NES_IDX_MPP_LB_DEBUG = 0x0b00,
 103         NES_IDX_DENALI_CTL_22 = 0x1058,
 104         NES_IDX_MAC_TX_CONTROL = 0x2000,
 105         NES_IDX_MAC_TX_CONFIG = 0x2004,
 106         NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008,
 107         NES_IDX_MAC_RX_CONTROL = 0x200c,
 108         NES_IDX_MAC_RX_CONFIG = 0x2010,
 109         NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c,
 110         NES_IDX_MAC_MDIO_CONTROL = 0x2084,
 111         NES_IDX_MAC_TX_OCTETS_LOW = 0x2100,
 112         NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104,
 113         NES_IDX_MAC_TX_FRAMES_LOW = 0x2108,
 114         NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c,
 115         NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118,
 116         NES_IDX_MAC_TX_ERRORS = 0x2138,
 117         NES_IDX_MAC_RX_OCTETS_LOW = 0x213c,
 118         NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140,
 119         NES_IDX_MAC_RX_FRAMES_LOW = 0x2144,
 120         NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148,
 121         NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c,
 122         NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150,
 123         NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154,
 124         NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174,
 125         NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178,
 126         NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c,
 127         NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180,
 128         NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184,
 129         NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188,
 130         NES_IDX_MAC_INT_STATUS = 0x21f0,
 131         NES_IDX_MAC_INT_MASK = 0x21f4,
 132         NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800,
 133         NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00,
 134         NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808,
 135         NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08,
 136         NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c,
 137         NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c,
 138         NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810,
 139         NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10,
 140         NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814,
 141         NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14,
 142         NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818,
 143         NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18,
 144         NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c,
 145         NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c,
 146         NES_IDX_ETH_SERDES_BYPASS0 = 0x2820,
 147         NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20,
 148         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824,
 149         NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24,
 150         NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828,
 151         NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28,
 152         NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c,
 153         NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c,
 154         NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830,
 155         NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30,
 156         NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834,
 157         NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34,
 158         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838,
 159         NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38,
 160         NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080,
 161         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000,
 162         NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004,
 163         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008,
 164         NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c,
 165         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000,
 166         NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004,
 167         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008,
 168         NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c,
 169         NES_IDX_WQM_CONFIG0 = 0x5000,
 170         NES_IDX_WQM_CONFIG1 = 0x5004,
 171         NES_IDX_CM_CONFIG = 0x5100,
 172         NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000,
 173         NES_IDX_NIC_PHYPORT_TO_USW = 0x6008,
 174         NES_IDX_NIC_ACTIVE = 0x6010,
 175         NES_IDX_NIC_UNICAST_ALL = 0x6018,
 176         NES_IDX_NIC_MULTICAST_ALL = 0x6020,
 177         NES_IDX_NIC_MULTICAST_ENABLE = 0x6028,
 178         NES_IDX_NIC_BROADCAST_ON = 0x6030,
 179         NES_IDX_USED_CHUNKS_TX = 0x60b0,
 180         NES_IDX_TX_POOL_SIZE = 0x60b8,
 181         NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148,
 182         NES_IDX_PERFECT_FILTER_LOW = 0x6200,
 183         NES_IDX_PERFECT_FILTER_HIGH = 0x6204,
 184         NES_IDX_IPV4_TCP_REXMITS = 0x7080,
 185         NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c,
 186         NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140,
 187         NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144,
 188         NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148,
 189         NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c,
 190         NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150,
 191         NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
 192 };
 193
 194 #define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE   1
 195 #define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
 196
 197 enum nes_cqp_opcodes {
 198         NES_CQP_CREATE_QP = 0x00,
 199         NES_CQP_MODIFY_QP = 0x01,
 200         NES_CQP_DESTROY_QP = 0x02,
 201         NES_CQP_CREATE_CQ = 0x03,
 202         NES_CQP_MODIFY_CQ = 0x04,
 203         NES_CQP_DESTROY_CQ = 0x05,
 204         NES_CQP_ALLOCATE_STAG = 0x09,
 205         NES_CQP_REGISTER_STAG = 0x0a,
 206         NES_CQP_QUERY_STAG = 0x0b,
 207         NES_CQP_REGISTER_SHARED_STAG = 0x0c,
 208         NES_CQP_DEALLOCATE_STAG = 0x0d,
 209         NES_CQP_MANAGE_ARP_CACHE = 0x0f,
 210         NES_CQP_DOWNLOAD_SEGMENT = 0x10,
 211         NES_CQP_SUSPEND_QPS = 0x11,
 212         NES_CQP_UPLOAD_CONTEXT = 0x13,
 213         NES_CQP_CREATE_CEQ = 0x16,
 214         NES_CQP_DESTROY_CEQ = 0x18,
 215         NES_CQP_CREATE_AEQ = 0x19,
 216         NES_CQP_DESTROY_AEQ = 0x1b,
 217         NES_CQP_LMI_ACCESS = 0x20,
 218         NES_CQP_FLUSH_WQES = 0x22,
 219         NES_CQP_MANAGE_APBVT = 0x23,
 220         NES_CQP_MANAGE_QUAD_HASH = 0x25
 221 };
 222
 223 enum nes_cqp_wqe_word_idx {
 224         NES_CQP_WQE_OPCODE_IDX = 0,
 225         NES_CQP_WQE_ID_IDX = 1,
 226         NES_CQP_WQE_COMP_CTX_LOW_IDX = 2,
 227         NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3,
 228         NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4,
 229         NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 230 };
 231
 232 enum nes_cqp_wqe_word_download_idx { /* format differs from other cqp ops */
 233         NES_CQP_WQE_DL_OPCODE_IDX = 0,
 234         NES_CQP_WQE_DL_COMP_CTX_LOW_IDX = 1,
 235         NES_CQP_WQE_DL_COMP_CTX_HIGH_IDX = 2,
 236         NES_CQP_WQE_DL_LENGTH_0_TOTAL_IDX = 3
 237         /* For index values 4-15 use NES_NIC_SQ_WQE_ values */
 238 };
 239
 240 enum nes_cqp_cq_wqeword_idx {
 241         NES_CQP_CQ_WQE_PBL_LOW_IDX = 6,
 242         NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7,
 243         NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8,
 244         NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9,
 245         NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10,
 246 };
 247
 248 enum nes_cqp_stag_wqeword_idx {
 249         NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1,
 250         NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6,
 251         NES_CQP_STAG_WQE_LEN_LOW_IDX = 7,
 252         NES_CQP_STAG_WQE_STAG_IDX = 8,
 253         NES_CQP_STAG_WQE_VA_LOW_IDX = 10,
 254         NES_CQP_STAG_WQE_VA_HIGH_IDX = 11,
 255         NES_CQP_STAG_WQE_PA_LOW_IDX = 12,
 256         NES_CQP_STAG_WQE_PA_HIGH_IDX = 13,
 257         NES_CQP_STAG_WQE_PBL_LEN_IDX = 14
 258 };
 259
 260 #define NES_CQP_OP_LOGICAL_PORT_SHIFT 26
 261 #define NES_CQP_OP_IWARP_STATE_SHIFT 28
 262 #define NES_CQP_OP_TERMLEN_SHIFT     28
 263
 264 enum nes_cqp_qp_bits {
 265         NES_CQP_QP_ARP_VALID = (1<<8),
 266         NES_CQP_QP_WINBUF_VALID = (1<<9),
 267         NES_CQP_QP_CONTEXT_VALID = (1<<10),
 268         NES_CQP_QP_ORD_VALID = (1<<11),
 269         NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12),
 270         NES_CQP_QP_VIRT_WQS = (1<<13),
 271         NES_CQP_QP_DEL_HTE = (1<<14),
 272         NES_CQP_QP_CQS_VALID = (1<<15),
 273         NES_CQP_QP_TYPE_TSA = 0,
 274         NES_CQP_QP_TYPE_IWARP = (1<<16),
 275         NES_CQP_QP_TYPE_CQP = (4<<16),
 276         NES_CQP_QP_TYPE_NIC = (5<<16),
 277         NES_CQP_QP_MSS_CHG = (1<<20),
 278         NES_CQP_QP_STATIC_RESOURCES = (1<<21),
 279         NES_CQP_QP_IGNORE_MW_BOUND = (1<<22),
 280         NES_CQP_QP_VWQ_USE_LMI = (1<<23),
 281         NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT),
 282         NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT),
 283         NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT),
 284         NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
 285         NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
 286         NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
 287         NES_CQP_QP_TERM_DONT_SEND_FIN = (1<<24),
 288         NES_CQP_QP_TERM_DONT_SEND_TERM_MSG = (1<<25),
 289         NES_CQP_QP_RESET = (1<<31),
 290 };
 291
 292 enum nes_cqp_qp_wqe_word_idx {
 293         NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
 294         NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
 295         NES_CQP_QP_WQE_FLUSH_SQ_CODE = 8,
 296         NES_CQP_QP_WQE_FLUSH_RQ_CODE = 9,
 297         NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
 298 };
 299
 300 enum nes_nic_ctx_bits {
 301         NES_NIC_CTX_RQ_SIZE_32 = (3<<8),
 302         NES_NIC_CTX_RQ_SIZE_512 = (3<<8),
 303         NES_NIC_CTX_SQ_SIZE_32 = (1<<10),
 304         NES_NIC_CTX_SQ_SIZE_512 = (3<<10),
 305 };
 306
 307 enum nes_nic_qp_ctx_word_idx {
 308         NES_NIC_CTX_MISC_IDX = 0,
 309         NES_NIC_CTX_SQ_LOW_IDX = 2,
 310         NES_NIC_CTX_SQ_HIGH_IDX = 3,
 311         NES_NIC_CTX_RQ_LOW_IDX = 4,
 312         NES_NIC_CTX_RQ_HIGH_IDX = 5,
 313 };
 314
 315 enum nes_cqp_cq_bits {
 316         NES_CQP_CQ_CEQE_MASK = (1<<9),
 317         NES_CQP_CQ_CEQ_VALID = (1<<10),
 318         NES_CQP_CQ_RESIZE = (1<<11),
 319         NES_CQP_CQ_CHK_OVERFLOW = (1<<12),
 320         NES_CQP_CQ_4KB_CHUNK = (1<<14),
 321         NES_CQP_CQ_VIRT = (1<<15),
 322 };
 323
 324 enum nes_cqp_stag_bits {
 325         NES_CQP_STAG_VA_TO = (1<<9),
 326         NES_CQP_STAG_DEALLOC_PBLS = (1<<10),
 327         NES_CQP_STAG_PBL_BLK_SIZE = (1<<11),
 328         NES_CQP_STAG_MR = (1<<13),
 329         NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16),
 330         NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17),
 331         NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18),
 332         NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19),
 333         NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20),
 334         NES_CQP_STAG_REM_ACC_EN = (1<<21),
 335         NES_CQP_STAG_LEAVE_PENDING = (1<<31),
 336 };
 337
 338 enum nes_cqp_ceq_wqeword_idx {
 339         NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1,
 340         NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6,
 341         NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7,
 342 };
 343
 344 enum nes_cqp_ceq_bits {
 345         NES_CQP_CEQ_4KB_CHUNK = (1<<14),
 346         NES_CQP_CEQ_VIRT = (1<<15),
 347 };
 348
 349 enum nes_cqp_aeq_wqeword_idx {
 350         NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1,
 351         NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6,
 352         NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7,
 353 };
 354
 355 enum nes_cqp_aeq_bits {
 356         NES_CQP_AEQ_4KB_CHUNK = (1<<14),
 357         NES_CQP_AEQ_VIRT = (1<<15),
 358 };
 359
 360 enum nes_cqp_lmi_wqeword_idx {
 361         NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1,
 362         NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8,
 363         NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9,
 364         NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10,
 365 };
 366
 367 enum nes_cqp_arp_wqeword_idx {
 368         NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6,
 369         NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7,
 370         NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1,
 371 };
 372
 373 enum nes_cqp_upload_wqeword_idx {
 374         NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6,
 375         NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7,
 376         NES_CQP_UPLOAD_WQE_HTE_IDX = 8,
 377 };
 378
 379 enum nes_cqp_arp_bits {
 380         NES_CQP_ARP_VALID = (1<<8),
 381         NES_CQP_ARP_PERM = (1<<9),
 382 };
 383
 384 enum nes_cqp_flush_bits {
 385         NES_CQP_FLUSH_SQ = (1<<30),
 386         NES_CQP_FLUSH_RQ = (1<<31),
 387         NES_CQP_FLUSH_MAJ_MIN = (1<<28),
 388 };
 389
 390 enum nes_cqe_opcode_bits {
 391         NES_CQE_STAG_VALID = (1<<6),
 392         NES_CQE_ERROR = (1<<7),
 393         NES_CQE_SQ = (1<<8),
 394         NES_CQE_SE = (1<<9),
 395         NES_CQE_PSH = (1<<29),
 396         NES_CQE_FIN = (1<<30),
 397         NES_CQE_VALID = (1<<31),
 398 };
 399
 400
 401 enum nes_cqe_word_idx {
 402         NES_CQE_PAYLOAD_LENGTH_IDX = 0,
 403         NES_CQE_COMP_COMP_CTX_LOW_IDX = 2,
 404         NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3,
 405         NES_CQE_INV_STAG_IDX = 4,
 406         NES_CQE_QP_ID_IDX = 5,
 407         NES_CQE_ERROR_CODE_IDX = 6,
 408         NES_CQE_OPCODE_IDX = 7,
 409 };
 410
 411 enum nes_ceqe_word_idx {
 412         NES_CEQE_CQ_CTX_LOW_IDX = 0,
 413         NES_CEQE_CQ_CTX_HIGH_IDX = 1,
 414 };
 415
 416 enum nes_ceqe_status_bit {
 417         NES_CEQE_VALID = (1<<31),
 418 };
 419
 420 enum nes_int_bits {
 421         NES_INT_CEQ0 = (1<<0),
 422         NES_INT_CEQ1 = (1<<1),
 423         NES_INT_CEQ2 = (1<<2),
 424         NES_INT_CEQ3 = (1<<3),
 425         NES_INT_CEQ4 = (1<<4),
 426         NES_INT_CEQ5 = (1<<5),
 427         NES_INT_CEQ6 = (1<<6),
 428         NES_INT_CEQ7 = (1<<7),
 429         NES_INT_CEQ8 = (1<<8),
 430         NES_INT_CEQ9 = (1<<9),
 431         NES_INT_CEQ10 = (1<<10),
 432         NES_INT_CEQ11 = (1<<11),
 433         NES_INT_CEQ12 = (1<<12),
 434         NES_INT_CEQ13 = (1<<13),
 435         NES_INT_CEQ14 = (1<<14),
 436         NES_INT_CEQ15 = (1<<15),
 437         NES_INT_AEQ0 = (1<<16),
 438         NES_INT_AEQ1 = (1<<17),
 439         NES_INT_AEQ2 = (1<<18),
 440         NES_INT_AEQ3 = (1<<19),
 441         NES_INT_AEQ4 = (1<<20),
 442         NES_INT_AEQ5 = (1<<21),
 443         NES_INT_AEQ6 = (1<<22),
 444         NES_INT_AEQ7 = (1<<23),
 445         NES_INT_MAC0 = (1<<24),
 446         NES_INT_MAC1 = (1<<25),
 447         NES_INT_MAC2 = (1<<26),
 448         NES_INT_MAC3 = (1<<27),
 449         NES_INT_TSW = (1<<28),
 450         NES_INT_TIMER = (1<<29),
 451         NES_INT_INTF = (1<<30),
 452 };
 453
 454 enum nes_intf_int_bits {
 455         NES_INTF_INT_PCIERR = (1<<0),
 456         NES_INTF_PERIODIC_TIMER = (1<<2),
 457         NES_INTF_ONE_SHOT_TIMER = (1<<3),
 458         NES_INTF_INT_CRITERR = (1<<14),
 459         NES_INTF_INT_AEQ0_OFLOW = (1<<16),
 460         NES_INTF_INT_AEQ1_OFLOW = (1<<17),
 461         NES_INTF_INT_AEQ2_OFLOW = (1<<18),
 462         NES_INTF_INT_AEQ3_OFLOW = (1<<19),
 463         NES_INTF_INT_AEQ4_OFLOW = (1<<20),
 464         NES_INTF_INT_AEQ5_OFLOW = (1<<21),
 465         NES_INTF_INT_AEQ6_OFLOW = (1<<22),
 466         NES_INTF_INT_AEQ7_OFLOW = (1<<23),
 467         NES_INTF_INT_AEQ_OFLOW = (0xff<<16),
 468 };
 469
 470 enum nes_mac_int_bits {
 471         NES_MAC_INT_LINK_STAT_CHG = (1<<1),
 472         NES_MAC_INT_XGMII_EXT = (1<<2),
 473         NES_MAC_INT_TX_UNDERFLOW = (1<<6),
 474         NES_MAC_INT_TX_ERROR = (1<<7),
 475 };
 476
 477 enum nes_cqe_allocate_bits {
 478         NES_CQE_ALLOC_INC_SELECT = (1<<28),
 479         NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29),
 480         NES_CQE_ALLOC_NOTIFY_SE = (1<<30),
 481         NES_CQE_ALLOC_RESET = (1<<31),
 482 };
 483
 484 enum nes_nic_rq_wqe_word_idx {
 485         NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0,
 486         NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1,
 487         NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2,
 488         NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3,
 489         NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4,
 490         NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5,
 491         NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6,
 492         NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7,
 493         NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8,
 494         NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9,
 495 };
 496
 497 enum nes_nic_sq_wqe_word_idx {
 498         NES_NIC_SQ_WQE_MISC_IDX = 0,
 499         NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1,
 500         NES_NIC_SQ_WQE_LSO_INFO_IDX = 2,
 501         NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3,
 502         NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4,
 503         NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5,
 504         NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6,
 505         NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7,
 506         NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8,
 507         NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9,
 508         NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10,
 509         NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11,
 510         NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12,
 511         NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13,
 512         NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14,
 513         NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15,
 514 };
 515
 516 enum nes_iwarp_sq_wqe_word_idx {
 517         NES_IWARP_SQ_WQE_MISC_IDX = 0,
 518         NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1,
 519         NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2,
 520         NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3,
 521         NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
 522         NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 523         NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7,
 524         NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8,
 525         NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9,
 526         NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10,
 527         NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11,
 528         NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12,
 529         NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16,
 530         NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17,
 531         NES_IWARP_SQ_WQE_LENGTH0_IDX = 18,
 532         NES_IWARP_SQ_WQE_STAG0_IDX = 19,
 533         NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20,
 534         NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21,
 535         NES_IWARP_SQ_WQE_LENGTH1_IDX = 22,
 536         NES_IWARP_SQ_WQE_STAG1_IDX = 23,
 537         NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24,
 538         NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25,
 539         NES_IWARP_SQ_WQE_LENGTH2_IDX = 26,
 540         NES_IWARP_SQ_WQE_STAG2_IDX = 27,
 541         NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28,
 542         NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29,
 543         NES_IWARP_SQ_WQE_LENGTH3_IDX = 30,
 544         NES_IWARP_SQ_WQE_STAG3_IDX = 31,
 545 };
 546
 547 enum nes_iwarp_sq_bind_wqe_word_idx {
 548         NES_IWARP_SQ_BIND_WQE_MR_IDX = 6,
 549         NES_IWARP_SQ_BIND_WQE_MW_IDX = 7,
 550         NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8,
 551         NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9,
 552         NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10,
 553         NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11,
 554 };
 555
 556 enum nes_iwarp_sq_fmr_wqe_word_idx {
 557         NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7,
 558         NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8,
 559         NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9,
 560         NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10,
 561         NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11,
 562         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12,
 563         NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13,
 564         NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14,
 565 };
 566
 567 enum nes_iwarp_sq_fmr_opcodes {
 568         NES_IWARP_SQ_FMR_WQE_ZERO_BASED                 = (1<<6),
 569         NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_4K               = (0<<7),
 570         NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_2M               = (1<<7),
 571         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_READ   = (1<<16),
 572         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_WRITE  = (1<<17),
 573         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_READ  = (1<<18),
 574         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_WRITE = (1<<19),
 575         NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_WINDOW_BIND  = (1<<20),
 576 };
 577
 578 #define NES_IWARP_SQ_FMR_WQE_MR_LENGTH_HIGH_MASK        0xFF;
 579
 580 enum nes_iwarp_sq_locinv_wqe_word_idx {
 581         NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6,
 582 };
 583
 584 enum nes_iwarp_rq_wqe_word_idx {
 585         NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1,
 586         NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2,
 587         NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3,
 588         NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
 589         NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
 590         NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8,
 591         NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9,
 592         NES_IWARP_RQ_WQE_LENGTH0_IDX = 10,
 593         NES_IWARP_RQ_WQE_STAG0_IDX = 11,
 594         NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12,
 595         NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13,
 596         NES_IWARP_RQ_WQE_LENGTH1_IDX = 14,
 597         NES_IWARP_RQ_WQE_STAG1_IDX = 15,
 598         NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16,
 599         NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17,
 600         NES_IWARP_RQ_WQE_LENGTH2_IDX = 18,
 601         NES_IWARP_RQ_WQE_STAG2_IDX = 19,
 602         NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20,
 603         NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21,
 604         NES_IWARP_RQ_WQE_LENGTH3_IDX = 22,
 605         NES_IWARP_RQ_WQE_STAG3_IDX = 23,
 606 };
 607
 608 enum nes_nic_sq_wqe_bits {
 609         NES_NIC_SQ_WQE_PHDR_CS_READY =  (1<<21),
 610         NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22),
 611         NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23),
 612         NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30),
 613         NES_NIC_SQ_WQE_COMPLETION = (1<<31),
 614 };
 615
 616 enum nes_nic_cqe_word_idx {
 617         NES_NIC_CQE_ACCQP_ID_IDX = 0,
 618         NES_NIC_CQE_HASH_RCVNXT = 1,
 619         NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2,
 620         NES_NIC_CQE_MISC_IDX = 3,
 621 };
 622
 623 #define NES_PKT_TYPE_APBVT_BITS 0xC112
 624 #define NES_PKT_TYPE_APBVT_MASK 0xff3e
 625
 626 #define NES_PKT_TYPE_PVALID_BITS 0x10000000
 627 #define NES_PKT_TYPE_PVALID_MASK 0x30000000
 628
 629 #define NES_PKT_TYPE_TCPV4_BITS 0x0110
 630 #define NES_PKT_TYPE_TCPV4_MASK 0x3f30
 631
 632 #define NES_PKT_TYPE_UDPV4_BITS 0x0210
 633 #define NES_PKT_TYPE_UDPV4_MASK 0x3f30
 634
 635 #define NES_PKT_TYPE_IPV4_BITS  0x0010
 636 #define NES_PKT_TYPE_IPV4_MASK  0x3f30
 637
 638 #define NES_PKT_TYPE_OTHER_BITS 0x0000
 639 #define NES_PKT_TYPE_OTHER_MASK 0x0030
 640
 641 #define NES_NIC_CQE_ERRV_SHIFT 16
 642 enum nes_nic_ev_bits {
 643         NES_NIC_ERRV_BITS_MODE = (1<<0),
 644         NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1),
 645         NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2),
 646         NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3),
 647         NES_NIC_ERRV_BITS_IPH_ERR = (1<<4),
 648 };
 649
 650 enum nes_nic_cqe_bits {
 651         NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT),
 652         NES_NIC_CQE_SQ = (1<<24),
 653         NES_NIC_CQE_ACCQP_PORT = (1<<28),
 654         NES_NIC_CQE_ACCQP_VALID = (1<<29),
 655         NES_NIC_CQE_TAG_VALID = (1<<30),
 656         NES_NIC_CQE_VALID = (1<<31),
 657 };
 658
 659 enum nes_aeqe_word_idx {
 660         NES_AEQE_COMP_CTXT_LOW_IDX = 0,
 661         NES_AEQE_COMP_CTXT_HIGH_IDX = 1,
 662         NES_AEQE_COMP_QP_CQ_ID_IDX = 2,
 663         NES_AEQE_MISC_IDX = 3,
 664 };
 665
 666 enum nes_aeqe_bits {
 667         NES_AEQE_QP = (1<<16),
 668         NES_AEQE_CQ = (1<<17),
 669         NES_AEQE_SQ = (1<<18),
 670         NES_AEQE_INBOUND_RDMA = (1<<19),
 671         NES_AEQE_IWARP_STATE_MASK = (7<<20),
 672         NES_AEQE_TCP_STATE_MASK = (0xf<<24),
 673         NES_AEQE_Q2_DATA_WRITTEN = (0x3<<28),
 674         NES_AEQE_VALID = (1<<31),
 675 };
 676
 677 #define NES_AEQE_IWARP_STATE_SHIFT      20
 678 #define NES_AEQE_TCP_STATE_SHIFT        24
 679 #define NES_AEQE_Q2_DATA_ETHERNET       (1<<28)
 680 #define NES_AEQE_Q2_DATA_MPA            (1<<29)
 681
 682 enum nes_aeqe_iwarp_state {
 683         NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
 684         NES_AEQE_IWARP_STATE_IDLE = 1,
 685         NES_AEQE_IWARP_STATE_RTS = 2,
 686         NES_AEQE_IWARP_STATE_CLOSING = 3,
 687         NES_AEQE_IWARP_STATE_TERMINATE = 5,
 688         NES_AEQE_IWARP_STATE_ERROR = 6
 689 };
 690
 691 enum nes_aeqe_tcp_state {
 692         NES_AEQE_TCP_STATE_NON_EXISTANT = 0,
 693         NES_AEQE_TCP_STATE_CLOSED = 1,
 694         NES_AEQE_TCP_STATE_LISTEN = 2,
 695         NES_AEQE_TCP_STATE_SYN_SENT = 3,
 696         NES_AEQE_TCP_STATE_SYN_RCVD = 4,
 697         NES_AEQE_TCP_STATE_ESTABLISHED = 5,
 698         NES_AEQE_TCP_STATE_CLOSE_WAIT = 6,
 699         NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7,
 700         NES_AEQE_TCP_STATE_CLOSING = 8,
 701         NES_AEQE_TCP_STATE_LAST_ACK = 9,
 702         NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10,
 703         NES_AEQE_TCP_STATE_TIME_WAIT = 11
 704 };
 705
 706 enum nes_aeqe_aeid {
 707         NES_AEQE_AEID_AMP_UNALLOCATED_STAG                            = 0x0102,
 708         NES_AEQE_AEID_AMP_INVALID_STAG                                = 0x0103,
 709         NES_AEQE_AEID_AMP_BAD_QP                                      = 0x0104,
 710         NES_AEQE_AEID_AMP_BAD_PD                                      = 0x0105,
 711         NES_AEQE_AEID_AMP_BAD_STAG_KEY                                = 0x0106,
 712         NES_AEQE_AEID_AMP_BAD_STAG_INDEX                              = 0x0107,
 713         NES_AEQE_AEID_AMP_BOUNDS_VIOLATION                            = 0x0108,
 714         NES_AEQE_AEID_AMP_RIGHTS_VIOLATION                            = 0x0109,
 715         NES_AEQE_AEID_AMP_TO_WRAP                                     = 0x010a,
 716         NES_AEQE_AEID_AMP_FASTREG_SHARED                              = 0x010b,
 717         NES_AEQE_AEID_AMP_FASTREG_VALID_STAG                          = 0x010c,
 718         NES_AEQE_AEID_AMP_FASTREG_MW_STAG                             = 0x010d,
 719         NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS                      = 0x010e,
 720         NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW                  = 0x010f,
 721         NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH                      = 0x0110,
 722         NES_AEQE_AEID_AMP_INVALIDATE_SHARED                           = 0x0111,
 723         NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS          = 0x0112,
 724         NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS            = 0x0113,
 725         NES_AEQE_AEID_AMP_MWBIND_VALID_STAG                           = 0x0114,
 726         NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG                           = 0x0115,
 727         NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG                   = 0x0116,
 728         NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG                           = 0x0117,
 729         NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS                       = 0x0118,
 730         NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS                       = 0x0119,
 731         NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT                    = 0x011a,
 732         NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED                        = 0x011b,
 733         NES_AEQE_AEID_BAD_CLOSE                                       = 0x0201,
 734         NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE                         = 0x0202,
 735         NES_AEQE_AEID_CQ_OPERATION_ERROR                              = 0x0203,
 736         NES_AEQE_AEID_PRIV_OPERATION_DENIED                           = 0x0204,
 737         NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO                        = 0x0205,
 738         NES_AEQE_AEID_STAG_ZERO_INVALID                               = 0x0206,
 739         NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN                      = 0x0301,
 740         NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID              = 0x0302,
 741         NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303,
 742         NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION                     = 0x0304,
 743         NES_AEQE_AEID_DDP_UBE_INVALID_MO                              = 0x0305,
 744         NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE         = 0x0306,
 745         NES_AEQE_AEID_DDP_UBE_INVALID_QN                              = 0x0307,
 746         NES_AEQE_AEID_DDP_NO_L_BIT                                    = 0x0308,
 747         NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION                 = 0x0311,
 748         NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE                     = 0x0312,
 749         NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST                   = 0x0313,
 750         NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP             = 0x0314,
 751         NES_AEQE_AEID_INVALID_ARP_ENTRY                               = 0x0401,
 752         NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD                         = 0x0402,
 753         NES_AEQE_AEID_STALE_ARP_ENTRY                                 = 0x0403,
 754         NES_AEQE_AEID_LLP_CLOSE_COMPLETE                              = 0x0501,
 755         NES_AEQE_AEID_LLP_CONNECTION_RESET                            = 0x0502,
 756         NES_AEQE_AEID_LLP_FIN_RECEIVED                                = 0x0503,
 757         NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH =  0x0504,
 758         NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR                      = 0x0505,
 759         NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE                           = 0x0506,
 760         NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL                           = 0x0507,
 761         NES_AEQE_AEID_LLP_SYN_RECEIVED                                = 0x0508,
 762         NES_AEQE_AEID_LLP_TERMINATE_RECEIVED                          = 0x0509,
 763         NES_AEQE_AEID_LLP_TOO_MANY_RETRIES                            = 0x050a,
 764         NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES                  = 0x050b,
 765         NES_AEQE_AEID_RESET_SENT                                      = 0x0601,
 766         NES_AEQE_AEID_TERMINATE_SENT                                  = 0x0602,
 767         NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC                      = 0x0700
 768 };
 769
 770 enum nes_iwarp_sq_opcodes {
 771         NES_IWARP_SQ_WQE_WRPDU = (1<<15),
 772         NES_IWARP_SQ_WQE_PSH = (1<<21),
 773         NES_IWARP_SQ_WQE_STREAMING = (1<<23),
 774         NES_IWARP_SQ_WQE_IMM_DATA = (1<<28),
 775         NES_IWARP_SQ_WQE_READ_FENCE = (1<<29),
 776         NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30),
 777         NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31),
 778 };
 779
 780 enum nes_iwarp_sq_wqe_bits {
 781         NES_IWARP_SQ_OP_RDMAW = 0,
 782         NES_IWARP_SQ_OP_RDMAR = 1,
 783         NES_IWARP_SQ_OP_SEND = 3,
 784         NES_IWARP_SQ_OP_SENDINV = 4,
 785         NES_IWARP_SQ_OP_SENDSE = 5,
 786         NES_IWARP_SQ_OP_SENDSEINV = 6,
 787         NES_IWARP_SQ_OP_BIND = 8,
 788         NES_IWARP_SQ_OP_FAST_REG = 9,
 789         NES_IWARP_SQ_OP_LOCINV = 10,
 790         NES_IWARP_SQ_OP_RDMAR_LOCINV = 11,
 791         NES_IWARP_SQ_OP_NOP = 12,
 792 };
 793
 794 enum nes_iwarp_cqe_major_code {
 795         NES_IWARP_CQE_MAJOR_FLUSH = 1,
 796         NES_IWARP_CQE_MAJOR_DRV = 0x8000
 797 };
 798
 799 enum nes_iwarp_cqe_minor_code {
 800         NES_IWARP_CQE_MINOR_FLUSH = 1
 801 };
 802
 803 #define NES_EEPROM_READ_REQUEST (1<<16)
 804 #define NES_MAC_ADDR_VALID      (1<<20)
 805
 806 /*
 807  * NES index registers init values.
 808  */
 809 struct nes_init_values {
 810         u32 index;
 811         u32 data;
 812         u8  wrt;
 813 };
 814
 815 /*
 816  * NES registers in BAR0.
 817  */
 818 struct nes_pci_regs {
 819         u32 int_status;
 820         u32 int_mask;
 821         u32 int_pending;
 822         u32 intf_int_status;
 823         u32 intf_int_mask;
 824         u32 other_regs[59];      /* pad out to 256 bytes for now */
 825 };
 826
 827 #define NES_CQP_SQ_SIZE    128
 828 #define NES_CCQ_SIZE       128
 829 #define NES_NIC_WQ_SIZE    512
 830 #define NES_NIC_CTX_SIZE   ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
 831 #define NES_NIC_BACK_STORE 0x00038000
 832
 833 struct nes_device;
 834
 835 struct nes_hw_nic_qp_context {
 836         __le32 context_words[6];
 837 };
 838
 839 struct nes_hw_nic_sq_wqe {
 840         __le32 wqe_words[16];
 841 };
 842
 843 struct nes_hw_nic_rq_wqe {
 844         __le32 wqe_words[16];
 845 };
 846
 847 struct nes_hw_nic_cqe {
 848         __le32 cqe_words[4];
 849 };
 850
 851 struct nes_hw_cqp_qp_context {
 852         __le32 context_words[4];
 853 };
 854
 855 struct nes_hw_cqp_wqe {
 856         __le32 wqe_words[16];
 857 };
 858
 859 struct nes_hw_qp_wqe {
 860         __le32 wqe_words[32];
 861 };
 862
 863 struct nes_hw_cqe {
 864         __le32 cqe_words[8];
 865 };
 866
 867 struct nes_hw_ceqe {
 868         __le32 ceqe_words[2];
 869 };
 870
 871 struct nes_hw_aeqe {
 872         __le32 aeqe_words[4];
 873 };
 874
 875 struct nes_cqp_request {
 876         union {
 877                 u64 cqp_callback_context;
 878                 void *cqp_callback_pointer;
 879         };
 880         wait_queue_head_t     waitq;
 881         struct nes_hw_cqp_wqe cqp_wqe;
 882         struct list_head      list;
 883         atomic_t              refcount;
 884         void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request);
 885         u16                   major_code;
 886         u16                   minor_code;
 887         u8                    waiting;
 888         u8                    request_done;
 889         u8                    dynamic;
 890         u8                    callback;
 891 };
 892
 893 struct nes_hw_cqp {
 894         struct nes_hw_cqp_wqe *sq_vbase;
 895         dma_addr_t            sq_pbase;
 896         spinlock_t            lock;
 897         wait_queue_head_t     waitq;
 898         u16                   qp_id;
 899         u16                   sq_head;
 900         u16                   sq_tail;
 901         u16                   sq_size;
 902 };
 903
 904 #define NES_FIRST_FRAG_SIZE 128
 905 struct nes_first_frag {
 906         u8 buffer[NES_FIRST_FRAG_SIZE];
 907 };
 908
 909 struct nes_hw_nic {
 910         struct nes_first_frag    *first_frag_vbase;     /* virtual address of first frags */
 911         struct nes_hw_nic_sq_wqe *sq_vbase;                     /* virtual address of sq */
 912         struct nes_hw_nic_rq_wqe *rq_vbase;                     /* virtual address of rq */
 913         struct sk_buff           *tx_skb[NES_NIC_WQ_SIZE];
 914         struct sk_buff           *rx_skb[NES_NIC_WQ_SIZE];
 915         dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
 916         unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
 917         dma_addr_t sq_pbase;                    /* PCI memory for host rings */
 918         dma_addr_t rq_pbase;                    /* PCI memory for host rings */
 919
 920         u16 qp_id;
 921         u16 sq_head;
 922         u16 sq_tail;
 923         u16 sq_size;
 924         u16 rq_head;
 925         u16 rq_tail;
 926         u16 rq_size;
 927         u8 replenishing_rq;
 928         u8 reserved;
 929
 930         spinlock_t rq_lock;
 931 };
 932
 933 struct nes_hw_nic_cq {
 934         struct nes_hw_nic_cqe volatile *cq_vbase;       /* PCI memory for host rings */
 935         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
 936         dma_addr_t cq_pbase;    /* PCI memory for host rings */
 937         int rx_cqes_completed;
 938         int cqe_allocs_pending;
 939         int rx_pkts_indicated;
 940         u16 cq_head;
 941         u16 cq_size;
 942         u16 cq_number;
 943         u8  cqes_pending;
 944 };
 945
 946 struct nes_hw_qp {
 947         struct nes_hw_qp_wqe *sq_vbase;         /* PCI memory for host rings */
 948         struct nes_hw_qp_wqe *rq_vbase;         /* PCI memory for host rings */
 949         void                 *q2_vbase;                 /* PCI memory for host rings */
 950         dma_addr_t sq_pbase;    /* PCI memory for host rings */
 951         dma_addr_t rq_pbase;    /* PCI memory for host rings */
 952         dma_addr_t q2_pbase;    /* PCI memory for host rings */
 953         u32 qp_id;
 954         u16 sq_head;
 955         u16 sq_tail;
 956         u16 sq_size;
 957         u16 rq_head;
 958         u16 rq_tail;
 959         u16 rq_size;
 960         u8  rq_encoded_size;
 961         u8  sq_encoded_size;
 962 };
 963
 964 struct nes_hw_cq {
 965         struct nes_hw_cqe *cq_vbase;    /* PCI memory for host rings */
 966         void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq);
 967         dma_addr_t cq_pbase;    /* PCI memory for host rings */
 968         u16 cq_head;
 969         u16 cq_size;
 970         u16 cq_number;
 971 };
 972
 973 struct nes_hw_ceq {
 974         struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */
 975         dma_addr_t ceq_pbase;   /* PCI memory for host rings */
 976         u16 ceq_head;
 977         u16 ceq_size;
 978 };
 979
 980 struct nes_hw_aeq {
 981         struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */
 982         dma_addr_t aeq_pbase;   /* PCI memory for host rings */
 983         u16 aeq_head;
 984         u16 aeq_size;
 985 };
 986
 987 struct nic_qp_map {
 988         u8 qpid;
 989         u8 nic_index;
 990         u8 logical_port;
 991         u8 is_hnic;
 992 };
 993
 994 #define NES_CQP_ARP_AEQ_INDEX_MASK  0x000f0000
 995 #define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
 996
 997 #define NES_CQP_APBVT_ADD                       0x00008000
 998 #define NES_CQP_APBVT_NIC_SHIFT         16
 999
1000 #define NES_ARP_ADD     1
1001 #define NES_ARP_DELETE  2
1002 #define NES_ARP_RESOLVE 3
1003
1004 #define NES_MAC_SW_IDLE      0
1005 #define NES_MAC_SW_INTERRUPT 1
1006 #define NES_MAC_SW_MH        2
1007
1008 struct nes_arp_entry {
1009         u32 ip_addr;
1010         u8  mac_addr[ETH_ALEN];
1011 };
1012
1013 #define NES_NIC_FAST_TIMER          96
1014 #define NES_NIC_FAST_TIMER_LOW      40
1015 #define NES_NIC_FAST_TIMER_HIGH     1000
1016 #define DEFAULT_NES_QL_HIGH         256
1017 #define DEFAULT_NES_QL_LOW          16
1018 #define DEFAULT_NES_QL_TARGET       64
1019 #define DEFAULT_JUMBO_NES_QL_LOW    12
1020 #define DEFAULT_JUMBO_NES_QL_TARGET 40
1021 #define DEFAULT_JUMBO_NES_QL_HIGH   128
1022 #define NES_NIC_CQ_DOWNWARD_TREND   16
1023 #define NES_PFT_SIZE                48
1024
1025 #define NES_MGT_WQ_COUNT 32
1026 #define NES_MGT_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_32) | (NES_NIC_CTX_SQ_SIZE_32))
1027 #define NES_MGT_QP_OFFSET 36
1028 #define NES_MGT_QP_COUNT 4
1029
1030 struct nes_hw_tune_timer {
1031     /* u16 cq_count; */
1032     u16 threshold_low;
1033     u16 threshold_target;
1034     u16 threshold_high;
1035     u16 timer_in_use;
1036     u16 timer_in_use_old;
1037     u16 timer_in_use_min;
1038     u16 timer_in_use_max;
1039     u8  timer_direction_upward;
1040     u8  timer_direction_downward;
1041     u16 cq_count_old;
1042     u8  cq_direction_downward;
1043 };
1044
1045 #define NES_TIMER_INT_LIMIT         2
1046 #define NES_TIMER_INT_LIMIT_DYNAMIC 10
1047 #define NES_TIMER_ENABLE_LIMIT      4
1048 #define NES_MAX_LINK_INTERRUPTS     128
1049 #define NES_MAX_LINK_CHECK          200
1050
1051 struct nes_adapter {
1052         u64              fw_ver;
1053         unsigned long    *allocated_qps;
1054         unsigned long    *allocated_cqs;
1055         unsigned long    *allocated_mrs;
1056         unsigned long    *allocated_pds;
1057         unsigned long    *allocated_arps;
1058         struct nes_qp    **qp_table;
1059         struct workqueue_struct *work_q;
1060
1061         struct list_head list;
1062         struct list_head active_listeners;
1063         /* list of the netdev's associated with each logical port */
1064         struct list_head nesvnic_list[4];
1065
1066         struct timer_list  mh_timer;
1067         struct timer_list  lc_timer;
1068         struct work_struct work;
1069         spinlock_t         resource_lock;
1070         spinlock_t         phy_lock;
1071         spinlock_t         pbl_lock;
1072         spinlock_t         periodic_timer_lock;
1073
1074         struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
1075
1076         /* Adapter CEQ and AEQs */
1077         struct nes_hw_ceq ceq[16];
1078         struct nes_hw_aeq aeq[8];
1079
1080         struct nes_hw_tune_timer tune_timer;
1081
1082         unsigned long doorbell_start;
1083
1084         u32 hw_rev;
1085         u32 vendor_id;
1086         u32 vendor_part_id;
1087         u32 device_cap_flags;
1088         u32 tick_delta;
1089         u32 timer_int_req;
1090         u32 arp_table_size;
1091         u32 next_arp_index;
1092
1093         u32 max_mr;
1094         u32 max_256pbl;
1095         u32 max_4kpbl;
1096         u32 free_256pbl;
1097         u32 free_4kpbl;
1098         u32 max_mr_size;
1099         u32 max_qp;
1100         u32 next_qp;
1101         u32 max_irrq;
1102         u32 max_qp_wr;
1103         u32 max_sge;
1104         u32 max_cq;
1105         u32 next_cq;
1106         u32 max_cqe;
1107         u32 max_pd;
1108         u32 base_pd;
1109         u32 next_pd;
1110         u32 hte_index_mask;
1111
1112         /* EEPROM information */
1113         u32 rx_pool_size;
1114         u32 tx_pool_size;
1115         u32 rx_threshold;
1116         u32 tcp_timer_core_clk_divisor;
1117         u32 iwarp_config;
1118         u32 cm_config;
1119         u32 sws_timer_config;
1120         u32 tcp_config1;
1121         u32 wqm_wat;
1122         u32 core_clock;
1123         u32 firmware_version;
1124         u32 eeprom_version;
1125
1126         u32 nic_rx_eth_route_err;
1127
1128         u32 et_rx_coalesce_usecs;
1129         u32 et_rx_max_coalesced_frames;
1130         u32 et_rx_coalesce_usecs_irq;
1131         u32 et_rx_max_coalesced_frames_irq;
1132         u32 et_pkt_rate_low;
1133         u32 et_rx_coalesce_usecs_low;
1134         u32 et_rx_max_coalesced_frames_low;
1135         u32 et_pkt_rate_high;
1136         u32 et_rx_coalesce_usecs_high;
1137         u32 et_rx_max_coalesced_frames_high;
1138         u32 et_rate_sample_interval;
1139         u32 timer_int_limit;
1140         u32 wqm_quanta;
1141         u8 allow_unaligned_fpdus;
1142
1143         /* Adapter base MAC address */
1144         u32 mac_addr_low;
1145         u16 mac_addr_high;
1146
1147         u16 firmware_eeprom_offset;
1148         u16 software_eeprom_offset;
1149
1150         u16 max_irrq_wr;
1151
1152         /* pd config for each port */
1153         u16 pd_config_size[4];
1154         u16 pd_config_base[4];
1155
1156         u16 link_interrupt_count[4];
1157         u8 crit_error_count[32];
1158
1159         /* the phy index for each port */
1160         u8  phy_index[4];
1161         u8  mac_sw_state[4];
1162         u8  mac_link_down[4];
1163         u8  phy_type[4];
1164         u8  log_port;
1165
1166         /* PCI information */
1167         unsigned int  devfn;
1168         unsigned char bus_number;
1169         unsigned char OneG_Mode;
1170
1171         unsigned char ref_count;
1172         u8            netdev_count;
1173         u8            netdev_max;       /* from host nic address count in EEPROM */
1174         u8            port_count;
1175         u8            virtwq;
1176         u8            send_term_ok;
1177         u8            et_use_adaptive_rx_coalesce;
1178         u8            adapter_fcn_count;
1179         u8 pft_mcast_map[NES_PFT_SIZE];
1180 };
1181
1182 struct nes_pbl {
1183         u64              *pbl_vbase;
1184         dma_addr_t       pbl_pbase;
1185         struct page      *page;
1186         unsigned long    user_base;
1187         u32              pbl_size;
1188         struct list_head list;
1189         /* TODO: need to add list for two level tables */
1190 };
1191
1192 #define NES_4K_PBL_CHUNK_SIZE   4096
1193
1194 struct nes_fast_mr_wqe_pbl {
1195         u64             *kva;
1196         dma_addr_t      paddr;
1197 };
1198
1199 struct nes_listener {
1200         struct work_struct      work;
1201         struct workqueue_struct *wq;
1202         struct nes_vnic         *nesvnic;
1203         struct iw_cm_id         *cm_id;
1204         struct list_head        list;
1205         unsigned long           socket;
1206         u8                      accept_failed;
1207 };
1208
1209 struct nes_ib_device;
1210
1211 #define NES_EVENT_DELAY msecs_to_jiffies(100)
1212
1213 struct nes_vnic {
1214         struct nes_ib_device *nesibdev;
1215         u64 sq_full;
1216         u64 tso_requests;
1217         u64 segmented_tso_requests;
1218         u64 linearized_skbs;
1219         u64 tx_sw_dropped;
1220         u64 endnode_nstat_rx_discard;
1221         u64 endnode_nstat_rx_octets;
1222         u64 endnode_nstat_rx_frames;
1223         u64 endnode_nstat_tx_octets;
1224         u64 endnode_nstat_tx_frames;
1225         u64 endnode_ipv4_tcp_retransmits;
1226         /* void *mem; */
1227         struct nes_device *nesdev;
1228         struct net_device *netdev;
1229         atomic_t          rx_skbs_needed;
1230         atomic_t          rx_skb_timer_running;
1231         int               budget;
1232         u32               msg_enable;
1233         /* u32 tx_avail; */
1234         __be32            local_ipaddr;
1235         struct napi_struct   napi;
1236         spinlock_t           tx_lock;   /* could use netdev tx lock? */
1237         struct timer_list    rq_wqes_timer;
1238         u32                  nic_mem_size;
1239         void                 *nic_vbase;
1240         dma_addr_t           nic_pbase;
1241         struct nes_hw_nic    nic;
1242         struct nes_hw_nic_cq nic_cq;
1243         u32    mcrq_qp_id;
1244         struct nes_ucontext *mcrq_ucontext;
1245         struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev);
1246         void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *);
1247         int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr );
1248         struct net_device_stats netstats;
1249         /* used to put the netdev on the adapters logical port list */
1250         struct list_head list;
1251         u16 max_frame_size;
1252         u8  netdev_open;
1253         u8  linkup;
1254         u8  logical_port;
1255         u8  netdev_index;  /* might not be needed, indexes nesdev->netdev */
1256         u8  perfect_filter_index;
1257         u8  nic_index;
1258         u8  qp_nic_index[4];
1259         u8  next_qp_nic_index;
1260         u8  of_device_registered;
1261         u8  rdma_enabled;
1262         struct timer_list event_timer;
1263         enum ib_event_type delayed_event;
1264         enum ib_event_type last_dispatched_event;
1265         spinlock_t port_ibevent_lock;
1266         u32 mgt_mem_size;
1267         void *mgt_vbase;
1268         dma_addr_t mgt_pbase;
1269         struct nes_vnic_mgt *mgtvnic[NES_MGT_QP_COUNT];
1270         struct task_struct *mgt_thread;
1271         wait_queue_head_t mgt_wait_queue;
1272         struct sk_buff_head mgt_skb_list;
1273
1274 };
1275
1276 struct nes_ib_device {
1277         struct ib_device ibdev;
1278         struct nes_vnic *nesvnic;
1279
1280         /* Virtual RNIC Limits */
1281         u32 max_mr;
1282         u32 max_qp;
1283         u32 max_cq;
1284         u32 max_pd;
1285         u32 num_mr;
1286         u32 num_qp;
1287         u32 num_cq;
1288         u32 num_pd;
1289 };
1290
1291 enum nes_hdrct_flags {
1292         DDP_LEN_FLAG                    = 0x80,
1293         DDP_HDR_FLAG                    = 0x40,
1294         RDMA_HDR_FLAG                   = 0x20
1295 };
1296
1297 enum nes_term_layers {
1298         LAYER_RDMA                      = 0,
1299         LAYER_DDP                       = 1,
1300         LAYER_MPA                       = 2
1301 };
1302
1303 enum nes_term_error_types {
1304         RDMAP_CATASTROPHIC              = 0,
1305         RDMAP_REMOTE_PROT               = 1,
1306         RDMAP_REMOTE_OP                 = 2,
1307         DDP_CATASTROPHIC                = 0,
1308         DDP_TAGGED_BUFFER               = 1,
1309         DDP_UNTAGGED_BUFFER             = 2,
1310         DDP_LLP                         = 3
1311 };
1312
1313 enum nes_term_rdma_errors {
1314         RDMAP_INV_STAG                  = 0x00,
1315         RDMAP_INV_BOUNDS                = 0x01,
1316         RDMAP_ACCESS                    = 0x02,
1317         RDMAP_UNASSOC_STAG              = 0x03,
1318         RDMAP_TO_WRAP                   = 0x04,
1319         RDMAP_INV_RDMAP_VER             = 0x05,
1320         RDMAP_UNEXPECTED_OP             = 0x06,
1321         RDMAP_CATASTROPHIC_LOCAL        = 0x07,
1322         RDMAP_CATASTROPHIC_GLOBAL       = 0x08,
1323         RDMAP_CANT_INV_STAG             = 0x09,
1324         RDMAP_UNSPECIFIED               = 0xff
1325 };
1326
1327 enum nes_term_ddp_errors {
1328         DDP_CATASTROPHIC_LOCAL          = 0x00,
1329         DDP_TAGGED_INV_STAG             = 0x00,
1330         DDP_TAGGED_BOUNDS               = 0x01,
1331         DDP_TAGGED_UNASSOC_STAG         = 0x02,
1332         DDP_TAGGED_TO_WRAP              = 0x03,
1333         DDP_TAGGED_INV_DDP_VER          = 0x04,
1334         DDP_UNTAGGED_INV_QN             = 0x01,
1335         DDP_UNTAGGED_INV_MSN_NO_BUF     = 0x02,
1336         DDP_UNTAGGED_INV_MSN_RANGE      = 0x03,
1337         DDP_UNTAGGED_INV_MO             = 0x04,
1338         DDP_UNTAGGED_INV_TOO_LONG       = 0x05,
1339         DDP_UNTAGGED_INV_DDP_VER        = 0x06
1340 };
1341
1342 enum nes_term_mpa_errors {
1343         MPA_CLOSED                      = 0x01,
1344         MPA_CRC                         = 0x02,
1345         MPA_MARKER                      = 0x03,
1346         MPA_REQ_RSP                     = 0x04,
1347 };
1348
1349 struct nes_terminate_hdr {
1350         u8 layer_etype;
1351         u8 error_code;
1352         u8 hdrct;
1353         u8 rsvd;
1354 };
1355
1356 /* Used to determine how to fill in terminate error codes */
1357 #define IWARP_OPCODE_WRITE              0
1358 #define IWARP_OPCODE_READREQ            1
1359 #define IWARP_OPCODE_READRSP            2
1360 #define IWARP_OPCODE_SEND               3
1361 #define IWARP_OPCODE_SEND_INV           4
1362 #define IWARP_OPCODE_SEND_SE            5
1363 #define IWARP_OPCODE_SEND_SE_INV        6
1364 #define IWARP_OPCODE_TERM               7
1365
1366 /* These values are used only during terminate processing */
1367 #define TERM_DDP_LEN_TAGGED     14
1368 #define TERM_DDP_LEN_UNTAGGED   18
1369 #define TERM_RDMA_LEN           28
1370 #define RDMA_OPCODE_MASK        0x0f
1371 #define RDMA_READ_REQ_OPCODE    1
1372 #define BAD_FRAME_OFFSET        64
1373 #define CQE_MAJOR_DRV           0x8000
1374
1375 /* Used for link status recheck after interrupt processing */
1376 #define NES_LINK_RECHECK_DELAY  msecs_to_jiffies(50)
1377 #define NES_LINK_RECHECK_MAX    60
1378
1379 #endif          /* __NES_HW_H */