drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #if defined(CONFIG_X86)
  41 #include <asm/pat.h>
  42 #endif
  43 #include <linux/sched.h>
  44 #include <linux/delay.h>
  45 #include <rdma/ib_user_verbs.h>
  46 #include <rdma/ib_addr.h>
  47 #include <rdma/ib_cache.h>
  48 #include <linux/mlx5/port.h>
  49 #include <linux/mlx5/vport.h>
  50 #include <linux/list.h>
  51 #include <rdma/ib_smi.h>
  52 #include <rdma/ib_umem.h>
  53 #include <linux/in.h>
  54 #include <linux/etherdevice.h>
  55 #include <linux/mlx5/fs.h>
  56 #include "mlx5_ib.h"
  57
  58 #define DRIVER_NAME "mlx5_ib"
  59 #define DRIVER_VERSION "2.2-1"
  60 #define DRIVER_RELDATE  "Feb 2014"
  61
  62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  64 MODULE_LICENSE("Dual BSD/GPL");
  65 MODULE_VERSION(DRIVER_VERSION);
  66
  67 static int deprecated_prof_sel = 2;
  68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  70
  71 static char mlx5_version[] =
  72         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  73         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  74
  75 enum {
  76         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  77 };
  78
  79 static enum rdma_link_layer
  80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  81 {
  82         switch (port_type_cap) {
  83         case MLX5_CAP_PORT_TYPE_IB:
  84                 return IB_LINK_LAYER_INFINIBAND;
  85         case MLX5_CAP_PORT_TYPE_ETH:
  86                 return IB_LINK_LAYER_ETHERNET;
  87         default:
  88                 return IB_LINK_LAYER_UNSPECIFIED;
  89         }
  90 }
  91
  92 static enum rdma_link_layer
  93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  94 {
  95         struct mlx5_ib_dev *dev = to_mdev(device);
  96         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  97
  98         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  99 }
 100
 101 static int mlx5_netdev_event(struct notifier_block *this,
 102                              unsigned long event, void *ptr)
 103 {
 104         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 105         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 106                                                  roce.nb);
 107
 108         switch (event) {
 109         case NETDEV_REGISTER:
 110         case NETDEV_UNREGISTER:
 111                 write_lock(&ibdev->roce.netdev_lock);
 112                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 113                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 114                                              NULL : ndev;
 115                 write_unlock(&ibdev->roce.netdev_lock);
 116                 break;
 117
 118         case NETDEV_UP:
 119         case NETDEV_DOWN: {
 120                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 121                 struct net_device *upper = NULL;
 122
 123                 if (lag_ndev) {
 124                         upper = netdev_master_upper_dev_get(lag_ndev);
 125                         dev_put(lag_ndev);
 126                 }
 127
 128                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 129                     && ibdev->ib_active) {
 130                         struct ib_event ibev = {0};
 131
 132                         ibev.device = &ibdev->ib_dev;
 133                         ibev.event = (event == NETDEV_UP) ?
 134                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
 135                         ibev.element.port_num = 1;
 136                         ib_dispatch_event(&ibev);
 137                 }
 138                 break;
 139         }
 140
 141         default:
 142                 break;
 143         }
 144
 145         return NOTIFY_DONE;
 146 }
 147
 148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 149                                              u8 port_num)
 150 {
 151         struct mlx5_ib_dev *ibdev = to_mdev(device);
 152         struct net_device *ndev;
 153
 154         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 155         if (ndev)
 156                 return ndev;
 157
 158         /* Ensure ndev does not disappear before we invoke dev_hold()
 159          */
 160         read_lock(&ibdev->roce.netdev_lock);
 161         ndev = ibdev->roce.netdev;
 162         if (ndev)
 163                 dev_hold(ndev);
 164         read_unlock(&ibdev->roce.netdev_lock);
 165
 166         return ndev;
 167 }
 168
 169 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 170                                 struct ib_port_attr *props)
 171 {
 172         struct mlx5_ib_dev *dev = to_mdev(device);
 173         struct net_device *ndev, *upper;
 174         enum ib_mtu ndev_ib_mtu;
 175         u16 qkey_viol_cntr;
 176
 177         memset(props, 0, sizeof(*props));
 178
 179         props->port_cap_flags  |= IB_PORT_CM_SUP;
 180         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 181
 182         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 183                                                 roce_address_table_size);
 184         props->max_mtu          = IB_MTU_4096;
 185         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 186         props->pkey_tbl_len     = 1;
 187         props->state            = IB_PORT_DOWN;
 188         props->phys_state       = 3;
 189
 190         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 191         props->qkey_viol_cntr = qkey_viol_cntr;
 192
 193         ndev = mlx5_ib_get_netdev(device, port_num);
 194         if (!ndev)
 195                 return 0;
 196
 197         if (mlx5_lag_is_active(dev->mdev)) {
 198                 rcu_read_lock();
 199                 upper = netdev_master_upper_dev_get_rcu(ndev);
 200                 if (upper) {
 201                         dev_put(ndev);
 202                         ndev = upper;
 203                         dev_hold(ndev);
 204                 }
 205                 rcu_read_unlock();
 206         }
 207
 208         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 209                 props->state      = IB_PORT_ACTIVE;
 210                 props->phys_state = 5;
 211         }
 212
 213         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 214
 215         dev_put(ndev);
 216
 217         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 218
 219         props->active_width     = IB_WIDTH_4X;  /* TODO */
 220         props->active_speed     = IB_SPEED_QDR; /* TODO */
 221
 222         return 0;
 223 }
 224
 225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 226                                      const struct ib_gid_attr *attr,
 227                                      void *mlx5_addr)
 228 {
 229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 230         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 231                                                source_l3_address);
 232         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 233                                                source_mac_47_32);
 234
 235         if (!gid)
 236                 return;
 237
 238         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 239
 240         if (is_vlan_dev(attr->ndev)) {
 241                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 242                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 243         }
 244
 245         switch (attr->gid_type) {
 246         case IB_GID_TYPE_IB:
 247                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 248                 break;
 249         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 250                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 251                 break;
 252
 253         default:
 254                 WARN_ON(true);
 255         }
 256
 257         if (attr->gid_type != IB_GID_TYPE_IB) {
 258                 if (ipv6_addr_v4mapped((void *)gid))
 259                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 260                                     MLX5_ROCE_L3_TYPE_IPV4);
 261                 else
 262                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 263                                     MLX5_ROCE_L3_TYPE_IPV6);
 264         }
 265
 266         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 267             !ipv6_addr_v4mapped((void *)gid))
 268                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 269         else
 270                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 271 }
 272
 273 static int set_roce_addr(struct ib_device *device, u8 port_num,
 274                          unsigned int index,
 275                          const union ib_gid *gid,
 276                          const struct ib_gid_attr *attr)
 277 {
 278         struct mlx5_ib_dev *dev = to_mdev(device);
 279         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
 280         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
 281         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 282         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 283
 284         if (ll != IB_LINK_LAYER_ETHERNET)
 285                 return -EINVAL;
 286
 287         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 288
 289         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 290         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 291         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 292 }
 293
 294 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 295                            unsigned int index, const union ib_gid *gid,
 296                            const struct ib_gid_attr *attr,
 297                            __always_unused void **context)
 298 {
 299         return set_roce_addr(device, port_num, index, gid, attr);
 300 }
 301
 302 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 303                            unsigned int index, __always_unused void **context)
 304 {
 305         return set_roce_addr(device, port_num, index, NULL, NULL);
 306 }
 307
 308 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 309                                int index)
 310 {
 311         struct ib_gid_attr attr;
 312         union ib_gid gid;
 313
 314         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 315                 return 0;
 316
 317         if (!attr.ndev)
 318                 return 0;
 319
 320         dev_put(attr.ndev);
 321
 322         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 323                 return 0;
 324
 325         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 326 }
 327
 328 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 329                            int index, enum ib_gid_type *gid_type)
 330 {
 331         struct ib_gid_attr attr;
 332         union ib_gid gid;
 333         int ret;
 334
 335         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 336         if (ret)
 337                 return ret;
 338
 339         if (!attr.ndev)
 340                 return -ENODEV;
 341
 342         dev_put(attr.ndev);
 343
 344         *gid_type = attr.gid_type;
 345
 346         return 0;
 347 }
 348
 349 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 350 {
 351         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 352                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 353         return 0;
 354 }
 355
 356 enum {
 357         MLX5_VPORT_ACCESS_METHOD_MAD,
 358         MLX5_VPORT_ACCESS_METHOD_HCA,
 359         MLX5_VPORT_ACCESS_METHOD_NIC,
 360 };
 361
 362 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 363 {
 364         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 365                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 366
 367         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 368             IB_LINK_LAYER_ETHERNET)
 369                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 370
 371         return MLX5_VPORT_ACCESS_METHOD_HCA;
 372 }
 373
 374 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 375                             struct ib_device_attr *props)
 376 {
 377         u8 tmp;
 378         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 379         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 380         u8 atomic_req_8B_endianness_mode =
 381                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 382
 383         /* Check if HW supports 8 bytes standard atomic operations and capable
 384          * of host endianness respond
 385          */
 386         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 387         if (((atomic_operations & tmp) == tmp) &&
 388             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 389             (atomic_req_8B_endianness_mode)) {
 390                 props->atomic_cap = IB_ATOMIC_HCA;
 391         } else {
 392                 props->atomic_cap = IB_ATOMIC_NONE;
 393         }
 394 }
 395
 396 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 397                                         __be64 *sys_image_guid)
 398 {
 399         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 400         struct mlx5_core_dev *mdev = dev->mdev;
 401         u64 tmp;
 402         int err;
 403
 404         switch (mlx5_get_vport_access_method(ibdev)) {
 405         case MLX5_VPORT_ACCESS_METHOD_MAD:
 406                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 407                                                             sys_image_guid);
 408
 409         case MLX5_VPORT_ACCESS_METHOD_HCA:
 410                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 411                 break;
 412
 413         case MLX5_VPORT_ACCESS_METHOD_NIC:
 414                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 415                 break;
 416
 417         default:
 418                 return -EINVAL;
 419         }
 420
 421         if (!err)
 422                 *sys_image_guid = cpu_to_be64(tmp);
 423
 424         return err;
 425
 426 }
 427
 428 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 429                                 u16 *max_pkeys)
 430 {
 431         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 432         struct mlx5_core_dev *mdev = dev->mdev;
 433
 434         switch (mlx5_get_vport_access_method(ibdev)) {
 435         case MLX5_VPORT_ACCESS_METHOD_MAD:
 436                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 437
 438         case MLX5_VPORT_ACCESS_METHOD_HCA:
 439         case MLX5_VPORT_ACCESS_METHOD_NIC:
 440                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 441                                                 pkey_table_size));
 442                 return 0;
 443
 444         default:
 445                 return -EINVAL;
 446         }
 447 }
 448
 449 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 450                                 u32 *vendor_id)
 451 {
 452         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 453
 454         switch (mlx5_get_vport_access_method(ibdev)) {
 455         case MLX5_VPORT_ACCESS_METHOD_MAD:
 456                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 457
 458         case MLX5_VPORT_ACCESS_METHOD_HCA:
 459         case MLX5_VPORT_ACCESS_METHOD_NIC:
 460                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 461
 462         default:
 463                 return -EINVAL;
 464         }
 465 }
 466
 467 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 468                                 __be64 *node_guid)
 469 {
 470         u64 tmp;
 471         int err;
 472
 473         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 474         case MLX5_VPORT_ACCESS_METHOD_MAD:
 475                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 476
 477         case MLX5_VPORT_ACCESS_METHOD_HCA:
 478                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 479                 break;
 480
 481         case MLX5_VPORT_ACCESS_METHOD_NIC:
 482                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 483                 break;
 484
 485         default:
 486                 return -EINVAL;
 487         }
 488
 489         if (!err)
 490                 *node_guid = cpu_to_be64(tmp);
 491
 492         return err;
 493 }
 494
 495 struct mlx5_reg_node_desc {
 496         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 497 };
 498
 499 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 500 {
 501         struct mlx5_reg_node_desc in;
 502
 503         if (mlx5_use_mad_ifc(dev))
 504                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 505
 506         memset(&in, 0, sizeof(in));
 507
 508         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 509                                     sizeof(struct mlx5_reg_node_desc),
 510                                     MLX5_REG_NODE_DESC, 0, 0);
 511 }
 512
 513 static int mlx5_ib_query_device(struct ib_device *ibdev,
 514                                 struct ib_device_attr *props,
 515                                 struct ib_udata *uhw)
 516 {
 517         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 518         struct mlx5_core_dev *mdev = dev->mdev;
 519         int err = -ENOMEM;
 520         int max_sq_desc;
 521         int max_rq_sg;
 522         int max_sq_sg;
 523         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 524         struct mlx5_ib_query_device_resp resp = {};
 525         size_t resp_len;
 526         u64 max_tso;
 527
 528         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 529         if (uhw->outlen && uhw->outlen < resp_len)
 530                 return -EINVAL;
 531         else
 532                 resp.response_length = resp_len;
 533
 534         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 535                 return -EINVAL;
 536
 537         memset(props, 0, sizeof(*props));
 538         err = mlx5_query_system_image_guid(ibdev,
 539                                            &props->sys_image_guid);
 540         if (err)
 541                 return err;
 542
 543         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 544         if (err)
 545                 return err;
 546
 547         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 548         if (err)
 549                 return err;
 550
 551         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 552                 (fw_rev_min(dev->mdev) << 16) |
 553                 fw_rev_sub(dev->mdev);
 554         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 555                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 556                 IB_DEVICE_SYS_IMAGE_GUID                |
 557                 IB_DEVICE_RC_RNR_NAK_GEN;
 558
 559         if (MLX5_CAP_GEN(mdev, pkv))
 560                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 561         if (MLX5_CAP_GEN(mdev, qkv))
 562                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 563         if (MLX5_CAP_GEN(mdev, apm))
 564                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 565         if (MLX5_CAP_GEN(mdev, xrc))
 566                 props->device_cap_flags |= IB_DEVICE_XRC;
 567         if (MLX5_CAP_GEN(mdev, imaicl)) {
 568                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 569                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 570                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 571                 /* We support 'Gappy' memory registration too */
 572                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 573         }
 574         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 575         if (MLX5_CAP_GEN(mdev, sho)) {
 576                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 577                 /* At this stage no support for signature handover */
 578                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 579                                       IB_PROT_T10DIF_TYPE_2 |
 580                                       IB_PROT_T10DIF_TYPE_3;
 581                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 582                                        IB_GUARD_T10DIF_CSUM;
 583         }
 584         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 585                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 586
 587         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 588                 if (MLX5_CAP_ETH(mdev, csum_cap))
 589                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 590
 591                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 592                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 593                         if (max_tso) {
 594                                 resp.tso_caps.max_tso = 1 << max_tso;
 595                                 resp.tso_caps.supported_qpts |=
 596                                         1 << IB_QPT_RAW_PACKET;
 597                                 resp.response_length += sizeof(resp.tso_caps);
 598                         }
 599                 }
 600
 601                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 602                         resp.rss_caps.rx_hash_function =
 603                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 604                         resp.rss_caps.rx_hash_fields_mask =
 605                                                 MLX5_RX_HASH_SRC_IPV4 |
 606                                                 MLX5_RX_HASH_DST_IPV4 |
 607                                                 MLX5_RX_HASH_SRC_IPV6 |
 608                                                 MLX5_RX_HASH_DST_IPV6 |
 609                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 610                                                 MLX5_RX_HASH_DST_PORT_TCP |
 611                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 612                                                 MLX5_RX_HASH_DST_PORT_UDP;
 613                         resp.response_length += sizeof(resp.rss_caps);
 614                 }
 615         } else {
 616                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 617                         resp.response_length += sizeof(resp.tso_caps);
 618                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 619                         resp.response_length += sizeof(resp.rss_caps);
 620         }
 621
 622         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 623                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 624                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 625         }
 626
 627         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 628             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
 629                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 630
 631         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 632                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 633
 634         props->vendor_part_id      = mdev->pdev->device;
 635         props->hw_ver              = mdev->pdev->revision;
 636
 637         props->max_mr_size         = ~0ull;
 638         props->page_size_cap       = ~(min_page_size - 1);
 639         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 640         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 641         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 642                      sizeof(struct mlx5_wqe_data_seg);
 643         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 644         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 645                      sizeof(struct mlx5_wqe_raddr_seg)) /
 646                 sizeof(struct mlx5_wqe_data_seg);
 647         props->max_sge = min(max_rq_sg, max_sq_sg);
 648         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 649         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 650         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 651         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 652         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 653         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 654         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 655         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 656         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 657         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 658         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 659         props->max_srq_sge         = max_rq_sg - 1;
 660         props->max_fast_reg_page_list_len =
 661                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 662         get_atomic_caps(dev, props);
 663         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 664         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 665         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 666         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 667                                            props->max_mcast_grp;
 668         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 669         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 670         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 671
 672 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 673         if (MLX5_CAP_GEN(mdev, pg))
 674                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 675         props->odp_caps = dev->odp_caps;
 676 #endif
 677
 678         if (MLX5_CAP_GEN(mdev, cd))
 679                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 680
 681         if (!mlx5_core_is_pf(mdev))
 682                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 683
 684         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 685             IB_LINK_LAYER_ETHERNET) {
 686                 props->rss_caps.max_rwq_indirection_tables =
 687                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 688                 props->rss_caps.max_rwq_indirection_table_size =
 689                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 690                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 691                 props->max_wq_type_rq =
 692                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 693         }
 694
 695         if (uhw->outlen) {
 696                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 697
 698                 if (err)
 699                         return err;
 700         }
 701
 702         return 0;
 703 }
 704
 705 enum mlx5_ib_width {
 706         MLX5_IB_WIDTH_1X        = 1 << 0,
 707         MLX5_IB_WIDTH_2X        = 1 << 1,
 708         MLX5_IB_WIDTH_4X        = 1 << 2,
 709         MLX5_IB_WIDTH_8X        = 1 << 3,
 710         MLX5_IB_WIDTH_12X       = 1 << 4
 711 };
 712
 713 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 714                                   u8 *ib_width)
 715 {
 716         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 717         int err = 0;
 718
 719         if (active_width & MLX5_IB_WIDTH_1X) {
 720                 *ib_width = IB_WIDTH_1X;
 721         } else if (active_width & MLX5_IB_WIDTH_2X) {
 722                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 723                             (int)active_width);
 724                 err = -EINVAL;
 725         } else if (active_width & MLX5_IB_WIDTH_4X) {
 726                 *ib_width = IB_WIDTH_4X;
 727         } else if (active_width & MLX5_IB_WIDTH_8X) {
 728                 *ib_width = IB_WIDTH_8X;
 729         } else if (active_width & MLX5_IB_WIDTH_12X) {
 730                 *ib_width = IB_WIDTH_12X;
 731         } else {
 732                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 733                             (int)active_width);
 734                 err = -EINVAL;
 735         }
 736
 737         return err;
 738 }
 739
 740 static int mlx5_mtu_to_ib_mtu(int mtu)
 741 {
 742         switch (mtu) {
 743         case 256: return 1;
 744         case 512: return 2;
 745         case 1024: return 3;
 746         case 2048: return 4;
 747         case 4096: return 5;
 748         default:
 749                 pr_warn("invalid mtu\n");
 750                 return -1;
 751         }
 752 }
 753
 754 enum ib_max_vl_num {
 755         __IB_MAX_VL_0           = 1,
 756         __IB_MAX_VL_0_1         = 2,
 757         __IB_MAX_VL_0_3         = 3,
 758         __IB_MAX_VL_0_7         = 4,
 759         __IB_MAX_VL_0_14        = 5,
 760 };
 761
 762 enum mlx5_vl_hw_cap {
 763         MLX5_VL_HW_0    = 1,
 764         MLX5_VL_HW_0_1  = 2,
 765         MLX5_VL_HW_0_2  = 3,
 766         MLX5_VL_HW_0_3  = 4,
 767         MLX5_VL_HW_0_4  = 5,
 768         MLX5_VL_HW_0_5  = 6,
 769         MLX5_VL_HW_0_6  = 7,
 770         MLX5_VL_HW_0_7  = 8,
 771         MLX5_VL_HW_0_14 = 15
 772 };
 773
 774 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 775                                 u8 *max_vl_num)
 776 {
 777         switch (vl_hw_cap) {
 778         case MLX5_VL_HW_0:
 779                 *max_vl_num = __IB_MAX_VL_0;
 780                 break;
 781         case MLX5_VL_HW_0_1:
 782                 *max_vl_num = __IB_MAX_VL_0_1;
 783                 break;
 784         case MLX5_VL_HW_0_3:
 785                 *max_vl_num = __IB_MAX_VL_0_3;
 786                 break;
 787         case MLX5_VL_HW_0_7:
 788                 *max_vl_num = __IB_MAX_VL_0_7;
 789                 break;
 790         case MLX5_VL_HW_0_14:
 791                 *max_vl_num = __IB_MAX_VL_0_14;
 792                 break;
 793
 794         default:
 795                 return -EINVAL;
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 802                                struct ib_port_attr *props)
 803 {
 804         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 805         struct mlx5_core_dev *mdev = dev->mdev;
 806         struct mlx5_hca_vport_context *rep;
 807         u16 max_mtu;
 808         u16 oper_mtu;
 809         int err;
 810         u8 ib_link_width_oper;
 811         u8 vl_hw_cap;
 812
 813         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 814         if (!rep) {
 815                 err = -ENOMEM;
 816                 goto out;
 817         }
 818
 819         memset(props, 0, sizeof(*props));
 820
 821         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 822         if (err)
 823                 goto out;
 824
 825         props->lid              = rep->lid;
 826         props->lmc              = rep->lmc;
 827         props->sm_lid           = rep->sm_lid;
 828         props->sm_sl            = rep->sm_sl;
 829         props->state            = rep->vport_state;
 830         props->phys_state       = rep->port_physical_state;
 831         props->port_cap_flags   = rep->cap_mask1;
 832         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 833         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 834         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 835         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 836         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 837         props->subnet_timeout   = rep->subnet_timeout;
 838         props->init_type_reply  = rep->init_type_reply;
 839         props->grh_required     = rep->grh_required;
 840
 841         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 842         if (err)
 843                 goto out;
 844
 845         err = translate_active_width(ibdev, ib_link_width_oper,
 846                                      &props->active_width);
 847         if (err)
 848                 goto out;
 849         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 850         if (err)
 851                 goto out;
 852
 853         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 854
 855         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 856
 857         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 858
 859         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 860
 861         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 862         if (err)
 863                 goto out;
 864
 865         err = translate_max_vl_num(ibdev, vl_hw_cap,
 866                                    &props->max_vl_num);
 867 out:
 868         kfree(rep);
 869         return err;
 870 }
 871
 872 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 873                        struct ib_port_attr *props)
 874 {
 875         switch (mlx5_get_vport_access_method(ibdev)) {
 876         case MLX5_VPORT_ACCESS_METHOD_MAD:
 877                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 878
 879         case MLX5_VPORT_ACCESS_METHOD_HCA:
 880                 return mlx5_query_hca_port(ibdev, port, props);
 881
 882         case MLX5_VPORT_ACCESS_METHOD_NIC:
 883                 return mlx5_query_port_roce(ibdev, port, props);
 884
 885         default:
 886                 return -EINVAL;
 887         }
 888 }
 889
 890 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 891                              union ib_gid *gid)
 892 {
 893         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 894         struct mlx5_core_dev *mdev = dev->mdev;
 895
 896         switch (mlx5_get_vport_access_method(ibdev)) {
 897         case MLX5_VPORT_ACCESS_METHOD_MAD:
 898                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 899
 900         case MLX5_VPORT_ACCESS_METHOD_HCA:
 901                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 902
 903         default:
 904                 return -EINVAL;
 905         }
 906
 907 }
 908
 909 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 910                               u16 *pkey)
 911 {
 912         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 913         struct mlx5_core_dev *mdev = dev->mdev;
 914
 915         switch (mlx5_get_vport_access_method(ibdev)) {
 916         case MLX5_VPORT_ACCESS_METHOD_MAD:
 917                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 918
 919         case MLX5_VPORT_ACCESS_METHOD_HCA:
 920         case MLX5_VPORT_ACCESS_METHOD_NIC:
 921                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 922                                                  pkey);
 923         default:
 924                 return -EINVAL;
 925         }
 926 }
 927
 928 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 929                                  struct ib_device_modify *props)
 930 {
 931         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 932         struct mlx5_reg_node_desc in;
 933         struct mlx5_reg_node_desc out;
 934         int err;
 935
 936         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 937                 return -EOPNOTSUPP;
 938
 939         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 940                 return 0;
 941
 942         /*
 943          * If possible, pass node desc to FW, so it can generate
 944          * a 144 trap.  If cmd fails, just ignore.
 945          */
 946         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 947         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 948                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 949         if (err)
 950                 return err;
 951
 952         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 953
 954         return err;
 955 }
 956
 957 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 958                                struct ib_port_modify *props)
 959 {
 960         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 961         struct ib_port_attr attr;
 962         u32 tmp;
 963         int err;
 964
 965         mutex_lock(&dev->cap_mask_mutex);
 966
 967         err = mlx5_ib_query_port(ibdev, port, &attr);
 968         if (err)
 969                 goto out;
 970
 971         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 972                 ~props->clr_port_cap_mask;
 973
 974         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 975
 976 out:
 977         mutex_unlock(&dev->cap_mask_mutex);
 978         return err;
 979 }
 980
 981 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 982                                                   struct ib_udata *udata)
 983 {
 984         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 985         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
 986         struct mlx5_ib_alloc_ucontext_resp resp = {};
 987         struct mlx5_ib_ucontext *context;
 988         struct mlx5_uuar_info *uuari;
 989         struct mlx5_uar *uars;
 990         int gross_uuars;
 991         int num_uars;
 992         int ver;
 993         int uuarn;
 994         int err;
 995         int i;
 996         size_t reqlen;
 997         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
 998                                      max_cqe_version);
 999
1000         if (!dev->ib_active)
1001                 return ERR_PTR(-EAGAIN);
1002
1003         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1004                 return ERR_PTR(-EINVAL);
1005
1006         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1007         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1008                 ver = 0;
1009         else if (reqlen >= min_req_v2)
1010                 ver = 2;
1011         else
1012                 return ERR_PTR(-EINVAL);
1013
1014         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1015         if (err)
1016                 return ERR_PTR(err);
1017
1018         if (req.flags)
1019                 return ERR_PTR(-EINVAL);
1020
1021         if (req.total_num_uuars > MLX5_MAX_UUARS)
1022                 return ERR_PTR(-ENOMEM);
1023
1024         if (req.total_num_uuars == 0)
1025                 return ERR_PTR(-EINVAL);
1026
1027         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1028                 return ERR_PTR(-EOPNOTSUPP);
1029
1030         if (reqlen > sizeof(req) &&
1031             !ib_is_udata_cleared(udata, sizeof(req),
1032                                  reqlen - sizeof(req)))
1033                 return ERR_PTR(-EOPNOTSUPP);
1034
1035         req.total_num_uuars = ALIGN(req.total_num_uuars,
1036                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
1037         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1038                 return ERR_PTR(-EINVAL);
1039
1040         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1041         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1042         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1043         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1044                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1045         resp.cache_line_size = cache_line_size();
1046         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1047         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1048         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1049         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1050         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1051         resp.cqe_version = min_t(__u8,
1052                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1053                                  req.max_cqe_version);
1054         resp.response_length = min(offsetof(typeof(resp), response_length) +
1055                                    sizeof(resp.response_length), udata->outlen);
1056
1057         context = kzalloc(sizeof(*context), GFP_KERNEL);
1058         if (!context)
1059                 return ERR_PTR(-ENOMEM);
1060
1061         uuari = &context->uuari;
1062         mutex_init(&uuari->lock);
1063         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1064         if (!uars) {
1065                 err = -ENOMEM;
1066                 goto out_ctx;
1067         }
1068
1069         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1070                                 sizeof(*uuari->bitmap),
1071                                 GFP_KERNEL);
1072         if (!uuari->bitmap) {
1073                 err = -ENOMEM;
1074                 goto out_uar_ctx;
1075         }
1076         /*
1077          * clear all fast path uuars
1078          */
1079         for (i = 0; i < gross_uuars; i++) {
1080                 uuarn = i & 3;
1081                 if (uuarn == 2 || uuarn == 3)
1082                         set_bit(i, uuari->bitmap);
1083         }
1084
1085         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1086         if (!uuari->count) {
1087                 err = -ENOMEM;
1088                 goto out_bitmap;
1089         }
1090
1091         for (i = 0; i < num_uars; i++) {
1092                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1093                 if (err)
1094                         goto out_count;
1095         }
1096
1097 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1098         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1099 #endif
1100
1101         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1102                 err = mlx5_core_alloc_transport_domain(dev->mdev,
1103                                                        &context->tdn);
1104                 if (err)
1105                         goto out_uars;
1106         }
1107
1108         INIT_LIST_HEAD(&context->vma_private_list);
1109         INIT_LIST_HEAD(&context->db_page_list);
1110         mutex_init(&context->db_page_mutex);
1111
1112         resp.tot_uuars = req.total_num_uuars;
1113         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1114
1115         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1116                 resp.response_length += sizeof(resp.cqe_version);
1117
1118         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1119                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1120                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1121         }
1122
1123         /*
1124          * We don't want to expose information from the PCI bar that is located
1125          * after 4096 bytes, so if the arch only supports larger pages, let's
1126          * pretend we don't support reading the HCA's core clock. This is also
1127          * forced by mmap function.
1128          */
1129         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1130                 if (PAGE_SIZE <= 4096) {
1131                         resp.comp_mask |=
1132                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1133                         resp.hca_core_clock_offset =
1134                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1135                 }
1136                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1137                                         sizeof(resp.reserved2);
1138         }
1139
1140         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1141         if (err)
1142                 goto out_td;
1143
1144         uuari->ver = ver;
1145         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1146         uuari->uars = uars;
1147         uuari->num_uars = num_uars;
1148         context->cqe_version = resp.cqe_version;
1149
1150         return &context->ibucontext;
1151
1152 out_td:
1153         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1154                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1155
1156 out_uars:
1157         for (i--; i >= 0; i--)
1158                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1159 out_count:
1160         kfree(uuari->count);
1161
1162 out_bitmap:
1163         kfree(uuari->bitmap);
1164
1165 out_uar_ctx:
1166         kfree(uars);
1167
1168 out_ctx:
1169         kfree(context);
1170         return ERR_PTR(err);
1171 }
1172
1173 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1174 {
1175         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1176         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1177         struct mlx5_uuar_info *uuari = &context->uuari;
1178         int i;
1179
1180         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1181                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1182
1183         for (i = 0; i < uuari->num_uars; i++) {
1184                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1185                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1186         }
1187
1188         kfree(uuari->count);
1189         kfree(uuari->bitmap);
1190         kfree(uuari->uars);
1191         kfree(context);
1192
1193         return 0;
1194 }
1195
1196 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1197 {
1198         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1199 }
1200
1201 static int get_command(unsigned long offset)
1202 {
1203         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1204 }
1205
1206 static int get_arg(unsigned long offset)
1207 {
1208         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1209 }
1210
1211 static int get_index(unsigned long offset)
1212 {
1213         return get_arg(offset);
1214 }
1215
1216 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1217 {
1218         /* vma_open is called when a new VMA is created on top of our VMA.  This
1219          * is done through either mremap flow or split_vma (usually due to
1220          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1221          * as this VMA is strongly hardware related.  Therefore we set the
1222          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1223          * calling us again and trying to do incorrect actions.  We assume that
1224          * the original VMA size is exactly a single page, and therefore all
1225          * "splitting" operation will not happen to it.
1226          */
1227         area->vm_ops = NULL;
1228 }
1229
1230 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1231 {
1232         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1233
1234         /* It's guaranteed that all VMAs opened on a FD are closed before the
1235          * file itself is closed, therefore no sync is needed with the regular
1236          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1237          * However need a sync with accessing the vma as part of
1238          * mlx5_ib_disassociate_ucontext.
1239          * The close operation is usually called under mm->mmap_sem except when
1240          * process is exiting.
1241          * The exiting case is handled explicitly as part of
1242          * mlx5_ib_disassociate_ucontext.
1243          */
1244         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1245
1246         /* setting the vma context pointer to null in the mlx5_ib driver's
1247          * private data, to protect a race condition in
1248          * mlx5_ib_disassociate_ucontext().
1249          */
1250         mlx5_ib_vma_priv_data->vma = NULL;
1251         list_del(&mlx5_ib_vma_priv_data->list);
1252         kfree(mlx5_ib_vma_priv_data);
1253 }
1254
1255 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1256         .open = mlx5_ib_vma_open,
1257         .close = mlx5_ib_vma_close
1258 };
1259
1260 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1261                                 struct mlx5_ib_ucontext *ctx)
1262 {
1263         struct mlx5_ib_vma_private_data *vma_prv;
1264         struct list_head *vma_head = &ctx->vma_private_list;
1265
1266         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1267         if (!vma_prv)
1268                 return -ENOMEM;
1269
1270         vma_prv->vma = vma;
1271         vma->vm_private_data = vma_prv;
1272         vma->vm_ops =  &mlx5_ib_vm_ops;
1273
1274         list_add(&vma_prv->list, vma_head);
1275
1276         return 0;
1277 }
1278
1279 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1280 {
1281         int ret;
1282         struct vm_area_struct *vma;
1283         struct mlx5_ib_vma_private_data *vma_private, *n;
1284         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1285         struct task_struct *owning_process  = NULL;
1286         struct mm_struct   *owning_mm       = NULL;
1287
1288         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1289         if (!owning_process)
1290                 return;
1291
1292         owning_mm = get_task_mm(owning_process);
1293         if (!owning_mm) {
1294                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1295                 while (1) {
1296                         put_task_struct(owning_process);
1297                         usleep_range(1000, 2000);
1298                         owning_process = get_pid_task(ibcontext->tgid,
1299                                                       PIDTYPE_PID);
1300                         if (!owning_process ||
1301                             owning_process->state == TASK_DEAD) {
1302                                 pr_info("disassociate ucontext done, task was terminated\n");
1303                                 /* in case task was dead need to release the
1304                                  * task struct.
1305                                  */
1306                                 if (owning_process)
1307                                         put_task_struct(owning_process);
1308                                 return;
1309                         }
1310                 }
1311         }
1312
1313         /* need to protect from a race on closing the vma as part of
1314          * mlx5_ib_vma_close.
1315          */
1316         down_read(&owning_mm->mmap_sem);
1317         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1318                                  list) {
1319                 vma = vma_private->vma;
1320                 ret = zap_vma_ptes(vma, vma->vm_start,
1321                                    PAGE_SIZE);
1322                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1323                 /* context going to be destroyed, should
1324                  * not access ops any more.
1325                  */
1326                 vma->vm_ops = NULL;
1327                 list_del(&vma_private->list);
1328                 kfree(vma_private);
1329         }
1330         up_read(&owning_mm->mmap_sem);
1331         mmput(owning_mm);
1332         put_task_struct(owning_process);
1333 }
1334
1335 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1336 {
1337         switch (cmd) {
1338         case MLX5_IB_MMAP_WC_PAGE:
1339                 return "WC";
1340         case MLX5_IB_MMAP_REGULAR_PAGE:
1341                 return "best effort WC";
1342         case MLX5_IB_MMAP_NC_PAGE:
1343                 return "NC";
1344         default:
1345                 return NULL;
1346         }
1347 }
1348
1349 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1350                     struct vm_area_struct *vma,
1351                     struct mlx5_ib_ucontext *context)
1352 {
1353         struct mlx5_uuar_info *uuari = &context->uuari;
1354         int err;
1355         unsigned long idx;
1356         phys_addr_t pfn, pa;
1357         pgprot_t prot;
1358
1359         switch (cmd) {
1360         case MLX5_IB_MMAP_WC_PAGE:
1361 /* Some architectures don't support WC memory */
1362 #if defined(CONFIG_X86)
1363                 if (!pat_enabled())
1364                         return -EPERM;
1365 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1366                         return -EPERM;
1367 #endif
1368         /* fall through */
1369         case MLX5_IB_MMAP_REGULAR_PAGE:
1370                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1371                 prot = pgprot_writecombine(vma->vm_page_prot);
1372                 break;
1373         case MLX5_IB_MMAP_NC_PAGE:
1374                 prot = pgprot_noncached(vma->vm_page_prot);
1375                 break;
1376         default:
1377                 return -EINVAL;
1378         }
1379
1380         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1381                 return -EINVAL;
1382
1383         idx = get_index(vma->vm_pgoff);
1384         if (idx >= uuari->num_uars)
1385                 return -EINVAL;
1386
1387         pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1388         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1389
1390         vma->vm_page_prot = prot;
1391         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1392                                  PAGE_SIZE, vma->vm_page_prot);
1393         if (err) {
1394                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1395                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1396                 return -EAGAIN;
1397         }
1398
1399         pa = pfn << PAGE_SHIFT;
1400         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1401                     vma->vm_start, &pa);
1402
1403         return mlx5_ib_set_vma_data(vma, context);
1404 }
1405
1406 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1407 {
1408         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1409         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1410         unsigned long command;
1411         phys_addr_t pfn;
1412
1413         command = get_command(vma->vm_pgoff);
1414         switch (command) {
1415         case MLX5_IB_MMAP_WC_PAGE:
1416         case MLX5_IB_MMAP_NC_PAGE:
1417         case MLX5_IB_MMAP_REGULAR_PAGE:
1418                 return uar_mmap(dev, command, vma, context);
1419
1420         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1421                 return -ENOSYS;
1422
1423         case MLX5_IB_MMAP_CORE_CLOCK:
1424                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1425                         return -EINVAL;
1426
1427                 if (vma->vm_flags & VM_WRITE)
1428                         return -EPERM;
1429
1430                 /* Don't expose to user-space information it shouldn't have */
1431                 if (PAGE_SIZE > 4096)
1432                         return -EOPNOTSUPP;
1433
1434                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1435                 pfn = (dev->mdev->iseg_base +
1436                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1437                         PAGE_SHIFT;
1438                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1439                                        PAGE_SIZE, vma->vm_page_prot))
1440                         return -EAGAIN;
1441
1442                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1443                             vma->vm_start,
1444                             (unsigned long long)pfn << PAGE_SHIFT);
1445                 break;
1446
1447         default:
1448                 return -EINVAL;
1449         }
1450
1451         return 0;
1452 }
1453
1454 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1455                                       struct ib_ucontext *context,
1456                                       struct ib_udata *udata)
1457 {
1458         struct mlx5_ib_alloc_pd_resp resp;
1459         struct mlx5_ib_pd *pd;
1460         int err;
1461
1462         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1463         if (!pd)
1464                 return ERR_PTR(-ENOMEM);
1465
1466         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1467         if (err) {
1468                 kfree(pd);
1469                 return ERR_PTR(err);
1470         }
1471
1472         if (context) {
1473                 resp.pdn = pd->pdn;
1474                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1475                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1476                         kfree(pd);
1477                         return ERR_PTR(-EFAULT);
1478                 }
1479         }
1480
1481         return &pd->ibpd;
1482 }
1483
1484 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1485 {
1486         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1487         struct mlx5_ib_pd *mpd = to_mpd(pd);
1488
1489         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1490         kfree(mpd);
1491
1492         return 0;
1493 }
1494
1495 enum {
1496         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1497         MATCH_CRITERIA_ENABLE_MISC_BIT,
1498         MATCH_CRITERIA_ENABLE_INNER_BIT
1499 };
1500
1501 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1502         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1503                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1504
1505 static u8 get_match_criteria_enable(u32 *match_criteria)
1506 {
1507         u8 match_criteria_enable;
1508
1509         match_criteria_enable =
1510                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1511                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1512         match_criteria_enable |=
1513                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1514                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1515         match_criteria_enable |=
1516                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1517                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1518
1519         return match_criteria_enable;
1520 }
1521
1522 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1523 {
1524         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1525         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1526 }
1527
1528 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1529 {
1530         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1531         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1532         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1533         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1534 }
1535
1536 #define LAST_ETH_FIELD vlan_tag
1537 #define LAST_IB_FIELD sl
1538 #define LAST_IPV4_FIELD tos
1539 #define LAST_IPV6_FIELD traffic_class
1540 #define LAST_TCP_UDP_FIELD src_port
1541
1542 /* Field is the last supported field */
1543 #define FIELDS_NOT_SUPPORTED(filter, field)\
1544         memchr_inv((void *)&filter.field  +\
1545                    sizeof(filter.field), 0,\
1546                    sizeof(filter) -\
1547                    offsetof(typeof(filter), field) -\
1548                    sizeof(filter.field))
1549
1550 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1551                            const union ib_flow_spec *ib_spec)
1552 {
1553         void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1554                                              outer_headers);
1555         void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1556                                              outer_headers);
1557         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1558                                            misc_parameters);
1559         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1560                                            misc_parameters);
1561
1562         switch (ib_spec->type) {
1563         case IB_FLOW_SPEC_ETH:
1564                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1565                         return -ENOTSUPP;
1566
1567                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1568                                              dmac_47_16),
1569                                 ib_spec->eth.mask.dst_mac);
1570                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1571                                              dmac_47_16),
1572                                 ib_spec->eth.val.dst_mac);
1573
1574                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1575                                              smac_47_16),
1576                                 ib_spec->eth.mask.src_mac);
1577                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1578                                              smac_47_16),
1579                                 ib_spec->eth.val.src_mac);
1580
1581                 if (ib_spec->eth.mask.vlan_tag) {
1582                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1583                                  vlan_tag, 1);
1584                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1585                                  vlan_tag, 1);
1586
1587                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1588                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1589                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1590                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1591
1592                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1593                                  first_cfi,
1594                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1595                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1596                                  first_cfi,
1597                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1598
1599                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1600                                  first_prio,
1601                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1602                         MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1603                                  first_prio,
1604                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1605                 }
1606                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1607                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1608                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1609                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1610                 break;
1611         case IB_FLOW_SPEC_IPV4:
1612                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1613                         return -ENOTSUPP;
1614
1615                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1616                          ethertype, 0xffff);
1617                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1618                          ethertype, ETH_P_IP);
1619
1620                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1621                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1622                        &ib_spec->ipv4.mask.src_ip,
1623                        sizeof(ib_spec->ipv4.mask.src_ip));
1624                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1625                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1626                        &ib_spec->ipv4.val.src_ip,
1627                        sizeof(ib_spec->ipv4.val.src_ip));
1628                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1629                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1630                        &ib_spec->ipv4.mask.dst_ip,
1631                        sizeof(ib_spec->ipv4.mask.dst_ip));
1632                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1633                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1634                        &ib_spec->ipv4.val.dst_ip,
1635                        sizeof(ib_spec->ipv4.val.dst_ip));
1636
1637                 set_tos(outer_headers_c, outer_headers_v,
1638                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1639
1640                 set_proto(outer_headers_c, outer_headers_v,
1641                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1642                 break;
1643         case IB_FLOW_SPEC_IPV6:
1644                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1645                         return -ENOTSUPP;
1646
1647                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1648                          ethertype, 0xffff);
1649                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1650                          ethertype, ETH_P_IPV6);
1651
1652                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1653                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1654                        &ib_spec->ipv6.mask.src_ip,
1655                        sizeof(ib_spec->ipv6.mask.src_ip));
1656                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1657                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1658                        &ib_spec->ipv6.val.src_ip,
1659                        sizeof(ib_spec->ipv6.val.src_ip));
1660                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1661                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1662                        &ib_spec->ipv6.mask.dst_ip,
1663                        sizeof(ib_spec->ipv6.mask.dst_ip));
1664                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1665                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1666                        &ib_spec->ipv6.val.dst_ip,
1667                        sizeof(ib_spec->ipv6.val.dst_ip));
1668
1669                 set_tos(outer_headers_c, outer_headers_v,
1670                         ib_spec->ipv6.mask.traffic_class,
1671                         ib_spec->ipv6.val.traffic_class);
1672
1673                 set_proto(outer_headers_c, outer_headers_v,
1674                           ib_spec->ipv6.mask.next_hdr,
1675                           ib_spec->ipv6.val.next_hdr);
1676
1677                 MLX5_SET(fte_match_set_misc, misc_params_c,
1678                          outer_ipv6_flow_label,
1679                          ntohl(ib_spec->ipv6.mask.flow_label));
1680                 MLX5_SET(fte_match_set_misc, misc_params_v,
1681                          outer_ipv6_flow_label,
1682                          ntohl(ib_spec->ipv6.val.flow_label));
1683                 break;
1684         case IB_FLOW_SPEC_TCP:
1685                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1686                                          LAST_TCP_UDP_FIELD))
1687                         return -ENOTSUPP;
1688
1689                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1690                          0xff);
1691                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1692                          IPPROTO_TCP);
1693
1694                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1695                          ntohs(ib_spec->tcp_udp.mask.src_port));
1696                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1697                          ntohs(ib_spec->tcp_udp.val.src_port));
1698
1699                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1700                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1701                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1702                          ntohs(ib_spec->tcp_udp.val.dst_port));
1703                 break;
1704         case IB_FLOW_SPEC_UDP:
1705                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1706                                          LAST_TCP_UDP_FIELD))
1707                         return -ENOTSUPP;
1708
1709                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1710                          0xff);
1711                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1712                          IPPROTO_UDP);
1713
1714                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1715                          ntohs(ib_spec->tcp_udp.mask.src_port));
1716                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1717                          ntohs(ib_spec->tcp_udp.val.src_port));
1718
1719                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1720                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1721                 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1722                          ntohs(ib_spec->tcp_udp.val.dst_port));
1723                 break;
1724         default:
1725                 return -EINVAL;
1726         }
1727
1728         return 0;
1729 }
1730
1731 /* If a flow could catch both multicast and unicast packets,
1732  * it won't fall into the multicast flow steering table and this rule
1733  * could steal other multicast packets.
1734  */
1735 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1736 {
1737         struct ib_flow_spec_eth *eth_spec;
1738
1739         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1740             ib_attr->size < sizeof(struct ib_flow_attr) +
1741             sizeof(struct ib_flow_spec_eth) ||
1742             ib_attr->num_of_specs < 1)
1743                 return false;
1744
1745         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1746         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1747             eth_spec->size != sizeof(*eth_spec))
1748                 return false;
1749
1750         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1751                is_multicast_ether_addr(eth_spec->val.dst_mac);
1752 }
1753
1754 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1755 {
1756         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1757         bool has_ipv4_spec = false;
1758         bool eth_type_ipv4 = true;
1759         unsigned int spec_index;
1760
1761         /* Validate that ethertype is correct */
1762         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1763                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1764                     ib_spec->eth.mask.ether_type) {
1765                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1766                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1767                                 eth_type_ipv4 = false;
1768                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1769                         has_ipv4_spec = true;
1770                 }
1771                 ib_spec = (void *)ib_spec + ib_spec->size;
1772         }
1773         return !has_ipv4_spec || eth_type_ipv4;
1774 }
1775
1776 static void put_flow_table(struct mlx5_ib_dev *dev,
1777                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1778 {
1779         prio->refcount -= !!ft_added;
1780         if (!prio->refcount) {
1781                 mlx5_destroy_flow_table(prio->flow_table);
1782                 prio->flow_table = NULL;
1783         }
1784 }
1785
1786 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1787 {
1788         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1789         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1790                                                           struct mlx5_ib_flow_handler,
1791                                                           ibflow);
1792         struct mlx5_ib_flow_handler *iter, *tmp;
1793
1794         mutex_lock(&dev->flow_db.lock);
1795
1796         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1797                 mlx5_del_flow_rule(iter->rule);
1798                 put_flow_table(dev, iter->prio, true);
1799                 list_del(&iter->list);
1800                 kfree(iter);
1801         }
1802
1803         mlx5_del_flow_rule(handler->rule);
1804         put_flow_table(dev, handler->prio, true);
1805         mutex_unlock(&dev->flow_db.lock);
1806
1807         kfree(handler);
1808
1809         return 0;
1810 }
1811
1812 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1813 {
1814         priority *= 2;
1815         if (!dont_trap)
1816                 priority++;
1817         return priority;
1818 }
1819
1820 enum flow_table_type {
1821         MLX5_IB_FT_RX,
1822         MLX5_IB_FT_TX
1823 };
1824
1825 #define MLX5_FS_MAX_TYPES        10
1826 #define MLX5_FS_MAX_ENTRIES      32000UL
1827 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1828                                                 struct ib_flow_attr *flow_attr,
1829                                                 enum flow_table_type ft_type)
1830 {
1831         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1832         struct mlx5_flow_namespace *ns = NULL;
1833         struct mlx5_ib_flow_prio *prio;
1834         struct mlx5_flow_table *ft;
1835         int num_entries;
1836         int num_groups;
1837         int priority;
1838         int err = 0;
1839
1840         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1841                 if (flow_is_multicast_only(flow_attr) &&
1842                     !dont_trap)
1843                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1844                 else
1845                         priority = ib_prio_to_core_prio(flow_attr->priority,
1846                                                         dont_trap);
1847                 ns = mlx5_get_flow_namespace(dev->mdev,
1848                                              MLX5_FLOW_NAMESPACE_BYPASS);
1849                 num_entries = MLX5_FS_MAX_ENTRIES;
1850                 num_groups = MLX5_FS_MAX_TYPES;
1851                 prio = &dev->flow_db.prios[priority];
1852         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1853                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1854                 ns = mlx5_get_flow_namespace(dev->mdev,
1855                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1856                 build_leftovers_ft_param(&priority,
1857                                          &num_entries,
1858                                          &num_groups);
1859                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1860         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1861                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1862                                         allow_sniffer_and_nic_rx_shared_tir))
1863                         return ERR_PTR(-ENOTSUPP);
1864
1865                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1866                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1867                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1868
1869                 prio = &dev->flow_db.sniffer[ft_type];
1870                 priority = 0;
1871                 num_entries = 1;
1872                 num_groups = 1;
1873         }
1874
1875         if (!ns)
1876                 return ERR_PTR(-ENOTSUPP);
1877
1878         ft = prio->flow_table;
1879         if (!ft) {
1880                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1881                                                          num_entries,
1882                                                          num_groups,
1883                                                          0);
1884
1885                 if (!IS_ERR(ft)) {
1886                         prio->refcount = 0;
1887                         prio->flow_table = ft;
1888                 } else {
1889                         err = PTR_ERR(ft);
1890                 }
1891         }
1892
1893         return err ? ERR_PTR(err) : prio;
1894 }
1895
1896 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1897                                                      struct mlx5_ib_flow_prio *ft_prio,
1898                                                      const struct ib_flow_attr *flow_attr,
1899                                                      struct mlx5_flow_destination *dst)
1900 {
1901         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1902         struct mlx5_ib_flow_handler *handler;
1903         struct mlx5_flow_spec *spec;
1904         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1905         unsigned int spec_index;
1906         u32 action;
1907         int err = 0;
1908
1909         if (!is_valid_attr(flow_attr))
1910                 return ERR_PTR(-EINVAL);
1911
1912         spec = mlx5_vzalloc(sizeof(*spec));
1913         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1914         if (!handler || !spec) {
1915                 err = -ENOMEM;
1916                 goto free;
1917         }
1918
1919         INIT_LIST_HEAD(&handler->list);
1920
1921         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1922                 err = parse_flow_attr(spec->match_criteria,
1923                                       spec->match_value, ib_flow);
1924                 if (err < 0)
1925                         goto free;
1926
1927                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1928         }
1929
1930         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1931         action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1932                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1933         handler->rule = mlx5_add_flow_rule(ft, spec,
1934                                            action,
1935                                            MLX5_FS_DEFAULT_FLOW_TAG,
1936                                            dst);
1937
1938         if (IS_ERR(handler->rule)) {
1939                 err = PTR_ERR(handler->rule);
1940                 goto free;
1941         }
1942
1943         ft_prio->refcount++;
1944         handler->prio = ft_prio;
1945
1946         ft_prio->flow_table = ft;
1947 free:
1948         if (err)
1949                 kfree(handler);
1950         kvfree(spec);
1951         return err ? ERR_PTR(err) : handler;
1952 }
1953
1954 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1955                                                           struct mlx5_ib_flow_prio *ft_prio,
1956                                                           struct ib_flow_attr *flow_attr,
1957                                                           struct mlx5_flow_destination *dst)
1958 {
1959         struct mlx5_ib_flow_handler *handler_dst = NULL;
1960         struct mlx5_ib_flow_handler *handler = NULL;
1961
1962         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1963         if (!IS_ERR(handler)) {
1964                 handler_dst = create_flow_rule(dev, ft_prio,
1965                                                flow_attr, dst);
1966                 if (IS_ERR(handler_dst)) {
1967                         mlx5_del_flow_rule(handler->rule);
1968                         ft_prio->refcount--;
1969                         kfree(handler);
1970                         handler = handler_dst;
1971                 } else {
1972                         list_add(&handler_dst->list, &handler->list);
1973                 }
1974         }
1975
1976         return handler;
1977 }
1978 enum {
1979         LEFTOVERS_MC,
1980         LEFTOVERS_UC,
1981 };
1982
1983 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1984                                                           struct mlx5_ib_flow_prio *ft_prio,
1985                                                           struct ib_flow_attr *flow_attr,
1986                                                           struct mlx5_flow_destination *dst)
1987 {
1988         struct mlx5_ib_flow_handler *handler_ucast = NULL;
1989         struct mlx5_ib_flow_handler *handler = NULL;
1990
1991         static struct {
1992                 struct ib_flow_attr     flow_attr;
1993                 struct ib_flow_spec_eth eth_flow;
1994         } leftovers_specs[] = {
1995                 [LEFTOVERS_MC] = {
1996                         .flow_attr = {
1997                                 .num_of_specs = 1,
1998                                 .size = sizeof(leftovers_specs[0])
1999                         },
2000                         .eth_flow = {
2001                                 .type = IB_FLOW_SPEC_ETH,
2002                                 .size = sizeof(struct ib_flow_spec_eth),
2003                                 .mask = {.dst_mac = {0x1} },
2004                                 .val =  {.dst_mac = {0x1} }
2005                         }
2006                 },
2007                 [LEFTOVERS_UC] = {
2008                         .flow_attr = {
2009                                 .num_of_specs = 1,
2010                                 .size = sizeof(leftovers_specs[0])
2011                         },
2012                         .eth_flow = {
2013                                 .type = IB_FLOW_SPEC_ETH,
2014                                 .size = sizeof(struct ib_flow_spec_eth),
2015                                 .mask = {.dst_mac = {0x1} },
2016                                 .val = {.dst_mac = {} }
2017                         }
2018                 }
2019         };
2020
2021         handler = create_flow_rule(dev, ft_prio,
2022                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2023                                    dst);
2024         if (!IS_ERR(handler) &&
2025             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2026                 handler_ucast = create_flow_rule(dev, ft_prio,
2027                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2028                                                  dst);
2029                 if (IS_ERR(handler_ucast)) {
2030                         mlx5_del_flow_rule(handler->rule);
2031                         ft_prio->refcount--;
2032                         kfree(handler);
2033                         handler = handler_ucast;
2034                 } else {
2035                         list_add(&handler_ucast->list, &handler->list);
2036                 }
2037         }
2038
2039         return handler;
2040 }
2041
2042 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2043                                                         struct mlx5_ib_flow_prio *ft_rx,
2044                                                         struct mlx5_ib_flow_prio *ft_tx,
2045                                                         struct mlx5_flow_destination *dst)
2046 {
2047         struct mlx5_ib_flow_handler *handler_rx;
2048         struct mlx5_ib_flow_handler *handler_tx;
2049         int err;
2050         static const struct ib_flow_attr flow_attr  = {
2051                 .num_of_specs = 0,
2052                 .size = sizeof(flow_attr)
2053         };
2054
2055         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2056         if (IS_ERR(handler_rx)) {
2057                 err = PTR_ERR(handler_rx);
2058                 goto err;
2059         }
2060
2061         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2062         if (IS_ERR(handler_tx)) {
2063                 err = PTR_ERR(handler_tx);
2064                 goto err_tx;
2065         }
2066
2067         list_add(&handler_tx->list, &handler_rx->list);
2068
2069         return handler_rx;
2070
2071 err_tx:
2072         mlx5_del_flow_rule(handler_rx->rule);
2073         ft_rx->refcount--;
2074         kfree(handler_rx);
2075 err:
2076         return ERR_PTR(err);
2077 }
2078
2079 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2080                                            struct ib_flow_attr *flow_attr,
2081                                            int domain)
2082 {
2083         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2084         struct mlx5_ib_qp *mqp = to_mqp(qp);
2085         struct mlx5_ib_flow_handler *handler = NULL;
2086         struct mlx5_flow_destination *dst = NULL;
2087         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2088         struct mlx5_ib_flow_prio *ft_prio;
2089         int err;
2090
2091         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2092                 return ERR_PTR(-ENOSPC);
2093
2094         if (domain != IB_FLOW_DOMAIN_USER ||
2095             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2096             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2097                 return ERR_PTR(-EINVAL);
2098
2099         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2100         if (!dst)
2101                 return ERR_PTR(-ENOMEM);
2102
2103         mutex_lock(&dev->flow_db.lock);
2104
2105         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2106         if (IS_ERR(ft_prio)) {
2107                 err = PTR_ERR(ft_prio);
2108                 goto unlock;
2109         }
2110         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2111                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2112                 if (IS_ERR(ft_prio_tx)) {
2113                         err = PTR_ERR(ft_prio_tx);
2114                         ft_prio_tx = NULL;
2115                         goto destroy_ft;
2116                 }
2117         }
2118
2119         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2120         if (mqp->flags & MLX5_IB_QP_RSS)
2121                 dst->tir_num = mqp->rss_qp.tirn;
2122         else
2123                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2124
2125         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2126                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2127                         handler = create_dont_trap_rule(dev, ft_prio,
2128                                                         flow_attr, dst);
2129                 } else {
2130                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2131                                                    dst);
2132                 }
2133         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2134                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2135                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2136                                                 dst);
2137         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2138                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2139         } else {
2140                 err = -EINVAL;
2141                 goto destroy_ft;
2142         }
2143
2144         if (IS_ERR(handler)) {
2145                 err = PTR_ERR(handler);
2146                 handler = NULL;
2147                 goto destroy_ft;
2148         }
2149
2150         mutex_unlock(&dev->flow_db.lock);
2151         kfree(dst);
2152
2153         return &handler->ibflow;
2154
2155 destroy_ft:
2156         put_flow_table(dev, ft_prio, false);
2157         if (ft_prio_tx)
2158                 put_flow_table(dev, ft_prio_tx, false);
2159 unlock:
2160         mutex_unlock(&dev->flow_db.lock);
2161         kfree(dst);
2162         kfree(handler);
2163         return ERR_PTR(err);
2164 }
2165
2166 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2167 {
2168         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2169         int err;
2170
2171         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2172         if (err)
2173                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2174                              ibqp->qp_num, gid->raw);
2175
2176         return err;
2177 }
2178
2179 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2180 {
2181         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2182         int err;
2183
2184         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2185         if (err)
2186                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2187                              ibqp->qp_num, gid->raw);
2188
2189         return err;
2190 }
2191
2192 static int init_node_data(struct mlx5_ib_dev *dev)
2193 {
2194         int err;
2195
2196         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2197         if (err)
2198                 return err;
2199
2200         dev->mdev->rev_id = dev->mdev->pdev->revision;
2201
2202         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2203 }
2204
2205 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2206                              char *buf)
2207 {
2208         struct mlx5_ib_dev *dev =
2209                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2210
2211         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2212 }
2213
2214 static ssize_t show_reg_pages(struct device *device,
2215                               struct device_attribute *attr, char *buf)
2216 {
2217         struct mlx5_ib_dev *dev =
2218                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2219
2220         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2221 }
2222
2223 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2224                         char *buf)
2225 {
2226         struct mlx5_ib_dev *dev =
2227                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2228         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2229 }
2230
2231 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2232                         char *buf)
2233 {
2234         struct mlx5_ib_dev *dev =
2235                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2236         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2237 }
2238
2239 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2240                           char *buf)
2241 {
2242         struct mlx5_ib_dev *dev =
2243                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2244         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2245                        dev->mdev->board_id);
2246 }
2247
2248 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2249 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2250 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2251 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2252 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2253
2254 static struct device_attribute *mlx5_class_attributes[] = {
2255         &dev_attr_hw_rev,
2256         &dev_attr_hca_type,
2257         &dev_attr_board_id,
2258         &dev_attr_fw_pages,
2259         &dev_attr_reg_pages,
2260 };
2261
2262 static void pkey_change_handler(struct work_struct *work)
2263 {
2264         struct mlx5_ib_port_resources *ports =
2265                 container_of(work, struct mlx5_ib_port_resources,
2266                              pkey_change_work);
2267
2268         mutex_lock(&ports->devr->mutex);
2269         mlx5_ib_gsi_pkey_change(ports->gsi);
2270         mutex_unlock(&ports->devr->mutex);
2271 }
2272
2273 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2274 {
2275         struct mlx5_ib_qp *mqp;
2276         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2277         struct mlx5_core_cq *mcq;
2278         struct list_head cq_armed_list;
2279         unsigned long flags_qp;
2280         unsigned long flags_cq;
2281         unsigned long flags;
2282
2283         INIT_LIST_HEAD(&cq_armed_list);
2284
2285         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2286         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2287         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2288                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2289                 if (mqp->sq.tail != mqp->sq.head) {
2290                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2291                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2292                         if (send_mcq->mcq.comp &&
2293                             mqp->ibqp.send_cq->comp_handler) {
2294                                 if (!send_mcq->mcq.reset_notify_added) {
2295                                         send_mcq->mcq.reset_notify_added = 1;
2296                                         list_add_tail(&send_mcq->mcq.reset_notify,
2297                                                       &cq_armed_list);
2298                                 }
2299                         }
2300                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2301                 }
2302                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2303                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2304                 /* no handling is needed for SRQ */
2305                 if (!mqp->ibqp.srq) {
2306                         if (mqp->rq.tail != mqp->rq.head) {
2307                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2308                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2309                                 if (recv_mcq->mcq.comp &&
2310                                     mqp->ibqp.recv_cq->comp_handler) {
2311                                         if (!recv_mcq->mcq.reset_notify_added) {
2312                                                 recv_mcq->mcq.reset_notify_added = 1;
2313                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2314                                                               &cq_armed_list);
2315                                         }
2316                                 }
2317                                 spin_unlock_irqrestore(&recv_mcq->lock,
2318                                                        flags_cq);
2319                         }
2320                 }
2321                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2322         }
2323         /*At that point all inflight post send were put to be executed as of we
2324          * lock/unlock above locks Now need to arm all involved CQs.
2325          */
2326         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2327                 mcq->comp(mcq);
2328         }
2329         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2330 }
2331
2332 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2333                           enum mlx5_dev_event event, unsigned long param)
2334 {
2335         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2336         struct ib_event ibev;
2337         bool fatal = false;
2338         u8 port = 0;
2339
2340         switch (event) {
2341         case MLX5_DEV_EVENT_SYS_ERROR:
2342                 ibev.event = IB_EVENT_DEVICE_FATAL;
2343                 mlx5_ib_handle_internal_error(ibdev);
2344                 fatal = true;
2345                 break;
2346
2347         case MLX5_DEV_EVENT_PORT_UP:
2348         case MLX5_DEV_EVENT_PORT_DOWN:
2349         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2350                 port = (u8)param;
2351
2352                 /* In RoCE, port up/down events are handled in
2353                  * mlx5_netdev_event().
2354                  */
2355                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2356                         IB_LINK_LAYER_ETHERNET)
2357                         return;
2358
2359                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2360                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2361                 break;
2362
2363         case MLX5_DEV_EVENT_LID_CHANGE:
2364                 ibev.event = IB_EVENT_LID_CHANGE;
2365                 port = (u8)param;
2366                 break;
2367
2368         case MLX5_DEV_EVENT_PKEY_CHANGE:
2369                 ibev.event = IB_EVENT_PKEY_CHANGE;
2370                 port = (u8)param;
2371
2372                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2373                 break;
2374
2375         case MLX5_DEV_EVENT_GUID_CHANGE:
2376                 ibev.event = IB_EVENT_GID_CHANGE;
2377                 port = (u8)param;
2378                 break;
2379
2380         case MLX5_DEV_EVENT_CLIENT_REREG:
2381                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2382                 port = (u8)param;
2383                 break;
2384         }
2385
2386         ibev.device           = &ibdev->ib_dev;
2387         ibev.element.port_num = port;
2388
2389         if (port < 1 || port > ibdev->num_ports) {
2390                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2391                 return;
2392         }
2393
2394         if (ibdev->ib_active)
2395                 ib_dispatch_event(&ibev);
2396
2397         if (fatal)
2398                 ibdev->ib_active = false;
2399 }
2400
2401 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2402 {
2403         int port;
2404
2405         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2406                 mlx5_query_ext_port_caps(dev, port);
2407 }
2408
2409 static int get_port_caps(struct mlx5_ib_dev *dev)
2410 {
2411         struct ib_device_attr *dprops = NULL;
2412         struct ib_port_attr *pprops = NULL;
2413         int err = -ENOMEM;
2414         int port;
2415         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2416
2417         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2418         if (!pprops)
2419                 goto out;
2420
2421         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2422         if (!dprops)
2423                 goto out;
2424
2425         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2426         if (err) {
2427                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2428                 goto out;
2429         }
2430
2431         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2432                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2433                 if (err) {
2434                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2435                                      port, err);
2436                         break;
2437                 }
2438                 dev->mdev->port_caps[port - 1].pkey_table_len =
2439                                                 dprops->max_pkeys;
2440                 dev->mdev->port_caps[port - 1].gid_table_len =
2441                                                 pprops->gid_tbl_len;
2442                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2443                             dprops->max_pkeys, pprops->gid_tbl_len);
2444         }
2445
2446 out:
2447         kfree(pprops);
2448         kfree(dprops);
2449
2450         return err;
2451 }
2452
2453 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2454 {
2455         int err;
2456
2457         err = mlx5_mr_cache_cleanup(dev);
2458         if (err)
2459                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2460
2461         mlx5_ib_destroy_qp(dev->umrc.qp);
2462         ib_free_cq(dev->umrc.cq);
2463         ib_dealloc_pd(dev->umrc.pd);
2464 }
2465
2466 enum {
2467         MAX_UMR_WR = 128,
2468 };
2469
2470 static int create_umr_res(struct mlx5_ib_dev *dev)
2471 {
2472         struct ib_qp_init_attr *init_attr = NULL;
2473         struct ib_qp_attr *attr = NULL;
2474         struct ib_pd *pd;
2475         struct ib_cq *cq;
2476         struct ib_qp *qp;
2477         int ret;
2478
2479         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2480         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2481         if (!attr || !init_attr) {
2482                 ret = -ENOMEM;
2483                 goto error_0;
2484         }
2485
2486         pd = ib_alloc_pd(&dev->ib_dev, 0);
2487         if (IS_ERR(pd)) {
2488                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2489                 ret = PTR_ERR(pd);
2490                 goto error_0;
2491         }
2492
2493         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2494         if (IS_ERR(cq)) {
2495                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2496                 ret = PTR_ERR(cq);
2497                 goto error_2;
2498         }
2499
2500         init_attr->send_cq = cq;
2501         init_attr->recv_cq = cq;
2502         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2503         init_attr->cap.max_send_wr = MAX_UMR_WR;
2504         init_attr->cap.max_send_sge = 1;
2505         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2506         init_attr->port_num = 1;
2507         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2508         if (IS_ERR(qp)) {
2509                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2510                 ret = PTR_ERR(qp);
2511                 goto error_3;
2512         }
2513         qp->device     = &dev->ib_dev;
2514         qp->real_qp    = qp;
2515         qp->uobject    = NULL;
2516         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2517         qp->send_cq    = init_attr->send_cq;
2518         qp->recv_cq    = init_attr->recv_cq;
2519
2520         attr->qp_state = IB_QPS_INIT;
2521         attr->port_num = 1;
2522         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2523                                 IB_QP_PORT, NULL);
2524         if (ret) {
2525                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2526                 goto error_4;
2527         }
2528
2529         memset(attr, 0, sizeof(*attr));
2530         attr->qp_state = IB_QPS_RTR;
2531         attr->path_mtu = IB_MTU_256;
2532
2533         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2534         if (ret) {
2535                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2536                 goto error_4;
2537         }
2538
2539         memset(attr, 0, sizeof(*attr));
2540         attr->qp_state = IB_QPS_RTS;
2541         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2542         if (ret) {
2543                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2544                 goto error_4;
2545         }
2546
2547         dev->umrc.qp = qp;
2548         dev->umrc.cq = cq;
2549         dev->umrc.pd = pd;
2550
2551         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2552         ret = mlx5_mr_cache_init(dev);
2553         if (ret) {
2554                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2555                 goto error_4;
2556         }
2557
2558         kfree(attr);
2559         kfree(init_attr);
2560
2561         return 0;
2562
2563 error_4:
2564         mlx5_ib_destroy_qp(qp);
2565
2566 error_3:
2567         ib_free_cq(cq);
2568
2569 error_2:
2570         ib_dealloc_pd(pd);
2571
2572 error_0:
2573         kfree(attr);
2574         kfree(init_attr);
2575         return ret;
2576 }
2577
2578 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2579 {
2580         switch (umr_fence_cap) {
2581         case MLX5_CAP_UMR_FENCE_NONE:
2582                 return MLX5_FENCE_MODE_NONE;
2583         case MLX5_CAP_UMR_FENCE_SMALL:
2584                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2585         default:
2586                 return MLX5_FENCE_MODE_STRONG_ORDERING;
2587         }
2588 }
2589
2590 static int create_dev_resources(struct mlx5_ib_resources *devr)
2591 {
2592         struct ib_srq_init_attr attr;
2593         struct mlx5_ib_dev *dev;
2594         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2595         int port;
2596         int ret = 0;
2597
2598         dev = container_of(devr, struct mlx5_ib_dev, devr);
2599
2600         mutex_init(&devr->mutex);
2601
2602         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2603         if (IS_ERR(devr->p0)) {
2604                 ret = PTR_ERR(devr->p0);
2605                 goto error0;
2606         }
2607         devr->p0->device  = &dev->ib_dev;
2608         devr->p0->uobject = NULL;
2609         atomic_set(&devr->p0->usecnt, 0);
2610
2611         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2612         if (IS_ERR(devr->c0)) {
2613                 ret = PTR_ERR(devr->c0);
2614                 goto error1;
2615         }
2616         devr->c0->device        = &dev->ib_dev;
2617         devr->c0->uobject       = NULL;
2618         devr->c0->comp_handler  = NULL;
2619         devr->c0->event_handler = NULL;
2620         devr->c0->cq_context    = NULL;
2621         atomic_set(&devr->c0->usecnt, 0);
2622
2623         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2624         if (IS_ERR(devr->x0)) {
2625                 ret = PTR_ERR(devr->x0);
2626                 goto error2;
2627         }
2628         devr->x0->device = &dev->ib_dev;
2629         devr->x0->inode = NULL;
2630         atomic_set(&devr->x0->usecnt, 0);
2631         mutex_init(&devr->x0->tgt_qp_mutex);
2632         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2633
2634         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2635         if (IS_ERR(devr->x1)) {
2636                 ret = PTR_ERR(devr->x1);
2637                 goto error3;
2638         }
2639         devr->x1->device = &dev->ib_dev;
2640         devr->x1->inode = NULL;
2641         atomic_set(&devr->x1->usecnt, 0);
2642         mutex_init(&devr->x1->tgt_qp_mutex);
2643         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2644
2645         memset(&attr, 0, sizeof(attr));
2646         attr.attr.max_sge = 1;
2647         attr.attr.max_wr = 1;
2648         attr.srq_type = IB_SRQT_XRC;
2649         attr.ext.xrc.cq = devr->c0;
2650         attr.ext.xrc.xrcd = devr->x0;
2651
2652         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2653         if (IS_ERR(devr->s0)) {
2654                 ret = PTR_ERR(devr->s0);
2655                 goto error4;
2656         }
2657         devr->s0->device        = &dev->ib_dev;
2658         devr->s0->pd            = devr->p0;
2659         devr->s0->uobject       = NULL;
2660         devr->s0->event_handler = NULL;
2661         devr->s0->srq_context   = NULL;
2662         devr->s0->srq_type      = IB_SRQT_XRC;
2663         devr->s0->ext.xrc.xrcd  = devr->x0;
2664         devr->s0->ext.xrc.cq    = devr->c0;
2665         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2666         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2667         atomic_inc(&devr->p0->usecnt);
2668         atomic_set(&devr->s0->usecnt, 0);
2669
2670         memset(&attr, 0, sizeof(attr));
2671         attr.attr.max_sge = 1;
2672         attr.attr.max_wr = 1;
2673         attr.srq_type = IB_SRQT_BASIC;
2674         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2675         if (IS_ERR(devr->s1)) {
2676                 ret = PTR_ERR(devr->s1);
2677                 goto error5;
2678         }
2679         devr->s1->device        = &dev->ib_dev;
2680         devr->s1->pd            = devr->p0;
2681         devr->s1->uobject       = NULL;
2682         devr->s1->event_handler = NULL;
2683         devr->s1->srq_context   = NULL;
2684         devr->s1->srq_type      = IB_SRQT_BASIC;
2685         devr->s1->ext.xrc.cq    = devr->c0;
2686         atomic_inc(&devr->p0->usecnt);
2687         atomic_set(&devr->s0->usecnt, 0);
2688
2689         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2690                 INIT_WORK(&devr->ports[port].pkey_change_work,
2691                           pkey_change_handler);
2692                 devr->ports[port].devr = devr;
2693         }
2694
2695         return 0;
2696
2697 error5:
2698         mlx5_ib_destroy_srq(devr->s0);
2699 error4:
2700         mlx5_ib_dealloc_xrcd(devr->x1);
2701 error3:
2702         mlx5_ib_dealloc_xrcd(devr->x0);
2703 error2:
2704         mlx5_ib_destroy_cq(devr->c0);
2705 error1:
2706         mlx5_ib_dealloc_pd(devr->p0);
2707 error0:
2708         return ret;
2709 }
2710
2711 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2712 {
2713         struct mlx5_ib_dev *dev =
2714                 container_of(devr, struct mlx5_ib_dev, devr);
2715         int port;
2716
2717         mlx5_ib_destroy_srq(devr->s1);
2718         mlx5_ib_destroy_srq(devr->s0);
2719         mlx5_ib_dealloc_xrcd(devr->x0);
2720         mlx5_ib_dealloc_xrcd(devr->x1);
2721         mlx5_ib_destroy_cq(devr->c0);
2722         mlx5_ib_dealloc_pd(devr->p0);
2723
2724         /* Make sure no change P_Key work items are still executing */
2725         for (port = 0; port < dev->num_ports; ++port)
2726                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2727 }
2728
2729 static u32 get_core_cap_flags(struct ib_device *ibdev)
2730 {
2731         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2732         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2733         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2734         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2735         u32 ret = 0;
2736
2737         if (ll == IB_LINK_LAYER_INFINIBAND)
2738                 return RDMA_CORE_PORT_IBA_IB;
2739
2740         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2741                 return 0;
2742
2743         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2744                 return 0;
2745
2746         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2747                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2748
2749         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2750                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2751
2752         return ret;
2753 }
2754
2755 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2756                                struct ib_port_immutable *immutable)
2757 {
2758         struct ib_port_attr attr;
2759         int err;
2760
2761         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2762         if (err)
2763                 return err;
2764
2765         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2766         immutable->gid_tbl_len = attr.gid_tbl_len;
2767         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2768         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2769
2770         return 0;
2771 }
2772
2773 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2774                            size_t str_len)
2775 {
2776         struct mlx5_ib_dev *dev =
2777                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2778         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2779                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2780 }
2781
2782 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2783 {
2784         struct mlx5_core_dev *mdev = dev->mdev;
2785         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2786                                                                  MLX5_FLOW_NAMESPACE_LAG);
2787         struct mlx5_flow_table *ft;
2788         int err;
2789
2790         if (!ns || !mlx5_lag_is_active(mdev))
2791                 return 0;
2792
2793         err = mlx5_cmd_create_vport_lag(mdev);
2794         if (err)
2795                 return err;
2796
2797         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2798         if (IS_ERR(ft)) {
2799                 err = PTR_ERR(ft);
2800                 goto err_destroy_vport_lag;
2801         }
2802
2803         dev->flow_db.lag_demux_ft = ft;
2804         return 0;
2805
2806 err_destroy_vport_lag:
2807         mlx5_cmd_destroy_vport_lag(mdev);
2808         return err;
2809 }
2810
2811 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2812 {
2813         struct mlx5_core_dev *mdev = dev->mdev;
2814
2815         if (dev->flow_db.lag_demux_ft) {
2816                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2817                 dev->flow_db.lag_demux_ft = NULL;
2818
2819                 mlx5_cmd_destroy_vport_lag(mdev);
2820         }
2821 }
2822
2823 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2824 {
2825         if (dev->roce.nb.notifier_call) {
2826                 unregister_netdevice_notifier(&dev->roce.nb);
2827                 dev->roce.nb.notifier_call = NULL;
2828         }
2829 }
2830
2831 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2832 {
2833         int err;
2834
2835         dev->roce.nb.notifier_call = mlx5_netdev_event;
2836         err = register_netdevice_notifier(&dev->roce.nb);
2837         if (err) {
2838                 dev->roce.nb.notifier_call = NULL;
2839                 return err;
2840         }
2841
2842         err = mlx5_nic_vport_enable_roce(dev->mdev);
2843         if (err)
2844                 goto err_unregister_netdevice_notifier;
2845
2846         err = mlx5_roce_lag_init(dev);
2847         if (err)
2848                 goto err_disable_roce;
2849
2850         return 0;
2851
2852 err_disable_roce:
2853         mlx5_nic_vport_disable_roce(dev->mdev);
2854
2855 err_unregister_netdevice_notifier:
2856         mlx5_remove_roce_notifier(dev);
2857         return err;
2858 }
2859
2860 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2861 {
2862         mlx5_roce_lag_cleanup(dev);
2863         mlx5_nic_vport_disable_roce(dev->mdev);
2864 }
2865
2866 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2867 {
2868         unsigned int i;
2869
2870         for (i = 0; i < dev->num_ports; i++)
2871                 mlx5_core_dealloc_q_counter(dev->mdev,
2872                                             dev->port[i].q_cnt_id);
2873 }
2874
2875 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2876 {
2877         int i;
2878         int ret;
2879
2880         for (i = 0; i < dev->num_ports; i++) {
2881                 ret = mlx5_core_alloc_q_counter(dev->mdev,
2882                                                 &dev->port[i].q_cnt_id);
2883                 if (ret) {
2884                         mlx5_ib_warn(dev,
2885                                      "couldn't allocate queue counter for port %d, err %d\n",
2886                                      i + 1, ret);
2887                         goto dealloc_counters;
2888                 }
2889         }
2890
2891         return 0;
2892
2893 dealloc_counters:
2894         while (--i >= 0)
2895                 mlx5_core_dealloc_q_counter(dev->mdev,
2896                                             dev->port[i].q_cnt_id);
2897
2898         return ret;
2899 }
2900
2901 static const char * const names[] = {
2902         "rx_write_requests",
2903         "rx_read_requests",
2904         "rx_atomic_requests",
2905         "out_of_buffer",
2906         "out_of_sequence",
2907         "duplicate_request",
2908         "rnr_nak_retry_err",
2909         "packet_seq_err",
2910         "implied_nak_seq_err",
2911         "local_ack_timeout_err",
2912 };
2913
2914 static const size_t stats_offsets[] = {
2915         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2916         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2917         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2918         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2919         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2920         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2921         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2922         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2923         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2924         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2925 };
2926
2927 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2928                                                     u8 port_num)
2929 {
2930         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2931
2932         /* We support only per port stats */
2933         if (port_num == 0)
2934                 return NULL;
2935
2936         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2937                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
2938 }
2939
2940 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2941                                 struct rdma_hw_stats *stats,
2942                                 u8 port, int index)
2943 {
2944         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2945         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2946         void *out;
2947         __be32 val;
2948         int ret;
2949         int i;
2950
2951         if (!port || !stats)
2952                 return -ENOSYS;
2953
2954         out = mlx5_vzalloc(outlen);
2955         if (!out)
2956                 return -ENOMEM;
2957
2958         ret = mlx5_core_query_q_counter(dev->mdev,
2959                                         dev->port[port - 1].q_cnt_id, 0,
2960                                         out, outlen);
2961         if (ret)
2962                 goto free;
2963
2964         for (i = 0; i < ARRAY_SIZE(names); i++) {
2965                 val = *(__be32 *)(out + stats_offsets[i]);
2966                 stats->value[i] = (u64)be32_to_cpu(val);
2967         }
2968 free:
2969         kvfree(out);
2970         return ARRAY_SIZE(names);
2971 }
2972
2973 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2974 {
2975         struct mlx5_ib_dev *dev;
2976         enum rdma_link_layer ll;
2977         int port_type_cap;
2978         const char *name;
2979         int err;
2980         int i;
2981
2982         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2983         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2984
2985         if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2986                 return NULL;
2987
2988         printk_once(KERN_INFO "%s", mlx5_version);
2989
2990         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2991         if (!dev)
2992                 return NULL;
2993
2994         dev->mdev = mdev;
2995
2996         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2997                             GFP_KERNEL);
2998         if (!dev->port)
2999                 goto err_dealloc;
3000
3001         rwlock_init(&dev->roce.netdev_lock);
3002         err = get_port_caps(dev);
3003         if (err)
3004                 goto err_free_port;
3005
3006         if (mlx5_use_mad_ifc(dev))
3007                 get_ext_port_caps(dev);
3008
3009         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
3010
3011         if (!mlx5_lag_is_active(mdev))
3012                 name = "mlx5_%d";
3013         else
3014                 name = "mlx5_bond_%d";
3015
3016         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3017         dev->ib_dev.owner               = THIS_MODULE;
3018         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3019         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3020         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
3021         dev->ib_dev.phys_port_cnt     = dev->num_ports;
3022         dev->ib_dev.num_comp_vectors    =
3023                 dev->mdev->priv.eq_table.num_comp_vectors;
3024         dev->ib_dev.dma_device  = &mdev->pdev->dev;
3025
3026         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
3027         dev->ib_dev.uverbs_cmd_mask     =
3028                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
3029                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
3030                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
3031                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
3032                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
3033                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
3034                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
3035                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
3036                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3037                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
3038                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
3039                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
3040                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
3041                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
3042                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
3043                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
3044                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
3045                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
3046                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
3047                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
3048                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
3049                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
3050                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
3051                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3052         dev->ib_dev.uverbs_ex_cmd_mask =
3053                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
3054                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3055                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3056
3057         dev->ib_dev.query_device        = mlx5_ib_query_device;
3058         dev->ib_dev.query_port          = mlx5_ib_query_port;
3059         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3060         if (ll == IB_LINK_LAYER_ETHERNET)
3061                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3062         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3063         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3064         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3065         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3066         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3067         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3068         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3069         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3070         dev->ib_dev.mmap                = mlx5_ib_mmap;
3071         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3072         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3073         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3074         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3075         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3076         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3077         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3078         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3079         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3080         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3081         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3082         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3083         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3084         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3085         dev->ib_dev.post_send           = mlx5_ib_post_send;
3086         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3087         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3088         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3089         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3090         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3091         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3092         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3093         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3094         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3095         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3096         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3097         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3098         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3099         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3100         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3101         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3102         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3103         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3104         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3105         if (mlx5_core_is_pf(mdev)) {
3106                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3107                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3108                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3109                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3110         }
3111
3112         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3113
3114         mlx5_ib_internal_fill_odp_caps(dev);
3115
3116         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3117
3118         if (MLX5_CAP_GEN(mdev, imaicl)) {
3119                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3120                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3121                 dev->ib_dev.uverbs_cmd_mask |=
3122                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3123                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3124         }
3125
3126         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3127             MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3128                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3129                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3130         }
3131
3132         if (MLX5_CAP_GEN(mdev, xrc)) {
3133                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3134                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3135                 dev->ib_dev.uverbs_cmd_mask |=
3136                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3137                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3138         }
3139
3140         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3141             IB_LINK_LAYER_ETHERNET) {
3142                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3143                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3144                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3145                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3146                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3147                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3148                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3149                 dev->ib_dev.uverbs_ex_cmd_mask |=
3150                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3151                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3152                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3153                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3154                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3155                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3156                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3157         }
3158         err = init_node_data(dev);
3159         if (err)
3160                 goto err_free_port;
3161
3162         mutex_init(&dev->flow_db.lock);
3163         mutex_init(&dev->cap_mask_mutex);
3164         INIT_LIST_HEAD(&dev->qp_list);
3165         spin_lock_init(&dev->reset_flow_resource_lock);
3166
3167         if (ll == IB_LINK_LAYER_ETHERNET) {
3168                 err = mlx5_enable_roce(dev);
3169                 if (err)
3170                         goto err_free_port;
3171         }
3172
3173         err = create_dev_resources(&dev->devr);
3174         if (err)
3175                 goto err_disable_roce;
3176
3177         err = mlx5_ib_odp_init_one(dev);
3178         if (err)
3179                 goto err_rsrc;
3180
3181         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3182                 err = mlx5_ib_alloc_q_counters(dev);
3183                 if (err)
3184                         goto err_odp;
3185         }
3186
3187         err = ib_register_device(&dev->ib_dev, NULL);
3188         if (err)
3189                 goto err_q_cnt;
3190
3191         err = create_umr_res(dev);
3192         if (err)
3193                 goto err_dev;
3194
3195         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3196                 err = device_create_file(&dev->ib_dev.dev,
3197                                          mlx5_class_attributes[i]);
3198                 if (err)
3199                         goto err_umrc;
3200         }
3201
3202         dev->ib_active = true;
3203
3204         return dev;
3205
3206 err_umrc:
3207         destroy_umrc_res(dev);
3208
3209 err_dev:
3210         ib_unregister_device(&dev->ib_dev);
3211
3212 err_q_cnt:
3213         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3214                 mlx5_ib_dealloc_q_counters(dev);
3215
3216 err_odp:
3217         mlx5_ib_odp_remove_one(dev);
3218
3219 err_rsrc:
3220         destroy_dev_resources(&dev->devr);
3221
3222 err_disable_roce:
3223         if (ll == IB_LINK_LAYER_ETHERNET) {
3224                 mlx5_disable_roce(dev);
3225                 mlx5_remove_roce_notifier(dev);
3226         }
3227
3228 err_free_port:
3229         kfree(dev->port);
3230
3231 err_dealloc:
3232         ib_dealloc_device((struct ib_device *)dev);
3233
3234         return NULL;
3235 }
3236
3237 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3238 {
3239         struct mlx5_ib_dev *dev = context;
3240         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3241
3242         mlx5_remove_roce_notifier(dev);
3243         ib_unregister_device(&dev->ib_dev);
3244         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3245                 mlx5_ib_dealloc_q_counters(dev);
3246         destroy_umrc_res(dev);
3247         mlx5_ib_odp_remove_one(dev);
3248         destroy_dev_resources(&dev->devr);
3249         if (ll == IB_LINK_LAYER_ETHERNET)
3250                 mlx5_disable_roce(dev);
3251         kfree(dev->port);
3252         ib_dealloc_device(&dev->ib_dev);
3253 }
3254
3255 static struct mlx5_interface mlx5_ib_interface = {
3256         .add            = mlx5_ib_add,
3257         .remove         = mlx5_ib_remove,
3258         .event          = mlx5_ib_event,
3259         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3260 };
3261
3262 static int __init mlx5_ib_init(void)
3263 {
3264         int err;
3265
3266         if (deprecated_prof_sel != 2)
3267                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3268
3269         err = mlx5_ib_odp_init();
3270         if (err)
3271                 return err;
3272
3273         err = mlx5_register_interface(&mlx5_ib_interface);
3274         if (err)
3275                 goto clean_odp;
3276
3277         return err;
3278
3279 clean_odp:
3280         mlx5_ib_odp_cleanup();
3281         return err;
3282 }
3283
3284 static void __exit mlx5_ib_cleanup(void)
3285 {
3286         mlx5_unregister_interface(&mlx5_ib_interface);
3287         mlx5_ib_odp_cleanup();
3288 }
3289
3290 module_init(mlx5_ib_init);
3291 module_exit(mlx5_ib_cleanup);