2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/netdevice.h>
39 #include <linux/inetdevice.h>
40 #include <linux/rtnetlink.h>
41 #include <linux/if_vlan.h>
43 #include <net/addrconf.h>
44 #include <net/devlink.h>
46 #include <rdma/ib_smi.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_cache.h>
51 #include <net/bonding.h>
53 #include <linux/mlx4/driver.h>
54 #include <linux/mlx4/cmd.h>
55 #include <linux/mlx4/qp.h>
58 #include <rdma/mlx4-abi.h>
60 #define DRV_NAME MLX4_IB_DRV_NAME
61 #define DRV_VERSION "2.2-1"
62 #define DRV_RELDATE "Feb 2014"
64 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
65 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
66 #define MLX4_IB_CARD_REV_A0 0xA0
68 MODULE_AUTHOR("Roland Dreier");
69 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
70 MODULE_LICENSE("Dual BSD/GPL");
71 MODULE_VERSION(DRV_VERSION);
73 int mlx4_ib_sm_guid_assign = 0;
74 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
75 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
77 static const char mlx4_ib_version[] =
78 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
79 DRV_VERSION " (" DRV_RELDATE ")\n";
81 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
83 static struct workqueue_struct *wq;
85 static void init_query_mad(struct ib_smp *mad)
87 mad->base_version = 1;
88 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
89 mad->class_version = 1;
90 mad->method = IB_MGMT_METHOD_GET;
93 static int check_flow_steering_support(struct mlx4_dev *dev)
95 int eth_num_ports = 0;
98 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
102 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
104 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
106 dmfs &= (!ib_num_ports ||
107 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
109 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
110 if (ib_num_ports && mlx4_is_mfunc(dev)) {
111 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
118 static int num_ib_ports(struct mlx4_dev *dev)
123 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
129 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
131 struct mlx4_ib_dev *ibdev = to_mdev(device);
132 struct net_device *dev;
135 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
138 if (mlx4_is_bonded(ibdev->dev)) {
139 struct net_device *upper = NULL;
141 upper = netdev_master_upper_dev_get_rcu(dev);
143 struct net_device *active;
145 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
158 static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
159 struct mlx4_ib_dev *ibdev,
162 struct mlx4_cmd_mailbox *mailbox;
164 struct mlx4_dev *dev = ibdev->dev;
166 union ib_gid *gid_tbl;
168 mailbox = mlx4_alloc_cmd_mailbox(dev);
172 gid_tbl = mailbox->buf;
174 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
175 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
177 err = mlx4_cmd(dev, mailbox->dma,
178 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
179 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
181 if (mlx4_is_bonded(dev))
182 err += mlx4_cmd(dev, mailbox->dma,
183 MLX4_SET_PORT_GID_TABLE << 8 | 2,
184 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
187 mlx4_free_cmd_mailbox(dev, mailbox);
191 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
192 struct mlx4_ib_dev *ibdev,
195 struct mlx4_cmd_mailbox *mailbox;
197 struct mlx4_dev *dev = ibdev->dev;
208 mailbox = mlx4_alloc_cmd_mailbox(dev);
212 gid_tbl = mailbox->buf;
213 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
214 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
215 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
216 gid_tbl[i].version = 2;
217 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
220 memset(&gid_tbl[i].gid, 0, 12);
224 err = mlx4_cmd(dev, mailbox->dma,
225 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
226 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
228 if (mlx4_is_bonded(dev))
229 err += mlx4_cmd(dev, mailbox->dma,
230 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
231 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
234 mlx4_free_cmd_mailbox(dev, mailbox);
238 static int mlx4_ib_update_gids(struct gid_entry *gids,
239 struct mlx4_ib_dev *ibdev,
242 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
243 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
245 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
248 static int mlx4_ib_add_gid(struct ib_device *device,
251 const union ib_gid *gid,
252 const struct ib_gid_attr *attr,
255 struct mlx4_ib_dev *ibdev = to_mdev(device);
256 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
257 struct mlx4_port_gid_table *port_gid_table;
258 int free = -1, found = -1;
262 struct gid_entry *gids = NULL;
264 if (!rdma_cap_roce_gid_table(device, port_num))
267 if (port_num > MLX4_MAX_PORTS)
273 port_gid_table = &iboe->gids[port_num - 1];
274 spin_lock_bh(&iboe->lock);
275 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
276 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
277 (port_gid_table->gids[i].gid_type == attr->gid_type)) {
281 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
282 free = i; /* HW has space */
289 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
290 if (!port_gid_table->gids[free].ctx) {
293 *context = port_gid_table->gids[free].ctx;
294 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
295 port_gid_table->gids[free].gid_type = attr->gid_type;
296 port_gid_table->gids[free].ctx->real_index = free;
297 port_gid_table->gids[free].ctx->refcount = 1;
302 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
306 if (!ret && hw_update) {
307 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
311 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
312 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
313 gids[i].gid_type = port_gid_table->gids[i].gid_type;
317 spin_unlock_bh(&iboe->lock);
319 if (!ret && hw_update) {
320 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
327 static int mlx4_ib_del_gid(struct ib_device *device,
332 struct gid_cache_context *ctx = *context;
333 struct mlx4_ib_dev *ibdev = to_mdev(device);
334 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
335 struct mlx4_port_gid_table *port_gid_table;
338 struct gid_entry *gids = NULL;
340 if (!rdma_cap_roce_gid_table(device, port_num))
343 if (port_num > MLX4_MAX_PORTS)
346 port_gid_table = &iboe->gids[port_num - 1];
347 spin_lock_bh(&iboe->lock);
350 if (!ctx->refcount) {
351 unsigned int real_index = ctx->real_index;
353 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
354 kfree(port_gid_table->gids[real_index].ctx);
355 port_gid_table->gids[real_index].ctx = NULL;
359 if (!ret && hw_update) {
362 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
366 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
367 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
370 spin_unlock_bh(&iboe->lock);
372 if (!ret && hw_update) {
373 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
379 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
380 u8 port_num, int index)
382 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
383 struct gid_cache_context *ctx = NULL;
385 struct mlx4_port_gid_table *port_gid_table;
386 int real_index = -EINVAL;
390 struct ib_gid_attr attr;
392 if (port_num > MLX4_MAX_PORTS)
395 if (mlx4_is_bonded(ibdev->dev))
398 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
401 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
408 if (!memcmp(&gid, &zgid, sizeof(gid)))
411 spin_lock_irqsave(&iboe->lock, flags);
412 port_gid_table = &iboe->gids[port_num - 1];
414 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
415 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
416 attr.gid_type == port_gid_table->gids[i].gid_type) {
417 ctx = port_gid_table->gids[i].ctx;
421 real_index = ctx->real_index;
422 spin_unlock_irqrestore(&iboe->lock, flags);
426 static int mlx4_ib_query_device(struct ib_device *ibdev,
427 struct ib_device_attr *props,
428 struct ib_udata *uhw)
430 struct mlx4_ib_dev *dev = to_mdev(ibdev);
431 struct ib_smp *in_mad = NULL;
432 struct ib_smp *out_mad = NULL;
435 struct mlx4_uverbs_ex_query_device cmd;
436 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
437 struct mlx4_clock_params clock_params;
440 if (uhw->inlen < sizeof(cmd))
443 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
454 resp.response_length = offsetof(typeof(resp), response_length) +
455 sizeof(resp.response_length);
456 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
457 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
458 if (!in_mad || !out_mad)
461 init_query_mad(in_mad);
462 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
464 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
465 1, NULL, NULL, in_mad, out_mad);
469 memset(props, 0, sizeof *props);
471 have_ib_ports = num_ib_ports(dev->dev);
473 props->fw_ver = dev->dev->caps.fw_ver;
474 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
475 IB_DEVICE_PORT_ACTIVE_EVENT |
476 IB_DEVICE_SYS_IMAGE_GUID |
477 IB_DEVICE_RC_RNR_NAK_GEN |
478 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
479 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
480 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
482 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
484 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
485 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
486 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
487 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
488 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
489 if (dev->dev->caps.max_gso_sz &&
490 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
491 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
492 props->device_cap_flags |= IB_DEVICE_UD_TSO;
493 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
494 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
495 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
496 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
497 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
498 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
499 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
500 props->device_cap_flags |= IB_DEVICE_XRC;
501 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
502 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
503 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
504 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
505 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
507 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
509 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
510 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
512 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
514 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
516 props->vendor_part_id = dev->dev->persist->pdev->device;
517 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
518 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
520 props->max_mr_size = ~0ull;
521 props->page_size_cap = dev->dev->caps.page_size_cap;
522 props->max_qp = dev->dev->quotas.qp;
523 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
524 props->max_sge = min(dev->dev->caps.max_sq_sg,
525 dev->dev->caps.max_rq_sg);
526 props->max_sge_rd = MLX4_MAX_SGE_RD;
527 props->max_cq = dev->dev->quotas.cq;
528 props->max_cqe = dev->dev->caps.max_cqes;
529 props->max_mr = dev->dev->quotas.mpt;
530 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
531 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
532 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
533 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
534 props->max_srq = dev->dev->quotas.srq;
535 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
536 props->max_srq_sge = dev->dev->caps.max_srq_sge;
537 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
538 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
539 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
540 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
541 props->masked_atomic_cap = props->atomic_cap;
542 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
543 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
544 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
545 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
546 props->max_mcast_grp;
547 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
548 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
549 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
551 if (!mlx4_is_slave(dev->dev))
552 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
554 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
555 resp.response_length += sizeof(resp.hca_core_clock_offset);
556 if (!err && !mlx4_is_slave(dev->dev)) {
557 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
558 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
563 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
574 static enum rdma_link_layer
575 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
577 struct mlx4_dev *dev = to_mdev(device)->dev;
579 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
580 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
583 static int ib_link_query_port(struct ib_device *ibdev, u8 port,
584 struct ib_port_attr *props, int netw_view)
586 struct ib_smp *in_mad = NULL;
587 struct ib_smp *out_mad = NULL;
588 int ext_active_speed;
589 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
592 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
593 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
594 if (!in_mad || !out_mad)
597 init_query_mad(in_mad);
598 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
599 in_mad->attr_mod = cpu_to_be32(port);
601 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
602 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
604 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
610 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
611 props->lmc = out_mad->data[34] & 0x7;
612 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
613 props->sm_sl = out_mad->data[36] & 0xf;
614 props->state = out_mad->data[32] & 0xf;
615 props->phys_state = out_mad->data[33] >> 4;
616 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
618 props->gid_tbl_len = out_mad->data[50];
620 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
621 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
622 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
623 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
624 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
625 props->active_width = out_mad->data[31] & 0xf;
626 props->active_speed = out_mad->data[35] >> 4;
627 props->max_mtu = out_mad->data[41] & 0xf;
628 props->active_mtu = out_mad->data[36] >> 4;
629 props->subnet_timeout = out_mad->data[51] & 0x1f;
630 props->max_vl_num = out_mad->data[37] >> 4;
631 props->init_type_reply = out_mad->data[41] >> 4;
633 /* Check if extended speeds (EDR/FDR/...) are supported */
634 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
635 ext_active_speed = out_mad->data[62] >> 4;
637 switch (ext_active_speed) {
639 props->active_speed = IB_SPEED_FDR;
642 props->active_speed = IB_SPEED_EDR;
647 /* If reported active speed is QDR, check if is FDR-10 */
648 if (props->active_speed == IB_SPEED_QDR) {
649 init_query_mad(in_mad);
650 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
651 in_mad->attr_mod = cpu_to_be32(port);
653 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
654 NULL, NULL, in_mad, out_mad);
658 /* Checking LinkSpeedActive for FDR-10 */
659 if (out_mad->data[15] & 0x1)
660 props->active_speed = IB_SPEED_FDR10;
663 /* Avoid wrong speed value returned by FW if the IB link is down. */
664 if (props->state == IB_PORT_DOWN)
665 props->active_speed = IB_SPEED_SDR;
673 static u8 state_to_phys_state(enum ib_port_state state)
675 return state == IB_PORT_ACTIVE ? 5 : 3;
678 static int eth_link_query_port(struct ib_device *ibdev, u8 port,
679 struct ib_port_attr *props, int netw_view)
682 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
683 struct mlx4_ib_iboe *iboe = &mdev->iboe;
684 struct net_device *ndev;
686 struct mlx4_cmd_mailbox *mailbox;
688 int is_bonded = mlx4_is_bonded(mdev->dev);
690 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
692 return PTR_ERR(mailbox);
694 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
695 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
700 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
701 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
702 IB_WIDTH_4X : IB_WIDTH_1X;
703 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
704 IB_SPEED_FDR : IB_SPEED_QDR;
705 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
706 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
707 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
708 props->pkey_tbl_len = 1;
709 props->max_mtu = IB_MTU_4096;
710 props->max_vl_num = 2;
711 props->state = IB_PORT_DOWN;
712 props->phys_state = state_to_phys_state(props->state);
713 props->active_mtu = IB_MTU_256;
714 spin_lock_bh(&iboe->lock);
715 ndev = iboe->netdevs[port - 1];
716 if (ndev && is_bonded) {
717 rcu_read_lock(); /* required to get upper dev */
718 ndev = netdev_master_upper_dev_get_rcu(ndev);
724 tmp = iboe_get_mtu(ndev->mtu);
725 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
727 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
728 IB_PORT_ACTIVE : IB_PORT_DOWN;
729 props->phys_state = state_to_phys_state(props->state);
731 spin_unlock_bh(&iboe->lock);
733 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
737 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
738 struct ib_port_attr *props, int netw_view)
742 memset(props, 0, sizeof *props);
744 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
745 ib_link_query_port(ibdev, port, props, netw_view) :
746 eth_link_query_port(ibdev, port, props, netw_view);
751 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
752 struct ib_port_attr *props)
754 /* returns host view */
755 return __mlx4_ib_query_port(ibdev, port, props, 0);
758 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
759 union ib_gid *gid, int netw_view)
761 struct ib_smp *in_mad = NULL;
762 struct ib_smp *out_mad = NULL;
764 struct mlx4_ib_dev *dev = to_mdev(ibdev);
766 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
768 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
769 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
770 if (!in_mad || !out_mad)
773 init_query_mad(in_mad);
774 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
775 in_mad->attr_mod = cpu_to_be32(port);
777 if (mlx4_is_mfunc(dev->dev) && netw_view)
778 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
780 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
784 memcpy(gid->raw, out_mad->data + 8, 8);
786 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
788 /* For any index > 0, return the null guid */
795 init_query_mad(in_mad);
796 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
797 in_mad->attr_mod = cpu_to_be32(index / 8);
799 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
800 NULL, NULL, in_mad, out_mad);
804 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
808 memset(gid->raw + 8, 0, 8);
814 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
819 if (rdma_protocol_ib(ibdev, port))
820 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
822 if (!rdma_protocol_roce(ibdev, port))
825 if (!rdma_cap_roce_gid_table(ibdev, port))
828 ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
829 if (ret == -EAGAIN) {
830 memcpy(gid, &zgid, sizeof(*gid));
837 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
839 union sl2vl_tbl_to_u64 sl2vl64;
840 struct ib_smp *in_mad = NULL;
841 struct ib_smp *out_mad = NULL;
842 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
846 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
851 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
852 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
853 if (!in_mad || !out_mad)
856 init_query_mad(in_mad);
857 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
858 in_mad->attr_mod = 0;
860 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
861 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
863 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
868 for (jj = 0; jj < 8; jj++)
869 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
870 *sl2vl_tbl = sl2vl64.sl64;
878 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
884 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
885 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
887 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
889 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
893 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
897 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
898 u16 *pkey, int netw_view)
900 struct ib_smp *in_mad = NULL;
901 struct ib_smp *out_mad = NULL;
902 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
905 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
906 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
907 if (!in_mad || !out_mad)
910 init_query_mad(in_mad);
911 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
912 in_mad->attr_mod = cpu_to_be32(index / 32);
914 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
915 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
917 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
922 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
930 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
932 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
935 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
936 struct ib_device_modify *props)
938 struct mlx4_cmd_mailbox *mailbox;
941 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
944 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
947 if (mlx4_is_slave(to_mdev(ibdev)->dev))
950 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
951 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
952 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
955 * If possible, pass node desc to FW, so it can generate
956 * a 144 trap. If cmd fails, just ignore.
958 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
962 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
963 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
964 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
966 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
971 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
974 struct mlx4_cmd_mailbox *mailbox;
977 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
979 return PTR_ERR(mailbox);
981 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
982 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
983 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
985 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
986 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
989 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
990 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
993 mlx4_free_cmd_mailbox(dev->dev, mailbox);
997 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
998 struct ib_port_modify *props)
1000 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1001 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
1002 struct ib_port_attr attr;
1006 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1007 * of whether port link layer is ETH or IB. For ETH ports, qkey
1008 * violations and port capabilities are not meaningful.
1013 mutex_lock(&mdev->cap_mask_mutex);
1015 err = mlx4_ib_query_port(ibdev, port, &attr);
1019 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1020 ~props->clr_port_cap_mask;
1022 err = mlx4_ib_SET_PORT(mdev, port,
1023 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1027 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1031 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
1032 struct ib_udata *udata)
1034 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1035 struct mlx4_ib_ucontext *context;
1036 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
1037 struct mlx4_ib_alloc_ucontext_resp resp;
1040 if (!dev->ib_active)
1041 return ERR_PTR(-EAGAIN);
1043 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1044 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1045 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1046 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1048 resp.dev_caps = dev->dev->caps.userspace_caps;
1049 resp.qp_tab_size = dev->dev->caps.num_qps;
1050 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1051 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1052 resp.cqe_size = dev->dev->caps.cqe_size;
1055 context = kzalloc(sizeof(*context), GFP_KERNEL);
1057 return ERR_PTR(-ENOMEM);
1059 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1062 return ERR_PTR(err);
1065 INIT_LIST_HEAD(&context->db_page_list);
1066 mutex_init(&context->db_page_mutex);
1068 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1069 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1071 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1074 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1076 return ERR_PTR(-EFAULT);
1079 return &context->ibucontext;
1082 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1084 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1086 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1092 static void mlx4_ib_vma_open(struct vm_area_struct *area)
1094 /* vma_open is called when a new VMA is created on top of our VMA.
1095 * This is done through either mremap flow or split_vma (usually due
1096 * to mlock, madvise, munmap, etc.). We do not support a clone of the
1097 * vma, as this VMA is strongly hardware related. Therefore we set the
1098 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1099 * calling us again and trying to do incorrect actions. We assume that
1100 * the original vma size is exactly a single page that there will be no
1101 * "splitting" operations on.
1103 area->vm_ops = NULL;
1106 static void mlx4_ib_vma_close(struct vm_area_struct *area)
1108 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
1110 /* It's guaranteed that all VMAs opened on a FD are closed before the
1111 * file itself is closed, therefore no sync is needed with the regular
1112 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
1113 * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
1114 * The close operation is usually called under mm->mmap_sem except when
1115 * process is exiting. The exiting case is handled explicitly as part
1116 * of mlx4_ib_disassociate_ucontext.
1118 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
1119 area->vm_private_data;
1121 /* set the vma context pointer to null in the mlx4_ib driver's private
1122 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
1124 mlx4_ib_vma_priv_data->vma = NULL;
1127 static const struct vm_operations_struct mlx4_ib_vm_ops = {
1128 .open = mlx4_ib_vma_open,
1129 .close = mlx4_ib_vma_close
1132 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1136 struct vm_area_struct *vma;
1137 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1138 struct task_struct *owning_process = NULL;
1139 struct mm_struct *owning_mm = NULL;
1141 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1142 if (!owning_process)
1145 owning_mm = get_task_mm(owning_process);
1147 pr_info("no mm, disassociate ucontext is pending task termination\n");
1149 /* make sure that task is dead before returning, it may
1150 * prevent a rare case of module down in parallel to a
1151 * call to mlx4_ib_vma_close.
1153 put_task_struct(owning_process);
1155 owning_process = get_pid_task(ibcontext->tgid,
1157 if (!owning_process ||
1158 owning_process->state == TASK_DEAD) {
1159 pr_info("disassociate ucontext done, task was terminated\n");
1160 /* in case task was dead need to release the task struct */
1162 put_task_struct(owning_process);
1168 /* need to protect from a race on closing the vma as part of
1169 * mlx4_ib_vma_close().
1171 down_read(&owning_mm->mmap_sem);
1172 for (i = 0; i < HW_BAR_COUNT; i++) {
1173 vma = context->hw_bar_info[i].vma;
1177 ret = zap_vma_ptes(context->hw_bar_info[i].vma,
1178 context->hw_bar_info[i].vma->vm_start,
1181 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
1185 /* context going to be destroyed, should not access ops any more */
1186 context->hw_bar_info[i].vma->vm_ops = NULL;
1189 up_read(&owning_mm->mmap_sem);
1191 put_task_struct(owning_process);
1194 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
1195 struct mlx4_ib_vma_private_data *vma_private_data)
1197 vma_private_data->vma = vma;
1198 vma->vm_private_data = vma_private_data;
1199 vma->vm_ops = &mlx4_ib_vm_ops;
1202 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1204 struct mlx4_ib_dev *dev = to_mdev(context->device);
1205 struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
1207 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1210 if (vma->vm_pgoff == 0) {
1211 /* We prevent double mmaping on same context */
1212 if (mucontext->hw_bar_info[HW_BAR_DB].vma)
1215 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1217 if (io_remap_pfn_range(vma, vma->vm_start,
1218 to_mucontext(context)->uar.pfn,
1219 PAGE_SIZE, vma->vm_page_prot))
1222 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
1224 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
1225 /* We prevent double mmaping on same context */
1226 if (mucontext->hw_bar_info[HW_BAR_BF].vma)
1229 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1231 if (io_remap_pfn_range(vma, vma->vm_start,
1232 to_mucontext(context)->uar.pfn +
1233 dev->dev->caps.num_uars,
1234 PAGE_SIZE, vma->vm_page_prot))
1237 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
1239 } else if (vma->vm_pgoff == 3) {
1240 struct mlx4_clock_params params;
1243 /* We prevent double mmaping on same context */
1244 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
1247 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms);
1252 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1253 if (io_remap_pfn_range(vma, vma->vm_start,
1254 (pci_resource_start(dev->dev->persist->pdev,
1258 PAGE_SIZE, vma->vm_page_prot))
1261 mlx4_ib_set_vma_data(vma,
1262 &mucontext->hw_bar_info[HW_BAR_CLOCK]);
1270 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
1271 struct ib_ucontext *context,
1272 struct ib_udata *udata)
1274 struct mlx4_ib_pd *pd;
1277 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1279 return ERR_PTR(-ENOMEM);
1281 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1284 return ERR_PTR(err);
1288 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
1289 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1291 return ERR_PTR(-EFAULT);
1297 static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
1299 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1305 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1306 struct ib_ucontext *context,
1307 struct ib_udata *udata)
1309 struct mlx4_ib_xrcd *xrcd;
1310 struct ib_cq_init_attr cq_attr = {};
1313 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1314 return ERR_PTR(-ENOSYS);
1316 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1318 return ERR_PTR(-ENOMEM);
1320 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1324 xrcd->pd = ib_alloc_pd(ibdev, 0);
1325 if (IS_ERR(xrcd->pd)) {
1326 err = PTR_ERR(xrcd->pd);
1331 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
1332 if (IS_ERR(xrcd->cq)) {
1333 err = PTR_ERR(xrcd->cq);
1337 return &xrcd->ibxrcd;
1340 ib_dealloc_pd(xrcd->pd);
1342 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1345 return ERR_PTR(err);
1348 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
1350 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1351 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1352 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1358 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1360 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1361 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1362 struct mlx4_ib_gid_entry *ge;
1364 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1369 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1370 ge->port = mqp->port;
1374 mutex_lock(&mqp->mutex);
1375 list_add_tail(&ge->list, &mqp->gid_list);
1376 mutex_unlock(&mqp->mutex);
1381 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1382 struct mlx4_ib_counters *ctr_table)
1384 struct counter_index *counter, *tmp_count;
1386 mutex_lock(&ctr_table->mutex);
1387 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1389 if (counter->allocated)
1390 mlx4_counter_free(ibdev->dev, counter->index);
1391 list_del(&counter->list);
1394 mutex_unlock(&ctr_table->mutex);
1397 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1400 struct net_device *ndev;
1406 spin_lock_bh(&mdev->iboe.lock);
1407 ndev = mdev->iboe.netdevs[mqp->port - 1];
1410 spin_unlock_bh(&mdev->iboe.lock);
1420 struct mlx4_ib_steering {
1421 struct list_head list;
1422 struct mlx4_flow_reg_id reg_id;
1426 #define LAST_ETH_FIELD vlan_tag
1427 #define LAST_IB_FIELD sl
1428 #define LAST_IPV4_FIELD dst_ip
1429 #define LAST_TCP_UDP_FIELD src_port
1431 /* Field is the last supported field */
1432 #define FIELDS_NOT_SUPPORTED(filter, field)\
1433 memchr_inv((void *)&filter.field +\
1434 sizeof(filter.field), 0,\
1436 offsetof(typeof(filter), field) -\
1437 sizeof(filter.field))
1439 static int parse_flow_attr(struct mlx4_dev *dev,
1441 union ib_flow_spec *ib_spec,
1442 struct _rule_hw *mlx4_spec)
1444 enum mlx4_net_trans_rule_id type;
1446 switch (ib_spec->type) {
1447 case IB_FLOW_SPEC_ETH:
1448 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1451 type = MLX4_NET_TRANS_RULE_ID_ETH;
1452 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1454 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1456 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1457 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1459 case IB_FLOW_SPEC_IB:
1460 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1463 type = MLX4_NET_TRANS_RULE_ID_IB;
1464 mlx4_spec->ib.l3_qpn =
1465 cpu_to_be32(qp_num);
1466 mlx4_spec->ib.qpn_mask =
1467 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1471 case IB_FLOW_SPEC_IPV4:
1472 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1475 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1476 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1477 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1478 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1479 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1482 case IB_FLOW_SPEC_TCP:
1483 case IB_FLOW_SPEC_UDP:
1484 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1487 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1488 MLX4_NET_TRANS_RULE_ID_TCP :
1489 MLX4_NET_TRANS_RULE_ID_UDP;
1490 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1491 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1492 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1493 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1499 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1500 mlx4_hw_rule_sz(dev, type) < 0)
1502 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1503 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1504 return mlx4_hw_rule_sz(dev, type);
1507 struct default_rules {
1508 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1509 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1510 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1513 static const struct default_rules default_table[] = {
1515 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1516 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1517 .rules_create_list = {IB_FLOW_SPEC_IB},
1518 .link_layer = IB_LINK_LAYER_INFINIBAND
1522 static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1523 struct ib_flow_attr *flow_attr)
1527 const struct default_rules *pdefault_rules = default_table;
1528 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1530 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
1531 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1532 memset(&field_types, 0, sizeof(field_types));
1534 if (link_layer != pdefault_rules->link_layer)
1537 ib_flow = flow_attr + 1;
1538 /* we assume the specs are sorted */
1539 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1540 j < flow_attr->num_of_specs; k++) {
1541 union ib_flow_spec *current_flow =
1542 (union ib_flow_spec *)ib_flow;
1544 /* same layer but different type */
1545 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1546 (pdefault_rules->mandatory_fields[k] &
1547 IB_FLOW_SPEC_LAYER_MASK)) &&
1548 (current_flow->type !=
1549 pdefault_rules->mandatory_fields[k]))
1552 /* same layer, try match next one */
1553 if (current_flow->type ==
1554 pdefault_rules->mandatory_fields[k]) {
1557 ((union ib_flow_spec *)ib_flow)->size;
1561 ib_flow = flow_attr + 1;
1562 for (j = 0; j < flow_attr->num_of_specs;
1563 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1564 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1565 /* same layer and same type */
1566 if (((union ib_flow_spec *)ib_flow)->type ==
1567 pdefault_rules->mandatory_not_fields[k])
1576 static int __mlx4_ib_create_default_rules(
1577 struct mlx4_ib_dev *mdev,
1579 const struct default_rules *pdefault_rules,
1580 struct _rule_hw *mlx4_spec) {
1584 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
1586 union ib_flow_spec ib_spec;
1587 switch (pdefault_rules->rules_create_list[i]) {
1591 case IB_FLOW_SPEC_IB:
1592 ib_spec.type = IB_FLOW_SPEC_IB;
1593 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1600 /* We must put empty rule, qpn is being ignored */
1601 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1604 pr_info("invalid parsing\n");
1608 mlx4_spec = (void *)mlx4_spec + ret;
1614 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1616 enum mlx4_net_trans_promisc_mode flow_type,
1622 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1623 struct mlx4_cmd_mailbox *mailbox;
1624 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
1627 static const u16 __mlx4_domain[] = {
1628 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1629 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1630 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1631 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1634 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1635 pr_err("Invalid priority value %d\n", flow_attr->priority);
1639 if (domain >= IB_FLOW_DOMAIN_NUM) {
1640 pr_err("Invalid domain value %d\n", domain);
1644 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1647 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1648 if (IS_ERR(mailbox))
1649 return PTR_ERR(mailbox);
1650 ctrl = mailbox->buf;
1652 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1653 flow_attr->priority);
1654 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1655 ctrl->port = flow_attr->port;
1656 ctrl->qpn = cpu_to_be32(qp->qp_num);
1658 ib_flow = flow_attr + 1;
1659 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
1660 /* Add default flows */
1661 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1662 if (default_flow >= 0) {
1663 ret = __mlx4_ib_create_default_rules(
1664 mdev, qp, default_table + default_flow,
1665 mailbox->buf + size);
1667 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1672 for (i = 0; i < flow_attr->num_of_specs; i++) {
1673 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1674 mailbox->buf + size);
1676 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1679 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1683 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1684 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1687 pr_err("mcg table is full. Fail to register network rule.\n");
1688 else if (ret == -ENXIO)
1689 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1691 pr_err("Invalid argument. Fail to register network rule.\n");
1693 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1697 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1700 err = mlx4_cmd(dev, reg_id, 0, 0,
1701 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1704 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1709 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1713 union ib_flow_spec *ib_spec;
1714 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1717 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1718 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
1719 return 0; /* do nothing */
1721 ib_flow = flow_attr + 1;
1722 ib_spec = (union ib_flow_spec *)ib_flow;
1724 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1725 return 0; /* do nothing */
1727 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1728 flow_attr->port, qp->qp_num,
1729 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1734 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1735 struct ib_flow_attr *flow_attr,
1736 enum mlx4_net_trans_promisc_mode *type)
1740 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1741 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1742 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1746 if (flow_attr->num_of_specs == 0) {
1747 type[0] = MLX4_FS_MC_SNIFFER;
1748 type[1] = MLX4_FS_UC_SNIFFER;
1750 union ib_flow_spec *ib_spec;
1752 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1753 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1756 /* if all is zero than MC and UC */
1757 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1758 type[0] = MLX4_FS_MC_SNIFFER;
1759 type[1] = MLX4_FS_UC_SNIFFER;
1761 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1762 ib_spec->eth.mask.dst_mac[1],
1763 ib_spec->eth.mask.dst_mac[2],
1764 ib_spec->eth.mask.dst_mac[3],
1765 ib_spec->eth.mask.dst_mac[4],
1766 ib_spec->eth.mask.dst_mac[5]};
1768 /* Above xor was only on MC bit, non empty mask is valid
1769 * only if this bit is set and rest are zero.
1771 if (!is_zero_ether_addr(&mac[0]))
1774 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1775 type[0] = MLX4_FS_MC_SNIFFER;
1777 type[0] = MLX4_FS_UC_SNIFFER;
1784 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1785 struct ib_flow_attr *flow_attr,
1788 int err = 0, i = 0, j = 0;
1789 struct mlx4_ib_flow *mflow;
1790 enum mlx4_net_trans_promisc_mode type[2];
1791 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1792 int is_bonded = mlx4_is_bonded(dev);
1794 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1795 return ERR_PTR(-EINVAL);
1797 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1798 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
1799 return ERR_PTR(-EOPNOTSUPP);
1801 memset(type, 0, sizeof(type));
1803 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1809 switch (flow_attr->type) {
1810 case IB_FLOW_ATTR_NORMAL:
1811 /* If dont trap flag (continue match) is set, under specific
1812 * condition traffic be replicated to given qp,
1813 * without stealing it
1815 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1816 err = mlx4_ib_add_dont_trap_rule(dev,
1822 type[0] = MLX4_FS_REGULAR;
1826 case IB_FLOW_ATTR_ALL_DEFAULT:
1827 type[0] = MLX4_FS_ALL_DEFAULT;
1830 case IB_FLOW_ATTR_MC_DEFAULT:
1831 type[0] = MLX4_FS_MC_DEFAULT;
1834 case IB_FLOW_ATTR_SNIFFER:
1835 type[0] = MLX4_FS_MIRROR_RX_PORT;
1836 type[1] = MLX4_FS_MIRROR_SX_PORT;
1844 while (i < ARRAY_SIZE(type) && type[i]) {
1845 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
1846 &mflow->reg_id[i].id);
1848 goto err_create_flow;
1850 /* Application always sees one port so the mirror rule
1851 * must be on port #2
1853 flow_attr->port = 2;
1854 err = __mlx4_ib_create_flow(qp, flow_attr,
1856 &mflow->reg_id[j].mirror);
1857 flow_attr->port = 1;
1859 goto err_create_flow;
1866 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1867 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1868 &mflow->reg_id[i].id);
1870 goto err_create_flow;
1873 flow_attr->port = 2;
1874 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1875 &mflow->reg_id[j].mirror);
1876 flow_attr->port = 1;
1878 goto err_create_flow;
1881 /* function to create mirror rule */
1885 return &mflow->ibflow;
1889 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1890 mflow->reg_id[i].id);
1895 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1896 mflow->reg_id[j].mirror);
1901 return ERR_PTR(err);
1904 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1908 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1909 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1911 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1912 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
1915 if (mflow->reg_id[i].mirror) {
1916 err = __mlx4_ib_destroy_flow(mdev->dev,
1917 mflow->reg_id[i].mirror);
1928 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1931 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1932 struct mlx4_dev *dev = mdev->dev;
1933 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1934 struct mlx4_ib_steering *ib_steering = NULL;
1935 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1936 struct mlx4_flow_reg_id reg_id;
1938 if (mdev->dev->caps.steering_mode ==
1939 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1940 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1945 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1947 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1950 pr_err("multicast attach op failed, err %d\n", err);
1955 if (mlx4_is_bonded(dev)) {
1956 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1957 (mqp->port == 1) ? 2 : 1,
1959 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1960 prot, ®_id.mirror);
1965 err = add_gid_entry(ibqp, gid);
1970 memcpy(ib_steering->gid.raw, gid->raw, 16);
1971 ib_steering->reg_id = reg_id;
1972 mutex_lock(&mqp->mutex);
1973 list_add(&ib_steering->list, &mqp->steering_rules);
1974 mutex_unlock(&mqp->mutex);
1979 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1982 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1983 prot, reg_id.mirror);
1990 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
1992 struct mlx4_ib_gid_entry *ge;
1993 struct mlx4_ib_gid_entry *tmp;
1994 struct mlx4_ib_gid_entry *ret = NULL;
1996 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1997 if (!memcmp(raw, ge->gid.raw, 16)) {
2006 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2009 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2010 struct mlx4_dev *dev = mdev->dev;
2011 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2012 struct net_device *ndev;
2013 struct mlx4_ib_gid_entry *ge;
2014 struct mlx4_flow_reg_id reg_id = {0, 0};
2015 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
2017 if (mdev->dev->caps.steering_mode ==
2018 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2019 struct mlx4_ib_steering *ib_steering;
2021 mutex_lock(&mqp->mutex);
2022 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
2023 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
2024 list_del(&ib_steering->list);
2028 mutex_unlock(&mqp->mutex);
2029 if (&ib_steering->list == &mqp->steering_rules) {
2030 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
2033 reg_id = ib_steering->reg_id;
2037 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2042 if (mlx4_is_bonded(dev)) {
2043 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2044 prot, reg_id.mirror);
2049 mutex_lock(&mqp->mutex);
2050 ge = find_gid_entry(mqp, gid->raw);
2052 spin_lock_bh(&mdev->iboe.lock);
2053 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
2056 spin_unlock_bh(&mdev->iboe.lock);
2059 list_del(&ge->list);
2062 pr_warn("could not find mgid entry\n");
2064 mutex_unlock(&mqp->mutex);
2069 static int init_node_data(struct mlx4_ib_dev *dev)
2071 struct ib_smp *in_mad = NULL;
2072 struct ib_smp *out_mad = NULL;
2073 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
2076 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
2077 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
2078 if (!in_mad || !out_mad)
2081 init_query_mad(in_mad);
2082 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
2083 if (mlx4_is_master(dev->dev))
2084 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
2086 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2090 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
2092 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2094 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2098 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
2099 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2107 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2110 struct mlx4_ib_dev *dev =
2111 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2112 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
2115 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2118 struct mlx4_ib_dev *dev =
2119 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2120 return sprintf(buf, "%x\n", dev->dev->rev_id);
2123 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2126 struct mlx4_ib_dev *dev =
2127 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2128 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2129 dev->dev->board_id);
2132 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2133 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2134 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2136 static struct device_attribute *mlx4_class_attributes[] = {
2142 struct diag_counter {
2147 #define DIAG_COUNTER(_name, _offset) \
2148 { .name = #_name, .offset = _offset }
2150 static const struct diag_counter diag_basic[] = {
2151 DIAG_COUNTER(rq_num_lle, 0x00),
2152 DIAG_COUNTER(sq_num_lle, 0x04),
2153 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2154 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2155 DIAG_COUNTER(rq_num_lpe, 0x18),
2156 DIAG_COUNTER(sq_num_lpe, 0x1C),
2157 DIAG_COUNTER(rq_num_wrfe, 0x20),
2158 DIAG_COUNTER(sq_num_wrfe, 0x24),
2159 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2160 DIAG_COUNTER(sq_num_bre, 0x34),
2161 DIAG_COUNTER(sq_num_rire, 0x44),
2162 DIAG_COUNTER(rq_num_rire, 0x48),
2163 DIAG_COUNTER(sq_num_rae, 0x4C),
2164 DIAG_COUNTER(rq_num_rae, 0x50),
2165 DIAG_COUNTER(sq_num_roe, 0x54),
2166 DIAG_COUNTER(sq_num_tree, 0x5C),
2167 DIAG_COUNTER(sq_num_rree, 0x64),
2168 DIAG_COUNTER(rq_num_rnr, 0x68),
2169 DIAG_COUNTER(sq_num_rnr, 0x6C),
2170 DIAG_COUNTER(rq_num_oos, 0x100),
2171 DIAG_COUNTER(sq_num_oos, 0x104),
2174 static const struct diag_counter diag_ext[] = {
2175 DIAG_COUNTER(rq_num_dup, 0x130),
2176 DIAG_COUNTER(sq_num_to, 0x134),
2179 static const struct diag_counter diag_device_only[] = {
2180 DIAG_COUNTER(num_cqovf, 0x1A0),
2181 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2184 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2187 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2188 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2190 if (!diag[!!port_num].name)
2193 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2194 diag[!!port_num].num_counters,
2195 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2198 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2199 struct rdma_hw_stats *stats,
2202 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2203 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2204 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2205 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2209 ret = mlx4_query_diag_counters(dev->dev,
2210 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2211 diag[!!port].offset, hw_value,
2212 diag[!!port].num_counters, port);
2217 for (i = 0; i < diag[!!port].num_counters; i++)
2218 stats->value[i] = hw_value[i];
2220 return diag[!!port].num_counters;
2223 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2231 num_counters = ARRAY_SIZE(diag_basic);
2233 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2234 num_counters += ARRAY_SIZE(diag_ext);
2237 num_counters += ARRAY_SIZE(diag_device_only);
2239 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2243 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2247 *num = num_counters;
2256 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2264 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2265 name[i] = diag_basic[i].name;
2266 offset[i] = diag_basic[i].offset;
2269 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2270 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2271 name[j] = diag_ext[i].name;
2272 offset[j] = diag_ext[i].offset;
2277 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2278 name[j] = diag_device_only[i].name;
2279 offset[j] = diag_device_only[i].offset;
2284 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2286 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2289 bool per_port = !!(ibdev->dev->caps.flags2 &
2290 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2292 if (mlx4_is_slave(ibdev->dev))
2295 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2296 /* i == 1 means we are building port counters */
2300 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2302 &diag[i].num_counters, i);
2306 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2310 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
2311 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
2317 kfree(diag[i - 1].name);
2318 kfree(diag[i - 1].offset);
2324 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2328 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2329 kfree(ibdev->diag_counters[i].offset);
2330 kfree(ibdev->diag_counters[i].name);
2334 #define MLX4_IB_INVALID_MAC ((u64)-1)
2335 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2336 struct net_device *dev,
2340 u64 release_mac = MLX4_IB_INVALID_MAC;
2341 struct mlx4_ib_qp *qp;
2343 read_lock(&dev_base_lock);
2344 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2345 read_unlock(&dev_base_lock);
2347 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2349 /* no need for update QP1 and mac registration in non-SRIOV */
2350 if (!mlx4_is_mfunc(ibdev->dev))
2353 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2354 qp = ibdev->qp1_proxy[port - 1];
2358 struct mlx4_update_qp_params update_params;
2360 mutex_lock(&qp->mutex);
2361 old_smac = qp->pri.smac;
2362 if (new_smac == old_smac)
2365 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2367 if (new_smac_index < 0)
2370 update_params.smac_index = new_smac_index;
2371 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
2373 release_mac = new_smac;
2376 /* if old port was zero, no mac was yet registered for this QP */
2377 if (qp->pri.smac_port)
2378 release_mac = old_smac;
2379 qp->pri.smac = new_smac;
2380 qp->pri.smac_port = port;
2381 qp->pri.smac_index = new_smac_index;
2385 if (release_mac != MLX4_IB_INVALID_MAC)
2386 mlx4_unregister_mac(ibdev->dev, port, release_mac);
2388 mutex_unlock(&qp->mutex);
2389 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
2392 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2393 struct net_device *dev,
2394 unsigned long event)
2397 struct mlx4_ib_iboe *iboe;
2398 int update_qps_port = -1;
2403 iboe = &ibdev->iboe;
2405 spin_lock_bh(&iboe->lock);
2406 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
2408 iboe->netdevs[port - 1] =
2409 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
2411 if (dev == iboe->netdevs[port - 1] &&
2412 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2413 event == NETDEV_UP || event == NETDEV_CHANGE))
2414 update_qps_port = port;
2417 spin_unlock_bh(&iboe->lock);
2419 if (update_qps_port > 0)
2420 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
2423 static int mlx4_ib_netdev_event(struct notifier_block *this,
2424 unsigned long event, void *ptr)
2426 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2427 struct mlx4_ib_dev *ibdev;
2429 if (!net_eq(dev_net(dev), &init_net))
2432 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
2433 mlx4_ib_scan_netdevs(ibdev, dev, event);
2438 static void init_pkeys(struct mlx4_ib_dev *ibdev)
2444 if (mlx4_is_master(ibdev->dev)) {
2445 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2447 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2449 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2451 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2452 /* master has the identity virt2phys pkey mapping */
2453 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2454 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2455 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2456 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2460 /* initialize pkey cache */
2461 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2463 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2465 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2471 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2473 int i, j, eq = 0, total_eqs = 0;
2475 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2476 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
2477 if (!ibdev->eq_table)
2480 for (i = 1; i <= dev->caps.num_ports; i++) {
2481 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2483 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2485 ibdev->eq_table[eq] = total_eqs;
2486 if (!mlx4_assign_eq(dev, i,
2487 &ibdev->eq_table[eq]))
2490 ibdev->eq_table[eq] = -1;
2494 for (i = eq; i < dev->caps.num_comp_vectors;
2495 ibdev->eq_table[i++] = -1)
2498 /* Advertise the new number of EQs to clients */
2499 ibdev->ib_dev.num_comp_vectors = eq;
2502 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2505 int total_eqs = ibdev->ib_dev.num_comp_vectors;
2507 /* no eqs were allocated */
2508 if (!ibdev->eq_table)
2511 /* Reset the advertised EQ number */
2512 ibdev->ib_dev.num_comp_vectors = 0;
2514 for (i = 0; i < total_eqs; i++)
2515 mlx4_release_eq(dev, ibdev->eq_table[i]);
2517 kfree(ibdev->eq_table);
2518 ibdev->eq_table = NULL;
2521 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2522 struct ib_port_immutable *immutable)
2524 struct ib_port_attr attr;
2525 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
2528 err = mlx4_ib_query_port(ibdev, port_num, &attr);
2532 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2533 immutable->gid_tbl_len = attr.gid_tbl_len;
2535 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
2536 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2538 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2539 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2540 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2541 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2542 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2545 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2550 static void get_fw_ver_str(struct ib_device *device, char *str,
2553 struct mlx4_ib_dev *dev =
2554 container_of(device, struct mlx4_ib_dev, ib_dev);
2555 snprintf(str, str_len, "%d.%d.%d",
2556 (int) (dev->dev->caps.fw_ver >> 32),
2557 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2558 (int) dev->dev->caps.fw_ver & 0xffff);
2561 static void *mlx4_ib_add(struct mlx4_dev *dev)
2563 struct mlx4_ib_dev *ibdev;
2567 struct mlx4_ib_iboe *iboe;
2568 int ib_num_ports = 0;
2569 int num_req_counters;
2572 struct counter_index *new_counter_index = NULL;
2574 pr_info_once("%s", mlx4_ib_version);
2577 mlx4_foreach_ib_transport_port(i, dev)
2580 /* No point in registering a device with no ports... */
2584 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2586 dev_err(&dev->persist->pdev->dev,
2587 "Device struct alloc failed\n");
2591 iboe = &ibdev->iboe;
2593 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2596 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2599 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2601 if (!ibdev->uar_map)
2603 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
2606 ibdev->bond_next_port = 0;
2608 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2609 ibdev->ib_dev.owner = THIS_MODULE;
2610 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
2611 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
2612 ibdev->num_ports = num_ports;
2613 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2614 1 : ibdev->num_ports;
2615 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
2616 ibdev->ib_dev.dma_device = &dev->persist->pdev->dev;
2617 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
2618 ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
2619 ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
2621 if (dev->caps.userspace_caps)
2622 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2624 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2626 ibdev->ib_dev.uverbs_cmd_mask =
2627 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2628 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2629 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2630 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2631 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2632 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2633 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2634 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2635 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2636 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2637 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2638 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2639 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2640 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2641 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2642 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2643 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2644 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2645 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2646 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2647 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2648 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2649 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2650 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2652 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2653 ibdev->ib_dev.query_port = mlx4_ib_query_port;
2654 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
2655 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2656 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2657 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2658 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2659 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2660 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2661 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2662 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2663 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2664 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2665 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2666 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2667 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2668 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
2669 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
2670 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2671 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2672 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2673 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
2674 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
2675 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2676 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2677 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2678 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
2679 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
2680 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
2681 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2682 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2683 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2684 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2685 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
2686 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
2687 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
2688 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
2689 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
2690 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2691 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2692 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
2693 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
2694 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
2695 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
2697 if (!mlx4_is_slave(ibdev->dev)) {
2698 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2699 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2700 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2701 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2704 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2705 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2706 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
2707 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2709 ibdev->ib_dev.uverbs_cmd_mask |=
2710 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2711 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2714 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2715 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2716 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2717 ibdev->ib_dev.uverbs_cmd_mask |=
2718 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2719 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2722 if (check_flow_steering_support(dev)) {
2723 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
2724 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2725 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2727 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2728 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2729 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2732 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2733 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2734 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2735 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2737 mlx4_ib_alloc_eqs(dev, ibdev);
2739 spin_lock_init(&iboe->lock);
2741 if (init_node_data(ibdev))
2743 mlx4_init_sl2vl_tbl(ibdev);
2745 for (i = 0; i < ibdev->num_ports; ++i) {
2746 mutex_init(&ibdev->counters_table[i].mutex);
2747 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2750 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2751 for (i = 0; i < num_req_counters; ++i) {
2752 mutex_init(&ibdev->qp1_proxy_lock[i]);
2754 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2755 IB_LINK_LAYER_ETHERNET) {
2756 err = mlx4_counter_alloc(ibdev->dev, &counter_index);
2757 /* if failed to allocate a new counter, use default */
2760 mlx4_get_default_counter_index(dev,
2764 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2765 counter_index = mlx4_get_default_counter_index(dev,
2768 new_counter_index = kmalloc(sizeof(*new_counter_index),
2770 if (!new_counter_index) {
2772 mlx4_counter_free(ibdev->dev, counter_index);
2775 new_counter_index->index = counter_index;
2776 new_counter_index->allocated = allocated;
2777 list_add_tail(&new_counter_index->list,
2778 &ibdev->counters_table[i].counters_list);
2779 ibdev->counters_table[i].default_counter = counter_index;
2780 pr_info("counter index %d for port %d allocated %d\n",
2781 counter_index, i + 1, allocated);
2783 if (mlx4_is_bonded(dev))
2784 for (i = 1; i < ibdev->num_ports ; ++i) {
2786 kmalloc(sizeof(struct counter_index),
2788 if (!new_counter_index)
2790 new_counter_index->index = counter_index;
2791 new_counter_index->allocated = 0;
2792 list_add_tail(&new_counter_index->list,
2793 &ibdev->counters_table[i].counters_list);
2794 ibdev->counters_table[i].default_counter =
2798 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2801 spin_lock_init(&ibdev->sm_lock);
2802 mutex_init(&ibdev->cap_mask_mutex);
2803 INIT_LIST_HEAD(&ibdev->qp_list);
2804 spin_lock_init(&ibdev->reset_flow_resource_lock);
2806 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2808 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2809 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2810 MLX4_IB_UC_STEER_QPN_ALIGN,
2811 &ibdev->steer_qpn_base, 0);
2815 ibdev->ib_uc_qpns_bitmap =
2816 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2819 if (!ibdev->ib_uc_qpns_bitmap) {
2820 dev_err(&dev->persist->pdev->dev,
2821 "bit map alloc failed\n");
2822 goto err_steer_qp_release;
2825 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2826 bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2827 ibdev->steer_qpn_count);
2828 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2829 dev, ibdev->steer_qpn_base,
2830 ibdev->steer_qpn_base +
2831 ibdev->steer_qpn_count - 1);
2833 goto err_steer_free_bitmap;
2835 bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2836 ibdev->steer_qpn_count);
2840 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2841 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2843 if (mlx4_ib_alloc_diag_counters(ibdev))
2844 goto err_steer_free_bitmap;
2846 if (ib_register_device(&ibdev->ib_dev, NULL))
2847 goto err_diag_counters;
2849 if (mlx4_ib_mad_init(ibdev))
2852 if (mlx4_ib_init_sriov(ibdev))
2855 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE ||
2856 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2857 if (!iboe->nb.notifier_call) {
2858 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2859 err = register_netdevice_notifier(&iboe->nb);
2861 iboe->nb.notifier_call = NULL;
2865 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2866 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2873 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
2874 if (device_create_file(&ibdev->ib_dev.dev,
2875 mlx4_class_attributes[j]))
2879 ibdev->ib_active = true;
2880 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2881 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2884 if (mlx4_is_mfunc(ibdev->dev))
2887 /* create paravirt contexts for any VFs which are active */
2888 if (mlx4_is_master(ibdev->dev)) {
2889 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2890 if (j == mlx4_master_func_num(ibdev->dev))
2892 if (mlx4_is_slave_active(ibdev->dev, j))
2893 do_slave_init(ibdev, j, 1);
2899 if (ibdev->iboe.nb.notifier_call) {
2900 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2901 pr_warn("failure unregistering notifier\n");
2902 ibdev->iboe.nb.notifier_call = NULL;
2904 flush_workqueue(wq);
2906 mlx4_ib_close_sriov(ibdev);
2909 mlx4_ib_mad_cleanup(ibdev);
2912 ib_unregister_device(&ibdev->ib_dev);
2915 mlx4_ib_diag_cleanup(ibdev);
2917 err_steer_free_bitmap:
2918 kfree(ibdev->ib_uc_qpns_bitmap);
2920 err_steer_qp_release:
2921 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
2922 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2923 ibdev->steer_qpn_count);
2925 for (i = 0; i < ibdev->num_ports; ++i)
2926 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2929 mlx4_ib_free_eqs(dev, ibdev);
2930 iounmap(ibdev->uar_map);
2933 mlx4_uar_free(dev, &ibdev->priv_uar);
2936 mlx4_pd_free(dev, ibdev->priv_pdn);
2939 ib_dealloc_device(&ibdev->ib_dev);
2944 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2948 WARN_ON(!dev->ib_uc_qpns_bitmap);
2950 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2951 dev->steer_qpn_count,
2952 get_count_order(count));
2956 *qpn = dev->steer_qpn_base + offset;
2960 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2963 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2966 BUG_ON(qpn < dev->steer_qpn_base);
2968 bitmap_release_region(dev->ib_uc_qpns_bitmap,
2969 qpn - dev->steer_qpn_base,
2970 get_count_order(count));
2973 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2978 struct ib_flow_attr *flow = NULL;
2979 struct ib_flow_spec_ib *ib_spec;
2982 flow_size = sizeof(struct ib_flow_attr) +
2983 sizeof(struct ib_flow_spec_ib);
2984 flow = kzalloc(flow_size, GFP_KERNEL);
2987 flow->port = mqp->port;
2988 flow->num_of_specs = 1;
2989 flow->size = flow_size;
2990 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
2991 ib_spec->type = IB_FLOW_SPEC_IB;
2992 ib_spec->size = sizeof(struct ib_flow_spec_ib);
2993 /* Add an empty rule for IB L2 */
2994 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
2996 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
3001 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
3007 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
3009 struct mlx4_ib_dev *ibdev = ibdev_ptr;
3013 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3014 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
3015 ibdev->ib_active = false;
3016 flush_workqueue(wq);
3018 mlx4_ib_close_sriov(ibdev);
3019 mlx4_ib_mad_cleanup(ibdev);
3020 ib_unregister_device(&ibdev->ib_dev);
3021 mlx4_ib_diag_cleanup(ibdev);
3022 if (ibdev->iboe.nb.notifier_call) {
3023 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
3024 pr_warn("failure unregistering notifier\n");
3025 ibdev->iboe.nb.notifier_call = NULL;
3028 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
3029 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3030 ibdev->steer_qpn_count);
3031 kfree(ibdev->ib_uc_qpns_bitmap);
3034 iounmap(ibdev->uar_map);
3035 for (p = 0; p < ibdev->num_ports; ++p)
3036 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3038 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
3039 mlx4_CLOSE_PORT(dev, p);
3041 mlx4_ib_free_eqs(dev, ibdev);
3043 mlx4_uar_free(dev, &ibdev->priv_uar);
3044 mlx4_pd_free(dev, ibdev->priv_pdn);
3045 ib_dealloc_device(&ibdev->ib_dev);
3048 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3050 struct mlx4_ib_demux_work **dm = NULL;
3051 struct mlx4_dev *dev = ibdev->dev;
3053 unsigned long flags;
3054 struct mlx4_active_ports actv_ports;
3056 unsigned int first_port;
3058 if (!mlx4_is_master(dev))
3061 actv_ports = mlx4_get_active_ports(dev, slave);
3062 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3063 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3065 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3067 pr_err("failed to allocate memory for tunneling qp update\n");
3071 for (i = 0; i < ports; i++) {
3072 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3074 pr_err("failed to allocate memory for tunneling qp update work struct\n");
3079 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
3080 dm[i]->port = first_port + i + 1;
3081 dm[i]->slave = slave;
3082 dm[i]->do_init = do_init;
3085 /* initialize or tear down tunnel QPs for the slave */
3086 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3087 if (!ibdev->sriov.is_going_down) {
3088 for (i = 0; i < ports; i++)
3089 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3090 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3092 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3093 for (i = 0; i < ports; i++)
3101 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3103 struct mlx4_ib_qp *mqp;
3104 unsigned long flags_qp;
3105 unsigned long flags_cq;
3106 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3107 struct list_head cq_notify_list;
3108 struct mlx4_cq *mcq;
3109 unsigned long flags;
3111 pr_warn("mlx4_ib_handle_catas_error was started\n");
3112 INIT_LIST_HEAD(&cq_notify_list);
3114 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3115 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3117 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3118 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3119 if (mqp->sq.tail != mqp->sq.head) {
3120 send_mcq = to_mcq(mqp->ibqp.send_cq);
3121 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3122 if (send_mcq->mcq.comp &&
3123 mqp->ibqp.send_cq->comp_handler) {
3124 if (!send_mcq->mcq.reset_notify_added) {
3125 send_mcq->mcq.reset_notify_added = 1;
3126 list_add_tail(&send_mcq->mcq.reset_notify,
3130 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3132 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3133 /* Now, handle the QP's receive queue */
3134 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3135 /* no handling is needed for SRQ */
3136 if (!mqp->ibqp.srq) {
3137 if (mqp->rq.tail != mqp->rq.head) {
3138 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3139 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3140 if (recv_mcq->mcq.comp &&
3141 mqp->ibqp.recv_cq->comp_handler) {
3142 if (!recv_mcq->mcq.reset_notify_added) {
3143 recv_mcq->mcq.reset_notify_added = 1;
3144 list_add_tail(&recv_mcq->mcq.reset_notify,
3148 spin_unlock_irqrestore(&recv_mcq->lock,
3152 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3155 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3158 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3159 pr_warn("mlx4_ib_handle_catas_error ended\n");
3162 static void handle_bonded_port_state_event(struct work_struct *work)
3164 struct ib_event_work *ew =
3165 container_of(work, struct ib_event_work, work);
3166 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3167 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3169 struct ib_event ibev;
3172 spin_lock_bh(&ibdev->iboe.lock);
3173 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3174 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
3175 enum ib_port_state curr_port_state;
3181 (netif_running(curr_netdev) &&
3182 netif_carrier_ok(curr_netdev)) ?
3183 IB_PORT_ACTIVE : IB_PORT_DOWN;
3185 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3186 curr_port_state : IB_PORT_ACTIVE;
3188 spin_unlock_bh(&ibdev->iboe.lock);
3190 ibev.device = &ibdev->ib_dev;
3191 ibev.element.port_num = 1;
3192 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3193 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3195 ib_dispatch_event(&ibev);
3198 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3203 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3205 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3209 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3212 static void ib_sl2vl_update_work(struct work_struct *work)
3214 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3215 struct mlx4_ib_dev *mdev = ew->ib_dev;
3216 int port = ew->port;
3218 mlx4_ib_sl2vl_update(mdev, port);
3223 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3226 struct ib_event_work *ew;
3228 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3230 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3233 queue_work(wq, &ew->work);
3235 pr_err("failed to allocate memory for sl2vl update work\n");
3239 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3240 enum mlx4_dev_event event, unsigned long param)
3242 struct ib_event ibev;
3243 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
3244 struct mlx4_eqe *eqe = NULL;
3245 struct ib_event_work *ew;
3248 if (mlx4_is_bonded(dev) &&
3249 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3250 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3251 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3254 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3256 queue_work(wq, &ew->work);
3260 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3261 eqe = (struct mlx4_eqe *)param;
3266 case MLX4_DEV_EVENT_PORT_UP:
3267 if (p > ibdev->num_ports)
3269 if (!mlx4_is_slave(dev) &&
3270 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3271 IB_LINK_LAYER_INFINIBAND) {
3272 if (mlx4_is_master(dev))
3273 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3274 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3275 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3276 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
3278 ibev.event = IB_EVENT_PORT_ACTIVE;
3281 case MLX4_DEV_EVENT_PORT_DOWN:
3282 if (p > ibdev->num_ports)
3284 ibev.event = IB_EVENT_PORT_ERR;
3287 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3288 ibdev->ib_active = false;
3289 ibev.event = IB_EVENT_DEVICE_FATAL;
3290 mlx4_ib_handle_catas_error(ibdev);
3293 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3294 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3296 pr_err("failed to allocate memory for events work\n");
3300 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3301 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3303 /* need to queue only for port owner, which uses GEN_EQE */
3304 if (mlx4_is_master(dev))
3305 queue_work(wq, &ew->work);
3307 handle_port_mgmt_change_event(&ew->work);
3310 case MLX4_DEV_EVENT_SLAVE_INIT:
3311 /* here, p is the slave id */
3312 do_slave_init(ibdev, p, 1);
3313 if (mlx4_is_master(dev)) {
3316 for (i = 1; i <= ibdev->num_ports; i++) {
3317 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3318 == IB_LINK_LAYER_INFINIBAND)
3319 mlx4_ib_slave_alias_guid_event(ibdev,
3326 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
3327 if (mlx4_is_master(dev)) {
3330 for (i = 1; i <= ibdev->num_ports; i++) {
3331 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3332 == IB_LINK_LAYER_INFINIBAND)
3333 mlx4_ib_slave_alias_guid_event(ibdev,
3338 /* here, p is the slave id */
3339 do_slave_init(ibdev, p, 0);
3346 ibev.device = ibdev_ptr;
3347 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
3349 ib_dispatch_event(&ibev);
3352 static struct mlx4_interface mlx4_ib_interface = {
3354 .remove = mlx4_ib_remove,
3355 .event = mlx4_ib_event,
3356 .protocol = MLX4_PROT_IB_IPV6,
3357 .flags = MLX4_INTFF_BONDING
3360 static int __init mlx4_ib_init(void)
3364 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
3368 err = mlx4_ib_mcg_init();
3372 err = mlx4_register_interface(&mlx4_ib_interface);
3379 mlx4_ib_mcg_destroy();
3382 destroy_workqueue(wq);
3386 static void __exit mlx4_ib_cleanup(void)
3388 mlx4_unregister_interface(&mlx4_ib_interface);
3389 mlx4_ib_mcg_destroy();
3390 destroy_workqueue(wq);
3393 module_init(mlx4_ib_init);
3394 module_exit(mlx4_ib_cleanup);