drivers/infiniband/hw/mlx4/cq.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/mlx4/cq.h>
  35 #include <linux/mlx4/qp.h>
  36 #include <linux/mlx4/srq.h>
  37 #include <linux/slab.h>
  38
  39 #include "mlx4_ib.h"
  40 #include "user.h"
  41
  42 static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
  43 {
  44         struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  45         ibcq->comp_handler(ibcq, ibcq->cq_context);
  46 }
  47
  48 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
  49 {
  50         struct ib_event event;
  51         struct ib_cq *ibcq;
  52
  53         if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
  54                 pr_warn("Unexpected event type %d "
  55                        "on CQ %06x\n", type, cq->cqn);
  56                 return;
  57         }
  58
  59         ibcq = &to_mibcq(cq)->ibcq;
  60         if (ibcq->event_handler) {
  61                 event.device     = ibcq->device;
  62                 event.event      = IB_EVENT_CQ_ERR;
  63                 event.element.cq = ibcq;
  64                 ibcq->event_handler(&event, ibcq->cq_context);
  65         }
  66 }
  67
  68 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
  69 {
  70         return mlx4_buf_offset(&buf->buf, n * buf->entry_size);
  71 }
  72
  73 static void *get_cqe(struct mlx4_ib_cq *cq, int n)
  74 {
  75         return get_cqe_from_buf(&cq->buf, n);
  76 }
  77
  78 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
  79 {
  80         struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  81         struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe);
  82
  83         return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
  84                 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
  85 }
  86
  87 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
  88 {
  89         return get_sw_cqe(cq, cq->mcq.cons_index);
  90 }
  91
  92 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
  93 {
  94         struct mlx4_ib_cq *mcq = to_mcq(cq);
  95         struct mlx4_ib_dev *dev = to_mdev(cq->device);
  96
  97         return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
  98 }
  99
 100 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
 101 {
 102         int err;
 103
 104         err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size,
 105                              PAGE_SIZE * 2, &buf->buf, GFP_KERNEL);
 106
 107         if (err)
 108                 goto out;
 109
 110         buf->entry_size = dev->dev->caps.cqe_size;
 111         err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
 112                                     &buf->mtt);
 113         if (err)
 114                 goto err_buf;
 115
 116         err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf, GFP_KERNEL);
 117         if (err)
 118                 goto err_mtt;
 119
 120         return 0;
 121
 122 err_mtt:
 123         mlx4_mtt_cleanup(dev->dev, &buf->mtt);
 124
 125 err_buf:
 126         mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf);
 127
 128 out:
 129         return err;
 130 }
 131
 132 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
 133 {
 134         mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf);
 135 }
 136
 137 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
 138                                struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
 139                                u64 buf_addr, int cqe)
 140 {
 141         int err;
 142         int cqe_size = dev->dev->caps.cqe_size;
 143
 144         *umem = ib_umem_get(context, buf_addr, cqe * cqe_size,
 145                             IB_ACCESS_LOCAL_WRITE, 1);
 146         if (IS_ERR(*umem))
 147                 return PTR_ERR(*umem);
 148
 149         err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
 150                             ilog2((*umem)->page_size), &buf->mtt);
 151         if (err)
 152                 goto err_buf;
 153
 154         err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
 155         if (err)
 156                 goto err_mtt;
 157
 158         return 0;
 159
 160 err_mtt:
 161         mlx4_mtt_cleanup(dev->dev, &buf->mtt);
 162
 163 err_buf:
 164         ib_umem_release(*umem);
 165
 166         return err;
 167 }
 168
 169 struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
 170                                 struct ib_ucontext *context,
 171                                 struct ib_udata *udata)
 172 {
 173         struct mlx4_ib_dev *dev = to_mdev(ibdev);
 174         struct mlx4_ib_cq *cq;
 175         struct mlx4_uar *uar;
 176         int err;
 177
 178         if (entries < 1 || entries > dev->dev->caps.max_cqes)
 179                 return ERR_PTR(-EINVAL);
 180
 181         cq = kmalloc(sizeof *cq, GFP_KERNEL);
 182         if (!cq)
 183                 return ERR_PTR(-ENOMEM);
 184
 185         entries      = roundup_pow_of_two(entries + 1);
 186         cq->ibcq.cqe = entries - 1;
 187         mutex_init(&cq->resize_mutex);
 188         spin_lock_init(&cq->lock);
 189         cq->resize_buf = NULL;
 190         cq->resize_umem = NULL;
 191
 192         if (context) {
 193                 struct mlx4_ib_create_cq ucmd;
 194
 195                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 196                         err = -EFAULT;
 197                         goto err_cq;
 198                 }
 199
 200                 err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
 201                                           ucmd.buf_addr, entries);
 202                 if (err)
 203                         goto err_cq;
 204
 205                 err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
 206                                           &cq->db);
 207                 if (err)
 208                         goto err_mtt;
 209
 210                 uar = &to_mucontext(context)->uar;
 211         } else {
 212                 err = mlx4_db_alloc(dev->dev, &cq->db, 1, GFP_KERNEL);
 213                 if (err)
 214                         goto err_cq;
 215
 216                 cq->mcq.set_ci_db  = cq->db.db;
 217                 cq->mcq.arm_db     = cq->db.db + 1;
 218                 *cq->mcq.set_ci_db = 0;
 219                 *cq->mcq.arm_db    = 0;
 220
 221                 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
 222                 if (err)
 223                         goto err_db;
 224
 225                 uar = &dev->priv_uar;
 226         }
 227
 228         if (dev->eq_table)
 229                 vector = dev->eq_table[vector % ibdev->num_comp_vectors];
 230
 231         err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
 232                             cq->db.dma, &cq->mcq, vector, 0, 0);
 233         if (err)
 234                 goto err_dbmap;
 235
 236         cq->mcq.comp  = mlx4_ib_cq_comp;
 237         cq->mcq.event = mlx4_ib_cq_event;
 238
 239         if (context)
 240                 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
 241                         err = -EFAULT;
 242                         goto err_cq_free;
 243                 }
 244
 245         return &cq->ibcq;
 246
 247 err_cq_free:
 248         mlx4_cq_free(dev->dev, &cq->mcq);
 249
 250 err_dbmap:
 251         if (context)
 252                 mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
 253
 254 err_mtt:
 255         mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
 256
 257         if (context)
 258                 ib_umem_release(cq->umem);
 259         else
 260                 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
 261
 262 err_db:
 263         if (!context)
 264                 mlx4_db_free(dev->dev, &cq->db);
 265
 266 err_cq:
 267         kfree(cq);
 268
 269         return ERR_PTR(err);
 270 }
 271
 272 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
 273                                   int entries)
 274 {
 275         int err;
 276
 277         if (cq->resize_buf)
 278                 return -EBUSY;
 279
 280         cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
 281         if (!cq->resize_buf)
 282                 return -ENOMEM;
 283
 284         err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
 285         if (err) {
 286                 kfree(cq->resize_buf);
 287                 cq->resize_buf = NULL;
 288                 return err;
 289         }
 290
 291         cq->resize_buf->cqe = entries - 1;
 292
 293         return 0;
 294 }
 295
 296 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
 297                                    int entries, struct ib_udata *udata)
 298 {
 299         struct mlx4_ib_resize_cq ucmd;
 300         int err;
 301
 302         if (cq->resize_umem)
 303                 return -EBUSY;
 304
 305         if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
 306                 return -EFAULT;
 307
 308         cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
 309         if (!cq->resize_buf)
 310                 return -ENOMEM;
 311
 312         err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
 313                                   &cq->resize_umem, ucmd.buf_addr, entries);
 314         if (err) {
 315                 kfree(cq->resize_buf);
 316                 cq->resize_buf = NULL;
 317                 return err;
 318         }
 319
 320         cq->resize_buf->cqe = entries - 1;
 321
 322         return 0;
 323 }
 324
 325 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
 326 {
 327         u32 i;
 328
 329         i = cq->mcq.cons_index;
 330         while (get_sw_cqe(cq, i))
 331                 ++i;
 332
 333         return i - cq->mcq.cons_index;
 334 }
 335
 336 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
 337 {
 338         struct mlx4_cqe *cqe, *new_cqe;
 339         int i;
 340         int cqe_size = cq->buf.entry_size;
 341         int cqe_inc = cqe_size == 64 ? 1 : 0;
 342
 343         i = cq->mcq.cons_index;
 344         cqe = get_cqe(cq, i & cq->ibcq.cqe);
 345         cqe += cqe_inc;
 346
 347         while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
 348                 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
 349                                            (i + 1) & cq->resize_buf->cqe);
 350                 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size);
 351                 new_cqe += cqe_inc;
 352
 353                 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
 354                         (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
 355                 cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
 356                 cqe += cqe_inc;
 357         }
 358         ++cq->mcq.cons_index;
 359 }
 360
 361 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
 362 {
 363         struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
 364         struct mlx4_ib_cq *cq = to_mcq(ibcq);
 365         struct mlx4_mtt mtt;
 366         int outst_cqe;
 367         int err;
 368
 369         mutex_lock(&cq->resize_mutex);
 370
 371         if (entries < 1) {
 372                 err = -EINVAL;
 373                 goto out;
 374         }
 375
 376         entries = roundup_pow_of_two(entries + 1);
 377         if (entries == ibcq->cqe + 1) {
 378                 err = 0;
 379                 goto out;
 380         }
 381
 382         if (entries > dev->dev->caps.max_cqes) {
 383                 err = -EINVAL;
 384                 goto out;
 385         }
 386
 387         if (ibcq->uobject) {
 388                 err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
 389                 if (err)
 390                         goto out;
 391         } else {
 392                 /* Can't be smaller than the number of outstanding CQEs */
 393                 outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
 394                 if (entries < outst_cqe + 1) {
 395                         err = 0;
 396                         goto out;
 397                 }
 398
 399                 err = mlx4_alloc_resize_buf(dev, cq, entries);
 400                 if (err)
 401                         goto out;
 402         }
 403
 404         mtt = cq->buf.mtt;
 405
 406         err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
 407         if (err)
 408                 goto err_buf;
 409
 410         mlx4_mtt_cleanup(dev->dev, &mtt);
 411         if (ibcq->uobject) {
 412                 cq->buf      = cq->resize_buf->buf;
 413                 cq->ibcq.cqe = cq->resize_buf->cqe;
 414                 ib_umem_release(cq->umem);
 415                 cq->umem     = cq->resize_umem;
 416
 417                 kfree(cq->resize_buf);
 418                 cq->resize_buf = NULL;
 419                 cq->resize_umem = NULL;
 420         } else {
 421                 struct mlx4_ib_cq_buf tmp_buf;
 422                 int tmp_cqe = 0;
 423
 424                 spin_lock_irq(&cq->lock);
 425                 if (cq->resize_buf) {
 426                         mlx4_ib_cq_resize_copy_cqes(cq);
 427                         tmp_buf = cq->buf;
 428                         tmp_cqe = cq->ibcq.cqe;
 429                         cq->buf      = cq->resize_buf->buf;
 430                         cq->ibcq.cqe = cq->resize_buf->cqe;
 431
 432                         kfree(cq->resize_buf);
 433                         cq->resize_buf = NULL;
 434                 }
 435                 spin_unlock_irq(&cq->lock);
 436
 437                 if (tmp_cqe)
 438                         mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
 439         }
 440
 441         goto out;
 442
 443 err_buf:
 444         mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
 445         if (!ibcq->uobject)
 446                 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
 447                                     cq->resize_buf->cqe);
 448
 449         kfree(cq->resize_buf);
 450         cq->resize_buf = NULL;
 451
 452         if (cq->resize_umem) {
 453                 ib_umem_release(cq->resize_umem);
 454                 cq->resize_umem = NULL;
 455         }
 456
 457 out:
 458         mutex_unlock(&cq->resize_mutex);
 459
 460         return err;
 461 }
 462
 463 int mlx4_ib_destroy_cq(struct ib_cq *cq)
 464 {
 465         struct mlx4_ib_dev *dev = to_mdev(cq->device);
 466         struct mlx4_ib_cq *mcq = to_mcq(cq);
 467
 468         mlx4_cq_free(dev->dev, &mcq->mcq);
 469         mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
 470
 471         if (cq->uobject) {
 472                 mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
 473                 ib_umem_release(mcq->umem);
 474         } else {
 475                 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
 476                 mlx4_db_free(dev->dev, &mcq->db);
 477         }
 478
 479         kfree(mcq);
 480
 481         return 0;
 482 }
 483
 484 static void dump_cqe(void *cqe)
 485 {
 486         __be32 *buf = cqe;
 487
 488         pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
 489                be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
 490                be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
 491                be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
 492 }
 493
 494 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
 495                                      struct ib_wc *wc)
 496 {
 497         if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
 498                 pr_debug("local QP operation err "
 499                        "(QPN %06x, WQE index %x, vendor syndrome %02x, "
 500                        "opcode = %02x)\n",
 501                        be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
 502                        cqe->vendor_err_syndrome,
 503                        cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
 504                 dump_cqe(cqe);
 505         }
 506
 507         switch (cqe->syndrome) {
 508         case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
 509                 wc->status = IB_WC_LOC_LEN_ERR;
 510                 break;
 511         case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
 512                 wc->status = IB_WC_LOC_QP_OP_ERR;
 513                 break;
 514         case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
 515                 wc->status = IB_WC_LOC_PROT_ERR;
 516                 break;
 517         case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
 518                 wc->status = IB_WC_WR_FLUSH_ERR;
 519                 break;
 520         case MLX4_CQE_SYNDROME_MW_BIND_ERR:
 521                 wc->status = IB_WC_MW_BIND_ERR;
 522                 break;
 523         case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
 524                 wc->status = IB_WC_BAD_RESP_ERR;
 525                 break;
 526         case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
 527                 wc->status = IB_WC_LOC_ACCESS_ERR;
 528                 break;
 529         case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
 530                 wc->status = IB_WC_REM_INV_REQ_ERR;
 531                 break;
 532         case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
 533                 wc->status = IB_WC_REM_ACCESS_ERR;
 534                 break;
 535         case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
 536                 wc->status = IB_WC_REM_OP_ERR;
 537                 break;
 538         case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
 539                 wc->status = IB_WC_RETRY_EXC_ERR;
 540                 break;
 541         case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
 542                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
 543                 break;
 544         case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
 545                 wc->status = IB_WC_REM_ABORT_ERR;
 546                 break;
 547         default:
 548                 wc->status = IB_WC_GENERAL_ERR;
 549                 break;
 550         }
 551
 552         wc->vendor_err = cqe->vendor_err_syndrome;
 553 }
 554
 555 static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
 556 {
 557         return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4      |
 558                                       MLX4_CQE_STATUS_IPV4F     |
 559                                       MLX4_CQE_STATUS_IPV4OPT   |
 560                                       MLX4_CQE_STATUS_IPV6      |
 561                                       MLX4_CQE_STATUS_IPOK)) ==
 562                 cpu_to_be16(MLX4_CQE_STATUS_IPV4        |
 563                             MLX4_CQE_STATUS_IPOK))              &&
 564                 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP       |
 565                                       MLX4_CQE_STATUS_TCP))     &&
 566                 checksum == cpu_to_be16(0xffff);
 567 }
 568
 569 static int use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
 570                            unsigned tail, struct mlx4_cqe *cqe, int is_eth)
 571 {
 572         struct mlx4_ib_proxy_sqp_hdr *hdr;
 573
 574         ib_dma_sync_single_for_cpu(qp->ibqp.device,
 575                                    qp->sqp_proxy_rcv[tail].map,
 576                                    sizeof (struct mlx4_ib_proxy_sqp_hdr),
 577                                    DMA_FROM_DEVICE);
 578         hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
 579         wc->pkey_index  = be16_to_cpu(hdr->tun.pkey_index);
 580         wc->src_qp      = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
 581         wc->wc_flags   |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
 582         wc->dlid_path_bits = 0;
 583
 584         if (is_eth) {
 585                 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid);
 586                 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4);
 587                 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2);
 588                 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
 589         } else {
 590                 wc->slid        = be16_to_cpu(hdr->tun.slid_mac_47_32);
 591                 wc->sl          = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
 592         }
 593
 594         return 0;
 595 }
 596
 597 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
 598                             struct mlx4_ib_qp **cur_qp,
 599                             struct ib_wc *wc)
 600 {
 601         struct mlx4_cqe *cqe;
 602         struct mlx4_qp *mqp;
 603         struct mlx4_ib_wq *wq;
 604         struct mlx4_ib_srq *srq;
 605         struct mlx4_srq *msrq = NULL;
 606         int is_send;
 607         int is_error;
 608         int is_eth;
 609         u32 g_mlpath_rqpn;
 610         u16 wqe_ctr;
 611         unsigned tail = 0;
 612
 613 repoll:
 614         cqe = next_cqe_sw(cq);
 615         if (!cqe)
 616                 return -EAGAIN;
 617
 618         if (cq->buf.entry_size == 64)
 619                 cqe++;
 620
 621         ++cq->mcq.cons_index;
 622
 623         /*
 624          * Make sure we read CQ entry contents after we've checked the
 625          * ownership bit.
 626          */
 627         rmb();
 628
 629         is_send  = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
 630         is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 631                 MLX4_CQE_OPCODE_ERROR;
 632
 633         if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
 634                      is_send)) {
 635                 pr_warn("Completion for NOP opcode detected!\n");
 636                 return -EINVAL;
 637         }
 638
 639         /* Resize CQ in progress */
 640         if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
 641                 if (cq->resize_buf) {
 642                         struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
 643
 644                         mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
 645                         cq->buf      = cq->resize_buf->buf;
 646                         cq->ibcq.cqe = cq->resize_buf->cqe;
 647
 648                         kfree(cq->resize_buf);
 649                         cq->resize_buf = NULL;
 650                 }
 651
 652                 goto repoll;
 653         }
 654
 655         if (!*cur_qp ||
 656             (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
 657                 /*
 658                  * We do not have to take the QP table lock here,
 659                  * because CQs will be locked while QPs are removed
 660                  * from the table.
 661                  */
 662                 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
 663                                        be32_to_cpu(cqe->vlan_my_qpn));
 664                 if (unlikely(!mqp)) {
 665                         pr_warn("CQ %06x with entry for unknown QPN %06x\n",
 666                                cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
 667                         return -EINVAL;
 668                 }
 669
 670                 *cur_qp = to_mibqp(mqp);
 671         }
 672
 673         wc->qp = &(*cur_qp)->ibqp;
 674
 675         if (wc->qp->qp_type == IB_QPT_XRC_TGT) {
 676                 u32 srq_num;
 677                 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
 678                 srq_num       = g_mlpath_rqpn & 0xffffff;
 679                 /* SRQ is also in the radix tree */
 680                 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev,
 681                                        srq_num);
 682                 if (unlikely(!msrq)) {
 683                         pr_warn("CQ %06x with entry for unknown SRQN %06x\n",
 684                                 cq->mcq.cqn, srq_num);
 685                         return -EINVAL;
 686                 }
 687         }
 688
 689         if (is_send) {
 690                 wq = &(*cur_qp)->sq;
 691                 if (!(*cur_qp)->sq_signal_bits) {
 692                         wqe_ctr = be16_to_cpu(cqe->wqe_index);
 693                         wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
 694                 }
 695                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
 696                 ++wq->tail;
 697         } else if ((*cur_qp)->ibqp.srq) {
 698                 srq = to_msrq((*cur_qp)->ibqp.srq);
 699                 wqe_ctr = be16_to_cpu(cqe->wqe_index);
 700                 wc->wr_id = srq->wrid[wqe_ctr];
 701                 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
 702         } else if (msrq) {
 703                 srq = to_mibsrq(msrq);
 704                 wqe_ctr = be16_to_cpu(cqe->wqe_index);
 705                 wc->wr_id = srq->wrid[wqe_ctr];
 706                 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
 707         } else {
 708                 wq        = &(*cur_qp)->rq;
 709                 tail      = wq->tail & (wq->wqe_cnt - 1);
 710                 wc->wr_id = wq->wrid[tail];
 711                 ++wq->tail;
 712         }
 713
 714         if (unlikely(is_error)) {
 715                 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
 716                 return 0;
 717         }
 718
 719         wc->status = IB_WC_SUCCESS;
 720
 721         if (is_send) {
 722                 wc->wc_flags = 0;
 723                 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
 724                 case MLX4_OPCODE_RDMA_WRITE_IMM:
 725                         wc->wc_flags |= IB_WC_WITH_IMM;
 726                 case MLX4_OPCODE_RDMA_WRITE:
 727                         wc->opcode    = IB_WC_RDMA_WRITE;
 728                         break;
 729                 case MLX4_OPCODE_SEND_IMM:
 730                         wc->wc_flags |= IB_WC_WITH_IMM;
 731                 case MLX4_OPCODE_SEND:
 732                 case MLX4_OPCODE_SEND_INVAL:
 733                         wc->opcode    = IB_WC_SEND;
 734                         break;
 735                 case MLX4_OPCODE_RDMA_READ:
 736                         wc->opcode    = IB_WC_RDMA_READ;
 737                         wc->byte_len  = be32_to_cpu(cqe->byte_cnt);
 738                         break;
 739                 case MLX4_OPCODE_ATOMIC_CS:
 740                         wc->opcode    = IB_WC_COMP_SWAP;
 741                         wc->byte_len  = 8;
 742                         break;
 743                 case MLX4_OPCODE_ATOMIC_FA:
 744                         wc->opcode    = IB_WC_FETCH_ADD;
 745                         wc->byte_len  = 8;
 746                         break;
 747                 case MLX4_OPCODE_MASKED_ATOMIC_CS:
 748                         wc->opcode    = IB_WC_MASKED_COMP_SWAP;
 749                         wc->byte_len  = 8;
 750                         break;
 751                 case MLX4_OPCODE_MASKED_ATOMIC_FA:
 752                         wc->opcode    = IB_WC_MASKED_FETCH_ADD;
 753                         wc->byte_len  = 8;
 754                         break;
 755                 case MLX4_OPCODE_BIND_MW:
 756                         wc->opcode    = IB_WC_BIND_MW;
 757                         break;
 758                 case MLX4_OPCODE_LSO:
 759                         wc->opcode    = IB_WC_LSO;
 760                         break;
 761                 case MLX4_OPCODE_FMR:
 762                         wc->opcode    = IB_WC_FAST_REG_MR;
 763                         break;
 764                 case MLX4_OPCODE_LOCAL_INVAL:
 765                         wc->opcode    = IB_WC_LOCAL_INV;
 766                         break;
 767                 }
 768         } else {
 769                 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
 770
 771                 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
 772                 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
 773                         wc->opcode      = IB_WC_RECV_RDMA_WITH_IMM;
 774                         wc->wc_flags    = IB_WC_WITH_IMM;
 775                         wc->ex.imm_data = cqe->immed_rss_invalid;
 776                         break;
 777                 case MLX4_RECV_OPCODE_SEND_INVAL:
 778                         wc->opcode      = IB_WC_RECV;
 779                         wc->wc_flags    = IB_WC_WITH_INVALIDATE;
 780                         wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
 781                         break;
 782                 case MLX4_RECV_OPCODE_SEND:
 783                         wc->opcode   = IB_WC_RECV;
 784                         wc->wc_flags = 0;
 785                         break;
 786                 case MLX4_RECV_OPCODE_SEND_IMM:
 787                         wc->opcode      = IB_WC_RECV;
 788                         wc->wc_flags    = IB_WC_WITH_IMM;
 789                         wc->ex.imm_data = cqe->immed_rss_invalid;
 790                         break;
 791                 }
 792
 793                 is_eth = (rdma_port_get_link_layer(wc->qp->device,
 794                                                   (*cur_qp)->port) ==
 795                           IB_LINK_LAYER_ETHERNET);
 796                 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
 797                         if ((*cur_qp)->mlx4_ib_qp_type &
 798                             (MLX4_IB_QPT_PROXY_SMI_OWNER |
 799                              MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
 800                                 return use_tunnel_data(*cur_qp, cq, wc, tail,
 801                                                        cqe, is_eth);
 802                 }
 803
 804                 wc->slid           = be16_to_cpu(cqe->rlid);
 805                 g_mlpath_rqpn      = be32_to_cpu(cqe->g_mlpath_rqpn);
 806                 wc->src_qp         = g_mlpath_rqpn & 0xffffff;
 807                 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
 808                 wc->wc_flags      |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
 809                 wc->pkey_index     = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
 810                 wc->wc_flags      |= mlx4_ib_ipoib_csum_ok(cqe->status,
 811                                         cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
 812                 if (is_eth) {
 813                         wc->sl  = be16_to_cpu(cqe->sl_vid) >> 13;
 814                         if (be32_to_cpu(cqe->vlan_my_qpn) &
 815                                         MLX4_CQE_VLAN_PRESENT_MASK) {
 816                                 wc->vlan_id = be16_to_cpu(cqe->sl_vid) &
 817                                         MLX4_CQE_VID_MASK;
 818                         } else {
 819                                 wc->vlan_id = 0xffff;
 820                         }
 821                         memcpy(wc->smac, cqe->smac, ETH_ALEN);
 822                         wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
 823                 } else {
 824                         wc->sl  = be16_to_cpu(cqe->sl_vid) >> 12;
 825                         wc->vlan_id = 0xffff;
 826                 }
 827         }
 828
 829         return 0;
 830 }
 831
 832 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
 833 {
 834         struct mlx4_ib_cq *cq = to_mcq(ibcq);
 835         struct mlx4_ib_qp *cur_qp = NULL;
 836         unsigned long flags;
 837         int npolled;
 838         int err = 0;
 839
 840         spin_lock_irqsave(&cq->lock, flags);
 841
 842         for (npolled = 0; npolled < num_entries; ++npolled) {
 843                 err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
 844                 if (err)
 845                         break;
 846         }
 847
 848         mlx4_cq_set_ci(&cq->mcq);
 849
 850         spin_unlock_irqrestore(&cq->lock, flags);
 851
 852         if (err == 0 || err == -EAGAIN)
 853                 return npolled;
 854         else
 855                 return err;
 856 }
 857
 858 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
 859 {
 860         mlx4_cq_arm(&to_mcq(ibcq)->mcq,
 861                     (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
 862                     MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
 863                     to_mdev(ibcq->device)->uar_map,
 864                     MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
 865
 866         return 0;
 867 }
 868
 869 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
 870 {
 871         u32 prod_index;
 872         int nfreed = 0;
 873         struct mlx4_cqe *cqe, *dest;
 874         u8 owner_bit;
 875         int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0;
 876
 877         /*
 878          * First we need to find the current producer index, so we
 879          * know where to start cleaning from.  It doesn't matter if HW
 880          * adds new entries after this loop -- the QP we're worried
 881          * about is already in RESET, so the new entries won't come
 882          * from our QP and therefore don't need to be checked.
 883          */
 884         for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
 885                 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
 886                         break;
 887
 888         /*
 889          * Now sweep backwards through the CQ, removing CQ entries
 890          * that match our QP by copying older entries on top of them.
 891          */
 892         while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
 893                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
 894                 cqe += cqe_inc;
 895
 896                 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
 897                         if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
 898                                 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
 899                         ++nfreed;
 900                 } else if (nfreed) {
 901                         dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
 902                         dest += cqe_inc;
 903
 904                         owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
 905                         memcpy(dest, cqe, sizeof *cqe);
 906                         dest->owner_sr_opcode = owner_bit |
 907                                 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
 908                 }
 909         }
 910
 911         if (nfreed) {
 912                 cq->mcq.cons_index += nfreed;
 913                 /*
 914                  * Make sure update of buffer contents is done before
 915                  * updating consumer index.
 916                  */
 917                 wmb();
 918                 mlx4_cq_set_ci(&cq->mcq);
 919         }
 920 }
 921
 922 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
 923 {
 924         spin_lock_irq(&cq->lock);
 925         __mlx4_ib_cq_clean(cq, qpn, srq);
 926         spin_unlock_irq(&cq->lock);
 927 }