2 * This file is part of STM32 ADC driver
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE.
16 * See the GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/iio/iio.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/timer/stm32-lptim-trigger.h>
29 #include <linux/iio/timer/stm32-timer-trigger.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/interrupt.h>
35 #include <linux/iopoll.h>
36 #include <linux/module.h>
37 #include <linux/platform_device.h>
39 #include <linux/of_device.h>
41 #include "stm32-adc-core.h"
43 /* STM32F4 - Registers for each ADC instance */
44 #define STM32F4_ADC_SR 0x00
45 #define STM32F4_ADC_CR1 0x04
46 #define STM32F4_ADC_CR2 0x08
47 #define STM32F4_ADC_SMPR1 0x0C
48 #define STM32F4_ADC_SMPR2 0x10
49 #define STM32F4_ADC_HTR 0x24
50 #define STM32F4_ADC_LTR 0x28
51 #define STM32F4_ADC_SQR1 0x2C
52 #define STM32F4_ADC_SQR2 0x30
53 #define STM32F4_ADC_SQR3 0x34
54 #define STM32F4_ADC_JSQR 0x38
55 #define STM32F4_ADC_JDR1 0x3C
56 #define STM32F4_ADC_JDR2 0x40
57 #define STM32F4_ADC_JDR3 0x44
58 #define STM32F4_ADC_JDR4 0x48
59 #define STM32F4_ADC_DR 0x4C
61 /* STM32F4_ADC_SR - bit fields */
62 #define STM32F4_STRT BIT(4)
63 #define STM32F4_EOC BIT(1)
65 /* STM32F4_ADC_CR1 - bit fields */
66 #define STM32F4_RES_SHIFT 24
67 #define STM32F4_RES_MASK GENMASK(25, 24)
68 #define STM32F4_SCAN BIT(8)
69 #define STM32F4_EOCIE BIT(5)
71 /* STM32F4_ADC_CR2 - bit fields */
72 #define STM32F4_SWSTART BIT(30)
73 #define STM32F4_EXTEN_SHIFT 28
74 #define STM32F4_EXTEN_MASK GENMASK(29, 28)
75 #define STM32F4_EXTSEL_SHIFT 24
76 #define STM32F4_EXTSEL_MASK GENMASK(27, 24)
77 #define STM32F4_EOCS BIT(10)
78 #define STM32F4_DDS BIT(9)
79 #define STM32F4_DMA BIT(8)
80 #define STM32F4_ADON BIT(0)
82 /* STM32H7 - Registers for each ADC instance */
83 #define STM32H7_ADC_ISR 0x00
84 #define STM32H7_ADC_IER 0x04
85 #define STM32H7_ADC_CR 0x08
86 #define STM32H7_ADC_CFGR 0x0C
87 #define STM32H7_ADC_SMPR1 0x14
88 #define STM32H7_ADC_SMPR2 0x18
89 #define STM32H7_ADC_PCSEL 0x1C
90 #define STM32H7_ADC_SQR1 0x30
91 #define STM32H7_ADC_SQR2 0x34
92 #define STM32H7_ADC_SQR3 0x38
93 #define STM32H7_ADC_SQR4 0x3C
94 #define STM32H7_ADC_DR 0x40
95 #define STM32H7_ADC_CALFACT 0xC4
96 #define STM32H7_ADC_CALFACT2 0xC8
98 /* STM32H7_ADC_ISR - bit fields */
99 #define STM32H7_EOC BIT(2)
100 #define STM32H7_ADRDY BIT(0)
102 /* STM32H7_ADC_IER - bit fields */
103 #define STM32H7_EOCIE STM32H7_EOC
105 /* STM32H7_ADC_CR - bit fields */
106 #define STM32H7_ADCAL BIT(31)
107 #define STM32H7_ADCALDIF BIT(30)
108 #define STM32H7_DEEPPWD BIT(29)
109 #define STM32H7_ADVREGEN BIT(28)
110 #define STM32H7_LINCALRDYW6 BIT(27)
111 #define STM32H7_LINCALRDYW5 BIT(26)
112 #define STM32H7_LINCALRDYW4 BIT(25)
113 #define STM32H7_LINCALRDYW3 BIT(24)
114 #define STM32H7_LINCALRDYW2 BIT(23)
115 #define STM32H7_LINCALRDYW1 BIT(22)
116 #define STM32H7_ADCALLIN BIT(16)
117 #define STM32H7_BOOST BIT(8)
118 #define STM32H7_ADSTP BIT(4)
119 #define STM32H7_ADSTART BIT(2)
120 #define STM32H7_ADDIS BIT(1)
121 #define STM32H7_ADEN BIT(0)
123 /* STM32H7_ADC_CFGR bit fields */
124 #define STM32H7_EXTEN_SHIFT 10
125 #define STM32H7_EXTEN_MASK GENMASK(11, 10)
126 #define STM32H7_EXTSEL_SHIFT 5
127 #define STM32H7_EXTSEL_MASK GENMASK(9, 5)
128 #define STM32H7_RES_SHIFT 2
129 #define STM32H7_RES_MASK GENMASK(4, 2)
130 #define STM32H7_DMNGT_SHIFT 0
131 #define STM32H7_DMNGT_MASK GENMASK(1, 0)
133 enum stm32h7_adc_dmngt {
134 STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */
135 STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */
136 STM32H7_DMNGT_DFSDM, /* DFSDM mode */
137 STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */
140 /* STM32H7_ADC_CALFACT - bit fields */
141 #define STM32H7_CALFACT_D_SHIFT 16
142 #define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
143 #define STM32H7_CALFACT_S_SHIFT 0
144 #define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
146 /* STM32H7_ADC_CALFACT2 - bit fields */
147 #define STM32H7_LINCALFACT_SHIFT 0
148 #define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
150 /* Number of linear calibration shadow registers / LINCALRDYW control bits */
151 #define STM32H7_LINCALFACT_NUM 6
153 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
154 #define STM32H7_BOOST_CLKRATE 20000000UL
156 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
157 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */
158 #define STM32_ADC_TIMEOUT_US 100000
159 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
161 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE
163 /* External trigger enable */
164 enum stm32_adc_exten {
166 STM32_EXTEN_HWTRIG_RISING_EDGE,
167 STM32_EXTEN_HWTRIG_FALLING_EDGE,
168 STM32_EXTEN_HWTRIG_BOTH_EDGES,
171 /* extsel - trigger mux selection value */
172 enum stm32_adc_extsel {
197 * struct stm32_adc_trig_info - ADC trigger info
198 * @name: name of the trigger, corresponding to its source
199 * @extsel: trigger selection
201 struct stm32_adc_trig_info {
203 enum stm32_adc_extsel extsel;
207 * struct stm32_adc_calib - optional adc calibration data
208 * @calfact_s: Calibration offset for single ended channels
209 * @calfact_d: Calibration offset in differential
210 * @lincalfact: Linearity calibration factor
212 struct stm32_adc_calib {
215 u32 lincalfact[STM32H7_LINCALFACT_NUM];
219 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
220 * @reg: register offset
221 * @mask: bitfield mask
224 struct stm32_adc_regs {
231 * stm32_adc_regspec - stm32 registers definition, compatible dependent data
232 * @dr: data register offset
233 * @ier_eoc: interrupt enable register & eocie bitfield
234 * @isr_eoc: interrupt status register & eoc bitfield
235 * @sqr: reference to sequence registers array
236 * @exten: trigger control register & bitfield
237 * @extsel: trigger selection register & bitfield
238 * @res: resolution selection register & bitfield
239 * @smpr: smpr1 & smpr2 registers offset array
240 * @smp_bits: smpr1 & smpr2 index and bitfields
242 struct stm32_adc_regspec {
244 const struct stm32_adc_regs ier_eoc;
245 const struct stm32_adc_regs isr_eoc;
246 const struct stm32_adc_regs *sqr;
247 const struct stm32_adc_regs exten;
248 const struct stm32_adc_regs extsel;
249 const struct stm32_adc_regs res;
251 const struct stm32_adc_regs *smp_bits;
257 * stm32_adc_cfg - stm32 compatible configuration data
258 * @regs: registers descriptions
259 * @adc_info: per instance input channels definitions
260 * @trigs: external trigger sources
261 * @clk_required: clock is required
262 * @selfcalib: optional routine for self-calibration
263 * @prepare: optional prepare routine (power-up, enable)
264 * @start_conv: routine to start conversions
265 * @stop_conv: routine to stop conversions
266 * @unprepare: optional unprepare routine (disable, power-down)
267 * @smp_cycles: programmable sampling time (ADC clock cycles)
269 struct stm32_adc_cfg {
270 const struct stm32_adc_regspec *regs;
271 const struct stm32_adc_info *adc_info;
272 struct stm32_adc_trig_info *trigs;
274 int (*selfcalib)(struct stm32_adc *);
275 int (*prepare)(struct stm32_adc *);
276 void (*start_conv)(struct stm32_adc *, bool dma);
277 void (*stop_conv)(struct stm32_adc *);
278 void (*unprepare)(struct stm32_adc *);
279 const unsigned int *smp_cycles;
283 * struct stm32_adc - private data of each ADC IIO instance
284 * @common: reference to ADC block common data
285 * @offset: ADC instance register offset in ADC block
286 * @cfg: compatible configuration data
287 * @completion: end of single conversion completion
288 * @buffer: data buffer
289 * @clk: clock for this adc instance
290 * @irq: interrupt for this adc instance
292 * @bufi: data buffer index
293 * @num_conv: expected number of scan conversions
294 * @res: data resolution (e.g. RES bitfield value)
295 * @trigger_polarity: external trigger polarity (e.g. exten)
296 * @dma_chan: dma channel
297 * @rx_buf: dma rx buffer cpu address
298 * @rx_dma_buf: dma rx buffer bus address
299 * @rx_buf_sz: dma rx buffer size
300 * @pcsel bitmask to preselect channels on some devices
301 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2)
302 * @cal: optional calibration data on some devices
305 struct stm32_adc_common *common;
307 const struct stm32_adc_cfg *cfg;
308 struct completion completion;
309 u16 buffer[STM32_ADC_MAX_SQ];
312 spinlock_t lock; /* interrupt lock */
314 unsigned int num_conv;
316 u32 trigger_polarity;
317 struct dma_chan *dma_chan;
319 dma_addr_t rx_dma_buf;
320 unsigned int rx_buf_sz;
323 struct stm32_adc_calib cal;
327 * struct stm32_adc_chan_spec - specification of stm32 adc channel
328 * @type: IIO channel type
329 * @channel: channel number (single ended)
330 * @name: channel name (single ended)
332 struct stm32_adc_chan_spec {
333 enum iio_chan_type type;
339 * struct stm32_adc_info - stm32 ADC, per instance config data
340 * @channels: Reference to stm32 channels spec
341 * @max_channels: Number of channels
342 * @resolutions: available resolutions
343 * @num_res: number of available resolutions
345 struct stm32_adc_info {
346 const struct stm32_adc_chan_spec *channels;
348 const unsigned int *resolutions;
349 const unsigned int num_res;
353 * Input definitions common for all instances:
354 * stm32f4 can have up to 16 channels
355 * stm32h7 can have up to 20 channels
357 static const struct stm32_adc_chan_spec stm32_adc_channels[] = {
358 { IIO_VOLTAGE, 0, "in0" },
359 { IIO_VOLTAGE, 1, "in1" },
360 { IIO_VOLTAGE, 2, "in2" },
361 { IIO_VOLTAGE, 3, "in3" },
362 { IIO_VOLTAGE, 4, "in4" },
363 { IIO_VOLTAGE, 5, "in5" },
364 { IIO_VOLTAGE, 6, "in6" },
365 { IIO_VOLTAGE, 7, "in7" },
366 { IIO_VOLTAGE, 8, "in8" },
367 { IIO_VOLTAGE, 9, "in9" },
368 { IIO_VOLTAGE, 10, "in10" },
369 { IIO_VOLTAGE, 11, "in11" },
370 { IIO_VOLTAGE, 12, "in12" },
371 { IIO_VOLTAGE, 13, "in13" },
372 { IIO_VOLTAGE, 14, "in14" },
373 { IIO_VOLTAGE, 15, "in15" },
374 { IIO_VOLTAGE, 16, "in16" },
375 { IIO_VOLTAGE, 17, "in17" },
376 { IIO_VOLTAGE, 18, "in18" },
377 { IIO_VOLTAGE, 19, "in19" },
380 static const unsigned int stm32f4_adc_resolutions[] = {
381 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
385 static const struct stm32_adc_info stm32f4_adc_info = {
386 .channels = stm32_adc_channels,
388 .resolutions = stm32f4_adc_resolutions,
389 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
392 static const unsigned int stm32h7_adc_resolutions[] = {
393 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
397 static const struct stm32_adc_info stm32h7_adc_info = {
398 .channels = stm32_adc_channels,
400 .resolutions = stm32h7_adc_resolutions,
401 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
405 * stm32f4_sq - describe regular sequence registers
406 * - L: sequence len (register & bit field)
407 * - SQ1..SQ16: sequence entries (register & bit field)
409 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = {
410 /* L: len bit field description to be kept as first element */
411 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
412 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
413 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
414 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
415 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
416 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
417 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
418 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
419 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
420 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
421 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
422 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
423 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
424 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
425 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
426 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
427 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
428 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
431 /* STM32F4 external trigger sources for all instances */
432 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
433 { TIM1_CH1, STM32_EXT0 },
434 { TIM1_CH2, STM32_EXT1 },
435 { TIM1_CH3, STM32_EXT2 },
436 { TIM2_CH2, STM32_EXT3 },
437 { TIM2_CH3, STM32_EXT4 },
438 { TIM2_CH4, STM32_EXT5 },
439 { TIM2_TRGO, STM32_EXT6 },
440 { TIM3_CH1, STM32_EXT7 },
441 { TIM3_TRGO, STM32_EXT8 },
442 { TIM4_CH4, STM32_EXT9 },
443 { TIM5_CH1, STM32_EXT10 },
444 { TIM5_CH2, STM32_EXT11 },
445 { TIM5_CH3, STM32_EXT12 },
446 { TIM8_CH1, STM32_EXT13 },
447 { TIM8_TRGO, STM32_EXT14 },
452 * stm32f4_smp_bits[] - describe sampling time register index & bit fields
453 * Sorted so it can be indexed by channel number.
455 static const struct stm32_adc_regs stm32f4_smp_bits[] = {
456 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
457 { 1, GENMASK(2, 0), 0 },
458 { 1, GENMASK(5, 3), 3 },
459 { 1, GENMASK(8, 6), 6 },
460 { 1, GENMASK(11, 9), 9 },
461 { 1, GENMASK(14, 12), 12 },
462 { 1, GENMASK(17, 15), 15 },
463 { 1, GENMASK(20, 18), 18 },
464 { 1, GENMASK(23, 21), 21 },
465 { 1, GENMASK(26, 24), 24 },
466 { 1, GENMASK(29, 27), 27 },
467 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
468 { 0, GENMASK(2, 0), 0 },
469 { 0, GENMASK(5, 3), 3 },
470 { 0, GENMASK(8, 6), 6 },
471 { 0, GENMASK(11, 9), 9 },
472 { 0, GENMASK(14, 12), 12 },
473 { 0, GENMASK(17, 15), 15 },
474 { 0, GENMASK(20, 18), 18 },
475 { 0, GENMASK(23, 21), 21 },
476 { 0, GENMASK(26, 24), 24 },
479 /* STM32F4 programmable sampling time (ADC clock cycles) */
480 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
481 3, 15, 28, 56, 84, 112, 144, 480,
484 static const struct stm32_adc_regspec stm32f4_adc_regspec = {
485 .dr = STM32F4_ADC_DR,
486 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
487 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
489 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
490 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
491 STM32F4_EXTSEL_SHIFT },
492 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
493 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
494 .smp_bits = stm32f4_smp_bits,
497 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
498 /* L: len bit field description to be kept as first element */
499 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
500 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
501 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
502 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
503 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
504 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
505 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
506 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
507 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
508 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
509 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
510 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
511 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
512 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
513 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
514 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
515 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
516 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
519 /* STM32H7 external trigger sources for all instances */
520 static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
521 { TIM1_CH1, STM32_EXT0 },
522 { TIM1_CH2, STM32_EXT1 },
523 { TIM1_CH3, STM32_EXT2 },
524 { TIM2_CH2, STM32_EXT3 },
525 { TIM3_TRGO, STM32_EXT4 },
526 { TIM4_CH4, STM32_EXT5 },
527 { TIM8_TRGO, STM32_EXT7 },
528 { TIM8_TRGO2, STM32_EXT8 },
529 { TIM1_TRGO, STM32_EXT9 },
530 { TIM1_TRGO2, STM32_EXT10 },
531 { TIM2_TRGO, STM32_EXT11 },
532 { TIM4_TRGO, STM32_EXT12 },
533 { TIM6_TRGO, STM32_EXT13 },
534 { TIM3_CH4, STM32_EXT15 },
535 { LPTIM1_OUT, STM32_EXT18 },
536 { LPTIM2_OUT, STM32_EXT19 },
537 { LPTIM3_OUT, STM32_EXT20 },
542 * stm32h7_smp_bits - describe sampling time register index & bit fields
543 * Sorted so it can be indexed by channel number.
545 static const struct stm32_adc_regs stm32h7_smp_bits[] = {
546 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
547 { 0, GENMASK(2, 0), 0 },
548 { 0, GENMASK(5, 3), 3 },
549 { 0, GENMASK(8, 6), 6 },
550 { 0, GENMASK(11, 9), 9 },
551 { 0, GENMASK(14, 12), 12 },
552 { 0, GENMASK(17, 15), 15 },
553 { 0, GENMASK(20, 18), 18 },
554 { 0, GENMASK(23, 21), 21 },
555 { 0, GENMASK(26, 24), 24 },
556 { 0, GENMASK(29, 27), 27 },
557 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
558 { 1, GENMASK(2, 0), 0 },
559 { 1, GENMASK(5, 3), 3 },
560 { 1, GENMASK(8, 6), 6 },
561 { 1, GENMASK(11, 9), 9 },
562 { 1, GENMASK(14, 12), 12 },
563 { 1, GENMASK(17, 15), 15 },
564 { 1, GENMASK(20, 18), 18 },
565 { 1, GENMASK(23, 21), 21 },
566 { 1, GENMASK(26, 24), 24 },
567 { 1, GENMASK(29, 27), 27 },
570 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
571 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
572 1, 2, 8, 16, 32, 64, 387, 810,
575 static const struct stm32_adc_regspec stm32h7_adc_regspec = {
576 .dr = STM32H7_ADC_DR,
577 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
578 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
580 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
581 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
582 STM32H7_EXTSEL_SHIFT },
583 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
584 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
585 .smp_bits = stm32h7_smp_bits,
589 * STM32 ADC registers access routines
590 * @adc: stm32 adc instance
591 * @reg: reg offset in adc instance
593 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
594 * for adc1, adc2 and adc3.
596 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
598 return readl_relaxed(adc->common->base + adc->offset + reg);
601 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
603 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
604 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
605 cond, sleep_us, timeout_us)
607 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
609 return readw_relaxed(adc->common->base + adc->offset + reg);
612 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
614 writel_relaxed(val, adc->common->base + adc->offset + reg);
617 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
621 spin_lock_irqsave(&adc->lock, flags);
622 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
623 spin_unlock_irqrestore(&adc->lock, flags);
626 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
630 spin_lock_irqsave(&adc->lock, flags);
631 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
632 spin_unlock_irqrestore(&adc->lock, flags);
636 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
637 * @adc: stm32 adc instance
639 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
641 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
642 adc->cfg->regs->ier_eoc.mask);
646 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
647 * @adc: stm32 adc instance
649 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
651 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
652 adc->cfg->regs->ier_eoc.mask);
655 static void stm32_adc_set_res(struct stm32_adc *adc)
657 const struct stm32_adc_regs *res = &adc->cfg->regs->res;
660 val = stm32_adc_readl(adc, res->reg);
661 val = (val & ~res->mask) | (adc->res << res->shift);
662 stm32_adc_writel(adc, res->reg, val);
666 * stm32f4_adc_start_conv() - Start conversions for regular channels.
667 * @adc: stm32 adc instance
668 * @dma: use dma to transfer conversion result
670 * Start conversions for regular channels.
671 * Also take care of normal or DMA mode. Circular DMA may be used for regular
672 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
673 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
675 static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma)
677 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
680 stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
681 STM32F4_DMA | STM32F4_DDS);
683 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
685 /* Wait for Power-up time (tSTAB from datasheet) */
688 /* Software start ? (e.g. trigger detection disabled ?) */
689 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
690 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
693 static void stm32f4_adc_stop_conv(struct stm32_adc *adc)
695 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
696 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
698 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
699 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
700 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
703 static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma)
705 enum stm32h7_adc_dmngt dmngt;
710 dmngt = STM32H7_DMNGT_DMA_CIRC;
712 dmngt = STM32H7_DMNGT_DR_ONLY;
714 spin_lock_irqsave(&adc->lock, flags);
715 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
716 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT);
717 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
718 spin_unlock_irqrestore(&adc->lock, flags);
720 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
723 static void stm32h7_adc_stop_conv(struct stm32_adc *adc)
725 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
729 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
731 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
732 !(val & (STM32H7_ADSTART)),
733 100, STM32_ADC_TIMEOUT_US);
735 dev_warn(&indio_dev->dev, "stop failed\n");
737 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
740 static void stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
742 /* Exit deep power down, then enable ADC voltage regulator */
743 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
744 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
746 if (adc->common->rate > STM32H7_BOOST_CLKRATE)
747 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
749 /* Wait for startup time */
750 usleep_range(10, 20);
753 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
755 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
757 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
758 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
761 static int stm32h7_adc_enable(struct stm32_adc *adc)
763 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
767 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
769 /* Poll for ADRDY to be set (after adc startup time) */
770 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
772 100, STM32_ADC_TIMEOUT_US);
774 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
775 dev_err(&indio_dev->dev, "Failed to enable ADC\n");
777 /* Clear ADRDY by writing one */
778 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
784 static void stm32h7_adc_disable(struct stm32_adc *adc)
786 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
790 /* Disable ADC and wait until it's effectively disabled */
791 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
792 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
793 !(val & STM32H7_ADEN), 100,
794 STM32_ADC_TIMEOUT_US);
796 dev_warn(&indio_dev->dev, "Failed to disable\n");
800 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
801 * @adc: stm32 adc instance
803 static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc)
805 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
807 u32 lincalrdyw_mask, val;
809 /* Enable adc so LINCALRDYW1..6 bits are writable */
810 ret = stm32h7_adc_enable(adc);
814 /* Read linearity calibration */
815 lincalrdyw_mask = STM32H7_LINCALRDYW6;
816 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
817 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
818 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
820 /* Poll: wait calib data to be ready in CALFACT2 register */
821 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
822 !(val & lincalrdyw_mask),
823 100, STM32_ADC_TIMEOUT_US);
825 dev_err(&indio_dev->dev, "Failed to read calfact\n");
829 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
830 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
831 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
833 lincalrdyw_mask >>= 1;
836 /* Read offset calibration */
837 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
838 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
839 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
840 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
841 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
844 stm32h7_adc_disable(adc);
850 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
851 * @adc: stm32 adc instance
852 * Note: ADC must be enabled, with no on-going conversions.
854 static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc)
856 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
858 u32 lincalrdyw_mask, val;
860 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
861 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
862 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
864 lincalrdyw_mask = STM32H7_LINCALRDYW6;
865 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
867 * Write saved calibration data to shadow registers:
868 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
869 * data write. Then poll to wait for complete transfer.
871 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
872 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
873 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
874 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
875 val & lincalrdyw_mask,
876 100, STM32_ADC_TIMEOUT_US);
878 dev_err(&indio_dev->dev, "Failed to write calfact\n");
883 * Read back calibration data, has two effects:
884 * - It ensures bits LINCALRDYW[6..1] are kept cleared
885 * for next time calibration needs to be restored.
886 * - BTW, bit clear triggers a read, then check data has been
889 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
890 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
891 !(val & lincalrdyw_mask),
892 100, STM32_ADC_TIMEOUT_US);
894 dev_err(&indio_dev->dev, "Failed to read calfact\n");
897 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
898 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
899 dev_err(&indio_dev->dev, "calfact not consistent\n");
903 lincalrdyw_mask >>= 1;
910 * Fixed timeout value for ADC calibration.
912 * - low clock frequency
913 * - maximum prescalers
914 * Calibration requires:
915 * - 131,072 ADC clock cycle for the linear calibration
916 * - 20 ADC clock cycle for the offset calibration
918 * Set to 100ms for now
920 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000
923 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down)
924 * @adc: stm32 adc instance
925 * Exit from power down, calibrate ADC, then return to power down.
927 static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
929 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
933 stm32h7_adc_exit_pwr_down(adc);
936 * Select calibration mode:
937 * - Offset calibration for single ended inputs
938 * - No linearity calibration (do it later, before reading it)
940 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
941 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
943 /* Start calibration, then wait for completion */
944 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
945 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
946 !(val & STM32H7_ADCAL), 100,
947 STM32H7_ADC_CALIB_TIMEOUT_US);
949 dev_err(&indio_dev->dev, "calibration failed\n");
954 * Select calibration mode, then start calibration:
955 * - Offset calibration for differential input
956 * - Linearity calibration (needs to be done only once for single/diff)
957 * will run simultaneously with offset calibration.
959 stm32_adc_set_bits(adc, STM32H7_ADC_CR,
960 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
961 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
962 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
963 !(val & STM32H7_ADCAL), 100,
964 STM32H7_ADC_CALIB_TIMEOUT_US);
966 dev_err(&indio_dev->dev, "calibration failed\n");
970 stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
971 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
973 /* Read calibration result for future reference */
974 ret = stm32h7_adc_read_selfcalib(adc);
977 stm32h7_adc_enter_pwr_down(adc);
983 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
984 * @adc: stm32 adc instance
985 * Leave power down mode.
987 * Restore calibration data.
988 * Pre-select channels that may be used in PCSEL (required by input MUX / IO).
990 static int stm32h7_adc_prepare(struct stm32_adc *adc)
994 stm32h7_adc_exit_pwr_down(adc);
996 ret = stm32h7_adc_enable(adc);
1000 ret = stm32h7_adc_restore_selfcalib(adc);
1004 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
1009 stm32h7_adc_disable(adc);
1011 stm32h7_adc_enter_pwr_down(adc);
1016 static void stm32h7_adc_unprepare(struct stm32_adc *adc)
1018 stm32h7_adc_disable(adc);
1019 stm32h7_adc_enter_pwr_down(adc);
1023 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
1024 * @indio_dev: IIO device
1025 * @scan_mask: channels to be converted
1027 * Conversion sequence :
1028 * Apply sampling time settings for all channels.
1029 * Configure ADC scan sequence based on selected channels in scan_mask.
1030 * Add channels to SQR registers, from scan_mask LSB to MSB, then
1031 * program sequence len.
1033 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
1034 const unsigned long *scan_mask)
1036 struct stm32_adc *adc = iio_priv(indio_dev);
1037 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
1038 const struct iio_chan_spec *chan;
1042 /* Apply sampling time settings */
1043 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
1044 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
1046 for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
1047 chan = indio_dev->channels + bit;
1049 * Assign one channel per SQ entry in regular
1050 * sequence, starting with SQ1.
1053 if (i > STM32_ADC_MAX_SQ)
1056 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
1057 __func__, chan->channel, i);
1059 val = stm32_adc_readl(adc, sqr[i].reg);
1060 val &= ~sqr[i].mask;
1061 val |= chan->channel << sqr[i].shift;
1062 stm32_adc_writel(adc, sqr[i].reg, val);
1069 val = stm32_adc_readl(adc, sqr[0].reg);
1070 val &= ~sqr[0].mask;
1071 val |= ((i - 1) << sqr[0].shift);
1072 stm32_adc_writel(adc, sqr[0].reg, val);
1078 * stm32_adc_get_trig_extsel() - Get external trigger selection
1081 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
1083 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,
1084 struct iio_trigger *trig)
1086 struct stm32_adc *adc = iio_priv(indio_dev);
1089 /* lookup triggers registered by stm32 timer trigger driver */
1090 for (i = 0; adc->cfg->trigs[i].name; i++) {
1092 * Checking both stm32 timer trigger type and trig name
1093 * should be safe against arbitrary trigger names.
1095 if ((is_stm32_timer_trigger(trig) ||
1096 is_stm32_lptim_trigger(trig)) &&
1097 !strcmp(adc->cfg->trigs[i].name, trig->name)) {
1098 return adc->cfg->trigs[i].extsel;
1106 * stm32_adc_set_trig() - Set a regular trigger
1107 * @indio_dev: IIO device
1108 * @trig: IIO trigger
1110 * Set trigger source/polarity (e.g. SW, or HW with polarity) :
1111 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
1112 * - if HW trigger enabled, set source & polarity
1114 static int stm32_adc_set_trig(struct iio_dev *indio_dev,
1115 struct iio_trigger *trig)
1117 struct stm32_adc *adc = iio_priv(indio_dev);
1118 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
1119 unsigned long flags;
1123 ret = stm32_adc_get_trig_extsel(indio_dev, trig);
1127 /* set trigger source and polarity (default to rising edge) */
1129 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
1132 spin_lock_irqsave(&adc->lock, flags);
1133 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
1134 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
1135 val |= exten << adc->cfg->regs->exten.shift;
1136 val |= extsel << adc->cfg->regs->extsel.shift;
1137 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
1138 spin_unlock_irqrestore(&adc->lock, flags);
1143 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
1144 const struct iio_chan_spec *chan,
1147 struct stm32_adc *adc = iio_priv(indio_dev);
1149 adc->trigger_polarity = type;
1154 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
1155 const struct iio_chan_spec *chan)
1157 struct stm32_adc *adc = iio_priv(indio_dev);
1159 return adc->trigger_polarity;
1162 static const char * const stm32_trig_pol_items[] = {
1163 "rising-edge", "falling-edge", "both-edges",
1166 static const struct iio_enum stm32_adc_trig_pol = {
1167 .items = stm32_trig_pol_items,
1168 .num_items = ARRAY_SIZE(stm32_trig_pol_items),
1169 .get = stm32_adc_get_trig_pol,
1170 .set = stm32_adc_set_trig_pol,
1174 * stm32_adc_single_conv() - Performs a single conversion
1175 * @indio_dev: IIO device
1176 * @chan: IIO channel
1177 * @res: conversion result
1179 * The function performs a single conversion on a given channel:
1180 * - Apply sampling time settings
1181 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1183 * - Start conversion, then wait for interrupt completion.
1185 static int stm32_adc_single_conv(struct iio_dev *indio_dev,
1186 const struct iio_chan_spec *chan,
1189 struct stm32_adc *adc = iio_priv(indio_dev);
1190 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1195 reinit_completion(&adc->completion);
1199 if (adc->cfg->prepare) {
1200 ret = adc->cfg->prepare(adc);
1205 /* Apply sampling time settings */
1206 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1207 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1209 /* Program chan number in regular sequence (SQ1) */
1210 val = stm32_adc_readl(adc, regs->sqr[1].reg);
1211 val &= ~regs->sqr[1].mask;
1212 val |= chan->channel << regs->sqr[1].shift;
1213 stm32_adc_writel(adc, regs->sqr[1].reg, val);
1215 /* Set regular sequence len (0 for 1 conversion) */
1216 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
1218 /* Trigger detection disabled (conversion can be launched in SW) */
1219 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
1221 stm32_adc_conv_irq_enable(adc);
1223 adc->cfg->start_conv(adc, false);
1225 timeout = wait_for_completion_interruptible_timeout(
1226 &adc->completion, STM32_ADC_TIMEOUT);
1229 } else if (timeout < 0) {
1232 *res = adc->buffer[0];
1236 adc->cfg->stop_conv(adc);
1238 stm32_adc_conv_irq_disable(adc);
1240 if (adc->cfg->unprepare)
1241 adc->cfg->unprepare(adc);
1246 static int stm32_adc_read_raw(struct iio_dev *indio_dev,
1247 struct iio_chan_spec const *chan,
1248 int *val, int *val2, long mask)
1250 struct stm32_adc *adc = iio_priv(indio_dev);
1254 case IIO_CHAN_INFO_RAW:
1255 ret = iio_device_claim_direct_mode(indio_dev);
1258 if (chan->type == IIO_VOLTAGE)
1259 ret = stm32_adc_single_conv(indio_dev, chan, val);
1262 iio_device_release_direct_mode(indio_dev);
1265 case IIO_CHAN_INFO_SCALE:
1266 *val = adc->common->vref_mv;
1267 *val2 = chan->scan_type.realbits;
1268 return IIO_VAL_FRACTIONAL_LOG2;
1275 static irqreturn_t stm32_adc_isr(int irq, void *data)
1277 struct stm32_adc *adc = data;
1278 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1279 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1280 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1282 if (status & regs->isr_eoc.mask) {
1283 /* Reading DR also clears EOC status flag */
1284 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
1285 if (iio_buffer_enabled(indio_dev)) {
1287 if (adc->bufi >= adc->num_conv) {
1288 stm32_adc_conv_irq_disable(adc);
1289 iio_trigger_poll(indio_dev->trig);
1292 complete(&adc->completion);
1301 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1302 * @indio_dev: IIO device
1303 * @trig: new trigger
1305 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1306 * driver, -EINVAL otherwise.
1308 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
1309 struct iio_trigger *trig)
1311 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1314 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1316 struct stm32_adc *adc = iio_priv(indio_dev);
1317 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
1318 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE;
1321 * dma cyclic transfers are used, buffer is split into two periods.
1323 * - always one buffer (period) dma is working on
1324 * - one buffer (period) driver can push with iio_trigger_poll().
1326 watermark = min(watermark, val * (unsigned)(sizeof(u16)));
1327 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
1332 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
1333 const unsigned long *scan_mask)
1335 struct stm32_adc *adc = iio_priv(indio_dev);
1338 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
1340 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
1347 static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
1348 const struct of_phandle_args *iiospec)
1352 for (i = 0; i < indio_dev->num_channels; i++)
1353 if (indio_dev->channels[i].channel == iiospec->args[0])
1360 * stm32_adc_debugfs_reg_access - read or write register value
1362 * To read a value from an ADC register:
1363 * echo [ADC reg offset] > direct_reg_access
1364 * cat direct_reg_access
1366 * To write a value in a ADC register:
1367 * echo [ADC_reg_offset] [value] > direct_reg_access
1369 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
1370 unsigned reg, unsigned writeval,
1373 struct stm32_adc *adc = iio_priv(indio_dev);
1376 stm32_adc_writel(adc, reg, writeval);
1378 *readval = stm32_adc_readl(adc, reg);
1383 static const struct iio_info stm32_adc_iio_info = {
1384 .read_raw = stm32_adc_read_raw,
1385 .validate_trigger = stm32_adc_validate_trigger,
1386 .hwfifo_set_watermark = stm32_adc_set_watermark,
1387 .update_scan_mode = stm32_adc_update_scan_mode,
1388 .debugfs_reg_access = stm32_adc_debugfs_reg_access,
1389 .of_xlate = stm32_adc_of_xlate,
1390 .driver_module = THIS_MODULE,
1393 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1395 struct dma_tx_state state;
1396 enum dma_status status;
1398 status = dmaengine_tx_status(adc->dma_chan,
1399 adc->dma_chan->cookie,
1401 if (status == DMA_IN_PROGRESS) {
1402 /* Residue is size in bytes from end of buffer */
1403 unsigned int i = adc->rx_buf_sz - state.residue;
1406 /* Return available bytes */
1408 size = i - adc->bufi;
1410 size = adc->rx_buf_sz + i - adc->bufi;
1418 static void stm32_adc_dma_buffer_done(void *data)
1420 struct iio_dev *indio_dev = data;
1422 iio_trigger_poll_chained(indio_dev->trig);
1425 static int stm32_adc_dma_start(struct iio_dev *indio_dev)
1427 struct stm32_adc *adc = iio_priv(indio_dev);
1428 struct dma_async_tx_descriptor *desc;
1429 dma_cookie_t cookie;
1435 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
1436 adc->rx_buf_sz, adc->rx_buf_sz / 2);
1438 /* Prepare a DMA cyclic transaction */
1439 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1441 adc->rx_buf_sz, adc->rx_buf_sz / 2,
1443 DMA_PREP_INTERRUPT);
1447 desc->callback = stm32_adc_dma_buffer_done;
1448 desc->callback_param = indio_dev;
1450 cookie = dmaengine_submit(desc);
1451 ret = dma_submit_error(cookie);
1453 dmaengine_terminate_all(adc->dma_chan);
1457 /* Issue pending DMA requests */
1458 dma_async_issue_pending(adc->dma_chan);
1463 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
1465 struct stm32_adc *adc = iio_priv(indio_dev);
1468 if (adc->cfg->prepare) {
1469 ret = adc->cfg->prepare(adc);
1474 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
1476 dev_err(&indio_dev->dev, "Can't set trigger\n");
1480 ret = stm32_adc_dma_start(indio_dev);
1482 dev_err(&indio_dev->dev, "Can't start dma\n");
1486 ret = iio_triggered_buffer_postenable(indio_dev);
1490 /* Reset adc buffer index */
1494 stm32_adc_conv_irq_enable(adc);
1496 adc->cfg->start_conv(adc, !!adc->dma_chan);
1502 dmaengine_terminate_all(adc->dma_chan);
1504 stm32_adc_set_trig(indio_dev, NULL);
1506 if (adc->cfg->unprepare)
1507 adc->cfg->unprepare(adc);
1512 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
1514 struct stm32_adc *adc = iio_priv(indio_dev);
1517 adc->cfg->stop_conv(adc);
1519 stm32_adc_conv_irq_disable(adc);
1521 ret = iio_triggered_buffer_predisable(indio_dev);
1523 dev_err(&indio_dev->dev, "predisable failed\n");
1526 dmaengine_terminate_all(adc->dma_chan);
1528 if (stm32_adc_set_trig(indio_dev, NULL))
1529 dev_err(&indio_dev->dev, "Can't clear trigger\n");
1531 if (adc->cfg->unprepare)
1532 adc->cfg->unprepare(adc);
1537 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
1538 .postenable = &stm32_adc_buffer_postenable,
1539 .predisable = &stm32_adc_buffer_predisable,
1542 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
1544 struct iio_poll_func *pf = p;
1545 struct iio_dev *indio_dev = pf->indio_dev;
1546 struct stm32_adc *adc = iio_priv(indio_dev);
1548 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1550 if (!adc->dma_chan) {
1551 /* reset buffer index */
1553 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
1556 int residue = stm32_adc_dma_residue(adc);
1558 while (residue >= indio_dev->scan_bytes) {
1559 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1561 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1563 residue -= indio_dev->scan_bytes;
1564 adc->bufi += indio_dev->scan_bytes;
1565 if (adc->bufi >= adc->rx_buf_sz)
1570 iio_trigger_notify_done(indio_dev->trig);
1572 /* re-enable eoc irq */
1574 stm32_adc_conv_irq_enable(adc);
1579 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = {
1580 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
1582 .name = "trigger_polarity_available",
1583 .shared = IIO_SHARED_BY_ALL,
1584 .read = iio_enum_available_read,
1585 .private = (uintptr_t)&stm32_adc_trig_pol,
1590 static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
1592 struct device_node *node = indio_dev->dev.of_node;
1593 struct stm32_adc *adc = iio_priv(indio_dev);
1597 if (of_property_read_u32(node, "assigned-resolution-bits", &res))
1598 res = adc->cfg->adc_info->resolutions[0];
1600 for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1601 if (res == adc->cfg->adc_info->resolutions[i])
1603 if (i >= adc->cfg->adc_info->num_res) {
1604 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
1608 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);
1614 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
1616 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1617 u32 period_ns, shift = smpr->shift, mask = smpr->mask;
1618 unsigned int smp, r = smpr->reg;
1620 /* Determine sampling time (ADC clock cycles) */
1621 period_ns = NSEC_PER_SEC / adc->common->rate;
1622 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++)
1623 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
1625 if (smp > STM32_ADC_MAX_SMP)
1626 smp = STM32_ADC_MAX_SMP;
1628 /* pre-build sampling time registers (e.g. smpr1, smpr2) */
1629 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
1632 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
1633 struct iio_chan_spec *chan,
1634 const struct stm32_adc_chan_spec *channel,
1635 int scan_index, u32 smp)
1637 struct stm32_adc *adc = iio_priv(indio_dev);
1639 chan->type = channel->type;
1640 chan->channel = channel->channel;
1641 chan->datasheet_name = channel->name;
1642 chan->scan_index = scan_index;
1644 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1645 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
1646 chan->scan_type.sign = 'u';
1647 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
1648 chan->scan_type.storagebits = 16;
1649 chan->ext_info = stm32_adc_ext_info;
1651 /* Prepare sampling time settings */
1652 stm32_adc_smpr_init(adc, chan->channel, smp);
1654 /* pre-build selected channels mask */
1655 adc->pcsel |= BIT(chan->channel);
1658 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
1660 struct device_node *node = indio_dev->dev.of_node;
1661 struct stm32_adc *adc = iio_priv(indio_dev);
1662 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1663 struct property *prop;
1665 struct iio_chan_spec *channels;
1666 int scan_index = 0, num_channels, ret;
1669 num_channels = of_property_count_u32_elems(node, "st,adc-channels");
1670 if (num_channels < 0 ||
1671 num_channels > adc_info->max_channels) {
1672 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1673 return num_channels < 0 ? num_channels : -EINVAL;
1676 /* Optional sample time is provided either for each, or all channels */
1677 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs");
1678 if (ret > 1 && ret != num_channels) {
1679 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
1683 channels = devm_kcalloc(&indio_dev->dev, num_channels,
1684 sizeof(struct iio_chan_spec), GFP_KERNEL);
1688 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
1689 if (val >= adc_info->max_channels) {
1690 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
1695 * Using of_property_read_u32_index(), smp value will only be
1696 * modified if valid u32 value can be decoded. This allows to
1697 * get either no value, 1 shared value for all indexes, or one
1698 * value per channel.
1700 of_property_read_u32_index(node, "st,min-sample-time-nsecs",
1703 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
1704 &adc_info->channels[val],
1709 indio_dev->num_channels = scan_index;
1710 indio_dev->channels = channels;
1715 static int stm32_adc_dma_request(struct iio_dev *indio_dev)
1717 struct stm32_adc *adc = iio_priv(indio_dev);
1718 struct dma_slave_config config;
1721 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
1725 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1726 STM32_DMA_BUFFER_SIZE,
1727 &adc->rx_dma_buf, GFP_KERNEL);
1733 /* Configure DMA channel to read data register */
1734 memset(&config, 0, sizeof(config));
1735 config.src_addr = (dma_addr_t)adc->common->phys_base;
1736 config.src_addr += adc->offset + adc->cfg->regs->dr;
1737 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1739 ret = dmaengine_slave_config(adc->dma_chan, &config);
1746 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
1747 adc->rx_buf, adc->rx_dma_buf);
1749 dma_release_channel(adc->dma_chan);
1754 static int stm32_adc_probe(struct platform_device *pdev)
1756 struct iio_dev *indio_dev;
1757 struct device *dev = &pdev->dev;
1758 struct stm32_adc *adc;
1761 if (!pdev->dev.of_node)
1764 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
1768 adc = iio_priv(indio_dev);
1769 adc->common = dev_get_drvdata(pdev->dev.parent);
1770 spin_lock_init(&adc->lock);
1771 init_completion(&adc->completion);
1772 adc->cfg = (const struct stm32_adc_cfg *)
1773 of_match_device(dev->driver->of_match_table, dev)->data;
1775 indio_dev->name = dev_name(&pdev->dev);
1776 indio_dev->dev.parent = &pdev->dev;
1777 indio_dev->dev.of_node = pdev->dev.of_node;
1778 indio_dev->info = &stm32_adc_iio_info;
1779 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
1781 platform_set_drvdata(pdev, adc);
1783 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
1785 dev_err(&pdev->dev, "missing reg property\n");
1789 adc->irq = platform_get_irq(pdev, 0);
1791 dev_err(&pdev->dev, "failed to get irq\n");
1795 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1796 0, pdev->name, adc);
1798 dev_err(&pdev->dev, "failed to request IRQ\n");
1802 adc->clk = devm_clk_get(&pdev->dev, NULL);
1803 if (IS_ERR(adc->clk)) {
1804 ret = PTR_ERR(adc->clk);
1805 if (ret == -ENOENT && !adc->cfg->clk_required) {
1808 dev_err(&pdev->dev, "Can't get clock\n");
1814 ret = clk_prepare_enable(adc->clk);
1816 dev_err(&pdev->dev, "clk enable failed\n");
1821 ret = stm32_adc_of_get_resolution(indio_dev);
1823 goto err_clk_disable;
1824 stm32_adc_set_res(adc);
1826 if (adc->cfg->selfcalib) {
1827 ret = adc->cfg->selfcalib(adc);
1829 goto err_clk_disable;
1832 ret = stm32_adc_chan_of_init(indio_dev);
1834 goto err_clk_disable;
1836 ret = stm32_adc_dma_request(indio_dev);
1838 goto err_clk_disable;
1840 ret = iio_triggered_buffer_setup(indio_dev,
1841 &iio_pollfunc_store_time,
1842 &stm32_adc_trigger_handler,
1843 &stm32_adc_buffer_setup_ops);
1845 dev_err(&pdev->dev, "buffer setup failed\n");
1846 goto err_dma_disable;
1849 ret = iio_device_register(indio_dev);
1851 dev_err(&pdev->dev, "iio dev register failed\n");
1852 goto err_buffer_cleanup;
1858 iio_triggered_buffer_cleanup(indio_dev);
1861 if (adc->dma_chan) {
1862 dma_free_coherent(adc->dma_chan->device->dev,
1863 STM32_DMA_BUFFER_SIZE,
1864 adc->rx_buf, adc->rx_dma_buf);
1865 dma_release_channel(adc->dma_chan);
1869 clk_disable_unprepare(adc->clk);
1874 static int stm32_adc_remove(struct platform_device *pdev)
1876 struct stm32_adc *adc = platform_get_drvdata(pdev);
1877 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1879 iio_device_unregister(indio_dev);
1880 iio_triggered_buffer_cleanup(indio_dev);
1881 if (adc->dma_chan) {
1882 dma_free_coherent(adc->dma_chan->device->dev,
1883 STM32_DMA_BUFFER_SIZE,
1884 adc->rx_buf, adc->rx_dma_buf);
1885 dma_release_channel(adc->dma_chan);
1888 clk_disable_unprepare(adc->clk);
1893 static const struct stm32_adc_cfg stm32f4_adc_cfg = {
1894 .regs = &stm32f4_adc_regspec,
1895 .adc_info = &stm32f4_adc_info,
1896 .trigs = stm32f4_adc_trigs,
1897 .clk_required = true,
1898 .start_conv = stm32f4_adc_start_conv,
1899 .stop_conv = stm32f4_adc_stop_conv,
1900 .smp_cycles = stm32f4_adc_smp_cycles,
1903 static const struct stm32_adc_cfg stm32h7_adc_cfg = {
1904 .regs = &stm32h7_adc_regspec,
1905 .adc_info = &stm32h7_adc_info,
1906 .trigs = stm32h7_adc_trigs,
1907 .selfcalib = stm32h7_adc_selfcalib,
1908 .start_conv = stm32h7_adc_start_conv,
1909 .stop_conv = stm32h7_adc_stop_conv,
1910 .prepare = stm32h7_adc_prepare,
1911 .unprepare = stm32h7_adc_unprepare,
1912 .smp_cycles = stm32h7_adc_smp_cycles,
1915 static const struct of_device_id stm32_adc_of_match[] = {
1916 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
1917 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
1920 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
1922 static struct platform_driver stm32_adc_driver = {
1923 .probe = stm32_adc_probe,
1924 .remove = stm32_adc_remove,
1926 .name = "stm32-adc",
1927 .of_match_table = stm32_adc_of_match,
1930 module_platform_driver(stm32_adc_driver);
1932 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
1933 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
1934 MODULE_LICENSE("GPL v2");
1935 MODULE_ALIAS("platform:stm32-adc");