drivers/i2c/busses/i2c-owl.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Actions Semiconductor Owl SoC's I2C driver
   4  *
   5  * Copyright (c) 2014 Actions Semi Inc.
   6  * Author: David Liu <liuwei@actions-semi.com>
   7  *
   8  * Copyright (c) 2018 Linaro Ltd.
   9  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/i2c.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/of_device.h>
  19
  20 /* I2C registers */
  21 #define OWL_I2C_REG_CTL         0x0000
  22 #define OWL_I2C_REG_CLKDIV      0x0004
  23 #define OWL_I2C_REG_STAT        0x0008
  24 #define OWL_I2C_REG_ADDR        0x000C
  25 #define OWL_I2C_REG_TXDAT       0x0010
  26 #define OWL_I2C_REG_RXDAT       0x0014
  27 #define OWL_I2C_REG_CMD         0x0018
  28 #define OWL_I2C_REG_FIFOCTL     0x001C
  29 #define OWL_I2C_REG_FIFOSTAT    0x0020
  30 #define OWL_I2C_REG_DATCNT      0x0024
  31 #define OWL_I2C_REG_RCNT        0x0028
  32
  33 /* I2Cx_CTL Bit Mask */
  34 #define OWL_I2C_CTL_RB          BIT(1)
  35 #define OWL_I2C_CTL_GBCC(x)     (((x) & 0x3) << 2)
  36 #define OWL_I2C_CTL_GBCC_NONE   OWL_I2C_CTL_GBCC(0)
  37 #define OWL_I2C_CTL_GBCC_START  OWL_I2C_CTL_GBCC(1)
  38 #define OWL_I2C_CTL_GBCC_STOP   OWL_I2C_CTL_GBCC(2)
  39 #define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
  40 #define OWL_I2C_CTL_IRQE        BIT(5)
  41 #define OWL_I2C_CTL_EN          BIT(7)
  42 #define OWL_I2C_CTL_AE          BIT(8)
  43 #define OWL_I2C_CTL_SHSM        BIT(10)
  44
  45 #define OWL_I2C_DIV_FACTOR(x)   ((x) & 0xff)
  46
  47 /* I2Cx_STAT Bit Mask */
  48 #define OWL_I2C_STAT_RACK       BIT(0)
  49 #define OWL_I2C_STAT_BEB        BIT(1)
  50 #define OWL_I2C_STAT_IRQP       BIT(2)
  51 #define OWL_I2C_STAT_LAB        BIT(3)
  52 #define OWL_I2C_STAT_STPD       BIT(4)
  53 #define OWL_I2C_STAT_STAD       BIT(5)
  54 #define OWL_I2C_STAT_BBB        BIT(6)
  55 #define OWL_I2C_STAT_TCB        BIT(7)
  56 #define OWL_I2C_STAT_LBST       BIT(8)
  57 #define OWL_I2C_STAT_SAMB       BIT(9)
  58 #define OWL_I2C_STAT_SRGC       BIT(10)
  59
  60 /* I2Cx_CMD Bit Mask */
  61 #define OWL_I2C_CMD_SBE         BIT(0)
  62 #define OWL_I2C_CMD_RBE         BIT(4)
  63 #define OWL_I2C_CMD_DE          BIT(8)
  64 #define OWL_I2C_CMD_NS          BIT(9)
  65 #define OWL_I2C_CMD_SE          BIT(10)
  66 #define OWL_I2C_CMD_MSS         BIT(11)
  67 #define OWL_I2C_CMD_WRS         BIT(12)
  68 #define OWL_I2C_CMD_SECL        BIT(15)
  69
  70 #define OWL_I2C_CMD_AS(x)       (((x) & 0x7) << 1)
  71 #define OWL_I2C_CMD_SAS(x)      (((x) & 0x7) << 5)
  72
  73 /* I2Cx_FIFOCTL Bit Mask */
  74 #define OWL_I2C_FIFOCTL_NIB     BIT(0)
  75 #define OWL_I2C_FIFOCTL_RFR     BIT(1)
  76 #define OWL_I2C_FIFOCTL_TFR     BIT(2)
  77
  78 /* I2Cc_FIFOSTAT Bit Mask */
  79 #define OWL_I2C_FIFOSTAT_RNB    BIT(1)
  80 #define OWL_I2C_FIFOSTAT_RFE    BIT(2)
  81 #define OWL_I2C_FIFOSTAT_TFF    BIT(5)
  82 #define OWL_I2C_FIFOSTAT_TFD    GENMASK(23, 16)
  83 #define OWL_I2C_FIFOSTAT_RFD    GENMASK(15, 8)
  84
  85 /* I2C bus timeout */
  86 #define OWL_I2C_TIMEOUT         msecs_to_jiffies(4 * 1000)
  87
  88 #define OWL_I2C_MAX_RETRIES     50
  89
  90 #define OWL_I2C_DEF_SPEED_HZ    100000
  91 #define OWL_I2C_MAX_SPEED_HZ    400000
  92
  93 struct owl_i2c_dev {
  94         struct i2c_adapter      adap;
  95         struct i2c_msg          *msg;
  96         struct completion       msg_complete;
  97         struct clk              *clk;
  98         spinlock_t              lock;
  99         void __iomem            *base;
 100         unsigned long           clk_rate;
 101         u32                     bus_freq;
 102         u32                     msg_ptr;
 103         int                     err;
 104 };
 105
 106 static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state)
 107 {
 108         unsigned int regval;
 109
 110         regval = readl(reg);
 111
 112         if (state)
 113                 regval |= val;
 114         else
 115                 regval &= ~val;
 116
 117         writel(regval, reg);
 118 }
 119
 120 static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
 121 {
 122         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 123                            OWL_I2C_CTL_EN, false);
 124         mdelay(1);
 125         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 126                            OWL_I2C_CTL_EN, true);
 127
 128         /* Clear status registers */
 129         writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
 130 }
 131
 132 static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev)
 133 {
 134         unsigned int val, timeout = 0;
 135
 136         /* Reset FIFO */
 137         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
 138                            OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
 139                            true);
 140
 141         /* Wait 50ms for FIFO reset complete */
 142         do {
 143                 val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
 144                 if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
 145                         break;
 146                 usleep_range(500, 1000);
 147         } while (timeout++ < OWL_I2C_MAX_RETRIES);
 148
 149         if (timeout > OWL_I2C_MAX_RETRIES) {
 150                 dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n");
 151                 return -ETIMEDOUT;
 152         }
 153
 154         return 0;
 155 }
 156
 157 static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
 158 {
 159         unsigned int val;
 160
 161         val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16);
 162
 163         /* Set clock divider factor */
 164         writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
 165 }
 166
 167 static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
 168 {
 169         struct owl_i2c_dev *i2c_dev = _dev;
 170         struct i2c_msg *msg = i2c_dev->msg;
 171         unsigned long flags;
 172         unsigned int stat, fifostat;
 173
 174         spin_lock_irqsave(&i2c_dev->lock, flags);
 175
 176         i2c_dev->err = 0;
 177
 178         /* Handle NACK from slave */
 179         fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
 180         if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
 181                 i2c_dev->err = -ENXIO;
 182                 goto stop;
 183         }
 184
 185         /* Handle bus error */
 186         stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
 187         if (stat & OWL_I2C_STAT_BEB) {
 188                 i2c_dev->err = -EIO;
 189                 goto stop;
 190         }
 191
 192         /* Handle FIFO read */
 193         if (msg->flags & I2C_M_RD) {
 194                 while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
 195                         OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) {
 196                         msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
 197                                                              OWL_I2C_REG_RXDAT);
 198                 }
 199         } else {
 200                 /* Handle the remaining bytes which were not sent */
 201                 while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
 202                          OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) {
 203                         writel(msg->buf[i2c_dev->msg_ptr++],
 204                                i2c_dev->base + OWL_I2C_REG_TXDAT);
 205                 }
 206         }
 207
 208 stop:
 209         /* Clear pending interrupts */
 210         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
 211                            OWL_I2C_STAT_IRQP, true);
 212
 213         complete_all(&i2c_dev->msg_complete);
 214         spin_unlock_irqrestore(&i2c_dev->lock, flags);
 215
 216         return IRQ_HANDLED;
 217 }
 218
 219 static u32 owl_i2c_func(struct i2c_adapter *adap)
 220 {
 221         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 222 }
 223
 224 static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
 225 {
 226         struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 227         unsigned long timeout;
 228
 229         /* Check for Bus busy */
 230         timeout = jiffies + OWL_I2C_TIMEOUT;
 231         while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) {
 232                 if (time_after(jiffies, timeout)) {
 233                         dev_err(&adap->dev, "Bus busy timeout\n");
 234                         return -ETIMEDOUT;
 235                 }
 236         }
 237
 238         return 0;
 239 }
 240
 241 static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 242                                int num)
 243 {
 244         struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 245         struct i2c_msg *msg;
 246         unsigned long time_left, flags;
 247         unsigned int i2c_cmd, val;
 248         unsigned int addr;
 249         int ret, idx;
 250
 251         spin_lock_irqsave(&i2c_dev->lock, flags);
 252
 253         /* Reset I2C controller */
 254         owl_i2c_reset(i2c_dev);
 255
 256         /* Set bus frequency */
 257         owl_i2c_set_freq(i2c_dev);
 258
 259         /*
 260          * Spinlock should be released before calling reset FIFO and
 261          * bus busy check since those functions may sleep
 262          */
 263         spin_unlock_irqrestore(&i2c_dev->lock, flags);
 264
 265         /* Reset FIFO */
 266         ret = owl_i2c_reset_fifo(i2c_dev);
 267         if (ret)
 268                 goto unlocked_err_exit;
 269
 270         /* Check for bus busy */
 271         ret = owl_i2c_check_bus_busy(adap);
 272         if (ret)
 273                 goto unlocked_err_exit;
 274
 275         spin_lock_irqsave(&i2c_dev->lock, flags);
 276
 277         /* Check for Arbitration lost */
 278         val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
 279         if (val & OWL_I2C_STAT_LAB) {
 280                 val &= ~OWL_I2C_STAT_LAB;
 281                 writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
 282                 ret = -EAGAIN;
 283                 goto err_exit;
 284         }
 285
 286         reinit_completion(&i2c_dev->msg_complete);
 287
 288         /* Enable I2C controller interrupt */
 289         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 290                            OWL_I2C_CTL_IRQE, true);
 291
 292         /*
 293          * Select: FIFO enable, Master mode, Stop enable, Data count enable,
 294          * Send start bit
 295          */
 296         i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE |
 297                   OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE;
 298
 299         /* Handle repeated start condition */
 300         if (num > 1) {
 301                 /* Set internal address length and enable repeated start */
 302                 i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) |
 303                            OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE;
 304
 305                 /* Write slave address */
 306                 addr = i2c_8bit_addr_from_msg(&msgs[0]);
 307                 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
 308
 309                 /* Write internal register address */
 310                 for (idx = 0; idx < msgs[0].len; idx++)
 311                         writel(msgs[0].buf[idx],
 312                                i2c_dev->base + OWL_I2C_REG_TXDAT);
 313
 314                 msg = &msgs[1];
 315         } else {
 316                 /* Set address length */
 317                 i2c_cmd |= OWL_I2C_CMD_AS(1);
 318                 msg = &msgs[0];
 319         }
 320
 321         i2c_dev->msg = msg;
 322         i2c_dev->msg_ptr = 0;
 323
 324         /* Set data count for the message */
 325         writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
 326
 327         addr = i2c_8bit_addr_from_msg(msg);
 328         writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
 329
 330         if (!(msg->flags & I2C_M_RD)) {
 331                 /* Write data to FIFO */
 332                 for (idx = 0; idx < msg->len; idx++) {
 333                         /* Check for FIFO full */
 334                         if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
 335                             OWL_I2C_FIFOSTAT_TFF)
 336                                 break;
 337
 338                         writel(msg->buf[idx],
 339                                i2c_dev->base + OWL_I2C_REG_TXDAT);
 340                 }
 341
 342                 i2c_dev->msg_ptr = idx;
 343         }
 344
 345         /* Ignore the NACK if needed */
 346         if (msg->flags & I2C_M_IGNORE_NAK)
 347                 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
 348                                    OWL_I2C_FIFOCTL_NIB, true);
 349         else
 350                 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
 351                                    OWL_I2C_FIFOCTL_NIB, false);
 352
 353         /* Start the transfer */
 354         writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
 355
 356         spin_unlock_irqrestore(&i2c_dev->lock, flags);
 357
 358         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
 359                                                 adap->timeout);
 360
 361         spin_lock_irqsave(&i2c_dev->lock, flags);
 362         if (time_left == 0) {
 363                 dev_err(&adap->dev, "Transaction timed out\n");
 364                 /* Send stop condition and release the bus */
 365                 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 366                                    OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB,
 367                                    true);
 368                 ret = -ETIMEDOUT;
 369                 goto err_exit;
 370         }
 371
 372         ret = i2c_dev->err < 0 ? i2c_dev->err : num;
 373
 374 err_exit:
 375         spin_unlock_irqrestore(&i2c_dev->lock, flags);
 376
 377 unlocked_err_exit:
 378         /* Disable I2C controller */
 379         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
 380                            OWL_I2C_CTL_EN, false);
 381
 382         return ret;
 383 }
 384
 385 static const struct i2c_algorithm owl_i2c_algorithm = {
 386         .master_xfer    = owl_i2c_master_xfer,
 387         .functionality  = owl_i2c_func,
 388 };
 389
 390 static const struct i2c_adapter_quirks owl_i2c_quirks = {
 391         .flags          = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
 392         .max_read_len   = 240,
 393         .max_write_len  = 240,
 394         .max_comb_1st_msg_len = 6,
 395         .max_comb_2nd_msg_len = 240,
 396 };
 397
 398 static int owl_i2c_probe(struct platform_device *pdev)
 399 {
 400         struct device *dev = &pdev->dev;
 401         struct owl_i2c_dev *i2c_dev;
 402         struct resource *res;
 403         int ret, irq;
 404
 405         i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
 406         if (!i2c_dev)
 407                 return -ENOMEM;
 408
 409         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 410         i2c_dev->base = devm_ioremap_resource(dev, res);
 411         if (IS_ERR(i2c_dev->base))
 412                 return PTR_ERR(i2c_dev->base);
 413
 414         irq = platform_get_irq(pdev, 0);
 415         if (irq < 0) {
 416                 dev_err(dev, "failed to get IRQ number\n");
 417                 return irq;
 418         }
 419
 420         if (of_property_read_u32(dev->of_node, "clock-frequency",
 421                                  &i2c_dev->bus_freq))
 422                 i2c_dev->bus_freq = OWL_I2C_DEF_SPEED_HZ;
 423
 424         /* We support only frequencies of 100k and 400k for now */
 425         if (i2c_dev->bus_freq != OWL_I2C_DEF_SPEED_HZ &&
 426             i2c_dev->bus_freq != OWL_I2C_MAX_SPEED_HZ) {
 427                 dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
 428                 return -EINVAL;
 429         }
 430
 431         i2c_dev->clk = devm_clk_get(dev, NULL);
 432         if (IS_ERR(i2c_dev->clk)) {
 433                 dev_err(dev, "failed to get clock\n");
 434                 return PTR_ERR(i2c_dev->clk);
 435         }
 436
 437         ret = clk_prepare_enable(i2c_dev->clk);
 438         if (ret)
 439                 return ret;
 440
 441         i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
 442         if (!i2c_dev->clk_rate) {
 443                 dev_err(dev, "input clock rate should not be zero\n");
 444                 ret = -EINVAL;
 445                 goto disable_clk;
 446         }
 447
 448         init_completion(&i2c_dev->msg_complete);
 449         spin_lock_init(&i2c_dev->lock);
 450         i2c_dev->adap.owner = THIS_MODULE;
 451         i2c_dev->adap.algo = &owl_i2c_algorithm;
 452         i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
 453         i2c_dev->adap.quirks = &owl_i2c_quirks;
 454         i2c_dev->adap.dev.parent = dev;
 455         i2c_dev->adap.dev.of_node = dev->of_node;
 456         snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
 457                  "%s", "OWL I2C adapter");
 458         i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
 459
 460         platform_set_drvdata(pdev, i2c_dev);
 461
 462         ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
 463                                i2c_dev);
 464         if (ret) {
 465                 dev_err(dev, "failed to request irq %d\n", irq);
 466                 goto disable_clk;
 467         }
 468
 469         return i2c_add_adapter(&i2c_dev->adap);
 470
 471 disable_clk:
 472         clk_disable_unprepare(i2c_dev->clk);
 473
 474         return ret;
 475 }
 476
 477 static const struct of_device_id owl_i2c_of_match[] = {
 478         { .compatible = "actions,s700-i2c" },
 479         { .compatible = "actions,s900-i2c" },
 480         { /* sentinel */ }
 481 };
 482 MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
 483
 484 static struct platform_driver owl_i2c_driver = {
 485         .probe          = owl_i2c_probe,
 486         .driver         = {
 487                 .name   = "owl-i2c",
 488                 .of_match_table = of_match_ptr(owl_i2c_of_match),
 489         },
 490 };
 491 module_platform_driver(owl_i2c_driver);
 492
 493 MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
 494 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
 495 MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver");
 496 MODULE_LICENSE("GPL");