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54 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
55 * S12xx Product Family.
57 * Features supported by this driver:
60 * Block process call transaction no
64 #include <linux/module.h>
65 #include <linux/pci.h>
66 #include <linux/kernel.h>
67 #include <linux/stddef.h>
68 #include <linux/completion.h>
69 #include <linux/dma-mapping.h>
70 #include <linux/i2c.h>
71 #include <linux/acpi.h>
72 #include <linux/interrupt.h>
74 #include <asm-generic/io-64-nonatomic-lo-hi.h>
76 /* PCI Address Constants */
79 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
80 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
81 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
82 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
84 #define ISMT_DESC_ENTRIES 32 /* number of descriptor entries */
85 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
87 /* Hardware Descriptor Constants - Control Field */
88 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
89 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
90 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
91 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
92 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
93 #define ISMT_DESC_INT 0x40 /* Interrupt */
94 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
96 /* Hardware Descriptor Constants - Status Field */
97 #define ISMT_DESC_SCS 0x01 /* Success */
98 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
99 #define ISMT_DESC_NAK 0x08 /* NAK Received */
100 #define ISMT_DESC_CRC 0x10 /* CRC Error */
101 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
102 #define ISMT_DESC_COL 0x40 /* Collisions */
103 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
106 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
108 /* iSMT General Register address offsets (SMBBAR + <addr>) */
109 #define ISMT_GR_GCTRL 0x000 /* General Control */
110 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
111 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
112 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
113 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
114 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
116 /* iSMT Master Registers */
117 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
118 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
119 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
120 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
121 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
123 /* iSMT Miscellaneous Registers */
124 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
126 /* General Control Register (GCTRL) bit definitions */
127 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
128 #define ISMT_GCTRL_KILL 0x08 /* Kill */
129 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
131 /* Master Control Register (MCTRL) bit definitions */
132 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
133 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
134 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
136 /* Master Status Register (MSTS) bit definitions */
137 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
138 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
139 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
140 #define ISMT_MSTS_IP 0x01 /* In Progress */
142 /* Master Descriptor Size (MDS) bit definitions */
143 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
145 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
146 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
147 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
148 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
149 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
150 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
153 /* MSI Control Register (MSICTL) bit definitions */
154 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
156 /* iSMT Hardware Descriptor */
158 u8 tgtaddr_rw; /* target address & r/w bit */
159 u8 wr_len_cmd; /* write length in bytes or a command */
160 u8 rd_len; /* read length */
161 u8 control; /* control bits */
162 u8 status; /* status bits */
163 u8 retry; /* collision retry and retry count */
164 u8 rxbytes; /* received bytes */
165 u8 txbytes; /* transmitted bytes */
166 u32 dptr_low; /* lower 32 bit of the data pointer */
167 u32 dptr_high; /* upper 32 bit of the data pointer */
171 struct i2c_adapter adapter;
172 void *smba; /* PCI BAR */
173 struct pci_dev *pci_dev;
174 struct ismt_desc *hw; /* descriptor virt base addr */
175 dma_addr_t io_rng_dma; /* descriptor HW base addr */
176 u8 head; /* ring buffer head pointer */
177 struct completion cmp; /* interrupt completion */
178 u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */
179 bool using_msi; /* type of interrupt flag */
183 * ismt_ids - PCI device IDs supported by this driver
185 static const struct pci_device_id ismt_ids[] = {
186 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
188 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
192 MODULE_DEVICE_TABLE(pci, ismt_ids);
194 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
195 static unsigned int bus_speed;
196 module_param(bus_speed, uint, S_IRUGO);
197 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
200 * __ismt_desc_dump() - dump the contents of a specific descriptor
202 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
205 dev_dbg(dev, "Descriptor struct: %p\n", desc);
206 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
207 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
208 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
209 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
210 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
211 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
212 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
213 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
214 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
215 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
218 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
219 * @priv: iSMT private data
221 static void ismt_desc_dump(struct ismt_priv *priv)
223 struct device *dev = &priv->pci_dev->dev;
224 struct ismt_desc *desc = &priv->hw[priv->head];
226 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
227 __ismt_desc_dump(dev, desc);
231 * ismt_gen_reg_dump() - dump the iSMT General Registers
232 * @priv: iSMT private data
234 static void ismt_gen_reg_dump(struct ismt_priv *priv)
236 struct device *dev = &priv->pci_dev->dev;
238 dev_dbg(dev, "Dump of the iSMT General Registers\n");
239 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
240 priv->smba + ISMT_GR_GCTRL,
241 readl(priv->smba + ISMT_GR_GCTRL));
242 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
243 priv->smba + ISMT_GR_SMTICL,
244 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
245 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
246 priv->smba + ISMT_GR_ERRINTMSK,
247 readl(priv->smba + ISMT_GR_ERRINTMSK));
248 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
249 priv->smba + ISMT_GR_ERRAERMSK,
250 readl(priv->smba + ISMT_GR_ERRAERMSK));
251 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
252 priv->smba + ISMT_GR_ERRSTS,
253 readl(priv->smba + ISMT_GR_ERRSTS));
254 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
255 priv->smba + ISMT_GR_ERRINFO,
256 readl(priv->smba + ISMT_GR_ERRINFO));
260 * ismt_mstr_reg_dump() - dump the iSMT Master Registers
261 * @priv: iSMT private data
263 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
265 struct device *dev = &priv->pci_dev->dev;
267 dev_dbg(dev, "Dump of the iSMT Master Registers\n");
268 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
269 priv->smba + ISMT_MSTR_MDBA,
270 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
271 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
272 priv->smba + ISMT_MSTR_MCTRL,
273 readl(priv->smba + ISMT_MSTR_MCTRL));
274 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
275 priv->smba + ISMT_MSTR_MSTS,
276 readl(priv->smba + ISMT_MSTR_MSTS));
277 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
278 priv->smba + ISMT_MSTR_MDS,
279 readl(priv->smba + ISMT_MSTR_MDS));
280 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
281 priv->smba + ISMT_MSTR_RPOLICY,
282 readl(priv->smba + ISMT_MSTR_RPOLICY));
283 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
284 priv->smba + ISMT_SPGT,
285 readl(priv->smba + ISMT_SPGT));
289 * ismt_submit_desc() - add a descriptor to the ring
290 * @priv: iSMT private data
292 static void ismt_submit_desc(struct ismt_priv *priv)
297 ismt_desc_dump(priv);
298 ismt_gen_reg_dump(priv);
299 ismt_mstr_reg_dump(priv);
301 /* Set the FMHP (Firmware Master Head Pointer)*/
302 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
303 val = readl(priv->smba + ISMT_MSTR_MCTRL);
304 writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
305 priv->smba + ISMT_MSTR_MCTRL);
307 /* Set the start bit */
308 val = readl(priv->smba + ISMT_MSTR_MCTRL);
309 writel(val | ISMT_MCTRL_SS,
310 priv->smba + ISMT_MSTR_MCTRL);
314 * ismt_process_desc() - handle the completion of the descriptor
315 * @desc: the iSMT hardware descriptor
316 * @data: data buffer from the upper layer
317 * @priv: ismt_priv struct holding our dma buffer
318 * @size: SMBus transaction type
319 * @read_write: flag to indicate if this is a read or write
321 static int ismt_process_desc(const struct ismt_desc *desc,
322 union i2c_smbus_data *data,
323 struct ismt_priv *priv, int size,
326 u8 *dma_buffer = priv->dma_buffer;
328 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
329 __ismt_desc_dump(&priv->pci_dev->dev, desc);
331 if (desc->status & ISMT_DESC_SCS) {
332 if (read_write == I2C_SMBUS_WRITE &&
333 size != I2C_SMBUS_PROC_CALL)
338 case I2C_SMBUS_BYTE_DATA:
339 data->byte = dma_buffer[0];
341 case I2C_SMBUS_WORD_DATA:
342 case I2C_SMBUS_PROC_CALL:
343 data->word = dma_buffer[0] | (dma_buffer[1] << 8);
345 case I2C_SMBUS_BLOCK_DATA:
346 if (desc->rxbytes != dma_buffer[0] + 1)
349 memcpy(data->block, dma_buffer, desc->rxbytes);
351 case I2C_SMBUS_I2C_BLOCK_DATA:
352 memcpy(&data->block[1], dma_buffer, desc->rxbytes);
353 data->block[0] = desc->rxbytes;
359 if (likely(desc->status & ISMT_DESC_NAK))
362 if (desc->status & ISMT_DESC_CRC)
365 if (desc->status & ISMT_DESC_COL)
368 if (desc->status & ISMT_DESC_LPR)
371 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
378 * ismt_access() - process an SMBus command
379 * @adap: the i2c host adapter
380 * @addr: address of the i2c/SMBus target
381 * @flags: command options
382 * @read_write: read from or write to device
383 * @command: the i2c/SMBus command to issue
384 * @size: SMBus transaction type
385 * @data: read/write data buffer
387 static int ismt_access(struct i2c_adapter *adap, u16 addr,
388 unsigned short flags, char read_write, u8 command,
389 int size, union i2c_smbus_data *data)
392 dma_addr_t dma_addr = 0; /* address of the data buffer */
394 enum dma_data_direction dma_direction = 0;
395 struct ismt_desc *desc;
396 struct ismt_priv *priv = i2c_get_adapdata(adap);
397 struct device *dev = &priv->pci_dev->dev;
399 desc = &priv->hw[priv->head];
401 /* Initialize the DMA buffer */
402 memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer));
404 /* Initialize the descriptor */
405 memset(desc, 0, sizeof(struct ismt_desc));
406 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
408 /* Initialize common control bits */
409 if (likely(priv->using_msi))
410 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
412 desc->control = ISMT_DESC_FAIR;
414 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
415 && (size != I2C_SMBUS_I2C_BLOCK_DATA))
416 desc->control |= ISMT_DESC_PEC;
419 case I2C_SMBUS_QUICK:
420 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
424 if (read_write == I2C_SMBUS_WRITE) {
427 * The command field contains the write data
429 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
430 desc->control |= ISMT_DESC_CWRL;
431 desc->wr_len_cmd = command;
434 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
436 dma_direction = DMA_FROM_DEVICE;
441 case I2C_SMBUS_BYTE_DATA:
442 if (read_write == I2C_SMBUS_WRITE) {
445 * Command plus 1 data byte
447 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
448 desc->wr_len_cmd = 2;
450 dma_direction = DMA_TO_DEVICE;
451 priv->dma_buffer[0] = command;
452 priv->dma_buffer[1] = data->byte;
455 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
456 desc->control |= ISMT_DESC_CWRL;
457 desc->wr_len_cmd = command;
460 dma_direction = DMA_FROM_DEVICE;
464 case I2C_SMBUS_WORD_DATA:
465 if (read_write == I2C_SMBUS_WRITE) {
467 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
468 desc->wr_len_cmd = 3;
470 dma_direction = DMA_TO_DEVICE;
471 priv->dma_buffer[0] = command;
472 priv->dma_buffer[1] = data->word & 0xff;
473 priv->dma_buffer[2] = data->word >> 8;
476 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
477 desc->wr_len_cmd = command;
478 desc->control |= ISMT_DESC_CWRL;
481 dma_direction = DMA_FROM_DEVICE;
485 case I2C_SMBUS_PROC_CALL:
486 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
487 desc->wr_len_cmd = 3;
490 dma_direction = DMA_BIDIRECTIONAL;
491 priv->dma_buffer[0] = command;
492 priv->dma_buffer[1] = data->word & 0xff;
493 priv->dma_buffer[2] = data->word >> 8;
496 case I2C_SMBUS_BLOCK_DATA:
497 if (read_write == I2C_SMBUS_WRITE) {
499 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
500 dma_size = data->block[0] + 1;
501 dma_direction = DMA_TO_DEVICE;
502 desc->wr_len_cmd = dma_size;
503 desc->control |= ISMT_DESC_BLK;
504 priv->dma_buffer[0] = command;
505 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
508 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
509 dma_size = I2C_SMBUS_BLOCK_MAX;
510 dma_direction = DMA_FROM_DEVICE;
511 desc->rd_len = dma_size;
512 desc->wr_len_cmd = command;
513 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
517 case I2C_SMBUS_I2C_BLOCK_DATA:
518 /* Make sure the length is valid */
519 if (data->block[0] < 1)
522 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
523 data->block[0] = I2C_SMBUS_BLOCK_MAX;
525 if (read_write == I2C_SMBUS_WRITE) {
526 /* i2c Block Write */
527 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n");
528 dma_size = data->block[0] + 1;
529 dma_direction = DMA_TO_DEVICE;
530 desc->wr_len_cmd = dma_size;
531 desc->control |= ISMT_DESC_I2C;
532 priv->dma_buffer[0] = command;
533 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
536 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n");
537 dma_size = data->block[0];
538 dma_direction = DMA_FROM_DEVICE;
539 desc->rd_len = dma_size;
540 desc->wr_len_cmd = command;
541 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
543 * Per the "Table 15-15. I2C Commands",
544 * in the External Design Specification (EDS),
545 * (Document Number: 508084, Revision: 2.0),
546 * the _rw bit must be 0
548 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
553 dev_err(dev, "Unsupported transaction %d\n",
558 /* map the data buffer */
560 dev_dbg(dev, " dev=%p\n", dev);
561 dev_dbg(dev, " data=%p\n", data);
562 dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer);
563 dev_dbg(dev, " dma_size=%d\n", dma_size);
564 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
566 dma_addr = dma_map_single(dev,
571 if (dma_mapping_error(dev, dma_addr)) {
572 dev_err(dev, "Error in mapping dma buffer %p\n",
577 dev_dbg(dev, " dma_addr = 0x%016llX\n",
578 (unsigned long long)dma_addr);
580 desc->dptr_low = lower_32_bits(dma_addr);
581 desc->dptr_high = upper_32_bits(dma_addr);
584 reinit_completion(&priv->cmp);
586 /* Add the descriptor */
587 ismt_submit_desc(priv);
589 /* Now we wait for interrupt completion, 1s */
590 ret = wait_for_completion_timeout(&priv->cmp, HZ*1);
592 /* unmap the data buffer */
594 dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
596 if (unlikely(!ret)) {
597 dev_err(dev, "completion wait timed out\n");
602 /* do any post processing of the descriptor here */
603 ret = ismt_process_desc(desc, data, priv, size, read_write);
606 /* Update the ring pointer */
608 priv->head %= ISMT_DESC_ENTRIES;
614 * ismt_func() - report which i2c commands are supported by this adapter
615 * @adap: the i2c host adapter
617 static u32 ismt_func(struct i2c_adapter *adap)
619 return I2C_FUNC_SMBUS_QUICK |
620 I2C_FUNC_SMBUS_BYTE |
621 I2C_FUNC_SMBUS_BYTE_DATA |
622 I2C_FUNC_SMBUS_WORD_DATA |
623 I2C_FUNC_SMBUS_PROC_CALL |
624 I2C_FUNC_SMBUS_BLOCK_DATA |
625 I2C_FUNC_SMBUS_I2C_BLOCK |
630 * smbus_algorithm - the adapter algorithm and supported functionality
631 * @smbus_xfer: the adapter algorithm
632 * @functionality: functionality supported by the adapter
634 static const struct i2c_algorithm smbus_algorithm = {
635 .smbus_xfer = ismt_access,
636 .functionality = ismt_func,
640 * ismt_handle_isr() - interrupt handler bottom half
641 * @priv: iSMT private data
643 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
645 complete(&priv->cmp);
652 * ismt_do_interrupt() - IRQ interrupt handler
653 * @vec: interrupt vector
654 * @data: iSMT private data
656 static irqreturn_t ismt_do_interrupt(int vec, void *data)
659 struct ismt_priv *priv = data;
662 * check to see it's our interrupt, return IRQ_NONE if not ours
663 * since we are sharing interrupt
665 val = readl(priv->smba + ISMT_MSTR_MSTS);
667 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
670 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
671 priv->smba + ISMT_MSTR_MSTS);
673 return ismt_handle_isr(priv);
677 * ismt_do_msi_interrupt() - MSI interrupt handler
678 * @vec: interrupt vector
679 * @data: iSMT private data
681 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
683 return ismt_handle_isr(data);
687 * ismt_hw_init() - initialize the iSMT hardware
688 * @priv: iSMT private data
690 static void ismt_hw_init(struct ismt_priv *priv)
693 struct device *dev = &priv->pci_dev->dev;
695 /* initialize the Master Descriptor Base Address (MDBA) */
696 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
698 /* initialize the Master Control Register (MCTRL) */
699 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
701 /* initialize the Master Status Register (MSTS) */
702 writel(0, priv->smba + ISMT_MSTR_MSTS);
704 /* initialize the Master Descriptor Size (MDS) */
705 val = readl(priv->smba + ISMT_MSTR_MDS);
706 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
707 priv->smba + ISMT_MSTR_MDS);
710 * Set the SMBus speed (could use this for slow HW debuggers)
713 val = readl(priv->smba + ISMT_SPGT);
720 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
721 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
722 priv->smba + ISMT_SPGT);
726 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
727 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
728 priv->smba + ISMT_SPGT);
732 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
733 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
734 priv->smba + ISMT_SPGT);
738 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
739 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
740 priv->smba + ISMT_SPGT);
744 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
748 val = readl(priv->smba + ISMT_SPGT);
750 switch (val & ISMT_SPGT_SPD_MASK) {
751 case ISMT_SPGT_SPD_80K:
754 case ISMT_SPGT_SPD_100K:
757 case ISMT_SPGT_SPD_400K:
760 case ISMT_SPGT_SPD_1M:
764 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
768 * ismt_dev_init() - initialize the iSMT data structures
769 * @priv: iSMT private data
771 static int ismt_dev_init(struct ismt_priv *priv)
773 /* allocate memory for the descriptor */
774 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
776 * sizeof(struct ismt_desc)),
782 memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
785 init_completion(&priv->cmp);
791 * ismt_int_init() - initialize interrupts
792 * @priv: iSMT private data
794 static int ismt_int_init(struct ismt_priv *priv)
798 /* Try using MSI interrupts */
799 err = pci_enable_msi(priv->pci_dev);
801 dev_warn(&priv->pci_dev->dev,
802 "Unable to use MSI interrupts, falling back to legacy\n");
806 err = devm_request_irq(&priv->pci_dev->dev,
808 ismt_do_msi_interrupt,
813 pci_disable_msi(priv->pci_dev);
817 priv->using_msi = true;
820 /* Try using legacy interrupts */
822 err = devm_request_irq(&priv->pci_dev->dev,
829 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
833 priv->using_msi = false;
839 static struct pci_driver ismt_driver;
842 * ismt_probe() - probe for iSMT devices
843 * @pdev: PCI-Express device
844 * @id: PCI-Express device ID
847 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
850 struct ismt_priv *priv;
851 unsigned long start, len;
853 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
857 pci_set_drvdata(pdev, priv);
858 i2c_set_adapdata(&priv->adapter, priv);
859 priv->adapter.owner = THIS_MODULE;
861 priv->adapter.class = I2C_CLASS_HWMON;
863 priv->adapter.algo = &smbus_algorithm;
865 /* set up the sysfs linkage to our parent device */
866 priv->adapter.dev.parent = &pdev->dev;
868 /* number of retries on lost arbitration */
869 priv->adapter.retries = ISMT_MAX_RETRIES;
871 priv->pci_dev = pdev;
873 err = pcim_enable_device(pdev);
875 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
880 /* enable bus mastering */
881 pci_set_master(pdev);
883 /* Determine the address of the SMBus area */
884 start = pci_resource_start(pdev, SMBBAR);
885 len = pci_resource_len(pdev, SMBBAR);
886 if (!start || !len) {
888 "SMBus base address uninitialized, upgrade BIOS\n");
892 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
893 "SMBus iSMT adapter at %lx", start);
895 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
896 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
898 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
900 dev_err(&pdev->dev, "ACPI resource conflict!\n");
904 err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
907 "Failed to request SMBus region 0x%lx-0x%lx\n",
912 priv->smba = pcim_iomap(pdev, SMBBAR, len);
914 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
919 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
920 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
921 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
922 (pci_set_consistent_dma_mask(pdev,
923 DMA_BIT_MASK(32)) != 0)) {
924 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
931 err = ismt_dev_init(priv);
937 err = ismt_int_init(priv);
941 err = i2c_add_adapter(&priv->adapter);
943 dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n");
950 pci_release_region(pdev, SMBBAR);
955 * ismt_remove() - release driver resources
956 * @pdev: PCI-Express device
958 static void ismt_remove(struct pci_dev *pdev)
960 struct ismt_priv *priv = pci_get_drvdata(pdev);
962 i2c_del_adapter(&priv->adapter);
963 pci_release_region(pdev, SMBBAR);
967 * ismt_suspend() - place the device in suspend
968 * @pdev: PCI-Express device
972 static int ismt_suspend(struct pci_dev *pdev, pm_message_t mesg)
974 pci_save_state(pdev);
975 pci_set_power_state(pdev, pci_choose_state(pdev, mesg));
980 * ismt_resume() - PCI resume code
981 * @pdev: PCI-Express device
983 static int ismt_resume(struct pci_dev *pdev)
985 pci_set_power_state(pdev, PCI_D0);
986 pci_restore_state(pdev);
987 return pci_enable_device(pdev);
992 #define ismt_suspend NULL
993 #define ismt_resume NULL
997 static struct pci_driver ismt_driver = {
998 .name = "ismt_smbus",
999 .id_table = ismt_ids,
1000 .probe = ismt_probe,
1001 .remove = ismt_remove,
1002 .suspend = ismt_suspend,
1003 .resume = ismt_resume,
1006 module_pci_driver(ismt_driver);
1008 MODULE_LICENSE("Dual BSD/GPL");
1009 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
1010 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");