drivers/i2c/busses/i2c-exynos5.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**
   3  * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
   4  *
   5  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   6 */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10
  11 #include <linux/i2c.h>
  12 #include <linux/time.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/delay.h>
  15 #include <linux/errno.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/slab.h>
  20 #include <linux/io.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/spinlock.h>
  25
  26 /*
  27  * HSI2C controller from Samsung supports 2 modes of operation
  28  * 1. Auto mode: Where in master automatically controls the whole transaction
  29  * 2. Manual mode: Software controls the transaction by issuing commands
  30  *    START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
  31  *
  32  * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
  33  *
  34  * Special bits are available for both modes of operation to set commands
  35  * and for checking transfer status
  36  */
  37
  38 /* Register Map */
  39 #define HSI2C_CTL               0x00
  40 #define HSI2C_FIFO_CTL          0x04
  41 #define HSI2C_TRAILIG_CTL       0x08
  42 #define HSI2C_CLK_CTL           0x0C
  43 #define HSI2C_CLK_SLOT          0x10
  44 #define HSI2C_INT_ENABLE        0x20
  45 #define HSI2C_INT_STATUS        0x24
  46 #define HSI2C_ERR_STATUS        0x2C
  47 #define HSI2C_FIFO_STATUS       0x30
  48 #define HSI2C_TX_DATA           0x34
  49 #define HSI2C_RX_DATA           0x38
  50 #define HSI2C_CONF              0x40
  51 #define HSI2C_AUTO_CONF         0x44
  52 #define HSI2C_TIMEOUT           0x48
  53 #define HSI2C_MANUAL_CMD        0x4C
  54 #define HSI2C_TRANS_STATUS      0x50
  55 #define HSI2C_TIMING_HS1        0x54
  56 #define HSI2C_TIMING_HS2        0x58
  57 #define HSI2C_TIMING_HS3        0x5C
  58 #define HSI2C_TIMING_FS1        0x60
  59 #define HSI2C_TIMING_FS2        0x64
  60 #define HSI2C_TIMING_FS3        0x68
  61 #define HSI2C_TIMING_SLA        0x6C
  62 #define HSI2C_ADDR              0x70
  63
  64 /* I2C_CTL Register bits */
  65 #define HSI2C_FUNC_MODE_I2C                     (1u << 0)
  66 #define HSI2C_MASTER                            (1u << 3)
  67 #define HSI2C_RXCHON                            (1u << 6)
  68 #define HSI2C_TXCHON                            (1u << 7)
  69 #define HSI2C_SW_RST                            (1u << 31)
  70
  71 /* I2C_FIFO_CTL Register bits */
  72 #define HSI2C_RXFIFO_EN                         (1u << 0)
  73 #define HSI2C_TXFIFO_EN                         (1u << 1)
  74 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x)           ((x) << 4)
  75 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x)           ((x) << 16)
  76
  77 /* I2C_TRAILING_CTL Register bits */
  78 #define HSI2C_TRAILING_COUNT                    (0xf)
  79
  80 /* I2C_INT_EN Register bits */
  81 #define HSI2C_INT_TX_ALMOSTEMPTY_EN             (1u << 0)
  82 #define HSI2C_INT_RX_ALMOSTFULL_EN              (1u << 1)
  83 #define HSI2C_INT_TRAILING_EN                   (1u << 6)
  84
  85 /* I2C_INT_STAT Register bits */
  86 #define HSI2C_INT_TX_ALMOSTEMPTY                (1u << 0)
  87 #define HSI2C_INT_RX_ALMOSTFULL                 (1u << 1)
  88 #define HSI2C_INT_TX_UNDERRUN                   (1u << 2)
  89 #define HSI2C_INT_TX_OVERRUN                    (1u << 3)
  90 #define HSI2C_INT_RX_UNDERRUN                   (1u << 4)
  91 #define HSI2C_INT_RX_OVERRUN                    (1u << 5)
  92 #define HSI2C_INT_TRAILING                      (1u << 6)
  93 #define HSI2C_INT_I2C                           (1u << 9)
  94
  95 #define HSI2C_INT_TRANS_DONE                    (1u << 7)
  96 #define HSI2C_INT_TRANS_ABORT                   (1u << 8)
  97 #define HSI2C_INT_NO_DEV_ACK                    (1u << 9)
  98 #define HSI2C_INT_NO_DEV                        (1u << 10)
  99 #define HSI2C_INT_TIMEOUT                       (1u << 11)
 100 #define HSI2C_INT_I2C_TRANS                     (HSI2C_INT_TRANS_DONE | \
 101                                                 HSI2C_INT_TRANS_ABORT | \
 102                                                 HSI2C_INT_NO_DEV_ACK |  \
 103                                                 HSI2C_INT_NO_DEV |      \
 104                                                 HSI2C_INT_TIMEOUT)
 105
 106 /* I2C_FIFO_STAT Register bits */
 107 #define HSI2C_RX_FIFO_EMPTY                     (1u << 24)
 108 #define HSI2C_RX_FIFO_FULL                      (1u << 23)
 109 #define HSI2C_RX_FIFO_LVL(x)                    ((x >> 16) & 0x7f)
 110 #define HSI2C_TX_FIFO_EMPTY                     (1u << 8)
 111 #define HSI2C_TX_FIFO_FULL                      (1u << 7)
 112 #define HSI2C_TX_FIFO_LVL(x)                    ((x >> 0) & 0x7f)
 113
 114 /* I2C_CONF Register bits */
 115 #define HSI2C_AUTO_MODE                         (1u << 31)
 116 #define HSI2C_10BIT_ADDR_MODE                   (1u << 30)
 117 #define HSI2C_HS_MODE                           (1u << 29)
 118
 119 /* I2C_AUTO_CONF Register bits */
 120 #define HSI2C_READ_WRITE                        (1u << 16)
 121 #define HSI2C_STOP_AFTER_TRANS                  (1u << 17)
 122 #define HSI2C_MASTER_RUN                        (1u << 31)
 123
 124 /* I2C_TIMEOUT Register bits */
 125 #define HSI2C_TIMEOUT_EN                        (1u << 31)
 126 #define HSI2C_TIMEOUT_MASK                      0xff
 127
 128 /* I2C_MANUAL_CMD register bits */
 129 #define HSI2C_CMD_READ_DATA                     (1u << 4)
 130 #define HSI2C_CMD_SEND_STOP                     (1u << 2)
 131
 132 /* I2C_TRANS_STATUS register bits */
 133 #define HSI2C_MASTER_BUSY                       (1u << 17)
 134 #define HSI2C_SLAVE_BUSY                        (1u << 16)
 135
 136 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
 137 #define HSI2C_TIMEOUT_AUTO                      (1u << 4)
 138 #define HSI2C_NO_DEV                            (1u << 3)
 139 #define HSI2C_NO_DEV_ACK                        (1u << 2)
 140 #define HSI2C_TRANS_ABORT                       (1u << 1)
 141 #define HSI2C_TRANS_DONE                        (1u << 0)
 142
 143 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
 144 #define HSI2C_MASTER_ST_MASK                    0xf
 145 #define HSI2C_MASTER_ST_IDLE                    0x0
 146 #define HSI2C_MASTER_ST_START                   0x1
 147 #define HSI2C_MASTER_ST_RESTART                 0x2
 148 #define HSI2C_MASTER_ST_STOP                    0x3
 149 #define HSI2C_MASTER_ST_MASTER_ID               0x4
 150 #define HSI2C_MASTER_ST_ADDR0                   0x5
 151 #define HSI2C_MASTER_ST_ADDR1                   0x6
 152 #define HSI2C_MASTER_ST_ADDR2                   0x7
 153 #define HSI2C_MASTER_ST_ADDR_SR                 0x8
 154 #define HSI2C_MASTER_ST_READ                    0x9
 155 #define HSI2C_MASTER_ST_WRITE                   0xa
 156 #define HSI2C_MASTER_ST_NO_ACK                  0xb
 157 #define HSI2C_MASTER_ST_LOSE                    0xc
 158 #define HSI2C_MASTER_ST_WAIT                    0xd
 159 #define HSI2C_MASTER_ST_WAIT_CMD                0xe
 160
 161 /* I2C_ADDR register bits */
 162 #define HSI2C_SLV_ADDR_SLV(x)                   ((x & 0x3ff) << 0)
 163 #define HSI2C_SLV_ADDR_MAS(x)                   ((x & 0x3ff) << 10)
 164 #define HSI2C_MASTER_ID(x)                      ((x & 0xff) << 24)
 165 #define MASTER_ID(x)                            ((x & 0x7) + 0x08)
 166
 167 /*
 168  * Controller operating frequency, timing values for operation
 169  * are calculated against this frequency
 170  */
 171 #define HSI2C_HS_TX_CLOCK       1000000
 172 #define HSI2C_FS_TX_CLOCK       100000
 173
 174 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
 175
 176 enum i2c_type_exynos {
 177         I2C_TYPE_EXYNOS5,
 178         I2C_TYPE_EXYNOS7,
 179 };
 180
 181 struct exynos5_i2c {
 182         struct i2c_adapter      adap;
 183
 184         struct i2c_msg          *msg;
 185         struct completion       msg_complete;
 186         unsigned int            msg_ptr;
 187
 188         unsigned int            irq;
 189
 190         void __iomem            *regs;
 191         struct clk              *clk;
 192         struct device           *dev;
 193         int                     state;
 194
 195         spinlock_t              lock;           /* IRQ synchronization */
 196
 197         /*
 198          * Since the TRANS_DONE bit is cleared on read, and we may read it
 199          * either during an IRQ or after a transaction, keep track of its
 200          * state here.
 201          */
 202         int                     trans_done;
 203
 204         /* Controller operating frequency */
 205         unsigned int            op_clock;
 206
 207         /* Version of HS-I2C Hardware */
 208         const struct exynos_hsi2c_variant *variant;
 209 };
 210
 211 /**
 212  * struct exynos_hsi2c_variant - platform specific HSI2C driver data
 213  * @fifo_depth: the fifo depth supported by the HSI2C module
 214  * @hw: the hardware variant of Exynos I2C controller
 215  *
 216  * Specifies platform specific configuration of HSI2C module.
 217  * Note: A structure for driver specific platform data is used for future
 218  * expansion of its usage.
 219  */
 220 struct exynos_hsi2c_variant {
 221         unsigned int            fifo_depth;
 222         enum i2c_type_exynos    hw;
 223 };
 224
 225 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
 226         .fifo_depth     = 64,
 227         .hw             = I2C_TYPE_EXYNOS5,
 228 };
 229
 230 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
 231         .fifo_depth     = 16,
 232         .hw             = I2C_TYPE_EXYNOS5,
 233 };
 234
 235 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
 236         .fifo_depth     = 16,
 237         .hw             = I2C_TYPE_EXYNOS7,
 238 };
 239
 240 static const struct of_device_id exynos5_i2c_match[] = {
 241         {
 242                 .compatible = "samsung,exynos5-hsi2c",
 243                 .data = &exynos5250_hsi2c_data
 244         }, {
 245                 .compatible = "samsung,exynos5250-hsi2c",
 246                 .data = &exynos5250_hsi2c_data
 247         }, {
 248                 .compatible = "samsung,exynos5260-hsi2c",
 249                 .data = &exynos5260_hsi2c_data
 250         }, {
 251                 .compatible = "samsung,exynos7-hsi2c",
 252                 .data = &exynos7_hsi2c_data
 253         }, {},
 254 };
 255 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
 256
 257 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
 258 {
 259         writel(readl(i2c->regs + HSI2C_INT_STATUS),
 260                                 i2c->regs + HSI2C_INT_STATUS);
 261 }
 262
 263 /*
 264  * exynos5_i2c_set_timing: updates the registers with appropriate
 265  * timing values calculated
 266  *
 267  * Returns 0 on success, -EINVAL if the cycle length cannot
 268  * be calculated.
 269  */
 270 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
 271 {
 272         u32 i2c_timing_s1;
 273         u32 i2c_timing_s2;
 274         u32 i2c_timing_s3;
 275         u32 i2c_timing_sla;
 276         unsigned int t_start_su, t_start_hd;
 277         unsigned int t_stop_su;
 278         unsigned int t_data_su, t_data_hd;
 279         unsigned int t_scl_l, t_scl_h;
 280         unsigned int t_sr_release;
 281         unsigned int t_ftl_cycle;
 282         unsigned int clkin = clk_get_rate(i2c->clk);
 283         unsigned int op_clk = hs_timings ? i2c->op_clock :
 284                 (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK :
 285                 i2c->op_clock;
 286         int div, clk_cycle, temp;
 287
 288         /*
 289          * In case of HSI2C controller in Exynos5 series
 290          * FPCLK / FI2C =
 291          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
 292          *
 293          * In case of HSI2C controllers in Exynos7 series
 294          * FPCLK / FI2C =
 295          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
 296          *
 297          * clk_cycle := TSCLK_L + TSCLK_H
 298          * temp := (CLK_DIV + 1) * (clk_cycle + 2)
 299          *
 300          * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
 301          *
 302          */
 303         t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
 304         temp = clkin / op_clk - 8 - t_ftl_cycle;
 305         if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
 306                 temp -= t_ftl_cycle;
 307         div = temp / 512;
 308         clk_cycle = temp / (div + 1) - 2;
 309         if (temp < 4 || div >= 256 || clk_cycle < 2) {
 310                 dev_err(i2c->dev, "%s clock set-up failed\n",
 311                         hs_timings ? "HS" : "FS");
 312                 return -EINVAL;
 313         }
 314
 315         t_scl_l = clk_cycle / 2;
 316         t_scl_h = clk_cycle / 2;
 317         t_start_su = t_scl_l;
 318         t_start_hd = t_scl_l;
 319         t_stop_su = t_scl_l;
 320         t_data_su = t_scl_l / 2;
 321         t_data_hd = t_scl_l / 2;
 322         t_sr_release = clk_cycle;
 323
 324         i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
 325         i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
 326         i2c_timing_s3 = div << 16 | t_sr_release << 0;
 327         i2c_timing_sla = t_data_hd << 0;
 328
 329         dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
 330                 t_start_su, t_start_hd, t_stop_su);
 331         dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
 332                 t_data_su, t_scl_l, t_scl_h);
 333         dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
 334                 div, t_sr_release);
 335         dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
 336
 337         if (hs_timings) {
 338                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
 339                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
 340                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
 341         } else {
 342                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
 343                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
 344                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
 345         }
 346         writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
 347
 348         return 0;
 349 }
 350
 351 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
 352 {
 353         /* always set Fast Speed timings */
 354         int ret = exynos5_i2c_set_timing(i2c, false);
 355
 356         if (ret < 0 || i2c->op_clock < HSI2C_HS_TX_CLOCK)
 357                 return ret;
 358
 359         return exynos5_i2c_set_timing(i2c, true);
 360 }
 361
 362 /*
 363  * exynos5_i2c_init: configures the controller for I2C functionality
 364  * Programs I2C controller for Master mode operation
 365  */
 366 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
 367 {
 368         u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
 369         u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
 370
 371         /* Clear to disable Timeout */
 372         i2c_timeout &= ~HSI2C_TIMEOUT_EN;
 373         writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
 374
 375         writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 376                                         i2c->regs + HSI2C_CTL);
 377         writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
 378
 379         if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) {
 380                 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
 381                                         i2c->regs + HSI2C_ADDR);
 382                 i2c_conf |= HSI2C_HS_MODE;
 383         }
 384
 385         writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
 386 }
 387
 388 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
 389 {
 390         u32 i2c_ctl;
 391
 392         /* Set and clear the bit for reset */
 393         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 394         i2c_ctl |= HSI2C_SW_RST;
 395         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 396
 397         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 398         i2c_ctl &= ~HSI2C_SW_RST;
 399         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 400
 401         /* We don't expect calculations to fail during the run */
 402         exynos5_hsi2c_clock_setup(i2c);
 403         /* Initialize the configure registers */
 404         exynos5_i2c_init(i2c);
 405 }
 406
 407 /*
 408  * exynos5_i2c_irq: top level IRQ servicing routine
 409  *
 410  * INT_STATUS registers gives the interrupt details. Further,
 411  * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
 412  * state of the bus.
 413  */
 414 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
 415 {
 416         struct exynos5_i2c *i2c = dev_id;
 417         u32 fifo_level, int_status, fifo_status, trans_status;
 418         unsigned char byte;
 419         int len = 0;
 420
 421         i2c->state = -EINVAL;
 422
 423         spin_lock(&i2c->lock);
 424
 425         int_status = readl(i2c->regs + HSI2C_INT_STATUS);
 426         writel(int_status, i2c->regs + HSI2C_INT_STATUS);
 427
 428         /* handle interrupt related to the transfer status */
 429         if (i2c->variant->hw == I2C_TYPE_EXYNOS7) {
 430                 if (int_status & HSI2C_INT_TRANS_DONE) {
 431                         i2c->trans_done = 1;
 432                         i2c->state = 0;
 433                 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
 434                         dev_dbg(i2c->dev, "Deal with arbitration lose\n");
 435                         i2c->state = -EAGAIN;
 436                         goto stop;
 437                 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
 438                         dev_dbg(i2c->dev, "No ACK from device\n");
 439                         i2c->state = -ENXIO;
 440                         goto stop;
 441                 } else if (int_status & HSI2C_INT_NO_DEV) {
 442                         dev_dbg(i2c->dev, "No device\n");
 443                         i2c->state = -ENXIO;
 444                         goto stop;
 445                 } else if (int_status & HSI2C_INT_TIMEOUT) {
 446                         dev_dbg(i2c->dev, "Accessing device timed out\n");
 447                         i2c->state = -ETIMEDOUT;
 448                         goto stop;
 449                 }
 450         } else if (int_status & HSI2C_INT_I2C) {
 451                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 452                 if (trans_status & HSI2C_NO_DEV_ACK) {
 453                         dev_dbg(i2c->dev, "No ACK from device\n");
 454                         i2c->state = -ENXIO;
 455                         goto stop;
 456                 } else if (trans_status & HSI2C_NO_DEV) {
 457                         dev_dbg(i2c->dev, "No device\n");
 458                         i2c->state = -ENXIO;
 459                         goto stop;
 460                 } else if (trans_status & HSI2C_TRANS_ABORT) {
 461                         dev_dbg(i2c->dev, "Deal with arbitration lose\n");
 462                         i2c->state = -EAGAIN;
 463                         goto stop;
 464                 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
 465                         dev_dbg(i2c->dev, "Accessing device timed out\n");
 466                         i2c->state = -ETIMEDOUT;
 467                         goto stop;
 468                 } else if (trans_status & HSI2C_TRANS_DONE) {
 469                         i2c->trans_done = 1;
 470                         i2c->state = 0;
 471                 }
 472         }
 473
 474         if ((i2c->msg->flags & I2C_M_RD) && (int_status &
 475                         (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
 476                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 477                 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
 478                 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
 479
 480                 while (len > 0) {
 481                         byte = (unsigned char)
 482                                 readl(i2c->regs + HSI2C_RX_DATA);
 483                         i2c->msg->buf[i2c->msg_ptr++] = byte;
 484                         len--;
 485                 }
 486                 i2c->state = 0;
 487         } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
 488                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 489                 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
 490
 491                 len = i2c->variant->fifo_depth - fifo_level;
 492                 if (len > (i2c->msg->len - i2c->msg_ptr)) {
 493                         u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
 494
 495                         int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
 496                         writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
 497                         len = i2c->msg->len - i2c->msg_ptr;
 498                 }
 499
 500                 while (len > 0) {
 501                         byte = i2c->msg->buf[i2c->msg_ptr++];
 502                         writel(byte, i2c->regs + HSI2C_TX_DATA);
 503                         len--;
 504                 }
 505                 i2c->state = 0;
 506         }
 507
 508  stop:
 509         if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
 510             (i2c->state < 0)) {
 511                 writel(0, i2c->regs + HSI2C_INT_ENABLE);
 512                 exynos5_i2c_clr_pend_irq(i2c);
 513                 complete(&i2c->msg_complete);
 514         }
 515
 516         spin_unlock(&i2c->lock);
 517
 518         return IRQ_HANDLED;
 519 }
 520
 521 /*
 522  * exynos5_i2c_wait_bus_idle
 523  *
 524  * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
 525  * cleared.
 526  *
 527  * Returns -EBUSY if the bus cannot be bought to idle
 528  */
 529 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
 530 {
 531         unsigned long stop_time;
 532         u32 trans_status;
 533
 534         /* wait for 100 milli seconds for the bus to be idle */
 535         stop_time = jiffies + msecs_to_jiffies(100) + 1;
 536         do {
 537                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 538                 if (!(trans_status & HSI2C_MASTER_BUSY))
 539                         return 0;
 540
 541                 usleep_range(50, 200);
 542         } while (time_before(jiffies, stop_time));
 543
 544         return -EBUSY;
 545 }
 546
 547 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
 548 {
 549         u32 val;
 550
 551         val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;
 552         writel(val, i2c->regs + HSI2C_CTL);
 553         val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;
 554         writel(val, i2c->regs + HSI2C_CONF);
 555
 556         /*
 557          * Specification says master should send nine clock pulses. It can be
 558          * emulated by sending manual read command (nine pulses for read eight
 559          * bits + one pulse for NACK).
 560          */
 561         writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
 562         exynos5_i2c_wait_bus_idle(i2c);
 563         writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
 564         exynos5_i2c_wait_bus_idle(i2c);
 565
 566         val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;
 567         writel(val, i2c->regs + HSI2C_CTL);
 568         val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;
 569         writel(val, i2c->regs + HSI2C_CONF);
 570 }
 571
 572 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
 573 {
 574         unsigned long timeout;
 575
 576         if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
 577                 return;
 578
 579         /*
 580          * HSI2C_MASTER_ST_LOSE state in EXYNOS7 variant before transaction
 581          * indicates that bus is stuck (SDA is low). In such case bus recovery
 582          * can be performed.
 583          */
 584         timeout = jiffies + msecs_to_jiffies(100);
 585         for (;;) {
 586                 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);
 587
 588                 if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE)
 589                         return;
 590
 591                 if (time_is_before_jiffies(timeout))
 592                         return;
 593
 594                 exynos5_i2c_bus_recover(i2c);
 595         }
 596 }
 597
 598 /*
 599  * exynos5_i2c_message_start: Configures the bus and starts the xfer
 600  * i2c: struct exynos5_i2c pointer for the current bus
 601  * stop: Enables stop after transfer if set. Set for last transfer of
 602  *       in the list of messages.
 603  *
 604  * Configures the bus for read/write function
 605  * Sets chip address to talk to, message length to be sent.
 606  * Enables appropriate interrupts and sends start xfer command.
 607  */
 608 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
 609 {
 610         u32 i2c_ctl;
 611         u32 int_en = 0;
 612         u32 i2c_auto_conf = 0;
 613         u32 fifo_ctl;
 614         unsigned long flags;
 615         unsigned short trig_lvl;
 616
 617         if (i2c->variant->hw == I2C_TYPE_EXYNOS7)
 618                 int_en |= HSI2C_INT_I2C_TRANS;
 619         else
 620                 int_en |= HSI2C_INT_I2C;
 621
 622         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 623         i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
 624         fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
 625
 626         if (i2c->msg->flags & I2C_M_RD) {
 627                 i2c_ctl |= HSI2C_RXCHON;
 628
 629                 i2c_auto_conf |= HSI2C_READ_WRITE;
 630
 631                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 632                         (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
 633                 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
 634
 635                 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
 636                         HSI2C_INT_TRAILING_EN);
 637         } else {
 638                 i2c_ctl |= HSI2C_TXCHON;
 639
 640                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 641                         (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
 642                 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
 643
 644                 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
 645         }
 646
 647         writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
 648
 649         writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
 650         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 651
 652         exynos5_i2c_bus_check(i2c);
 653
 654         /*
 655          * Enable interrupts before starting the transfer so that we don't
 656          * miss any INT_I2C interrupts.
 657          */
 658         spin_lock_irqsave(&i2c->lock, flags);
 659         writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
 660
 661         if (stop == 1)
 662                 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
 663         i2c_auto_conf |= i2c->msg->len;
 664         i2c_auto_conf |= HSI2C_MASTER_RUN;
 665         writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
 666         spin_unlock_irqrestore(&i2c->lock, flags);
 667 }
 668
 669 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
 670                               struct i2c_msg *msgs, int stop)
 671 {
 672         unsigned long timeout;
 673         int ret;
 674
 675         i2c->msg = msgs;
 676         i2c->msg_ptr = 0;
 677         i2c->trans_done = 0;
 678
 679         reinit_completion(&i2c->msg_complete);
 680
 681         exynos5_i2c_message_start(i2c, stop);
 682
 683         timeout = wait_for_completion_timeout(&i2c->msg_complete,
 684                                               EXYNOS5_I2C_TIMEOUT);
 685         if (timeout == 0)
 686                 ret = -ETIMEDOUT;
 687         else
 688                 ret = i2c->state;
 689
 690         /*
 691          * If this is the last message to be transfered (stop == 1)
 692          * Then check if the bus can be brought back to idle.
 693          */
 694         if (ret == 0 && stop)
 695                 ret = exynos5_i2c_wait_bus_idle(i2c);
 696
 697         if (ret < 0) {
 698                 exynos5_i2c_reset(i2c);
 699                 if (ret == -ETIMEDOUT)
 700                         dev_warn(i2c->dev, "%s timeout\n",
 701                                  (msgs->flags & I2C_M_RD) ? "rx" : "tx");
 702         }
 703
 704         /* Return the state as in interrupt routine */
 705         return ret;
 706 }
 707
 708 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
 709                         struct i2c_msg *msgs, int num)
 710 {
 711         struct exynos5_i2c *i2c = adap->algo_data;
 712         int i, ret;
 713
 714         ret = clk_enable(i2c->clk);
 715         if (ret)
 716                 return ret;
 717
 718         for (i = 0; i < num; ++i) {
 719                 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);
 720                 if (ret)
 721                         break;
 722         }
 723
 724         clk_disable(i2c->clk);
 725
 726         return ret ?: num;
 727 }
 728
 729 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
 730 {
 731         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 732 }
 733
 734 static const struct i2c_algorithm exynos5_i2c_algorithm = {
 735         .master_xfer            = exynos5_i2c_xfer,
 736         .functionality          = exynos5_i2c_func,
 737 };
 738
 739 static int exynos5_i2c_probe(struct platform_device *pdev)
 740 {
 741         struct device_node *np = pdev->dev.of_node;
 742         struct exynos5_i2c *i2c;
 743         struct resource *mem;
 744         int ret;
 745
 746         i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
 747         if (!i2c)
 748                 return -ENOMEM;
 749
 750         if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
 751                 i2c->op_clock = HSI2C_FS_TX_CLOCK;
 752
 753         strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
 754         i2c->adap.owner   = THIS_MODULE;
 755         i2c->adap.algo    = &exynos5_i2c_algorithm;
 756         i2c->adap.retries = 3;
 757
 758         i2c->dev = &pdev->dev;
 759         i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
 760         if (IS_ERR(i2c->clk)) {
 761                 dev_err(&pdev->dev, "cannot get clock\n");
 762                 return -ENOENT;
 763         }
 764
 765         ret = clk_prepare_enable(i2c->clk);
 766         if (ret)
 767                 return ret;
 768
 769         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 770         i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
 771         if (IS_ERR(i2c->regs)) {
 772                 ret = PTR_ERR(i2c->regs);
 773                 goto err_clk;
 774         }
 775
 776         i2c->adap.dev.of_node = np;
 777         i2c->adap.algo_data = i2c;
 778         i2c->adap.dev.parent = &pdev->dev;
 779
 780         /* Clear pending interrupts from u-boot or misc causes */
 781         exynos5_i2c_clr_pend_irq(i2c);
 782
 783         spin_lock_init(&i2c->lock);
 784         init_completion(&i2c->msg_complete);
 785
 786         i2c->irq = ret = platform_get_irq(pdev, 0);
 787         if (ret <= 0) {
 788                 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
 789                 ret = -EINVAL;
 790                 goto err_clk;
 791         }
 792
 793         ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
 794                                IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);
 795         if (ret != 0) {
 796                 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
 797                 goto err_clk;
 798         }
 799
 800         i2c->variant = of_device_get_match_data(&pdev->dev);
 801
 802         ret = exynos5_hsi2c_clock_setup(i2c);
 803         if (ret)
 804                 goto err_clk;
 805
 806         exynos5_i2c_reset(i2c);
 807
 808         ret = i2c_add_adapter(&i2c->adap);
 809         if (ret < 0)
 810                 goto err_clk;
 811
 812         platform_set_drvdata(pdev, i2c);
 813
 814         clk_disable(i2c->clk);
 815
 816         return 0;
 817
 818  err_clk:
 819         clk_disable_unprepare(i2c->clk);
 820         return ret;
 821 }
 822
 823 static int exynos5_i2c_remove(struct platform_device *pdev)
 824 {
 825         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 826
 827         i2c_del_adapter(&i2c->adap);
 828
 829         clk_unprepare(i2c->clk);
 830
 831         return 0;
 832 }
 833
 834 #ifdef CONFIG_PM_SLEEP
 835 static int exynos5_i2c_suspend_noirq(struct device *dev)
 836 {
 837         struct exynos5_i2c *i2c = dev_get_drvdata(dev);
 838
 839         i2c_mark_adapter_suspended(&i2c->adap);
 840         clk_unprepare(i2c->clk);
 841
 842         return 0;
 843 }
 844
 845 static int exynos5_i2c_resume_noirq(struct device *dev)
 846 {
 847         struct exynos5_i2c *i2c = dev_get_drvdata(dev);
 848         int ret = 0;
 849
 850         ret = clk_prepare_enable(i2c->clk);
 851         if (ret)
 852                 return ret;
 853
 854         ret = exynos5_hsi2c_clock_setup(i2c);
 855         if (ret) {
 856                 clk_disable_unprepare(i2c->clk);
 857                 return ret;
 858         }
 859
 860         exynos5_i2c_init(i2c);
 861         clk_disable(i2c->clk);
 862         i2c_mark_adapter_resumed(&i2c->adap);
 863
 864         return 0;
 865 }
 866 #endif
 867
 868 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
 869         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
 870                                       exynos5_i2c_resume_noirq)
 871 };
 872
 873 static struct platform_driver exynos5_i2c_driver = {
 874         .probe          = exynos5_i2c_probe,
 875         .remove         = exynos5_i2c_remove,
 876         .driver         = {
 877                 .name   = "exynos5-hsi2c",
 878                 .pm     = &exynos5_i2c_dev_pm_ops,
 879                 .of_match_table = exynos5_i2c_match,
 880         },
 881 };
 882
 883 module_platform_driver(exynos5_i2c_driver);
 884
 885 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
 886 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
 887 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
 888 MODULE_LICENSE("GPL v2");