2 * TI DAVINCI I2C adapter driver.
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
7 * Updated by Vinod & Sudhakar Feb 2005
9 * ----------------------------------------------------------------------------
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * ----------------------------------------------------------------------------
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/i2c.h>
31 #include <linux/clk.h>
32 #include <linux/errno.h>
33 #include <linux/sched.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/platform_device.h>
38 #include <linux/slab.h>
39 #include <linux/cpufreq.h>
40 #include <linux/gpio.h>
41 #include <linux/of_device.h>
42 #include <linux/platform_data/i2c-davinci.h>
44 /* ----- global defines ----------------------------------------------- */
46 #define DAVINCI_I2C_TIMEOUT (1*HZ)
47 #define DAVINCI_I2C_MAX_TRIES 2
48 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
49 DAVINCI_I2C_IMR_SCD | \
50 DAVINCI_I2C_IMR_ARDY | \
51 DAVINCI_I2C_IMR_NACK | \
54 #define DAVINCI_I2C_OAR_REG 0x00
55 #define DAVINCI_I2C_IMR_REG 0x04
56 #define DAVINCI_I2C_STR_REG 0x08
57 #define DAVINCI_I2C_CLKL_REG 0x0c
58 #define DAVINCI_I2C_CLKH_REG 0x10
59 #define DAVINCI_I2C_CNT_REG 0x14
60 #define DAVINCI_I2C_DRR_REG 0x18
61 #define DAVINCI_I2C_SAR_REG 0x1c
62 #define DAVINCI_I2C_DXR_REG 0x20
63 #define DAVINCI_I2C_MDR_REG 0x24
64 #define DAVINCI_I2C_IVR_REG 0x28
65 #define DAVINCI_I2C_EMDR_REG 0x2c
66 #define DAVINCI_I2C_PSC_REG 0x30
68 #define DAVINCI_I2C_IVR_AAS 0x07
69 #define DAVINCI_I2C_IVR_SCD 0x06
70 #define DAVINCI_I2C_IVR_XRDY 0x05
71 #define DAVINCI_I2C_IVR_RDR 0x04
72 #define DAVINCI_I2C_IVR_ARDY 0x03
73 #define DAVINCI_I2C_IVR_NACK 0x02
74 #define DAVINCI_I2C_IVR_AL 0x01
76 #define DAVINCI_I2C_STR_BB BIT(12)
77 #define DAVINCI_I2C_STR_RSFULL BIT(11)
78 #define DAVINCI_I2C_STR_SCD BIT(5)
79 #define DAVINCI_I2C_STR_ARDY BIT(2)
80 #define DAVINCI_I2C_STR_NACK BIT(1)
81 #define DAVINCI_I2C_STR_AL BIT(0)
83 #define DAVINCI_I2C_MDR_NACK BIT(15)
84 #define DAVINCI_I2C_MDR_STT BIT(13)
85 #define DAVINCI_I2C_MDR_STP BIT(11)
86 #define DAVINCI_I2C_MDR_MST BIT(10)
87 #define DAVINCI_I2C_MDR_TRX BIT(9)
88 #define DAVINCI_I2C_MDR_XA BIT(8)
89 #define DAVINCI_I2C_MDR_RM BIT(7)
90 #define DAVINCI_I2C_MDR_IRS BIT(5)
92 #define DAVINCI_I2C_IMR_AAS BIT(6)
93 #define DAVINCI_I2C_IMR_SCD BIT(5)
94 #define DAVINCI_I2C_IMR_XRDY BIT(4)
95 #define DAVINCI_I2C_IMR_RRDY BIT(3)
96 #define DAVINCI_I2C_IMR_ARDY BIT(2)
97 #define DAVINCI_I2C_IMR_NACK BIT(1)
98 #define DAVINCI_I2C_IMR_AL BIT(0)
100 struct davinci_i2c_dev {
103 struct completion cmd_complete;
111 struct i2c_adapter adapter;
112 #ifdef CONFIG_CPU_FREQ
113 struct completion xfr_complete;
114 struct notifier_block freq_transition;
116 struct davinci_i2c_platform_data *pdata;
119 /* default platform data to use if not supplied in the platform_device */
120 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
125 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
128 writew_relaxed(val, i2c_dev->base + reg);
131 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
133 return readw_relaxed(i2c_dev->base + reg);
136 /* Generate a pulse on the i2c clock pin. */
137 static void davinci_i2c_clock_pulse(unsigned int scl_pin)
142 /* Send high and low on the SCL line */
143 for (i = 0; i < 9; i++) {
144 gpio_set_value(scl_pin, 0);
146 gpio_set_value(scl_pin, 1);
152 /* This routine does i2c bus recovery as specified in the
153 * i2c protocol Rev. 03 section 3.16 titled "Bus clear"
155 static void davinci_i2c_recover_bus(struct davinci_i2c_dev *dev)
158 struct davinci_i2c_platform_data *pdata = dev->pdata;
160 dev_err(dev->dev, "initiating i2c bus recovery\n");
161 /* Send NACK to the slave */
162 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
163 flag |= DAVINCI_I2C_MDR_NACK;
164 /* write the data into mode register */
165 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
166 davinci_i2c_clock_pulse(pdata->scl_pin);
168 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
169 flag |= DAVINCI_I2C_MDR_STP;
170 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
173 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
178 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
179 if (!val) /* put I2C into reset */
180 w &= ~DAVINCI_I2C_MDR_IRS;
181 else /* take I2C out of reset */
182 w |= DAVINCI_I2C_MDR_IRS;
184 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
187 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
189 struct davinci_i2c_platform_data *pdata = dev->pdata;
195 u32 input_clock = clk_get_rate(dev->clk);
197 /* NOTE: I2C Clock divider programming info
198 * As per I2C specs the following formulas provide prescaler
199 * and low/high divider values
200 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
203 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
206 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
208 * where if PSC == 0, d = 7,
213 /* get minimum of 7 MHz clock, but max of 12 MHz */
214 psc = (input_clock / 7000000) - 1;
215 if ((input_clock / (psc + 1)) > 12000000)
216 psc++; /* better to run under spec than over */
217 d = (psc >= 2) ? 5 : 7 - psc;
219 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
223 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
224 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
225 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
227 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
231 * This function configures I2C and brings I2C out of reset.
232 * This function is called during I2C init function. This function
233 * also gets called if I2C encounters any errors.
235 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
237 struct davinci_i2c_platform_data *pdata = dev->pdata;
239 /* put I2C into reset */
240 davinci_i2c_reset_ctrl(dev, 0);
242 /* compute clock dividers */
243 i2c_davinci_calc_clk_dividers(dev);
245 /* Respond at reserved "SMBus Host" slave address" (and zero);
246 * we seem to have no option to not respond...
248 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
250 dev_dbg(dev->dev, "PSC = %d\n",
251 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
252 dev_dbg(dev->dev, "CLKL = %d\n",
253 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
254 dev_dbg(dev->dev, "CLKH = %d\n",
255 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
256 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
257 pdata->bus_freq, pdata->bus_delay);
260 /* Take the I2C module out of reset: */
261 davinci_i2c_reset_ctrl(dev, 1);
263 /* Enable interrupts */
264 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
270 * Waiting for bus not busy
272 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
275 unsigned long timeout;
278 timeout = jiffies + dev->adapter.timeout;
279 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
280 & DAVINCI_I2C_STR_BB) {
281 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
282 if (time_after(jiffies, timeout)) {
284 "timeout waiting for bus ready\n");
289 davinci_i2c_recover_bus(dev);
290 i2c_davinci_init(dev);
301 * Low level master read/write transaction. This function is called
302 * from i2c_davinci_xfer.
305 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
307 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
308 struct davinci_i2c_platform_data *pdata = dev->pdata;
313 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
314 if (pdata->bus_delay)
315 udelay(pdata->bus_delay);
317 /* set the slave address */
318 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
321 dev->buf_len = msg->len;
324 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
326 reinit_completion(&dev->cmd_complete);
329 /* Take I2C out of reset and configure it as master */
330 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
332 /* if the slave address is ten bit address, enable XA bit */
333 if (msg->flags & I2C_M_TEN)
334 flag |= DAVINCI_I2C_MDR_XA;
335 if (!(msg->flags & I2C_M_RD))
336 flag |= DAVINCI_I2C_MDR_TRX;
338 flag |= DAVINCI_I2C_MDR_RM;
340 /* Enable receive or transmit interrupts */
341 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
342 if (msg->flags & I2C_M_RD)
343 w |= DAVINCI_I2C_IMR_RRDY;
345 w |= DAVINCI_I2C_IMR_XRDY;
346 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
351 * Write mode register first as needed for correct behaviour
352 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
353 * occurring before we have loaded DXR
355 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
358 * First byte should be set here, not after interrupt,
359 * because transmit-data-ready interrupt can come before
360 * NACK-interrupt during sending of previous message and
361 * ICDXR may have wrong data
362 * It also saves us one interrupt, slightly faster
364 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
365 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
369 /* Set STT to begin transmit now DXR is loaded */
370 flag |= DAVINCI_I2C_MDR_STT;
371 if (stop && msg->len != 0)
372 flag |= DAVINCI_I2C_MDR_STP;
373 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
375 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
376 dev->adapter.timeout);
378 dev_err(dev->dev, "controller timed out\n");
379 davinci_i2c_recover_bus(dev);
380 i2c_davinci_init(dev);
385 /* This should be 0 if all bytes were transferred
386 * or dev->cmd_err denotes an error.
387 * A signal may have aborted the transfer.
390 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
402 if (likely(!dev->cmd_err))
405 /* We have an error */
406 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
407 i2c_davinci_init(dev);
411 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
412 if (msg->flags & I2C_M_IGNORE_NAK)
414 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
415 w |= DAVINCI_I2C_MDR_STP;
416 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
423 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
426 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
428 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
432 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
434 ret = i2c_davinci_wait_bus_not_busy(dev, 1);
436 dev_warn(dev->dev, "timeout waiting for bus ready\n");
440 for (i = 0; i < num; i++) {
441 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
442 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
448 #ifdef CONFIG_CPU_FREQ
449 complete(&dev->xfr_complete);
455 static u32 i2c_davinci_func(struct i2c_adapter *adap)
457 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
460 static void terminate_read(struct davinci_i2c_dev *dev)
462 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
463 w |= DAVINCI_I2C_MDR_NACK;
464 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
466 /* Throw away data */
467 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
469 dev_err(dev->dev, "RDR IRQ while no data requested\n");
471 static void terminate_write(struct davinci_i2c_dev *dev)
473 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
474 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
475 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
478 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
482 * Interrupt service routine. This gets called whenever an I2C interrupt
485 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
487 struct davinci_i2c_dev *dev = dev_id;
492 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
493 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
494 if (count++ == 100) {
495 dev_warn(dev->dev, "Too much work in one IRQ\n");
500 case DAVINCI_I2C_IVR_AL:
501 /* Arbitration lost, must retry */
502 dev->cmd_err |= DAVINCI_I2C_STR_AL;
504 complete(&dev->cmd_complete);
507 case DAVINCI_I2C_IVR_NACK:
508 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
510 complete(&dev->cmd_complete);
513 case DAVINCI_I2C_IVR_ARDY:
514 davinci_i2c_write_reg(dev,
515 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
516 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
517 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
518 w = davinci_i2c_read_reg(dev,
519 DAVINCI_I2C_MDR_REG);
520 w |= DAVINCI_I2C_MDR_STP;
521 davinci_i2c_write_reg(dev,
522 DAVINCI_I2C_MDR_REG, w);
524 complete(&dev->cmd_complete);
527 case DAVINCI_I2C_IVR_RDR:
530 davinci_i2c_read_reg(dev,
531 DAVINCI_I2C_DRR_REG);
536 davinci_i2c_write_reg(dev,
538 DAVINCI_I2C_IMR_RRDY);
540 /* signal can terminate transfer */
545 case DAVINCI_I2C_IVR_XRDY:
547 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
553 w = davinci_i2c_read_reg(dev,
554 DAVINCI_I2C_IMR_REG);
555 w &= ~DAVINCI_I2C_IMR_XRDY;
556 davinci_i2c_write_reg(dev,
560 /* signal can terminate transfer */
561 terminate_write(dev);
565 case DAVINCI_I2C_IVR_SCD:
566 davinci_i2c_write_reg(dev,
567 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
568 complete(&dev->cmd_complete);
571 case DAVINCI_I2C_IVR_AAS:
572 dev_dbg(dev->dev, "Address as slave interrupt\n");
576 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
581 return count ? IRQ_HANDLED : IRQ_NONE;
584 #ifdef CONFIG_CPU_FREQ
585 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
586 unsigned long val, void *data)
588 struct davinci_i2c_dev *dev;
590 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
591 if (val == CPUFREQ_PRECHANGE) {
592 wait_for_completion(&dev->xfr_complete);
593 davinci_i2c_reset_ctrl(dev, 0);
594 } else if (val == CPUFREQ_POSTCHANGE) {
595 i2c_davinci_calc_clk_dividers(dev);
596 davinci_i2c_reset_ctrl(dev, 1);
602 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
604 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
606 return cpufreq_register_notifier(&dev->freq_transition,
607 CPUFREQ_TRANSITION_NOTIFIER);
610 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
612 cpufreq_unregister_notifier(&dev->freq_transition,
613 CPUFREQ_TRANSITION_NOTIFIER);
616 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
621 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
626 static struct i2c_algorithm i2c_davinci_algo = {
627 .master_xfer = i2c_davinci_xfer,
628 .functionality = i2c_davinci_func,
631 static const struct of_device_id davinci_i2c_of_match[] = {
632 {.compatible = "ti,davinci-i2c", },
635 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
637 static int davinci_i2c_probe(struct platform_device *pdev)
639 struct davinci_i2c_dev *dev;
640 struct i2c_adapter *adap;
641 struct resource *mem, *irq;
644 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
646 dev_err(&pdev->dev, "no irq resource?\n");
650 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
653 dev_err(&pdev->dev, "Memory allocation failed\n");
657 init_completion(&dev->cmd_complete);
658 #ifdef CONFIG_CPU_FREQ
659 init_completion(&dev->xfr_complete);
661 dev->dev = &pdev->dev;
662 dev->irq = irq->start;
663 dev->pdata = dev_get_platdata(&pdev->dev);
664 platform_set_drvdata(pdev, dev);
666 if (!dev->pdata && pdev->dev.of_node) {
669 dev->pdata = devm_kzalloc(&pdev->dev,
670 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
674 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
675 sizeof(struct davinci_i2c_platform_data));
676 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
678 dev->pdata->bus_freq = prop / 1000;
679 } else if (!dev->pdata) {
680 dev->pdata = &davinci_i2c_platform_data_default;
683 dev->clk = devm_clk_get(&pdev->dev, NULL);
684 if (IS_ERR(dev->clk))
686 clk_prepare_enable(dev->clk);
688 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
689 dev->base = devm_ioremap_resource(&pdev->dev, mem);
690 if (IS_ERR(dev->base)) {
691 r = PTR_ERR(dev->base);
692 goto err_unuse_clocks;
695 i2c_davinci_init(dev);
697 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
700 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
701 goto err_unuse_clocks;
704 r = i2c_davinci_cpufreq_register(dev);
706 dev_err(&pdev->dev, "failed to register cpufreq\n");
707 goto err_unuse_clocks;
710 adap = &dev->adapter;
711 i2c_set_adapdata(adap, dev);
712 adap->owner = THIS_MODULE;
713 adap->class = I2C_CLASS_HWMON;
714 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
715 adap->algo = &i2c_davinci_algo;
716 adap->dev.parent = &pdev->dev;
717 adap->timeout = DAVINCI_I2C_TIMEOUT;
718 adap->dev.of_node = pdev->dev.of_node;
721 r = i2c_add_numbered_adapter(adap);
723 dev_err(&pdev->dev, "failure adding adapter\n");
724 goto err_unuse_clocks;
730 clk_disable_unprepare(dev->clk);
735 static int davinci_i2c_remove(struct platform_device *pdev)
737 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
739 i2c_davinci_cpufreq_deregister(dev);
741 i2c_del_adapter(&dev->adapter);
743 clk_disable_unprepare(dev->clk);
746 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
752 static int davinci_i2c_suspend(struct device *dev)
754 struct platform_device *pdev = to_platform_device(dev);
755 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
757 /* put I2C into reset */
758 davinci_i2c_reset_ctrl(i2c_dev, 0);
759 clk_disable_unprepare(i2c_dev->clk);
764 static int davinci_i2c_resume(struct device *dev)
766 struct platform_device *pdev = to_platform_device(dev);
767 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
769 clk_prepare_enable(i2c_dev->clk);
770 /* take I2C out of reset */
771 davinci_i2c_reset_ctrl(i2c_dev, 1);
776 static const struct dev_pm_ops davinci_i2c_pm = {
777 .suspend = davinci_i2c_suspend,
778 .resume = davinci_i2c_resume,
781 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
783 #define davinci_i2c_pm_ops NULL
786 /* work with hotplug and coldplug */
787 MODULE_ALIAS("platform:i2c_davinci");
789 static struct platform_driver davinci_i2c_driver = {
790 .probe = davinci_i2c_probe,
791 .remove = davinci_i2c_remove,
793 .name = "i2c_davinci",
794 .owner = THIS_MODULE,
795 .pm = davinci_i2c_pm_ops,
796 .of_match_table = davinci_i2c_of_match,
800 /* I2C may be needed to bring up other drivers */
801 static int __init davinci_i2c_init_driver(void)
803 return platform_driver_register(&davinci_i2c_driver);
805 subsys_initcall(davinci_i2c_init_driver);
807 static void __exit davinci_i2c_exit_driver(void)
809 platform_driver_unregister(&davinci_i2c_driver);
811 module_exit(davinci_i2c_exit_driver);
813 MODULE_AUTHOR("Texas Instruments India");
814 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
815 MODULE_LICENSE("GPL");