drivers/hid/intel-ish-hid/ipc/ipc.c

   1 /*
   2  * H/W layer of ISHTP provider device (ISH)
   3  *
   4  * Copyright (c) 2014-2016, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/sched.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/delay.h>
  19 #include <linux/jiffies.h>
  20 #include "client.h"
  21 #include "hw-ish.h"
  22 #include "hbm.h"
  23
  24 /* For FW reset flow */
  25 static struct work_struct fw_reset_work;
  26 static struct ishtp_device *ishtp_dev;
  27
  28 /**
  29  * ish_reg_read() - Read register
  30  * @dev: ISHTP device pointer
  31  * @offset: Register offset
  32  *
  33  * Read 32 bit register at a given offset
  34  *
  35  * Return: Read register value
  36  */
  37 static inline uint32_t ish_reg_read(const struct ishtp_device *dev,
  38         unsigned long offset)
  39 {
  40         struct ish_hw *hw = to_ish_hw(dev);
  41
  42         return readl(hw->mem_addr + offset);
  43 }
  44
  45 /**
  46  * ish_reg_write() - Write register
  47  * @dev: ISHTP device pointer
  48  * @offset: Register offset
  49  * @value: Value to write
  50  *
  51  * Writes 32 bit register at a give offset
  52  */
  53 static inline void ish_reg_write(struct ishtp_device *dev,
  54                                  unsigned long offset,
  55                                  uint32_t value)
  56 {
  57         struct ish_hw *hw = to_ish_hw(dev);
  58
  59         writel(value, hw->mem_addr + offset);
  60 }
  61
  62 /**
  63  * _ish_read_fw_sts_reg() - Read FW status register
  64  * @dev: ISHTP device pointer
  65  *
  66  * Read FW status register
  67  *
  68  * Return: Read register value
  69  */
  70 static inline uint32_t _ish_read_fw_sts_reg(struct ishtp_device *dev)
  71 {
  72         return ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
  73 }
  74
  75 /**
  76  * check_generated_interrupt() - Check if ISH interrupt
  77  * @dev: ISHTP device pointer
  78  *
  79  * Check if an interrupt was generated for ISH
  80  *
  81  * Return: Read true or false
  82  */
  83 static bool check_generated_interrupt(struct ishtp_device *dev)
  84 {
  85         bool interrupt_generated = true;
  86         uint32_t pisr_val = 0;
  87
  88         if (dev->pdev->device == CHV_DEVICE_ID) {
  89                 pisr_val = ish_reg_read(dev, IPC_REG_PISR_CHV_AB);
  90                 interrupt_generated =
  91                         IPC_INT_FROM_ISH_TO_HOST_CHV_AB(pisr_val);
  92         } else {
  93                 pisr_val = ish_reg_read(dev, IPC_REG_PISR_BXT);
  94                 interrupt_generated = !!pisr_val;
  95                 /* only busy-clear bit is RW, others are RO */
  96                 if (pisr_val)
  97                         ish_reg_write(dev, IPC_REG_PISR_BXT, pisr_val);
  98         }
  99
 100         return interrupt_generated;
 101 }
 102
 103 /**
 104  * ish_is_input_ready() - Check if FW ready for RX
 105  * @dev: ISHTP device pointer
 106  *
 107  * Check if ISH FW is ready for receiving data
 108  *
 109  * Return: Read true or false
 110  */
 111 static bool ish_is_input_ready(struct ishtp_device *dev)
 112 {
 113         uint32_t doorbell_val;
 114
 115         doorbell_val = ish_reg_read(dev, IPC_REG_HOST2ISH_DRBL);
 116         return !IPC_IS_BUSY(doorbell_val);
 117 }
 118
 119 /**
 120  * set_host_ready() - Indicate host ready
 121  * @dev: ISHTP device pointer
 122  *
 123  * Set host ready indication to FW
 124  */
 125 static void set_host_ready(struct ishtp_device *dev)
 126 {
 127         if (dev->pdev->device == CHV_DEVICE_ID) {
 128                 if (dev->pdev->revision == REVISION_ID_CHT_A0 ||
 129                                 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
 130                                 REVISION_ID_CHT_Ax_SI)
 131                         ish_reg_write(dev, IPC_REG_HOST_COMM, 0x81);
 132                 else if (dev->pdev->revision == REVISION_ID_CHT_B0 ||
 133                                 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
 134                                 REVISION_ID_CHT_Bx_SI ||
 135                                 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
 136                                 REVISION_ID_CHT_Kx_SI ||
 137                                 (dev->pdev->revision & REVISION_ID_SI_MASK) ==
 138                                 REVISION_ID_CHT_Dx_SI) {
 139                         uint32_t host_comm_val;
 140
 141                         host_comm_val = ish_reg_read(dev, IPC_REG_HOST_COMM);
 142                         host_comm_val |= IPC_HOSTCOMM_INT_EN_BIT_CHV_AB | 0x81;
 143                         ish_reg_write(dev, IPC_REG_HOST_COMM, host_comm_val);
 144                 }
 145         } else {
 146                         uint32_t host_pimr_val;
 147
 148                         host_pimr_val = ish_reg_read(dev, IPC_REG_PIMR_BXT);
 149                         host_pimr_val |= IPC_PIMR_INT_EN_BIT_BXT;
 150                         /*
 151                          * disable interrupt generated instead of
 152                          * RX_complete_msg
 153                          */
 154                         host_pimr_val &= ~IPC_HOST2ISH_BUSYCLEAR_MASK_BIT;
 155
 156                         ish_reg_write(dev, IPC_REG_PIMR_BXT, host_pimr_val);
 157         }
 158 }
 159
 160 /**
 161  * ishtp_fw_is_ready() - Check if FW ready
 162  * @dev: ISHTP device pointer
 163  *
 164  * Check if ISH FW is ready
 165  *
 166  * Return: Read true or false
 167  */
 168 static bool ishtp_fw_is_ready(struct ishtp_device *dev)
 169 {
 170         uint32_t ish_status = _ish_read_fw_sts_reg(dev);
 171
 172         return IPC_IS_ISH_ILUP(ish_status) &&
 173                 IPC_IS_ISH_ISHTP_READY(ish_status);
 174 }
 175
 176 /**
 177  * ish_set_host_rdy() - Indicate host ready
 178  * @dev: ISHTP device pointer
 179  *
 180  * Set host ready indication to FW
 181  */
 182 static void ish_set_host_rdy(struct ishtp_device *dev)
 183 {
 184         uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM);
 185
 186         IPC_SET_HOST_READY(host_status);
 187         ish_reg_write(dev, IPC_REG_HOST_COMM, host_status);
 188 }
 189
 190 /**
 191  * ish_clr_host_rdy() - Indicate host not ready
 192  * @dev: ISHTP device pointer
 193  *
 194  * Send host not ready indication to FW
 195  */
 196 static void ish_clr_host_rdy(struct ishtp_device *dev)
 197 {
 198         uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM);
 199
 200         IPC_CLEAR_HOST_READY(host_status);
 201         ish_reg_write(dev, IPC_REG_HOST_COMM, host_status);
 202 }
 203
 204 /**
 205  * _ishtp_read_hdr() - Read message header
 206  * @dev: ISHTP device pointer
 207  *
 208  * Read header of 32bit length
 209  *
 210  * Return: Read register value
 211  */
 212 static uint32_t _ishtp_read_hdr(const struct ishtp_device *dev)
 213 {
 214         return ish_reg_read(dev, IPC_REG_ISH2HOST_MSG);
 215 }
 216
 217 /**
 218  * _ishtp_read - Read message
 219  * @dev: ISHTP device pointer
 220  * @buffer: message buffer
 221  * @buffer_length: length of message buffer
 222  *
 223  * Read message from FW
 224  *
 225  * Return: Always 0
 226  */
 227 static int _ishtp_read(struct ishtp_device *dev, unsigned char *buffer,
 228         unsigned long buffer_length)
 229 {
 230         uint32_t        i;
 231         uint32_t        *r_buf = (uint32_t *)buffer;
 232         uint32_t        msg_offs;
 233
 234         msg_offs = IPC_REG_ISH2HOST_MSG + sizeof(struct ishtp_msg_hdr);
 235         for (i = 0; i < buffer_length; i += sizeof(uint32_t))
 236                 *r_buf++ = ish_reg_read(dev, msg_offs + i);
 237
 238         return 0;
 239 }
 240
 241 /**
 242  * write_ipc_from_queue() - try to write ipc msg from Tx queue to device
 243  * @dev: ishtp device pointer
 244  *
 245  * Check if DRBL is cleared. if it is - write the first IPC msg,  then call
 246  * the callback function (unless it's NULL)
 247  *
 248  * Return: 0 for success else failure code
 249  */
 250 static int write_ipc_from_queue(struct ishtp_device *dev)
 251 {
 252         struct wr_msg_ctl_info  *ipc_link;
 253         unsigned long   length;
 254         unsigned long   rem;
 255         unsigned long   flags;
 256         uint32_t        doorbell_val;
 257         uint32_t        *r_buf;
 258         uint32_t        reg_addr;
 259         int     i;
 260         void    (*ipc_send_compl)(void *);
 261         void    *ipc_send_compl_prm;
 262         static int      out_ipc_locked;
 263         unsigned long   out_ipc_flags;
 264
 265         if (dev->dev_state == ISHTP_DEV_DISABLED)
 266                 return  -EINVAL;
 267
 268         spin_lock_irqsave(&dev->out_ipc_spinlock, out_ipc_flags);
 269         if (out_ipc_locked) {
 270                 spin_unlock_irqrestore(&dev->out_ipc_spinlock, out_ipc_flags);
 271                 return -EBUSY;
 272         }
 273         out_ipc_locked = 1;
 274         if (!ish_is_input_ready(dev)) {
 275                 out_ipc_locked = 0;
 276                 spin_unlock_irqrestore(&dev->out_ipc_spinlock, out_ipc_flags);
 277                 return -EBUSY;
 278         }
 279         spin_unlock_irqrestore(&dev->out_ipc_spinlock, out_ipc_flags);
 280
 281         spin_lock_irqsave(&dev->wr_processing_spinlock, flags);
 282         /*
 283          * if tx send list is empty - return 0;
 284          * may happen, as RX_COMPLETE handler doesn't check list emptiness.
 285          */
 286         if (list_empty(&dev->wr_processing_list_head.link)) {
 287                 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
 288                 out_ipc_locked = 0;
 289                 return  0;
 290         }
 291
 292         ipc_link = list_entry(dev->wr_processing_list_head.link.next,
 293                               struct wr_msg_ctl_info, link);
 294         /* first 4 bytes of the data is the doorbell value (IPC header) */
 295         length = ipc_link->length - sizeof(uint32_t);
 296         doorbell_val = *(uint32_t *)ipc_link->inline_data;
 297         r_buf = (uint32_t *)(ipc_link->inline_data + sizeof(uint32_t));
 298
 299         /* If sending MNG_SYNC_FW_CLOCK, update clock again */
 300         if (IPC_HEADER_GET_PROTOCOL(doorbell_val) == IPC_PROTOCOL_MNG &&
 301                 IPC_HEADER_GET_MNG_CMD(doorbell_val) == MNG_SYNC_FW_CLOCK) {
 302                 uint64_t usec_system, usec_utc;
 303                 struct ipc_time_update_msg time_update;
 304                 struct time_sync_format ts_format;
 305
 306                 usec_system = ktime_to_us(ktime_get_boottime());
 307                 usec_utc = ktime_to_us(ktime_get_real());
 308                 ts_format.ts1_source = HOST_SYSTEM_TIME_USEC;
 309                 ts_format.ts2_source = HOST_UTC_TIME_USEC;
 310                 ts_format.reserved = 0;
 311
 312                 time_update.primary_host_time = usec_system;
 313                 time_update.secondary_host_time = usec_utc;
 314                 time_update.sync_info = ts_format;
 315
 316                 memcpy(r_buf, &time_update,
 317                        sizeof(struct ipc_time_update_msg));
 318         }
 319
 320         for (i = 0, reg_addr = IPC_REG_HOST2ISH_MSG; i < length >> 2; i++,
 321                         reg_addr += 4)
 322                 ish_reg_write(dev, reg_addr, r_buf[i]);
 323
 324         rem = length & 0x3;
 325         if (rem > 0) {
 326                 uint32_t reg = 0;
 327
 328                 memcpy(&reg, &r_buf[length >> 2], rem);
 329                 ish_reg_write(dev, reg_addr, reg);
 330         }
 331         /* Flush writes to msg registers and doorbell */
 332         ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
 333
 334         /* Update IPC counters */
 335         ++dev->ipc_tx_cnt;
 336         dev->ipc_tx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val);
 337
 338         ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, doorbell_val);
 339         out_ipc_locked = 0;
 340
 341         ipc_send_compl = ipc_link->ipc_send_compl;
 342         ipc_send_compl_prm = ipc_link->ipc_send_compl_prm;
 343         list_del_init(&ipc_link->link);
 344         list_add_tail(&ipc_link->link, &dev->wr_free_list_head.link);
 345         spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
 346
 347         /*
 348          * callback will be called out of spinlock,
 349          * after ipc_link returned to free list
 350          */
 351         if (ipc_send_compl)
 352                 ipc_send_compl(ipc_send_compl_prm);
 353
 354         return 0;
 355 }
 356
 357 /**
 358  * write_ipc_to_queue() - write ipc msg to Tx queue
 359  * @dev: ishtp device instance
 360  * @ipc_send_compl: Send complete callback
 361  * @ipc_send_compl_prm: Parameter to send in complete callback
 362  * @msg: Pointer to message
 363  * @length: Length of message
 364  *
 365  * Recived msg with IPC (and upper protocol) header  and add it to the device
 366  *  Tx-to-write list then try to send the first IPC waiting msg
 367  *  (if DRBL is cleared)
 368  * This function returns negative value for failure (means free list
 369  *  is empty, or msg too long) and 0 for success.
 370  *
 371  * Return: 0 for success else failure code
 372  */
 373 static int write_ipc_to_queue(struct ishtp_device *dev,
 374         void (*ipc_send_compl)(void *), void *ipc_send_compl_prm,
 375         unsigned char *msg, int length)
 376 {
 377         struct wr_msg_ctl_info *ipc_link;
 378         unsigned long   flags;
 379
 380         if (length > IPC_FULL_MSG_SIZE)
 381                 return -EMSGSIZE;
 382
 383         spin_lock_irqsave(&dev->wr_processing_spinlock, flags);
 384         if (list_empty(&dev->wr_free_list_head.link)) {
 385                 spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
 386                 return -ENOMEM;
 387         }
 388         ipc_link = list_entry(dev->wr_free_list_head.link.next,
 389                 struct wr_msg_ctl_info, link);
 390         list_del_init(&ipc_link->link);
 391
 392         ipc_link->ipc_send_compl = ipc_send_compl;
 393         ipc_link->ipc_send_compl_prm = ipc_send_compl_prm;
 394         ipc_link->length = length;
 395         memcpy(ipc_link->inline_data, msg, length);
 396
 397         list_add_tail(&ipc_link->link, &dev->wr_processing_list_head.link);
 398         spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
 399
 400         write_ipc_from_queue(dev);
 401
 402         return 0;
 403 }
 404
 405 /**
 406  * ipc_send_mng_msg() - Send management message
 407  * @dev: ishtp device instance
 408  * @msg_code: Message code
 409  * @msg: Pointer to message
 410  * @size: Length of message
 411  *
 412  * Send management message to FW
 413  *
 414  * Return: 0 for success else failure code
 415  */
 416 static int ipc_send_mng_msg(struct ishtp_device *dev, uint32_t msg_code,
 417         void *msg, size_t size)
 418 {
 419         unsigned char   ipc_msg[IPC_FULL_MSG_SIZE];
 420         uint32_t        drbl_val = IPC_BUILD_MNG_MSG(msg_code, size);
 421
 422         memcpy(ipc_msg, &drbl_val, sizeof(uint32_t));
 423         memcpy(ipc_msg + sizeof(uint32_t), msg, size);
 424         return  write_ipc_to_queue(dev, NULL, NULL, ipc_msg,
 425                 sizeof(uint32_t) + size);
 426 }
 427
 428 #define WAIT_FOR_FW_RDY                 0x1
 429 #define WAIT_FOR_INPUT_RDY              0x2
 430
 431 /**
 432  * timed_wait_for_timeout() - wait special event with timeout
 433  * @dev: ISHTP device pointer
 434  * @condition: indicate the condition for waiting
 435  * @timeinc: time slice for every wait cycle, in ms
 436  * @timeout: time in ms for timeout
 437  *
 438  * This function will check special event to be ready in a loop, the loop
 439  * period is specificd in timeinc. Wait timeout will causes failure.
 440  *
 441  * Return: 0 for success else failure code
 442  */
 443 static int timed_wait_for_timeout(struct ishtp_device *dev, int condition,
 444                                 unsigned int timeinc, unsigned int timeout)
 445 {
 446         bool complete = false;
 447         int ret;
 448
 449         do {
 450                 if (condition == WAIT_FOR_FW_RDY) {
 451                         complete = ishtp_fw_is_ready(dev);
 452                 } else if (condition == WAIT_FOR_INPUT_RDY) {
 453                         complete = ish_is_input_ready(dev);
 454                 } else {
 455                         ret = -EINVAL;
 456                         goto out;
 457                 }
 458
 459                 if (!complete) {
 460                         unsigned long left_time;
 461
 462                         left_time = msleep_interruptible(timeinc);
 463                         timeout -= (timeinc - left_time);
 464                 }
 465         } while (!complete && timeout > 0);
 466
 467         if (complete)
 468                 ret = 0;
 469         else
 470                 ret = -EBUSY;
 471
 472 out:
 473         return ret;
 474 }
 475
 476 #define TIME_SLICE_FOR_FW_RDY_MS                100
 477 #define TIME_SLICE_FOR_INPUT_RDY_MS             100
 478 #define TIMEOUT_FOR_FW_RDY_MS                   2000
 479 #define TIMEOUT_FOR_INPUT_RDY_MS                2000
 480
 481 /**
 482  * ish_fw_reset_handler() - FW reset handler
 483  * @dev: ishtp device pointer
 484  *
 485  * Handle FW reset
 486  *
 487  * Return: 0 for success else failure code
 488  */
 489 static int ish_fw_reset_handler(struct ishtp_device *dev)
 490 {
 491         uint32_t        reset_id;
 492         unsigned long   flags;
 493         struct wr_msg_ctl_info *processing, *next;
 494
 495         /* Read reset ID */
 496         reset_id = ish_reg_read(dev, IPC_REG_ISH2HOST_MSG) & 0xFFFF;
 497
 498         /* Clear IPC output queue */
 499         spin_lock_irqsave(&dev->wr_processing_spinlock, flags);
 500         list_for_each_entry_safe(processing, next,
 501                         &dev->wr_processing_list_head.link, link) {
 502                 list_move_tail(&processing->link, &dev->wr_free_list_head.link);
 503         }
 504         spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags);
 505
 506         /* ISHTP notification in IPC_RESET */
 507         ishtp_reset_handler(dev);
 508
 509         if (!ish_is_input_ready(dev))
 510                 timed_wait_for_timeout(dev, WAIT_FOR_INPUT_RDY,
 511                         TIME_SLICE_FOR_INPUT_RDY_MS, TIMEOUT_FOR_INPUT_RDY_MS);
 512
 513         /* ISH FW is dead */
 514         if (!ish_is_input_ready(dev))
 515                 return  -EPIPE;
 516         /*
 517          * Set HOST2ISH.ILUP. Apparently we need this BEFORE sending
 518          * RESET_NOTIFY_ACK - FW will be checking for it
 519          */
 520         ish_set_host_rdy(dev);
 521         /* Send RESET_NOTIFY_ACK (with reset_id) */
 522         ipc_send_mng_msg(dev, MNG_RESET_NOTIFY_ACK, &reset_id,
 523                          sizeof(uint32_t));
 524
 525         /* Wait for ISH FW'es ILUP and ISHTP_READY */
 526         timed_wait_for_timeout(dev, WAIT_FOR_FW_RDY,
 527                         TIME_SLICE_FOR_FW_RDY_MS, TIMEOUT_FOR_FW_RDY_MS);
 528         if (!ishtp_fw_is_ready(dev)) {
 529                 /* ISH FW is dead */
 530                 uint32_t        ish_status;
 531
 532                 ish_status = _ish_read_fw_sts_reg(dev);
 533                 dev_err(dev->devc,
 534                         "[ishtp-ish]: completed reset, ISH is dead (FWSTS = %08X)\n",
 535                         ish_status);
 536                 return -ENODEV;
 537         }
 538         return  0;
 539 }
 540
 541 #define TIMEOUT_FOR_HW_RDY_MS                   300
 542
 543 /**
 544  * ish_fw_reset_work_fn() - FW reset worker function
 545  * @unused: not used
 546  *
 547  * Call ish_fw_reset_handler to complete FW reset
 548  */
 549 static void fw_reset_work_fn(struct work_struct *unused)
 550 {
 551         int     rv;
 552
 553         rv = ish_fw_reset_handler(ishtp_dev);
 554         if (!rv) {
 555                 /* ISH is ILUP & ISHTP-ready. Restart ISHTP */
 556                 msleep_interruptible(TIMEOUT_FOR_HW_RDY_MS);
 557                 ishtp_dev->recvd_hw_ready = 1;
 558                 wake_up_interruptible(&ishtp_dev->wait_hw_ready);
 559
 560                 /* ISHTP notification in IPC_RESET sequence completion */
 561                 ishtp_reset_compl_handler(ishtp_dev);
 562         } else
 563                 dev_err(ishtp_dev->devc, "[ishtp-ish]: FW reset failed (%d)\n",
 564                         rv);
 565 }
 566
 567 /**
 568  * _ish_sync_fw_clock() -Sync FW clock with the OS clock
 569  * @dev: ishtp device pointer
 570  *
 571  * Sync FW and OS time
 572  */
 573 static void _ish_sync_fw_clock(struct ishtp_device *dev)
 574 {
 575         static unsigned long    prev_sync;
 576         uint64_t        usec;
 577
 578         if (prev_sync && jiffies - prev_sync < 20 * HZ)
 579                 return;
 580
 581         prev_sync = jiffies;
 582         usec = ktime_to_us(ktime_get_boottime());
 583         ipc_send_mng_msg(dev, MNG_SYNC_FW_CLOCK, &usec, sizeof(uint64_t));
 584 }
 585
 586 /**
 587  * recv_ipc() - Receive and process IPC management messages
 588  * @dev: ishtp device instance
 589  * @doorbell_val: doorbell value
 590  *
 591  * This function runs in ISR context.
 592  * NOTE: Any other mng command than reset_notify and reset_notify_ack
 593  * won't wake BH handler
 594  */
 595 static void     recv_ipc(struct ishtp_device *dev, uint32_t doorbell_val)
 596 {
 597         uint32_t        mng_cmd;
 598
 599         mng_cmd = IPC_HEADER_GET_MNG_CMD(doorbell_val);
 600
 601         switch (mng_cmd) {
 602         default:
 603                 break;
 604
 605         case MNG_RX_CMPL_INDICATION:
 606                 if (dev->suspend_flag) {
 607                         dev->suspend_flag = 0;
 608                         wake_up_interruptible(&dev->suspend_wait);
 609                 }
 610                 if (dev->resume_flag) {
 611                         dev->resume_flag = 0;
 612                         wake_up_interruptible(&dev->resume_wait);
 613                 }
 614
 615                 write_ipc_from_queue(dev);
 616                 break;
 617
 618         case MNG_RESET_NOTIFY:
 619                 if (!ishtp_dev) {
 620                         ishtp_dev = dev;
 621                         INIT_WORK(&fw_reset_work, fw_reset_work_fn);
 622                 }
 623                 schedule_work(&fw_reset_work);
 624                 break;
 625
 626         case MNG_RESET_NOTIFY_ACK:
 627                 dev->recvd_hw_ready = 1;
 628                 wake_up_interruptible(&dev->wait_hw_ready);
 629                 break;
 630         }
 631 }
 632
 633 /**
 634  * ish_irq_handler() - ISH IRQ handler
 635  * @irq: irq number
 636  * @dev_id: ishtp device pointer
 637  *
 638  * ISH IRQ handler. If interrupt is generated and is for ISH it will process
 639  * the interrupt.
 640  */
 641 irqreturn_t ish_irq_handler(int irq, void *dev_id)
 642 {
 643         struct ishtp_device     *dev = dev_id;
 644         uint32_t        doorbell_val;
 645         bool    interrupt_generated;
 646
 647         /* Check that it's interrupt from ISH (may be shared) */
 648         interrupt_generated = check_generated_interrupt(dev);
 649
 650         if (!interrupt_generated)
 651                 return IRQ_NONE;
 652
 653         doorbell_val = ish_reg_read(dev, IPC_REG_ISH2HOST_DRBL);
 654         if (!IPC_IS_BUSY(doorbell_val))
 655                 return IRQ_HANDLED;
 656
 657         if (dev->dev_state == ISHTP_DEV_DISABLED)
 658                 return  IRQ_HANDLED;
 659
 660         /* Sanity check: IPC dgram length in header */
 661         if (IPC_HEADER_GET_LENGTH(doorbell_val) > IPC_PAYLOAD_SIZE) {
 662                 dev_err(dev->devc,
 663                         "IPC hdr - bad length: %u; dropped\n",
 664                         (unsigned int)IPC_HEADER_GET_LENGTH(doorbell_val));
 665                 goto    eoi;
 666         }
 667
 668         switch (IPC_HEADER_GET_PROTOCOL(doorbell_val)) {
 669         default:
 670                 break;
 671         case IPC_PROTOCOL_MNG:
 672                 recv_ipc(dev, doorbell_val);
 673                 break;
 674         case IPC_PROTOCOL_ISHTP:
 675                 ishtp_recv(dev);
 676                 break;
 677         }
 678
 679 eoi:
 680         /* Update IPC counters */
 681         ++dev->ipc_rx_cnt;
 682         dev->ipc_rx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val);
 683
 684         ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0);
 685         /* Flush write to doorbell */
 686         ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
 687
 688         return  IRQ_HANDLED;
 689 }
 690
 691 /**
 692  * ish_disable_dma() - disable dma communication between host and ISHFW
 693  * @dev: ishtp device pointer
 694  *
 695  * Clear the dma enable bit and wait for dma inactive.
 696  *
 697  * Return: 0 for success else error code.
 698  */
 699 static int ish_disable_dma(struct ishtp_device *dev)
 700 {
 701         unsigned int    dma_delay;
 702
 703         /* Clear the dma enable bit */
 704         ish_reg_write(dev, IPC_REG_ISH_RMP2, 0);
 705
 706         /* wait for dma inactive */
 707         for (dma_delay = 0; dma_delay < MAX_DMA_DELAY &&
 708                 _ish_read_fw_sts_reg(dev) & (IPC_ISH_IN_DMA);
 709                 dma_delay += 5)
 710                 mdelay(5);
 711
 712         if (dma_delay >= MAX_DMA_DELAY) {
 713                 dev_err(dev->devc,
 714                         "Wait for DMA inactive timeout\n");
 715                 return  -EBUSY;
 716         }
 717
 718         return 0;
 719 }
 720
 721 /**
 722  * ish_wakeup() - wakeup ishfw from waiting-for-host state
 723  * @dev: ishtp device pointer
 724  *
 725  * Set the dma enable bit and send a void message to FW,
 726  * it wil wakeup FW from waiting-for-host state.
 727  */
 728 static void ish_wakeup(struct ishtp_device *dev)
 729 {
 730         /* Set dma enable bit */
 731         ish_reg_write(dev, IPC_REG_ISH_RMP2, IPC_RMP2_DMA_ENABLED);
 732
 733         /*
 734          * Send 0 IPC message so that ISH FW wakes up if it was already
 735          * asleep.
 736          */
 737         ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, IPC_DRBL_BUSY_BIT);
 738
 739         /* Flush writes to doorbell and REMAP2 */
 740         ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
 741 }
 742
 743 /**
 744  * _ish_hw_reset() - HW reset
 745  * @dev: ishtp device pointer
 746  *
 747  * Reset ISH HW to recover if any error
 748  *
 749  * Return: 0 for success else error fault code
 750  */
 751 static int _ish_hw_reset(struct ishtp_device *dev)
 752 {
 753         struct pci_dev *pdev = dev->pdev;
 754         int     rv;
 755         uint16_t csr;
 756
 757         if (!pdev)
 758                 return  -ENODEV;
 759
 760         rv = pci_reset_function(pdev);
 761         if (!rv)
 762                 dev->dev_state = ISHTP_DEV_RESETTING;
 763
 764         if (!pdev->pm_cap) {
 765                 dev_err(&pdev->dev, "Can't reset - no PM caps\n");
 766                 return  -EINVAL;
 767         }
 768
 769         /* Disable dma communication between FW and host */
 770         if (ish_disable_dma(dev)) {
 771                 dev_err(&pdev->dev,
 772                         "Can't reset - stuck with DMA in-progress\n");
 773                 return  -EBUSY;
 774         }
 775
 776         pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &csr);
 777
 778         csr &= ~PCI_PM_CTRL_STATE_MASK;
 779         csr |= PCI_D3hot;
 780         pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);
 781
 782         mdelay(pdev->d3_delay);
 783
 784         csr &= ~PCI_PM_CTRL_STATE_MASK;
 785         csr |= PCI_D0;
 786         pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);
 787
 788         /* Now we can enable ISH DMA operation and wakeup ISHFW */
 789         ish_wakeup(dev);
 790
 791         return  0;
 792 }
 793
 794 /**
 795  * _ish_ipc_reset() - IPC reset
 796  * @dev: ishtp device pointer
 797  *
 798  * Resets host and fw IPC and upper layers
 799  *
 800  * Return: 0 for success else error fault code
 801  */
 802 static int _ish_ipc_reset(struct ishtp_device *dev)
 803 {
 804         struct ipc_rst_payload_type ipc_mng_msg;
 805         int     rv = 0;
 806
 807         ipc_mng_msg.reset_id = 1;
 808         ipc_mng_msg.reserved = 0;
 809
 810         set_host_ready(dev);
 811
 812         /* Clear the incoming doorbell */
 813         ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0);
 814         /* Flush write to doorbell */
 815         ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS);
 816
 817         dev->recvd_hw_ready = 0;
 818
 819         /* send message */
 820         rv = ipc_send_mng_msg(dev, MNG_RESET_NOTIFY, &ipc_mng_msg,
 821                 sizeof(struct ipc_rst_payload_type));
 822         if (rv) {
 823                 dev_err(dev->devc, "Failed to send IPC MNG_RESET_NOTIFY\n");
 824                 return  rv;
 825         }
 826
 827         wait_event_interruptible_timeout(dev->wait_hw_ready,
 828                                          dev->recvd_hw_ready, 2 * HZ);
 829         if (!dev->recvd_hw_ready) {
 830                 dev_err(dev->devc, "Timed out waiting for HW ready\n");
 831                 rv = -ENODEV;
 832         }
 833
 834         return rv;
 835 }
 836
 837 /**
 838  * ish_hw_start() -Start ISH HW
 839  * @dev: ishtp device pointer
 840  *
 841  * Set host to ready state and wait for FW reset
 842  *
 843  * Return: 0 for success else error fault code
 844  */
 845 int ish_hw_start(struct ishtp_device *dev)
 846 {
 847         ish_set_host_rdy(dev);
 848
 849         set_host_ready(dev);
 850
 851         /* After that we can enable ISH DMA operation and wakeup ISHFW */
 852         ish_wakeup(dev);
 853
 854         /* wait for FW-initiated reset flow */
 855         if (!dev->recvd_hw_ready)
 856                 wait_event_interruptible_timeout(dev->wait_hw_ready,
 857                                                  dev->recvd_hw_ready,
 858                                                  10 * HZ);
 859
 860         if (!dev->recvd_hw_ready) {
 861                 dev_err(dev->devc,
 862                         "[ishtp-ish]: Timed out waiting for FW-initiated reset\n");
 863                 return  -ENODEV;
 864         }
 865
 866         return 0;
 867 }
 868
 869 /**
 870  * ish_ipc_get_header() -Get doorbell value
 871  * @dev: ishtp device pointer
 872  * @length: length of message
 873  * @busy: busy status
 874  *
 875  * Get door bell value from message header
 876  *
 877  * Return: door bell value
 878  */
 879 static uint32_t ish_ipc_get_header(struct ishtp_device *dev, int length,
 880                                    int busy)
 881 {
 882         uint32_t drbl_val;
 883
 884         drbl_val = IPC_BUILD_HEADER(length, IPC_PROTOCOL_ISHTP, busy);
 885
 886         return drbl_val;
 887 }
 888
 889 static const struct ishtp_hw_ops ish_hw_ops = {
 890         .hw_reset = _ish_hw_reset,
 891         .ipc_reset = _ish_ipc_reset,
 892         .ipc_get_header = ish_ipc_get_header,
 893         .ishtp_read = _ishtp_read,
 894         .write = write_ipc_to_queue,
 895         .get_fw_status = _ish_read_fw_sts_reg,
 896         .sync_fw_clock = _ish_sync_fw_clock,
 897         .ishtp_read_hdr = _ishtp_read_hdr
 898 };
 899
 900 /**
 901  * ish_dev_init() -Initialize ISH devoce
 902  * @pdev: PCI device
 903  *
 904  * Allocate ISHTP device and initialize IPC processing
 905  *
 906  * Return: ISHTP device instance on success else NULL
 907  */
 908 struct ishtp_device *ish_dev_init(struct pci_dev *pdev)
 909 {
 910         struct ishtp_device *dev;
 911         int     i;
 912
 913         dev = devm_kzalloc(&pdev->dev,
 914                            sizeof(struct ishtp_device) + sizeof(struct ish_hw),
 915                            GFP_KERNEL);
 916         if (!dev)
 917                 return NULL;
 918
 919         ishtp_device_init(dev);
 920
 921         init_waitqueue_head(&dev->wait_hw_ready);
 922
 923         spin_lock_init(&dev->wr_processing_spinlock);
 924         spin_lock_init(&dev->out_ipc_spinlock);
 925
 926         /* Init IPC processing and free lists */
 927         INIT_LIST_HEAD(&dev->wr_processing_list_head.link);
 928         INIT_LIST_HEAD(&dev->wr_free_list_head.link);
 929         for (i = 0; i < IPC_TX_FIFO_SIZE; ++i) {
 930                 struct wr_msg_ctl_info  *tx_buf;
 931
 932                 tx_buf = devm_kzalloc(&pdev->dev,
 933                                       sizeof(struct wr_msg_ctl_info),
 934                                       GFP_KERNEL);
 935                 if (!tx_buf) {
 936                         /*
 937                          * IPC buffers may be limited or not available
 938                          * at all - although this shouldn't happen
 939                          */
 940                         dev_err(dev->devc,
 941                                 "[ishtp-ish]: failure in Tx FIFO allocations (%d)\n",
 942                                 i);
 943                         break;
 944                 }
 945                 list_add_tail(&tx_buf->link, &dev->wr_free_list_head.link);
 946         }
 947
 948         dev->ops = &ish_hw_ops;
 949         dev->devc = &pdev->dev;
 950         dev->mtu = IPC_PAYLOAD_SIZE - sizeof(struct ishtp_msg_hdr);
 951         return dev;
 952 }
 953
 954 /**
 955  * ish_device_disable() - Disable ISH device
 956  * @dev: ISHTP device pointer
 957  *
 958  * Disable ISH by clearing host ready to inform firmware.
 959  */
 960 void    ish_device_disable(struct ishtp_device *dev)
 961 {
 962         struct pci_dev *pdev = dev->pdev;
 963
 964         if (!pdev)
 965                 return;
 966
 967         /* Disable dma communication between FW and host */
 968         if (ish_disable_dma(dev)) {
 969                 dev_err(&pdev->dev,
 970                         "Can't reset - stuck with DMA in-progress\n");
 971                 return;
 972         }
 973
 974         /* Put ISH to D3hot state for power saving */
 975         pci_set_power_state(pdev, PCI_D3hot);
 976
 977         dev->dev_state = ISHTP_DEV_DISABLED;
 978         ish_clr_host_rdy(dev);
 979 }