drivers/gpu/host1x/drm/hdmi.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/gpio.h>
  13 #include <linux/hdmi.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/clk/tegra.h>
  19
  20 #include <drm/drm_edid.h>
  21
  22 #include "hdmi.h"
  23 #include "drm.h"
  24 #include "dc.h"
  25 #include "host1x_client.h"
  26
  27 struct tegra_hdmi {
  28         struct host1x_client client;
  29         struct tegra_output output;
  30         struct device *dev;
  31
  32         struct regulator *vdd;
  33         struct regulator *pll;
  34
  35         void __iomem *regs;
  36         unsigned int irq;
  37
  38         struct clk *clk_parent;
  39         struct clk *clk;
  40
  41         unsigned int audio_source;
  42         unsigned int audio_freq;
  43         bool stereo;
  44         bool dvi;
  45
  46         struct drm_info_list *debugfs_files;
  47         struct drm_minor *minor;
  48         struct dentry *debugfs;
  49 };
  50
  51 static inline struct tegra_hdmi *
  52 host1x_client_to_hdmi(struct host1x_client *client)
  53 {
  54         return container_of(client, struct tegra_hdmi, client);
  55 }
  56
  57 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
  58 {
  59         return container_of(output, struct tegra_hdmi, output);
  60 }
  61
  62 #define HDMI_AUDIOCLK_FREQ 216000000
  63 #define HDMI_REKEY_DEFAULT 56
  64
  65 enum {
  66         AUTO = 0,
  67         SPDIF,
  68         HDA,
  69 };
  70
  71 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
  72                                              unsigned long reg)
  73 {
  74         return readl(hdmi->regs + (reg << 2));
  75 }
  76
  77 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
  78                                      unsigned long reg)
  79 {
  80         writel(val, hdmi->regs + (reg << 2));
  81 }
  82
  83 struct tegra_hdmi_audio_config {
  84         unsigned int pclk;
  85         unsigned int n;
  86         unsigned int cts;
  87         unsigned int aval;
  88 };
  89
  90 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
  91         {  25200000, 4096,  25200, 24000 },
  92         {  27000000, 4096,  27000, 24000 },
  93         {  74250000, 4096,  74250, 24000 },
  94         { 148500000, 4096, 148500, 24000 },
  95         {         0,    0,      0,     0 },
  96 };
  97
  98 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
  99         {  25200000, 5880,  26250, 25000 },
 100         {  27000000, 5880,  28125, 25000 },
 101         {  74250000, 4704,  61875, 20000 },
 102         { 148500000, 4704, 123750, 20000 },
 103         {         0,    0,      0,     0 },
 104 };
 105
 106 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
 107         {  25200000, 6144,  25200, 24000 },
 108         {  27000000, 6144,  27000, 24000 },
 109         {  74250000, 6144,  74250, 24000 },
 110         { 148500000, 6144, 148500, 24000 },
 111         {         0,    0,      0,     0 },
 112 };
 113
 114 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
 115         {  25200000, 11760,  26250, 25000 },
 116         {  27000000, 11760,  28125, 25000 },
 117         {  74250000,  9408,  61875, 20000 },
 118         { 148500000,  9408, 123750, 20000 },
 119         {         0,     0,      0,     0 },
 120 };
 121
 122 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
 123         {  25200000, 12288,  25200, 24000 },
 124         {  27000000, 12288,  27000, 24000 },
 125         {  74250000, 12288,  74250, 24000 },
 126         { 148500000, 12288, 148500, 24000 },
 127         {         0,     0,      0,     0 },
 128 };
 129
 130 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
 131         {  25200000, 23520,  26250, 25000 },
 132         {  27000000, 23520,  28125, 25000 },
 133         {  74250000, 18816,  61875, 20000 },
 134         { 148500000, 18816, 123750, 20000 },
 135         {         0,     0,      0,     0 },
 136 };
 137
 138 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
 139         {  25200000, 24576,  25200, 24000 },
 140         {  27000000, 24576,  27000, 24000 },
 141         {  74250000, 24576,  74250, 24000 },
 142         { 148500000, 24576, 148500, 24000 },
 143         {         0,     0,      0,     0 },
 144 };
 145
 146 struct tmds_config {
 147         unsigned int pclk;
 148         u32 pll0;
 149         u32 pll1;
 150         u32 pe_current;
 151         u32 drive_current;
 152 };
 153
 154 static const struct tmds_config tegra2_tmds_config[] = {
 155         { /* slow pixel clock modes */
 156                 .pclk = 27000000,
 157                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 158                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 159                         SOR_PLL_TX_REG_LOAD(3),
 160                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 161                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 162                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 163                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 164                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 165                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 166                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 167                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 168                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 169         },
 170         { /* high pixel clock modes */
 171                 .pclk = UINT_MAX,
 172                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 173                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 174                         SOR_PLL_TX_REG_LOAD(3),
 175                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 176                 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
 177                         PE_CURRENT1(PE_CURRENT_6_0_mA) |
 178                         PE_CURRENT2(PE_CURRENT_6_0_mA) |
 179                         PE_CURRENT3(PE_CURRENT_6_0_mA),
 180                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 181                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 182                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 183                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 184         },
 185 };
 186
 187 static const struct tmds_config tegra3_tmds_config[] = {
 188         { /* 480p modes */
 189                 .pclk = 27000000,
 190                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 191                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 192                         SOR_PLL_TX_REG_LOAD(0),
 193                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 194                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 195                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 196                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 197                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 198                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 199                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 200                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 201                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 202         }, { /* 720p modes */
 203                 .pclk = 74250000,
 204                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 205                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 206                         SOR_PLL_TX_REG_LOAD(0),
 207                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 208                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 209                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 210                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 211                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 212                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 213                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 214                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 215                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 216         }, { /* 1080p modes */
 217                 .pclk = UINT_MAX,
 218                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 219                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
 220                         SOR_PLL_TX_REG_LOAD(0),
 221                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 222                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 223                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 224                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 225                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 226                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 227                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 228                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 229                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 230         },
 231 };
 232
 233 static const struct tegra_hdmi_audio_config *
 234 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
 235 {
 236         const struct tegra_hdmi_audio_config *table;
 237
 238         switch (audio_freq) {
 239         case 32000:
 240                 table = tegra_hdmi_audio_32k;
 241                 break;
 242
 243         case 44100:
 244                 table = tegra_hdmi_audio_44_1k;
 245                 break;
 246
 247         case 48000:
 248                 table = tegra_hdmi_audio_48k;
 249                 break;
 250
 251         case 88200:
 252                 table = tegra_hdmi_audio_88_2k;
 253                 break;
 254
 255         case 96000:
 256                 table = tegra_hdmi_audio_96k;
 257                 break;
 258
 259         case 176400:
 260                 table = tegra_hdmi_audio_176_4k;
 261                 break;
 262
 263         case 192000:
 264                 table = tegra_hdmi_audio_192k;
 265                 break;
 266
 267         default:
 268                 return NULL;
 269         }
 270
 271         while (table->pclk) {
 272                 if (table->pclk == pclk)
 273                         return table;
 274
 275                 table++;
 276         }
 277
 278         return NULL;
 279 }
 280
 281 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
 282 {
 283         const unsigned int freqs[] = {
 284                 32000, 44100, 48000, 88200, 96000, 176400, 192000
 285         };
 286         unsigned int i;
 287
 288         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
 289                 unsigned int f = freqs[i];
 290                 unsigned int eight_half;
 291                 unsigned long value;
 292                 unsigned int delta;
 293
 294                 if (f > 96000)
 295                         delta = 2;
 296                 else if (f > 480000)
 297                         delta = 6;
 298                 else
 299                         delta = 9;
 300
 301                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
 302                 value = AUDIO_FS_LOW(eight_half - delta) |
 303                         AUDIO_FS_HIGH(eight_half + delta);
 304                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
 305         }
 306 }
 307
 308 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
 309 {
 310         struct device_node *node = hdmi->dev->of_node;
 311         const struct tegra_hdmi_audio_config *config;
 312         unsigned int offset = 0;
 313         unsigned long value;
 314
 315         switch (hdmi->audio_source) {
 316         case HDA:
 317                 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
 318                 break;
 319
 320         case SPDIF:
 321                 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 322                 break;
 323
 324         default:
 325                 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 326                 break;
 327         }
 328
 329         if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
 330                 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
 331                          AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
 332                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
 333         } else {
 334                 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
 335                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
 336
 337                 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
 338                         AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
 339                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
 340         }
 341
 342         config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
 343         if (!config) {
 344                 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
 345                         hdmi->audio_freq, pclk);
 346                 return -EINVAL;
 347         }
 348
 349         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 350
 351         value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
 352                 AUDIO_N_VALUE(config->n - 1);
 353         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 354
 355         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
 356                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 357
 358         value = ACR_SUBPACK_CTS(config->cts);
 359         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 360
 361         value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
 362         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
 363
 364         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
 365         value &= ~AUDIO_N_RESETF;
 366         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 367
 368         if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
 369                 switch (hdmi->audio_freq) {
 370                 case 32000:
 371                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
 372                         break;
 373
 374                 case 44100:
 375                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
 376                         break;
 377
 378                 case 48000:
 379                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
 380                         break;
 381
 382                 case 88200:
 383                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
 384                         break;
 385
 386                 case 96000:
 387                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
 388                         break;
 389
 390                 case 176400:
 391                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
 392                         break;
 393
 394                 case 192000:
 395                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
 396                         break;
 397                 }
 398
 399                 tegra_hdmi_writel(hdmi, config->aval, offset);
 400         }
 401
 402         tegra_hdmi_setup_audio_fs_tables(hdmi);
 403
 404         return 0;
 405 }
 406
 407 static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size)
 408 {
 409         unsigned long value = 0;
 410         size_t i;
 411
 412         for (i = size; i > 0; i--)
 413                 value = (value << 8) | ptr[i - 1];
 414
 415         return value;
 416 }
 417
 418 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
 419                                       size_t size)
 420 {
 421         const u8 *ptr = data;
 422         unsigned long offset;
 423         unsigned long value;
 424         size_t i, j;
 425
 426         switch (ptr[0]) {
 427         case HDMI_INFOFRAME_TYPE_AVI:
 428                 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
 429                 break;
 430
 431         case HDMI_INFOFRAME_TYPE_AUDIO:
 432                 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
 433                 break;
 434
 435         case HDMI_INFOFRAME_TYPE_VENDOR:
 436                 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
 437                 break;
 438
 439         default:
 440                 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
 441                         ptr[0]);
 442                 return;
 443         }
 444
 445         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
 446                 INFOFRAME_HEADER_VERSION(ptr[1]) |
 447                 INFOFRAME_HEADER_LEN(ptr[2]);
 448         tegra_hdmi_writel(hdmi, value, offset);
 449         offset++;
 450
 451         /*
 452          * Each subpack contains 7 bytes, divided into:
 453          * - subpack_low: bytes 0 - 3
 454          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
 455          */
 456         for (i = 3, j = 0; i < size; i += 7, j += 8) {
 457                 size_t rem = size - i, num = min_t(size_t, rem, 4);
 458
 459                 value = tegra_hdmi_subpack(&ptr[i], num);
 460                 tegra_hdmi_writel(hdmi, value, offset++);
 461
 462                 num = min_t(size_t, rem - num, 3);
 463
 464                 value = tegra_hdmi_subpack(&ptr[i + 4], num);
 465                 tegra_hdmi_writel(hdmi, value, offset++);
 466         }
 467 }
 468
 469 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
 470                                            struct drm_display_mode *mode)
 471 {
 472         struct hdmi_avi_infoframe frame;
 473         u8 buffer[17];
 474         ssize_t err;
 475
 476         if (hdmi->dvi) {
 477                 tegra_hdmi_writel(hdmi, 0,
 478                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 479                 return;
 480         }
 481
 482         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 483         if (err < 0) {
 484                 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
 485                 return;
 486         }
 487
 488         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 489         if (err < 0) {
 490                 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
 491                 return;
 492         }
 493
 494         tegra_hdmi_write_infopack(hdmi, buffer, err);
 495
 496         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 497                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 498 }
 499
 500 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
 501 {
 502         struct hdmi_audio_infoframe frame;
 503         u8 buffer[14];
 504         ssize_t err;
 505
 506         if (hdmi->dvi) {
 507                 tegra_hdmi_writel(hdmi, 0,
 508                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 509                 return;
 510         }
 511
 512         err = hdmi_audio_infoframe_init(&frame);
 513         if (err < 0) {
 514                 dev_err(hdmi->dev, "failed to initialize audio infoframe: %d\n",
 515                         err);
 516                 return;
 517         }
 518
 519         frame.channels = 2;
 520
 521         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
 522         if (err < 0) {
 523                 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
 524                         err);
 525                 return;
 526         }
 527
 528         /*
 529          * The audio infoframe has only one set of subpack registers, so the
 530          * infoframe needs to be truncated. One set of subpack registers can
 531          * contain 7 bytes. Including the 3 byte header only the first 10
 532          * bytes can be programmed.
 533          */
 534         tegra_hdmi_write_infopack(hdmi, buffer, min(10, err));
 535
 536         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 537                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 538 }
 539
 540 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
 541 {
 542         struct hdmi_vendor_infoframe frame;
 543         unsigned long value;
 544         u8 buffer[10];
 545         ssize_t err;
 546
 547         if (!hdmi->stereo) {
 548                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 549                 value &= ~GENERIC_CTRL_ENABLE;
 550                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 551                 return;
 552         }
 553
 554         memset(&frame, 0, sizeof(frame));
 555
 556         frame.type = HDMI_INFOFRAME_TYPE_VENDOR;
 557         frame.version = 0x01;
 558         frame.length = 6;
 559
 560         frame.data[0] = 0x03; /* regid0 */
 561         frame.data[1] = 0x0c; /* regid1 */
 562         frame.data[2] = 0x00; /* regid2 */
 563         frame.data[3] = 0x02 << 5; /* video format */
 564
 565         /* TODO: 74 MHz limit? */
 566         if (1) {
 567                 frame.data[4] = 0x00 << 4; /* 3D structure */
 568         } else {
 569                 frame.data[4] = 0x08 << 4; /* 3D structure */
 570                 frame.data[5] = 0x00 << 4; /* 3D ext. data */
 571         }
 572
 573         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
 574         if (err < 0) {
 575                 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
 576                         err);
 577                 return;
 578         }
 579
 580         tegra_hdmi_write_infopack(hdmi, buffer, err);
 581
 582         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 583         value |= GENERIC_CTRL_ENABLE;
 584         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 585 }
 586
 587 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
 588                                   const struct tmds_config *tmds)
 589 {
 590         unsigned long value;
 591
 592         tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
 593         tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
 594         tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
 595
 596         value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
 597         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 598 }
 599
 600 static int tegra_output_hdmi_enable(struct tegra_output *output)
 601 {
 602         unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
 603         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
 604         struct drm_display_mode *mode = &dc->base.mode;
 605         struct tegra_hdmi *hdmi = to_hdmi(output);
 606         struct device_node *node = hdmi->dev->of_node;
 607         unsigned int pulse_start, div82, pclk;
 608         const struct tmds_config *tmds;
 609         unsigned int num_tmds;
 610         unsigned long value;
 611         int retries = 1000;
 612         int err;
 613
 614         pclk = mode->clock * 1000;
 615         h_sync_width = mode->hsync_end - mode->hsync_start;
 616         h_back_porch = mode->htotal - mode->hsync_end;
 617         h_front_porch = mode->hsync_start - mode->hdisplay;
 618
 619         err = regulator_enable(hdmi->vdd);
 620         if (err < 0) {
 621                 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
 622                 return err;
 623         }
 624
 625         err = regulator_enable(hdmi->pll);
 626         if (err < 0) {
 627                 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
 628                 return err;
 629         }
 630
 631         /*
 632          * This assumes that the display controller will divide its parent
 633          * clock by 2 to generate the pixel clock.
 634          */
 635         err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
 636         if (err < 0) {
 637                 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
 638                 return err;
 639         }
 640
 641         err = clk_set_rate(hdmi->clk, pclk);
 642         if (err < 0)
 643                 return err;
 644
 645         err = clk_enable(hdmi->clk);
 646         if (err < 0) {
 647                 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
 648                 return err;
 649         }
 650
 651         tegra_periph_reset_assert(hdmi->clk);
 652         usleep_range(1000, 2000);
 653         tegra_periph_reset_deassert(hdmi->clk);
 654
 655         tegra_dc_writel(dc, VSYNC_H_POSITION(1),
 656                         DC_DISP_DISP_TIMING_OPTIONS);
 657         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
 658                         DC_DISP_DISP_COLOR_CONTROL);
 659
 660         /* video_preamble uses h_pulse2 */
 661         pulse_start = 1 + h_sync_width + h_back_porch - 10;
 662
 663         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
 664
 665         value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
 666                 PULSE_LAST_END_A;
 667         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
 668
 669         value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
 670         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
 671
 672         value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
 673                 VSYNC_WINDOW_ENABLE;
 674         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 675
 676         if (dc->pipe)
 677                 value = HDMI_SRC_DISPLAYB;
 678         else
 679                 value = HDMI_SRC_DISPLAYA;
 680
 681         if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
 682                                         (mode->vdisplay == 576)))
 683                 tegra_hdmi_writel(hdmi,
 684                                   value | ARM_VIDEO_RANGE_FULL,
 685                                   HDMI_NV_PDISP_INPUT_CONTROL);
 686         else
 687                 tegra_hdmi_writel(hdmi,
 688                                   value | ARM_VIDEO_RANGE_LIMITED,
 689                                   HDMI_NV_PDISP_INPUT_CONTROL);
 690
 691         div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
 692         value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
 693         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
 694
 695         if (!hdmi->dvi) {
 696                 err = tegra_hdmi_setup_audio(hdmi, pclk);
 697                 if (err < 0)
 698                         hdmi->dvi = true;
 699         }
 700
 701         if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
 702                 /*
 703                  * TODO: add ELD support
 704                  */
 705         }
 706
 707         rekey = HDMI_REKEY_DEFAULT;
 708         value = HDMI_CTRL_REKEY(rekey);
 709         value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
 710                                           h_front_porch - rekey - 18) / 32);
 711
 712         if (!hdmi->dvi)
 713                 value |= HDMI_CTRL_ENABLE;
 714
 715         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
 716
 717         if (hdmi->dvi)
 718                 tegra_hdmi_writel(hdmi, 0x0,
 719                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 720         else
 721                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
 722                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 723
 724         tegra_hdmi_setup_avi_infoframe(hdmi, mode);
 725         tegra_hdmi_setup_audio_infoframe(hdmi);
 726         tegra_hdmi_setup_stereo_infoframe(hdmi);
 727
 728         /* TMDS CONFIG */
 729         if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
 730                 num_tmds = ARRAY_SIZE(tegra3_tmds_config);
 731                 tmds = tegra3_tmds_config;
 732         } else {
 733                 num_tmds = ARRAY_SIZE(tegra2_tmds_config);
 734                 tmds = tegra2_tmds_config;
 735         }
 736
 737         for (i = 0; i < num_tmds; i++) {
 738                 if (pclk <= tmds[i].pclk) {
 739                         tegra_hdmi_setup_tmds(hdmi, &tmds[i]);
 740                         break;
 741                 }
 742         }
 743
 744         tegra_hdmi_writel(hdmi,
 745                           SOR_SEQ_CTL_PU_PC(0) |
 746                           SOR_SEQ_PU_PC_ALT(0) |
 747                           SOR_SEQ_PD_PC(8) |
 748                           SOR_SEQ_PD_PC_ALT(8),
 749                           HDMI_NV_PDISP_SOR_SEQ_CTL);
 750
 751         value = SOR_SEQ_INST_WAIT_TIME(1) |
 752                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
 753                 SOR_SEQ_INST_HALT |
 754                 SOR_SEQ_INST_PIN_A_LOW |
 755                 SOR_SEQ_INST_PIN_B_LOW |
 756                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
 757
 758         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
 759         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
 760
 761         value = 0x1c800;
 762         value &= ~SOR_CSTM_ROTCLK(~0);
 763         value |= SOR_CSTM_ROTCLK(2);
 764         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
 765
 766         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
 767         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 768         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 769
 770         /* start SOR */
 771         tegra_hdmi_writel(hdmi,
 772                           SOR_PWR_NORMAL_STATE_PU |
 773                           SOR_PWR_NORMAL_START_NORMAL |
 774                           SOR_PWR_SAFE_STATE_PD |
 775                           SOR_PWR_SETTING_NEW_TRIGGER,
 776                           HDMI_NV_PDISP_SOR_PWR);
 777         tegra_hdmi_writel(hdmi,
 778                           SOR_PWR_NORMAL_STATE_PU |
 779                           SOR_PWR_NORMAL_START_NORMAL |
 780                           SOR_PWR_SAFE_STATE_PD |
 781                           SOR_PWR_SETTING_NEW_DONE,
 782                           HDMI_NV_PDISP_SOR_PWR);
 783
 784         do {
 785                 BUG_ON(--retries < 0);
 786                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
 787         } while (value & SOR_PWR_SETTING_NEW_PENDING);
 788
 789         value = SOR_STATE_ASY_CRCMODE_COMPLETE |
 790                 SOR_STATE_ASY_OWNER_HEAD0 |
 791                 SOR_STATE_ASY_SUBOWNER_BOTH |
 792                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
 793                 SOR_STATE_ASY_DEPOL_POS;
 794
 795         /* setup sync polarities */
 796         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 797                 value |= SOR_STATE_ASY_HSYNCPOL_POS;
 798
 799         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 800                 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
 801
 802         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 803                 value |= SOR_STATE_ASY_VSYNCPOL_POS;
 804
 805         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 806                 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
 807
 808         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
 809
 810         value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
 811         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
 812
 813         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
 814         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
 815         tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
 816                           HDMI_NV_PDISP_SOR_STATE1);
 817         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
 818
 819         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
 820
 821         value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 822                 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
 823         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
 824
 825         value = DISP_CTRL_MODE_C_DISPLAY;
 826         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
 827
 828         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 829         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 830
 831         /* TODO: add HDCP support */
 832
 833         return 0;
 834 }
 835
 836 static int tegra_output_hdmi_disable(struct tegra_output *output)
 837 {
 838         struct tegra_hdmi *hdmi = to_hdmi(output);
 839
 840         tegra_periph_reset_assert(hdmi->clk);
 841         clk_disable(hdmi->clk);
 842         regulator_disable(hdmi->pll);
 843         regulator_disable(hdmi->vdd);
 844
 845         return 0;
 846 }
 847
 848 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
 849                                          struct clk *clk, unsigned long pclk)
 850 {
 851         struct tegra_hdmi *hdmi = to_hdmi(output);
 852         struct clk *base;
 853         int err;
 854
 855         err = clk_set_parent(clk, hdmi->clk_parent);
 856         if (err < 0) {
 857                 dev_err(output->dev, "failed to set parent: %d\n", err);
 858                 return err;
 859         }
 860
 861         base = clk_get_parent(hdmi->clk_parent);
 862
 863         /*
 864          * This assumes that the parent clock is pll_d_out0 or pll_d2_out
 865          * respectively, each of which divides the base pll_d by 2.
 866          */
 867         err = clk_set_rate(base, pclk * 2);
 868         if (err < 0)
 869                 dev_err(output->dev,
 870                         "failed to set base clock rate to %lu Hz\n",
 871                         pclk * 2);
 872
 873         return 0;
 874 }
 875
 876 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
 877                                         struct drm_display_mode *mode,
 878                                         enum drm_mode_status *status)
 879 {
 880         struct tegra_hdmi *hdmi = to_hdmi(output);
 881         unsigned long pclk = mode->clock * 1000;
 882         struct clk *parent;
 883         long err;
 884
 885         parent = clk_get_parent(hdmi->clk_parent);
 886
 887         err = clk_round_rate(parent, pclk * 4);
 888         if (err < 0)
 889                 *status = MODE_NOCLOCK;
 890         else
 891                 *status = MODE_OK;
 892
 893         return 0;
 894 }
 895
 896 static const struct tegra_output_ops hdmi_ops = {
 897         .enable = tegra_output_hdmi_enable,
 898         .disable = tegra_output_hdmi_disable,
 899         .setup_clock = tegra_output_hdmi_setup_clock,
 900         .check_mode = tegra_output_hdmi_check_mode,
 901 };
 902
 903 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
 904 {
 905         struct drm_info_node *node = s->private;
 906         struct tegra_hdmi *hdmi = node->info_ent->data;
 907
 908 #define DUMP_REG(name)                                          \
 909         seq_printf(s, "%-56s %#05x %08lx\n", #name, name,       \
 910                 tegra_hdmi_readl(hdmi, name))
 911
 912         DUMP_REG(HDMI_CTXSW);
 913         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
 914         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
 915         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
 916         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
 917         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
 918         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
 919         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
 920         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
 921         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
 922         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
 923         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
 924         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
 925         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
 926         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
 927         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
 928         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
 929         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
 930         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
 931         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
 932         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
 933         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
 934         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
 935         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
 936         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
 937         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
 938         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
 939         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
 940         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
 941         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
 942         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 943         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
 944         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
 945         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
 946         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
 947         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 948         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
 949         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
 950         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
 951         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
 952         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
 953         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
 954         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 955         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
 956         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
 957         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
 958         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
 959         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
 960         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
 961         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
 962         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
 963         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
 964         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
 965         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
 966         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
 967         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
 968         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 969         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 970         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
 971         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
 972         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
 973         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
 974         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
 975         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
 976         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
 977         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
 978         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
 979         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
 980         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
 981         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
 982         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 983         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
 984         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
 985         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
 986         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
 987         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
 988         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
 989         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
 990         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
 991         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
 992         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
 993         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
 994         DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
 995         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
 996         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
 997         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
 998         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
 999         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1000         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1001         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1002         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1003         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1004         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1005         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1006         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1007         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1008         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1009         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1010         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1011         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1012         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1013         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1014         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1015         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1016         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1017         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1018         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1019         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1020         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1021         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1022         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1023         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1024         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1025         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1026         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1027         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1028         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1029         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1030         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1031         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1032         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1033         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1034         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1035         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1036         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1037         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1038         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1039         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1040         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1041         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1042         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1043         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1044         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1045         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1046         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1047         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1048         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1049         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1050         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1051         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1052         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1053         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1054         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1055         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1056         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1057         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1058         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1059         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1060         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1061         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1062         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1063         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1064         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1065         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1066         DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1067         DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1068         DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1069
1070 #undef DUMP_REG
1071
1072         return 0;
1073 }
1074
1075 static struct drm_info_list debugfs_files[] = {
1076         { "regs", tegra_hdmi_show_regs, 0, NULL },
1077 };
1078
1079 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1080                                    struct drm_minor *minor)
1081 {
1082         unsigned int i;
1083         int err;
1084
1085         hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1086         if (!hdmi->debugfs)
1087                 return -ENOMEM;
1088
1089         hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1090                                       GFP_KERNEL);
1091         if (!hdmi->debugfs_files) {
1092                 err = -ENOMEM;
1093                 goto remove;
1094         }
1095
1096         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1097                 hdmi->debugfs_files[i].data = hdmi;
1098
1099         err = drm_debugfs_create_files(hdmi->debugfs_files,
1100                                        ARRAY_SIZE(debugfs_files),
1101                                        hdmi->debugfs, minor);
1102         if (err < 0)
1103                 goto free;
1104
1105         hdmi->minor = minor;
1106
1107         return 0;
1108
1109 free:
1110         kfree(hdmi->debugfs_files);
1111         hdmi->debugfs_files = NULL;
1112 remove:
1113         debugfs_remove(hdmi->debugfs);
1114         hdmi->debugfs = NULL;
1115
1116         return err;
1117 }
1118
1119 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1120 {
1121         drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1122                                  hdmi->minor);
1123         hdmi->minor = NULL;
1124
1125         kfree(hdmi->debugfs_files);
1126         hdmi->debugfs_files = NULL;
1127
1128         debugfs_remove(hdmi->debugfs);
1129         hdmi->debugfs = NULL;
1130
1131         return 0;
1132 }
1133
1134 static int tegra_hdmi_drm_init(struct host1x_client *client,
1135                                struct drm_device *drm)
1136 {
1137         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1138         int err;
1139
1140         hdmi->output.type = TEGRA_OUTPUT_HDMI;
1141         hdmi->output.dev = client->dev;
1142         hdmi->output.ops = &hdmi_ops;
1143
1144         err = tegra_output_init(drm, &hdmi->output);
1145         if (err < 0) {
1146                 dev_err(client->dev, "output setup failed: %d\n", err);
1147                 return err;
1148         }
1149
1150         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1151                 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1152                 if (err < 0)
1153                         dev_err(client->dev, "debugfs setup failed: %d\n", err);
1154         }
1155
1156         return 0;
1157 }
1158
1159 static int tegra_hdmi_drm_exit(struct host1x_client *client)
1160 {
1161         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1162         int err;
1163
1164         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1165                 err = tegra_hdmi_debugfs_exit(hdmi);
1166                 if (err < 0)
1167                         dev_err(client->dev, "debugfs cleanup failed: %d\n",
1168                                 err);
1169         }
1170
1171         err = tegra_output_disable(&hdmi->output);
1172         if (err < 0) {
1173                 dev_err(client->dev, "output failed to disable: %d\n", err);
1174                 return err;
1175         }
1176
1177         err = tegra_output_exit(&hdmi->output);
1178         if (err < 0) {
1179                 dev_err(client->dev, "output cleanup failed: %d\n", err);
1180                 return err;
1181         }
1182
1183         return 0;
1184 }
1185
1186 static const struct host1x_client_ops hdmi_client_ops = {
1187         .drm_init = tegra_hdmi_drm_init,
1188         .drm_exit = tegra_hdmi_drm_exit,
1189 };
1190
1191 static int tegra_hdmi_probe(struct platform_device *pdev)
1192 {
1193         struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
1194         struct tegra_hdmi *hdmi;
1195         struct resource *regs;
1196         int err;
1197
1198         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1199         if (!hdmi)
1200                 return -ENOMEM;
1201
1202         hdmi->dev = &pdev->dev;
1203         hdmi->audio_source = AUTO;
1204         hdmi->audio_freq = 44100;
1205         hdmi->stereo = false;
1206         hdmi->dvi = false;
1207
1208         hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1209         if (IS_ERR(hdmi->clk)) {
1210                 dev_err(&pdev->dev, "failed to get clock\n");
1211                 return PTR_ERR(hdmi->clk);
1212         }
1213
1214         err = clk_prepare(hdmi->clk);
1215         if (err < 0)
1216                 return err;
1217
1218         hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1219         if (IS_ERR(hdmi->clk_parent))
1220                 return PTR_ERR(hdmi->clk_parent);
1221
1222         err = clk_prepare(hdmi->clk_parent);
1223         if (err < 0)
1224                 return err;
1225
1226         err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1227         if (err < 0) {
1228                 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1229                 return err;
1230         }
1231
1232         hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1233         if (IS_ERR(hdmi->vdd)) {
1234                 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1235                 return PTR_ERR(hdmi->vdd);
1236         }
1237
1238         hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1239         if (IS_ERR(hdmi->pll)) {
1240                 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1241                 return PTR_ERR(hdmi->pll);
1242         }
1243
1244         hdmi->output.dev = &pdev->dev;
1245
1246         err = tegra_output_parse_dt(&hdmi->output);
1247         if (err < 0)
1248                 return err;
1249
1250         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1251         if (!regs)
1252                 return -ENXIO;
1253
1254         hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1255         if (IS_ERR(hdmi->regs))
1256                 return PTR_ERR(hdmi->regs);
1257
1258         err = platform_get_irq(pdev, 0);
1259         if (err < 0)
1260                 return err;
1261
1262         hdmi->irq = err;
1263
1264         hdmi->client.ops = &hdmi_client_ops;
1265         INIT_LIST_HEAD(&hdmi->client.list);
1266         hdmi->client.dev = &pdev->dev;
1267
1268         err = host1x_register_client(host1x, &hdmi->client);
1269         if (err < 0) {
1270                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1271                         err);
1272                 return err;
1273         }
1274
1275         platform_set_drvdata(pdev, hdmi);
1276
1277         return 0;
1278 }
1279
1280 static int tegra_hdmi_remove(struct platform_device *pdev)
1281 {
1282         struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
1283         struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1284         int err;
1285
1286         err = host1x_unregister_client(host1x, &hdmi->client);
1287         if (err < 0) {
1288                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1289                         err);
1290                 return err;
1291         }
1292
1293         clk_unprepare(hdmi->clk_parent);
1294         clk_unprepare(hdmi->clk);
1295
1296         return 0;
1297 }
1298
1299 static struct of_device_id tegra_hdmi_of_match[] = {
1300         { .compatible = "nvidia,tegra30-hdmi", },
1301         { .compatible = "nvidia,tegra20-hdmi", },
1302         { },
1303 };
1304
1305 struct platform_driver tegra_hdmi_driver = {
1306         .driver = {
1307                 .name = "tegra-hdmi",
1308                 .owner = THIS_MODULE,
1309                 .of_match_table = tegra_hdmi_of_match,
1310         },
1311         .probe = tegra_hdmi_probe,
1312         .remove = tegra_hdmi_remove,
1313 };