2 * Copyright 2016 Linaro Ltd.
3 * Copyright 2016 ZTE Corporation.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
11 #ifndef __ZX_VOU_REGS_H__
12 #define __ZX_VOU_REGS_H__
14 /* Sub-module offset */
15 #define MAIN_GL_OFFSET 0x130
16 #define MAIN_CSC_OFFSET 0x580
17 #define MAIN_HBSC_OFFSET 0x820
18 #define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */
20 #define AUX_GL_OFFSET 0x200
21 #define AUX_CSC_OFFSET 0x5d0
22 #define AUX_HBSC_OFFSET 0x860
23 #define AUX_RSZ_OFFSET 0x800
25 #define OSD_VL0_OFFSET 0x040
26 #define OSD_VL_OFFSET(i) (OSD_VL0_OFFSET + 0x050 * (i))
28 #define HBSC_VL0_OFFSET 0x760
29 #define HBSC_VL_OFFSET(i) (HBSC_VL0_OFFSET + 0x040 * (i))
31 #define RSZ_VL1_U0 0xa00
32 #define RSZ_VL_OFFSET(i) (RSZ_VL1_U0 + 0x200 * (i))
34 /* OSD (GPC_GLOBAL) registers */
35 #define OSD_INT_STA 0x04
36 #define OSD_INT_CLRSTA 0x08
37 #define OSD_INT_MSK 0x0c
38 #define OSD_INT_AUX_UPT BIT(14)
39 #define OSD_INT_MAIN_UPT BIT(13)
40 #define OSD_INT_GL1_LBW BIT(10)
41 #define OSD_INT_GL0_LBW BIT(9)
42 #define OSD_INT_VL2_LBW BIT(8)
43 #define OSD_INT_VL1_LBW BIT(7)
44 #define OSD_INT_VL0_LBW BIT(6)
45 #define OSD_INT_BUS_ERR BIT(3)
46 #define OSD_INT_CFG_ERR BIT(2)
47 #define OSD_INT_ERROR (\
48 OSD_INT_GL1_LBW | OSD_INT_GL0_LBW | \
49 OSD_INT_VL2_LBW | OSD_INT_VL1_LBW | OSD_INT_VL0_LBW | \
50 OSD_INT_BUS_ERR | OSD_INT_CFG_ERR \
52 #define OSD_INT_ENABLE (OSD_INT_ERROR | OSD_INT_AUX_UPT | OSD_INT_MAIN_UPT)
53 #define OSD_CTRL0 0x10
54 #define OSD_CTRL0_VL0_EN BIT(13)
55 #define OSD_CTRL0_VL0_SEL BIT(12)
56 #define OSD_CTRL0_VL1_EN BIT(11)
57 #define OSD_CTRL0_VL1_SEL BIT(10)
58 #define OSD_CTRL0_VL2_EN BIT(9)
59 #define OSD_CTRL0_VL2_SEL BIT(8)
60 #define OSD_CTRL0_GL0_EN BIT(7)
61 #define OSD_CTRL0_GL0_SEL BIT(6)
62 #define OSD_CTRL0_GL1_EN BIT(5)
63 #define OSD_CTRL0_GL1_SEL BIT(4)
64 #define OSD_RST_CLR 0x1c
65 #define RST_PER_FRAME BIT(19)
67 /* Main/Aux channel registers */
68 #define OSD_MAIN_CHN 0x470
69 #define OSD_AUX_CHN 0x4d0
70 #define CHN_CTRL0 0x00
71 #define CHN_ENABLE BIT(0)
72 #define CHN_CTRL1 0x04
73 #define CHN_SCREEN_W_SHIFT 18
74 #define CHN_SCREEN_W_MASK (0x1fff << CHN_SCREEN_W_SHIFT)
75 #define CHN_SCREEN_H_SHIFT 5
76 #define CHN_SCREEN_H_MASK (0x1fff << CHN_SCREEN_H_SHIFT)
77 #define CHN_UPDATE 0x08
78 #define CHN_INTERLACE_BUF_CTRL 0x24
79 #define CHN_INTERLACE_EN BIT(2)
81 /* TIMING_CTRL registers */
82 #define TIMING_TC_ENABLE 0x04
83 #define AUX_TC_EN BIT(1)
84 #define MAIN_TC_EN BIT(0)
85 #define FIR_MAIN_ACTIVE 0x08
86 #define FIR_AUX_ACTIVE 0x0c
87 #define V_ACTIVE_SHIFT 16
88 #define V_ACTIVE_MASK (0xffff << V_ACTIVE_SHIFT)
89 #define H_ACTIVE_SHIFT 0
90 #define H_ACTIVE_MASK (0xffff << H_ACTIVE_SHIFT)
91 #define FIR_MAIN_H_TIMING 0x10
92 #define FIR_MAIN_V_TIMING 0x14
93 #define FIR_AUX_H_TIMING 0x18
94 #define FIR_AUX_V_TIMING 0x1c
95 #define SYNC_WIDE_SHIFT 22
96 #define SYNC_WIDE_MASK (0x3ff << SYNC_WIDE_SHIFT)
97 #define BACK_PORCH_SHIFT 11
98 #define BACK_PORCH_MASK (0x7ff << BACK_PORCH_SHIFT)
99 #define FRONT_PORCH_SHIFT 0
100 #define FRONT_PORCH_MASK (0x7ff << FRONT_PORCH_SHIFT)
101 #define TIMING_CTRL 0x20
102 #define AUX_POL_SHIFT 3
103 #define AUX_POL_MASK (0x7 << AUX_POL_SHIFT)
104 #define MAIN_POL_SHIFT 0
105 #define MAIN_POL_MASK (0x7 << MAIN_POL_SHIFT)
106 #define POL_DE_SHIFT 2
107 #define POL_VSYNC_SHIFT 1
108 #define POL_HSYNC_SHIFT 0
109 #define TIMING_INT_CTRL 0x24
110 #define TIMING_INT_STATE 0x28
111 #define TIMING_INT_AUX_FRAME BIT(3)
112 #define TIMING_INT_MAIN_FRAME BIT(1)
113 #define TIMING_INT_AUX_FRAME_SEL_VSW (0x2 << 10)
114 #define TIMING_INT_MAIN_FRAME_SEL_VSW (0x2 << 6)
115 #define TIMING_INT_ENABLE (\
116 TIMING_INT_MAIN_FRAME_SEL_VSW | TIMING_INT_AUX_FRAME_SEL_VSW | \
117 TIMING_INT_MAIN_FRAME | TIMING_INT_AUX_FRAME \
119 #define TIMING_MAIN_SHIFT 0x2c
120 #define TIMING_AUX_SHIFT 0x30
121 #define H_SHIFT_VAL 0x0048
122 #define V_SHIFT_VAL 0x0001
123 #define SCAN_CTRL 0x34
124 #define AUX_PI_EN BIT(19)
125 #define MAIN_PI_EN BIT(18)
126 #define AUX_INTERLACE_SEL BIT(1)
127 #define MAIN_INTERLACE_SEL BIT(0)
128 #define SEC_V_ACTIVE 0x38
129 #define SEC_VACT_MAIN_SHIFT 0
130 #define SEC_VACT_MAIN_MASK (0xffff << SEC_VACT_MAIN_SHIFT)
131 #define SEC_VACT_AUX_SHIFT 16
132 #define SEC_VACT_AUX_MASK (0xffff << SEC_VACT_AUX_SHIFT)
133 #define SEC_MAIN_V_TIMING 0x3c
134 #define SEC_AUX_V_TIMING 0x40
135 #define TIMING_MAIN_PI_SHIFT 0x68
136 #define TIMING_AUX_PI_SHIFT 0x6c
137 #define H_PI_SHIFT_VAL 0x000f
139 #define V_ACTIVE(x) (((x) << V_ACTIVE_SHIFT) & V_ACTIVE_MASK)
140 #define H_ACTIVE(x) (((x) << H_ACTIVE_SHIFT) & H_ACTIVE_MASK)
142 #define SYNC_WIDE(x) (((x) << SYNC_WIDE_SHIFT) & SYNC_WIDE_MASK)
143 #define BACK_PORCH(x) (((x) << BACK_PORCH_SHIFT) & BACK_PORCH_MASK)
144 #define FRONT_PORCH(x) (((x) << FRONT_PORCH_SHIFT) & FRONT_PORCH_MASK)
147 #define DTRC_F0_CTRL 0x2c
148 #define DTRC_F1_CTRL 0x5c
149 #define DTRC_DECOMPRESS_BYPASS BIT(17)
150 #define DTRC_DETILE_CTRL 0x68
151 #define TILE2RASTESCAN_BYPASS_MODE BIT(30)
152 #define DETILE_ARIDR_MODE_MASK (0x3 << 0)
153 #define DETILE_ARID_ALL 0
154 #define DETILE_ARID_IN_ARIDR 1
155 #define DETILE_ARID_BYP_BUT_ARIDR 2
156 #define DETILE_ARID_IN_ARIDR2 3
157 #define DTRC_ARID 0x6c
158 #define DTRC_ARID3_SHIFT 24
159 #define DTRC_ARID3_MASK (0xff << DTRC_ARID3_SHIFT)
160 #define DTRC_ARID2_SHIFT 16
161 #define DTRC_ARID2_MASK (0xff << DTRC_ARID2_SHIFT)
162 #define DTRC_ARID1_SHIFT 8
163 #define DTRC_ARID1_MASK (0xff << DTRC_ARID1_SHIFT)
164 #define DTRC_ARID0_SHIFT 0
165 #define DTRC_ARID0_MASK (0xff << DTRC_ARID0_SHIFT)
166 #define DTRC_DEC2DDR_ARID 0x70
168 #define DTRC_ARID3(x) (((x) << DTRC_ARID3_SHIFT) & DTRC_ARID3_MASK)
169 #define DTRC_ARID2(x) (((x) << DTRC_ARID2_SHIFT) & DTRC_ARID2_MASK)
170 #define DTRC_ARID1(x) (((x) << DTRC_ARID1_SHIFT) & DTRC_ARID1_MASK)
171 #define DTRC_ARID0(x) (((x) << DTRC_ARID0_SHIFT) & DTRC_ARID0_MASK)
173 /* VOU_CTRL registers */
174 #define VOU_INF_EN 0x00
175 #define VOU_INF_CH_SEL 0x04
176 #define VOU_INF_DATA_SEL 0x08
177 #define VOU_SOFT_RST 0x14
178 #define VOU_CLK_SEL 0x18
179 #define VGA_AUX_DIV_SHIFT 29
180 #define VGA_MAIN_DIV_SHIFT 26
181 #define PIC_MAIN_DIV_SHIFT 23
182 #define PIC_AUX_DIV_SHIFT 20
183 #define VOU_CLK_VL2_SEL BIT(8)
184 #define VOU_CLK_VL1_SEL BIT(7)
185 #define VOU_CLK_VL0_SEL BIT(6)
186 #define VOU_CLK_GL1_SEL BIT(5)
187 #define VOU_CLK_GL0_SEL BIT(4)
188 #define VOU_DIV_PARA 0x1c
189 #define DIV_PARA_UPDATE BIT(31)
190 #define TVENC_AUX_DIV_SHIFT 28
191 #define HDMI_AUX_PNX_DIV_SHIFT 25
192 #define HDMI_MAIN_PNX_DIV_SHIFT 22
193 #define HDMI_AUX_DIV_SHIFT 19
194 #define HDMI_MAIN_DIV_SHIFT 16
195 #define TVENC_MAIN_DIV_SHIFT 13
196 #define INF_AUX_DIV_SHIFT 9
197 #define INF_MAIN_DIV_SHIFT 6
198 #define LAYER_AUX_DIV_SHIFT 3
199 #define LAYER_MAIN_DIV_SHIFT 0
200 #define VOU_CLK_REQEN 0x20
201 #define VOU_CLK_EN 0x24
202 #define VOU_INF_HDMI_CTRL 0x30
203 #define VOU_HDMI_AUD_MASK 0x1f
205 /* OTFPPU_CTRL registers */
206 #define OTFPPU_RSZ_DATA_SOURCE 0x04
208 #endif /* __ZX_VOU_REGS_H__ */