2 * Copyright © 2014 Broadcom
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * DOC: Shader validator for VC4.
27 * The VC4 has no IOMMU between it and system memory, so a user with
28 * access to execute shaders could escalate privilege by overwriting
29 * system memory (using the VPM write address register in the
30 * general-purpose DMA mode) or reading system memory it shouldn't
31 * (reading it as a texture, or uniform data, or vertex data).
33 * This walks over a shader BO, ensuring that its accesses are
34 * appropriately bounded, and recording how many texture accesses are
35 * made and where so that we can do relocations for them in the
40 #include "vc4_qpu_defines.h"
42 #define LIVE_REG_COUNT (32 + 32 + 4)
44 struct vc4_shader_validation_state {
45 /* Current IP being validated. */
48 /* IP at the end of the BO, do not read shader[max_ip] */
53 struct vc4_texture_sample_info tmu_setup[2];
54 int tmu_write_count[2];
56 /* For registers that were last written to by a MIN instruction with
57 * one argument being a uniform, the address of the uniform.
60 * This is used for the validation of direct address memory reads.
62 uint32_t live_min_clamp_offsets[LIVE_REG_COUNT];
63 bool live_max_clamp_regs[LIVE_REG_COUNT];
64 uint32_t live_immediates[LIVE_REG_COUNT];
66 /* Bitfield of which IPs are used as branch targets.
68 * Used for validation that the uniform stream is updated at the right
69 * points and clearing the texturing/clamping state.
71 unsigned long *branch_targets;
73 /* Set when entering a basic block, and cleared when the uniform
74 * address update is found. This is used to make sure that we don't
75 * read uniforms when the address is undefined.
77 bool needs_uniform_address_update;
79 /* Set when we find a backwards branch. If the branch is backwards,
80 * the taraget is probably doing an address reset to read uniforms,
81 * and so we need to be sure that a uniforms address is present in the
82 * stream, even if the shader didn't need to read uniforms in later
85 bool needs_uniform_address_for_loop;
87 /* Set when we find an instruction writing the top half of the
88 * register files. If we allowed writing the unusable regs in
89 * a threaded shader, then the other shader running on our
90 * QPU's clamp validation would be invalid.
92 bool all_registers_used;
96 waddr_to_live_reg_index(uint32_t waddr, bool is_b)
103 } else if (waddr <= QPU_W_ACC3) {
104 return 64 + waddr - QPU_W_ACC0;
111 raddr_add_a_to_live_reg_index(uint64_t inst)
113 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
114 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
115 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
116 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
118 if (add_a == QPU_MUX_A)
120 else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM)
122 else if (add_a <= QPU_MUX_R3)
129 live_reg_is_upper_half(uint32_t lri)
131 return (lri >= 16 && lri < 32) ||
132 (lri >= 32 + 16 && lri < 32 + 32);
136 is_tmu_submit(uint32_t waddr)
138 return (waddr == QPU_W_TMU0_S ||
139 waddr == QPU_W_TMU1_S);
143 is_tmu_write(uint32_t waddr)
145 return (waddr >= QPU_W_TMU0_S &&
146 waddr <= QPU_W_TMU1_B);
150 record_texture_sample(struct vc4_validated_shader_info *validated_shader,
151 struct vc4_shader_validation_state *validation_state,
154 uint32_t s = validated_shader->num_texture_samples;
156 struct vc4_texture_sample_info *temp_samples;
158 temp_samples = krealloc(validated_shader->texture_samples,
159 (s + 1) * sizeof(*temp_samples),
164 memcpy(&temp_samples[s],
165 &validation_state->tmu_setup[tmu],
166 sizeof(*temp_samples));
168 validated_shader->num_texture_samples = s + 1;
169 validated_shader->texture_samples = temp_samples;
171 for (i = 0; i < 4; i++)
172 validation_state->tmu_setup[tmu].p_offset[i] = ~0;
178 check_tmu_write(struct vc4_validated_shader_info *validated_shader,
179 struct vc4_shader_validation_state *validation_state,
182 uint64_t inst = validation_state->shader[validation_state->ip];
183 uint32_t waddr = (is_mul ?
184 QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
185 QPU_GET_FIELD(inst, QPU_WADDR_ADD));
186 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
187 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
188 int tmu = waddr > QPU_W_TMU0_B;
189 bool submit = is_tmu_submit(waddr);
190 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0;
191 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
194 uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
195 uint32_t clamp_reg, clamp_offset;
197 if (sig == QPU_SIG_SMALL_IMM) {
198 DRM_ERROR("direct TMU read used small immediate\n");
202 /* Make sure that this texture load is an add of the base
203 * address of the UBO to a clamped offset within the UBO.
206 QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
207 DRM_ERROR("direct TMU load wasn't an add\n");
211 /* We assert that the clamped address is the first
212 * argument, and the UBO base address is the second argument.
213 * This is arbitrary, but simpler than supporting flipping the
216 clamp_reg = raddr_add_a_to_live_reg_index(inst);
217 if (clamp_reg == ~0) {
218 DRM_ERROR("direct TMU load wasn't clamped\n");
222 clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg];
223 if (clamp_offset == ~0) {
224 DRM_ERROR("direct TMU load wasn't clamped\n");
228 /* Store the clamp value's offset in p1 (see reloc_tex() in
231 validation_state->tmu_setup[tmu].p_offset[1] =
234 if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
235 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
236 DRM_ERROR("direct TMU load didn't add to a uniform\n");
240 validation_state->tmu_setup[tmu].is_direct = true;
242 if (raddr_a == QPU_R_UNIF || (sig != QPU_SIG_SMALL_IMM &&
243 raddr_b == QPU_R_UNIF)) {
244 DRM_ERROR("uniform read in the same instruction as "
250 if (validation_state->tmu_write_count[tmu] >= 4) {
251 DRM_ERROR("TMU%d got too many parameters before dispatch\n",
255 validation_state->tmu_setup[tmu].p_offset[validation_state->tmu_write_count[tmu]] =
256 validated_shader->uniforms_size;
257 validation_state->tmu_write_count[tmu]++;
258 /* Since direct uses a RADDR uniform reference, it will get counted in
259 * check_instruction_reads()
262 if (validation_state->needs_uniform_address_update) {
263 DRM_ERROR("Texturing with undefined uniform address\n");
267 validated_shader->uniforms_size += 4;
271 if (!record_texture_sample(validated_shader,
272 validation_state, tmu)) {
276 validation_state->tmu_write_count[tmu] = 0;
282 static bool require_uniform_address_uniform(struct vc4_validated_shader_info *validated_shader)
284 uint32_t o = validated_shader->num_uniform_addr_offsets;
285 uint32_t num_uniforms = validated_shader->uniforms_size / 4;
287 validated_shader->uniform_addr_offsets =
288 krealloc(validated_shader->uniform_addr_offsets,
290 sizeof(*validated_shader->uniform_addr_offsets),
292 if (!validated_shader->uniform_addr_offsets)
295 validated_shader->uniform_addr_offsets[o] = num_uniforms;
296 validated_shader->num_uniform_addr_offsets++;
302 validate_uniform_address_write(struct vc4_validated_shader_info *validated_shader,
303 struct vc4_shader_validation_state *validation_state,
306 uint64_t inst = validation_state->shader[validation_state->ip];
307 u32 add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
308 u32 raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
309 u32 raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
310 u32 add_lri = raddr_add_a_to_live_reg_index(inst);
311 /* We want our reset to be pointing at whatever uniform follows the
312 * uniforms base address.
314 u32 expected_offset = validated_shader->uniforms_size + 4;
316 /* We only support absolute uniform address changes, and we
317 * require that they be in the current basic block before any
318 * of its uniform reads.
320 * One could potentially emit more efficient QPU code, by
321 * noticing that (say) an if statement does uniform control
322 * flow for all threads and that the if reads the same number
323 * of uniforms on each side. However, this scheme is easy to
324 * validate so it's all we allow for now.
326 switch (QPU_GET_FIELD(inst, QPU_SIG)) {
328 case QPU_SIG_SCOREBOARD_UNLOCK:
329 case QPU_SIG_COLOR_LOAD:
330 case QPU_SIG_LOAD_TMU0:
331 case QPU_SIG_LOAD_TMU1:
334 DRM_ERROR("uniforms address change must be "
339 if (is_mul || QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
340 DRM_ERROR("Uniform address reset must be an ADD.\n");
344 if (QPU_GET_FIELD(inst, QPU_COND_ADD) != QPU_COND_ALWAYS) {
345 DRM_ERROR("Uniform address reset must be unconditional.\n");
349 if (QPU_GET_FIELD(inst, QPU_PACK) != QPU_PACK_A_NOP &&
351 DRM_ERROR("No packing allowed on uniforms reset\n");
356 DRM_ERROR("First argument of uniform address write must be "
357 "an immediate value.\n");
361 if (validation_state->live_immediates[add_lri] != expected_offset) {
362 DRM_ERROR("Resetting uniforms with offset %db instead of %db\n",
363 validation_state->live_immediates[add_lri],
368 if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
369 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
370 DRM_ERROR("Second argument of uniform address write must be "
375 validation_state->needs_uniform_address_update = false;
376 validation_state->needs_uniform_address_for_loop = false;
377 return require_uniform_address_uniform(validated_shader);
381 check_reg_write(struct vc4_validated_shader_info *validated_shader,
382 struct vc4_shader_validation_state *validation_state,
385 uint64_t inst = validation_state->shader[validation_state->ip];
386 uint32_t waddr = (is_mul ?
387 QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
388 QPU_GET_FIELD(inst, QPU_WADDR_ADD));
389 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
390 bool ws = inst & QPU_WS;
391 bool is_b = is_mul ^ ws;
392 u32 lri = waddr_to_live_reg_index(waddr, is_b);
395 uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
396 uint32_t cond_mul = QPU_GET_FIELD(inst, QPU_COND_MUL);
398 if (sig == QPU_SIG_LOAD_IMM &&
399 QPU_GET_FIELD(inst, QPU_PACK) == QPU_PACK_A_NOP &&
400 ((is_mul && cond_mul == QPU_COND_ALWAYS) ||
401 (!is_mul && cond_add == QPU_COND_ALWAYS))) {
402 validation_state->live_immediates[lri] =
403 QPU_GET_FIELD(inst, QPU_LOAD_IMM);
405 validation_state->live_immediates[lri] = ~0;
408 if (live_reg_is_upper_half(lri))
409 validation_state->all_registers_used = true;
413 case QPU_W_UNIFORMS_ADDRESS:
415 DRM_ERROR("relative uniforms address change "
420 return validate_uniform_address_write(validated_shader,
424 case QPU_W_TLB_COLOR_MS:
425 case QPU_W_TLB_COLOR_ALL:
427 /* These only interact with the tile buffer, not main memory,
440 return check_tmu_write(validated_shader, validation_state,
444 case QPU_W_TMU_NOSWAP:
445 case QPU_W_TLB_ALPHA_MASK:
446 case QPU_W_MUTEX_RELEASE:
447 /* XXX: I haven't thought about these, so don't support them
450 DRM_ERROR("Unsupported waddr %d\n", waddr);
454 DRM_ERROR("General VPM DMA unsupported\n");
458 case QPU_W_VPMVCD_SETUP:
459 /* We allow VPM setup in general, even including VPM DMA
460 * configuration setup, because the (unsafe) DMA can only be
461 * triggered by QPU_W_VPM_ADDR writes.
465 case QPU_W_TLB_STENCIL_SETUP:
473 track_live_clamps(struct vc4_validated_shader_info *validated_shader,
474 struct vc4_shader_validation_state *validation_state)
476 uint64_t inst = validation_state->shader[validation_state->ip];
477 uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
478 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
479 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
480 uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
481 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
482 uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
483 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
484 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
485 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
486 bool ws = inst & QPU_WS;
487 uint32_t lri_add_a, lri_add, lri_mul;
490 /* Check whether OP_ADD's A argumennt comes from a live MAX(x, 0),
491 * before we clear previous live state.
493 lri_add_a = raddr_add_a_to_live_reg_index(inst);
494 add_a_is_min_0 = (lri_add_a != ~0 &&
495 validation_state->live_max_clamp_regs[lri_add_a]);
497 /* Clear live state for registers written by our instruction. */
498 lri_add = waddr_to_live_reg_index(waddr_add, ws);
499 lri_mul = waddr_to_live_reg_index(waddr_mul, !ws);
501 validation_state->live_max_clamp_regs[lri_mul] = false;
502 validation_state->live_min_clamp_offsets[lri_mul] = ~0;
505 validation_state->live_max_clamp_regs[lri_add] = false;
506 validation_state->live_min_clamp_offsets[lri_add] = ~0;
508 /* Nothing further to do for live tracking, since only ADDs
509 * generate new live clamp registers.
514 /* Now, handle remaining live clamp tracking for the ADD operation. */
516 if (cond_add != QPU_COND_ALWAYS)
519 if (op_add == QPU_A_MAX) {
520 /* Track live clamps of a value to a minimum of 0 (in either
523 if (sig != QPU_SIG_SMALL_IMM || raddr_b != 0 ||
524 (add_a != QPU_MUX_B && add_b != QPU_MUX_B)) {
528 validation_state->live_max_clamp_regs[lri_add] = true;
529 } else if (op_add == QPU_A_MIN) {
530 /* Track live clamps of a value clamped to a minimum of 0 and
531 * a maximum of some uniform's offset.
536 if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
537 !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF &&
538 sig != QPU_SIG_SMALL_IMM)) {
542 validation_state->live_min_clamp_offsets[lri_add] =
543 validated_shader->uniforms_size;
548 check_instruction_writes(struct vc4_validated_shader_info *validated_shader,
549 struct vc4_shader_validation_state *validation_state)
551 uint64_t inst = validation_state->shader[validation_state->ip];
552 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
553 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
556 if (is_tmu_write(waddr_add) && is_tmu_write(waddr_mul)) {
557 DRM_ERROR("ADD and MUL both set up textures\n");
561 ok = (check_reg_write(validated_shader, validation_state, false) &&
562 check_reg_write(validated_shader, validation_state, true));
564 track_live_clamps(validated_shader, validation_state);
570 check_branch(uint64_t inst,
571 struct vc4_validated_shader_info *validated_shader,
572 struct vc4_shader_validation_state *validation_state,
575 int32_t branch_imm = QPU_GET_FIELD(inst, QPU_BRANCH_TARGET);
576 uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
577 uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
579 if ((int)branch_imm < 0)
580 validation_state->needs_uniform_address_for_loop = true;
582 /* We don't want to have to worry about validation of this, and
583 * there's no need for it.
585 if (waddr_add != QPU_W_NOP || waddr_mul != QPU_W_NOP) {
586 DRM_ERROR("branch instruction at %d wrote a register.\n",
587 validation_state->ip);
595 check_instruction_reads(struct vc4_validated_shader_info *validated_shader,
596 struct vc4_shader_validation_state *validation_state)
598 uint64_t inst = validation_state->shader[validation_state->ip];
599 uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
600 uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
601 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
603 if (raddr_a == QPU_R_UNIF ||
604 (raddr_b == QPU_R_UNIF && sig != QPU_SIG_SMALL_IMM)) {
605 /* This can't overflow the uint32_t, because we're reading 8
606 * bytes of instruction to increment by 4 here, so we'd
609 validated_shader->uniforms_size += 4;
611 if (validation_state->needs_uniform_address_update) {
612 DRM_ERROR("Uniform read with undefined uniform "
618 if ((raddr_a >= 16 && raddr_a < 32) ||
619 (raddr_b >= 16 && raddr_b < 32 && sig != QPU_SIG_SMALL_IMM)) {
620 validation_state->all_registers_used = true;
626 /* Make sure that all branches are absolute and point within the shader, and
627 * note their targets for later.
630 vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
632 uint32_t max_branch_target = 0;
634 int last_branch = -2;
636 for (ip = 0; ip < validation_state->max_ip; ip++) {
637 uint64_t inst = validation_state->shader[ip];
638 int32_t branch_imm = QPU_GET_FIELD(inst, QPU_BRANCH_TARGET);
639 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
640 uint32_t after_delay_ip = ip + 4;
641 uint32_t branch_target_ip;
643 if (sig == QPU_SIG_PROG_END) {
644 /* There are two delay slots after program end is
645 * signaled that are still executed, then we're
646 * finished. validation_state->max_ip is the
647 * instruction after the last valid instruction in the
650 validation_state->max_ip = ip + 3;
654 if (sig != QPU_SIG_BRANCH)
657 if (ip - last_branch < 4) {
658 DRM_ERROR("Branch at %d during delay slots\n", ip);
663 if (inst & QPU_BRANCH_REG) {
664 DRM_ERROR("branching from register relative "
669 if (!(inst & QPU_BRANCH_REL)) {
670 DRM_ERROR("relative branching required\n");
674 /* The actual branch target is the instruction after the delay
675 * slots, plus whatever byte offset is in the low 32 bits of
676 * the instruction. Make sure we're not branching beyond the
677 * end of the shader object.
679 if (branch_imm % sizeof(inst) != 0) {
680 DRM_ERROR("branch target not aligned\n");
684 branch_target_ip = after_delay_ip + (branch_imm >> 3);
685 if (branch_target_ip >= validation_state->max_ip) {
686 DRM_ERROR("Branch at %d outside of shader (ip %d/%d)\n",
687 ip, branch_target_ip,
688 validation_state->max_ip);
691 set_bit(branch_target_ip, validation_state->branch_targets);
693 /* Make sure that the non-branching path is also not outside
696 if (after_delay_ip >= validation_state->max_ip) {
697 DRM_ERROR("Branch at %d continues past shader end "
699 ip, after_delay_ip, validation_state->max_ip);
702 set_bit(after_delay_ip, validation_state->branch_targets);
703 max_branch_target = max(max_branch_target, after_delay_ip);
706 if (max_branch_target > validation_state->max_ip - 3) {
707 DRM_ERROR("Branch landed after QPU_SIG_PROG_END");
714 /* Resets any known state for the shader, used when we may be branched to from
715 * multiple locations in the program (or at shader start).
718 reset_validation_state(struct vc4_shader_validation_state *validation_state)
722 for (i = 0; i < 8; i++)
723 validation_state->tmu_setup[i / 4].p_offset[i % 4] = ~0;
725 for (i = 0; i < LIVE_REG_COUNT; i++) {
726 validation_state->live_min_clamp_offsets[i] = ~0;
727 validation_state->live_max_clamp_regs[i] = false;
728 validation_state->live_immediates[i] = ~0;
733 texturing_in_progress(struct vc4_shader_validation_state *validation_state)
735 return (validation_state->tmu_write_count[0] != 0 ||
736 validation_state->tmu_write_count[1] != 0);
740 vc4_handle_branch_target(struct vc4_shader_validation_state *validation_state)
742 uint32_t ip = validation_state->ip;
744 if (!test_bit(ip, validation_state->branch_targets))
747 if (texturing_in_progress(validation_state)) {
748 DRM_ERROR("Branch target landed during TMU setup\n");
752 /* Reset our live values tracking, since this instruction may have
753 * multiple predecessors.
755 * One could potentially do analysis to determine that, for
756 * example, all predecessors have a live max clamp in the same
757 * register, but we don't bother with that.
759 reset_validation_state(validation_state);
761 /* Since we've entered a basic block from potentially multiple
762 * predecessors, we need the uniforms address to be updated before any
763 * unforms are read. We require that after any branch point, the next
764 * uniform to be loaded is a uniform address offset. That uniform's
765 * offset will be marked by the uniform address register write
766 * validation, or a one-off the end-of-program check.
768 validation_state->needs_uniform_address_update = true;
773 struct vc4_validated_shader_info *
774 vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
776 bool found_shader_end = false;
777 int shader_end_ip = 0;
778 uint32_t last_thread_switch_ip = -3;
780 struct vc4_validated_shader_info *validated_shader = NULL;
781 struct vc4_shader_validation_state validation_state;
783 memset(&validation_state, 0, sizeof(validation_state));
784 validation_state.shader = shader_obj->vaddr;
785 validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t);
787 reset_validation_state(&validation_state);
789 validation_state.branch_targets =
790 kcalloc(BITS_TO_LONGS(validation_state.max_ip),
791 sizeof(unsigned long), GFP_KERNEL);
792 if (!validation_state.branch_targets)
795 validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL);
796 if (!validated_shader)
799 if (!vc4_validate_branches(&validation_state))
802 for (ip = 0; ip < validation_state.max_ip; ip++) {
803 uint64_t inst = validation_state.shader[ip];
804 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
806 validation_state.ip = ip;
808 if (!vc4_handle_branch_target(&validation_state))
811 if (ip == last_thread_switch_ip + 3) {
812 /* Reset r0-r3 live clamp data */
815 for (i = 64; i < LIVE_REG_COUNT; i++) {
816 validation_state.live_min_clamp_offsets[i] = ~0;
817 validation_state.live_max_clamp_regs[i] = false;
818 validation_state.live_immediates[i] = ~0;
824 case QPU_SIG_WAIT_FOR_SCOREBOARD:
825 case QPU_SIG_SCOREBOARD_UNLOCK:
826 case QPU_SIG_COLOR_LOAD:
827 case QPU_SIG_LOAD_TMU0:
828 case QPU_SIG_LOAD_TMU1:
829 case QPU_SIG_PROG_END:
830 case QPU_SIG_SMALL_IMM:
831 case QPU_SIG_THREAD_SWITCH:
832 case QPU_SIG_LAST_THREAD_SWITCH:
833 if (!check_instruction_writes(validated_shader,
834 &validation_state)) {
835 DRM_ERROR("Bad write at ip %d\n", ip);
839 if (!check_instruction_reads(validated_shader,
843 if (sig == QPU_SIG_PROG_END) {
844 found_shader_end = true;
848 if (sig == QPU_SIG_THREAD_SWITCH ||
849 sig == QPU_SIG_LAST_THREAD_SWITCH) {
850 validated_shader->is_threaded = true;
852 if (ip < last_thread_switch_ip + 3) {
853 DRM_ERROR("Thread switch too soon after "
854 "last switch at ip %d\n", ip);
857 last_thread_switch_ip = ip;
862 case QPU_SIG_LOAD_IMM:
863 if (!check_instruction_writes(validated_shader,
864 &validation_state)) {
865 DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
871 if (!check_branch(inst, validated_shader,
872 &validation_state, ip))
875 if (ip < last_thread_switch_ip + 3) {
876 DRM_ERROR("Branch in thread switch at ip %d",
883 DRM_ERROR("Unsupported QPU signal %d at "
884 "instruction %d\n", sig, ip);
888 /* There are two delay slots after program end is signaled
889 * that are still executed, then we're finished.
891 if (found_shader_end && ip == shader_end_ip + 2)
895 if (ip == validation_state.max_ip) {
896 DRM_ERROR("shader failed to terminate before "
897 "shader BO end at %zd\n",
898 shader_obj->base.size);
902 /* Might corrupt other thread */
903 if (validated_shader->is_threaded &&
904 validation_state.all_registers_used) {
905 DRM_ERROR("Shader uses threading, but uses the upper "
906 "half of the registers, too\n");
910 /* If we did a backwards branch and we haven't emitted a uniforms
911 * reset since then, we still need the uniforms stream to have the
912 * uniforms address available so that the backwards branch can do its
915 * We could potentially prove that the backwards branch doesn't
916 * contain any uses of uniforms until program exit, but that doesn't
917 * seem to be worth the trouble.
919 if (validation_state.needs_uniform_address_for_loop) {
920 if (!require_uniform_address_uniform(validated_shader))
922 validated_shader->uniforms_size += 4;
925 /* Again, no chance of integer overflow here because the worst case
926 * scenario is 8 bytes of uniforms plus handles per 8-byte
929 validated_shader->uniforms_src_size =
930 (validated_shader->uniforms_size +
931 4 * validated_shader->num_texture_samples);
933 kfree(validation_state.branch_targets);
935 return validated_shader;
938 kfree(validation_state.branch_targets);
939 if (validated_shader) {
940 kfree(validated_shader->texture_samples);
941 kfree(validated_shader);