drivers/gpu/drm/sun4i/sun4i_backend.h

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <maxime.ripard@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #ifndef _SUN4I_BACKEND_H_
  14 #define _SUN4I_BACKEND_H_
  15
  16 #include <linux/clk.h>
  17 #include <linux/list.h>
  18 #include <linux/of.h>
  19 #include <linux/regmap.h>
  20 #include <linux/reset.h>
  21
  22 #include "sunxi_engine.h"
  23
  24 #define SUN4I_BACKEND_MODCTL_REG                0x800
  25 #define SUN4I_BACKEND_MODCTL_LINE_SEL                   BIT(29)
  26 #define SUN4I_BACKEND_MODCTL_ITLMOD_EN                  BIT(28)
  27 #define SUN4I_BACKEND_MODCTL_OUT_SEL                    GENMASK(22, 20)
  28 #define SUN4I_BACKEND_MODCTL_OUT_LCD                            (0 << 20)
  29 #define SUN4I_BACKEND_MODCTL_OUT_FE0                            (6 << 20)
  30 #define SUN4I_BACKEND_MODCTL_OUT_FE1                            (7 << 20)
  31 #define SUN4I_BACKEND_MODCTL_HWC_EN                     BIT(16)
  32 #define SUN4I_BACKEND_MODCTL_LAY_EN(l)                  BIT(8 + l)
  33 #define SUN4I_BACKEND_MODCTL_OCSC_EN                    BIT(5)
  34 #define SUN4I_BACKEND_MODCTL_DFLK_EN                    BIT(4)
  35 #define SUN4I_BACKEND_MODCTL_DLP_START_CTL              BIT(2)
  36 #define SUN4I_BACKEND_MODCTL_START_CTL                  BIT(1)
  37 #define SUN4I_BACKEND_MODCTL_DEBE_EN                    BIT(0)
  38
  39 #define SUN4I_BACKEND_BACKCOLOR_REG             0x804
  40 #define SUN4I_BACKEND_BACKCOLOR(r, g, b)                (((r) << 16) | ((g) << 8) | (b))
  41
  42 #define SUN4I_BACKEND_DISSIZE_REG               0x808
  43 #define SUN4I_BACKEND_DISSIZE(w, h)                     (((((h) - 1) & 0xffff) << 16) | \
  44                                                          (((w) - 1) & 0xffff))
  45
  46 #define SUN4I_BACKEND_LAYSIZE_REG(l)            (0x810 + (0x4 * (l)))
  47 #define SUN4I_BACKEND_LAYSIZE(w, h)                     (((((h) - 1) & 0x1fff) << 16) | \
  48                                                          (((w) - 1) & 0x1fff))
  49
  50 #define SUN4I_BACKEND_LAYCOOR_REG(l)            (0x820 + (0x4 * (l)))
  51 #define SUN4I_BACKEND_LAYCOOR(x, y)                     ((((u32)(y) & 0xffff) << 16) | \
  52                                                          ((u32)(x) & 0xffff))
  53
  54 #define SUN4I_BACKEND_LAYLINEWIDTH_REG(l)       (0x840 + (0x4 * (l)))
  55
  56 #define SUN4I_BACKEND_LAYFB_L32ADD_REG(l)       (0x850 + (0x4 * (l)))
  57
  58 #define SUN4I_BACKEND_LAYFB_H4ADD_REG           0x860
  59 #define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l)                GENMASK(3 + ((l) * 8), (l) * 8)
  60 #define SUN4I_BACKEND_LAYFB_H4ADD(l, val)               ((val) << ((l) * 8))
  61
  62 #define SUN4I_BACKEND_REGBUFFCTL_REG            0x870
  63 #define SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS           BIT(1)
  64 #define SUN4I_BACKEND_REGBUFFCTL_LOADCTL                BIT(0)
  65
  66 #define SUN4I_BACKEND_CKMAX_REG                 0x880
  67 #define SUN4I_BACKEND_CKMIN_REG                 0x884
  68 #define SUN4I_BACKEND_CKCFG_REG                 0x888
  69 #define SUN4I_BACKEND_ATTCTL_REG0(l)            (0x890 + (0x4 * (l)))
  70 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK      BIT(15)
  71 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(x)                ((x) << 15)
  72 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK       GENMASK(11, 10)
  73 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(x)                 ((x) << 10)
  74
  75 #define SUN4I_BACKEND_ATTCTL_REG1(l)            (0x8a0 + (0x4 * (l)))
  76 #define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCT           GENMASK(15, 14)
  77 #define SUN4I_BACKEND_ATTCTL_REG1_LAY_WSCAFCT           GENMASK(13, 12)
  78 #define SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT             GENMASK(11, 8)
  79 #define SUN4I_BACKEND_LAY_FBFMT_1BPP                            (0 << 8)
  80 #define SUN4I_BACKEND_LAY_FBFMT_2BPP                            (1 << 8)
  81 #define SUN4I_BACKEND_LAY_FBFMT_4BPP                            (2 << 8)
  82 #define SUN4I_BACKEND_LAY_FBFMT_8BPP                            (3 << 8)
  83 #define SUN4I_BACKEND_LAY_FBFMT_RGB655                          (4 << 8)
  84 #define SUN4I_BACKEND_LAY_FBFMT_RGB565                          (5 << 8)
  85 #define SUN4I_BACKEND_LAY_FBFMT_RGB556                          (6 << 8)
  86 #define SUN4I_BACKEND_LAY_FBFMT_ARGB1555                        (7 << 8)
  87 #define SUN4I_BACKEND_LAY_FBFMT_RGBA5551                        (8 << 8)
  88 #define SUN4I_BACKEND_LAY_FBFMT_XRGB8888                        (9 << 8)
  89 #define SUN4I_BACKEND_LAY_FBFMT_ARGB8888                        (10 << 8)
  90 #define SUN4I_BACKEND_LAY_FBFMT_RGB888                          (11 << 8)
  91 #define SUN4I_BACKEND_LAY_FBFMT_ARGB4444                        (12 << 8)
  92 #define SUN4I_BACKEND_LAY_FBFMT_RGBA4444                        (13 << 8)
  93
  94 #define SUN4I_BACKEND_DLCDPCTL_REG              0x8b0
  95 #define SUN4I_BACKEND_DLCDPFRMBUF_ADDRCTL_REG   0x8b4
  96 #define SUN4I_BACKEND_DLCDPCOOR_REG0            0x8b8
  97 #define SUN4I_BACKEND_DLCDPCOOR_REG1            0x8bc
  98
  99 #define SUN4I_BACKEND_INT_EN_REG                0x8c0
 100 #define SUN4I_BACKEND_INT_FLAG_REG              0x8c4
 101 #define SUN4I_BACKEND_REG_LOAD_FINISHED                 BIT(1)
 102
 103 #define SUN4I_BACKEND_HWCCTL_REG                0x8d8
 104 #define SUN4I_BACKEND_HWCFBCTL_REG              0x8e0
 105 #define SUN4I_BACKEND_WBCTL_REG                 0x8f0
 106 #define SUN4I_BACKEND_WBADD_REG                 0x8f4
 107 #define SUN4I_BACKEND_WBLINEWIDTH_REG           0x8f8
 108 #define SUN4I_BACKEND_SPREN_REG                 0x900
 109 #define SUN4I_BACKEND_SPRFMTCTL_REG             0x908
 110 #define SUN4I_BACKEND_SPRALPHACTL_REG           0x90c
 111 #define SUN4I_BACKEND_IYUVCTL_REG               0x920
 112 #define SUN4I_BACKEND_IYUVADD_REG(c)            (0x930 + (0x4 * (c)))
 113 #define SUN4I_BACKEND_IYUVLINEWITDTH_REG(c)     (0x940 + (0x4 * (c)))
 114 #define SUN4I_BACKEND_YGCOEF_REG(c)             (0x950 + (0x4 * (c)))
 115 #define SUN4I_BACKEND_YGCONS_REG                0x95c
 116 #define SUN4I_BACKEND_URCOEF_REG(c)             (0x960 + (0x4 * (c)))
 117 #define SUN4I_BACKEND_URCONS_REG                0x96c
 118 #define SUN4I_BACKEND_VBCOEF_REG(c)             (0x970 + (0x4 * (c)))
 119 #define SUN4I_BACKEND_VBCONS_REG                0x97c
 120 #define SUN4I_BACKEND_KSCTL_REG                 0x980
 121 #define SUN4I_BACKEND_KSBKCOLOR_REG             0x984
 122 #define SUN4I_BACKEND_KSFSTLINEWIDTH_REG        0x988
 123 #define SUN4I_BACKEND_KSVSCAFCT_REG             0x98c
 124 #define SUN4I_BACKEND_KSHSCACOEF_REG(x)         (0x9a0 + (0x4 * (x)))
 125 #define SUN4I_BACKEND_OCCTL_REG                 0x9c0
 126 #define SUN4I_BACKEND_OCCTL_ENABLE                      BIT(0)
 127
 128 #define SUN4I_BACKEND_OCRCOEF_REG(x)            (0x9d0 + (0x4 * (x)))
 129 #define SUN4I_BACKEND_OCRCONS_REG               0x9dc
 130 #define SUN4I_BACKEND_OCGCOEF_REG(x)            (0x9e0 + (0x4 * (x)))
 131 #define SUN4I_BACKEND_OCGCONS_REG               0x9ec
 132 #define SUN4I_BACKEND_OCBCOEF_REG(x)            (0x9f0 + (0x4 * (x)))
 133 #define SUN4I_BACKEND_OCBCONS_REG               0x9fc
 134 #define SUN4I_BACKEND_SPRCOORCTL_REG(s)         (0xa00 + (0x4 * (s)))
 135 #define SUN4I_BACKEND_SPRATTCTL_REG(s)          (0xb00 + (0x4 * (s)))
 136 #define SUN4I_BACKEND_SPRADD_REG(s)             (0xc00 + (0x4 * (s)))
 137 #define SUN4I_BACKEND_SPRLINEWIDTH_REG(s)       (0xd00 + (0x4 * (s)))
 138
 139 #define SUN4I_BACKEND_SPRPALTAB_OFF             0x4000
 140 #define SUN4I_BACKEND_GAMMATAB_OFF              0x4400
 141 #define SUN4I_BACKEND_HWCPATTERN_OFF            0x4800
 142 #define SUN4I_BACKEND_HWCCOLORTAB_OFF           0x4c00
 143 #define SUN4I_BACKEND_PIPE_OFF(p)               (0x5000 + (0x400 * (p)))
 144
 145 struct sun4i_backend {
 146         struct sunxi_engine     engine;
 147
 148         struct reset_control    *reset;
 149
 150         struct clk              *bus_clk;
 151         struct clk              *mod_clk;
 152         struct clk              *ram_clk;
 153
 154         struct clk              *sat_clk;
 155         struct reset_control    *sat_reset;
 156 };
 157
 158 static inline struct sun4i_backend *
 159 engine_to_sun4i_backend(struct sunxi_engine *engine)
 160 {
 161         return container_of(engine, struct sun4i_backend, engine);
 162 }
 163
 164 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
 165                                 int layer, bool enable);
 166 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
 167                                      int layer, struct drm_plane *plane);
 168 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
 169                                        int layer, struct drm_plane *plane);
 170 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
 171                                       int layer, struct drm_plane *plane);
 172
 173 #endif /* _SUN4I_BACKEND_H_ */