drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "sid.h"
  27 #include "r600_dpm.h"
  28 #include "si_dpm.h"
  29 #include "atom.h"
  30 #include <linux/math64.h>
  31 #include <linux/seq_file.h>
  32
  33 #define MC_CG_ARB_FREQ_F0           0x0a
  34 #define MC_CG_ARB_FREQ_F1           0x0b
  35 #define MC_CG_ARB_FREQ_F2           0x0c
  36 #define MC_CG_ARB_FREQ_F3           0x0d
  37
  38 #define SMC_RAM_END                 0x20000
  39
  40 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  41
  42 static const struct si_cac_config_reg cac_weights_tahiti[] =
  43 {
  44         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  45         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  46         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  48         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  49         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  55         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  57         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  58         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  60         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  62         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  63         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  64         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  66         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  67         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  76         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  79         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  80         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  82         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  83         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  85         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 104         { 0xFFFFFFFF }
 105 };
 106
 107 static const struct si_cac_config_reg lcac_tahiti[] =
 108 {
 109         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 110         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 111         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 113         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 115         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 117         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 119         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 123         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 125         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 127         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 129         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 133         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 137         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 139         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 141         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 143         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 145         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 147         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 149         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 151         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 153         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 155         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 157         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 161         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 163         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 165         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 167         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 169         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 173         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 175         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 177         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 179         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 183         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 185         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 187         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 189         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 191         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 195         { 0xFFFFFFFF }
 196
 197 };
 198
 199 static const struct si_cac_config_reg cac_override_tahiti[] =
 200 {
 201         { 0xFFFFFFFF }
 202 };
 203
 204 static const struct si_powertune_data powertune_data_tahiti =
 205 {
 206         ((1 << 16) | 27027),
 207         6,
 208         0,
 209         4,
 210         95,
 211         {
 212                 0UL,
 213                 0UL,
 214                 4521550UL,
 215                 309631529UL,
 216                 -1270850L,
 217                 4513710L,
 218                 40
 219         },
 220         595000000UL,
 221         12,
 222         {
 223                 0,
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0
 231         },
 232         true
 233 };
 234
 235 static const struct si_dte_data dte_data_tahiti =
 236 {
 237         { 1159409, 0, 0, 0, 0 },
 238         { 777, 0, 0, 0, 0 },
 239         2,
 240         54000,
 241         127000,
 242         25,
 243         2,
 244         10,
 245         13,
 246         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 247         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 248         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 249         85,
 250         false
 251 };
 252
 253 static const struct si_dte_data dte_data_tahiti_le =
 254 {
 255         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 256         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 257         0x5,
 258         0xAFC8,
 259         0x64,
 260         0x32,
 261         1,
 262         0,
 263         0x10,
 264         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 265         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 266         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 267         85,
 268         true
 269 };
 270
 271 static const struct si_dte_data dte_data_tahiti_pro =
 272 {
 273         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 274         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 275         5,
 276         45000,
 277         100,
 278         0xA,
 279         1,
 280         0,
 281         0x10,
 282         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 283         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 284         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 285         90,
 286         true
 287 };
 288
 289 static const struct si_dte_data dte_data_new_zealand =
 290 {
 291         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 292         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 293         0x5,
 294         0xAFC8,
 295         0x69,
 296         0x32,
 297         1,
 298         0,
 299         0x10,
 300         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 301         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 302         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 303         85,
 304         true
 305 };
 306
 307 static const struct si_dte_data dte_data_aruba_pro =
 308 {
 309         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 310         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 311         5,
 312         45000,
 313         100,
 314         0xA,
 315         1,
 316         0,
 317         0x10,
 318         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 319         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 320         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 321         90,
 322         true
 323 };
 324
 325 static const struct si_dte_data dte_data_malta =
 326 {
 327         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 328         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 329         5,
 330         45000,
 331         100,
 332         0xA,
 333         1,
 334         0,
 335         0x10,
 336         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 337         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 338         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 339         90,
 340         true
 341 };
 342
 343 struct si_cac_config_reg cac_weights_pitcairn[] =
 344 {
 345         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 346         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 347         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 348         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 349         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 350         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 351         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 352         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 353         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 354         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 355         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 356         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 357         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 358         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 359         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 360         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 361         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 363         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 364         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 365         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 366         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 367         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 368         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 369         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 370         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 371         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 372         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 373         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 374         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 376         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 377         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 378         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 379         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 380         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 381         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 382         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 383         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 384         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 385         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 405         { 0xFFFFFFFF }
 406 };
 407
 408 static const struct si_cac_config_reg lcac_pitcairn[] =
 409 {
 410         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 411         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 412         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 413         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 414         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 415         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 416         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 417         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 418         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 419         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 420         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 421         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 422         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 423         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 424         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 425         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 426         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 427         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 428         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 429         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 430         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 431         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 432         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 433         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 434         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 435         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 436         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 437         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 438         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 439         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 440         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 441         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 442         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 443         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 444         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 445         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 446         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 447         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 448         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 449         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 450         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 451         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 452         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 453         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 454         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 455         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 456         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 458         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 462         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 463         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 464         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 465         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 466         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 467         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 468         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 470         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 471         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 472         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 473         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 474         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 476         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 477         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 478         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 479         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 480         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 481         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 482         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 483         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 484         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 485         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 486         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 487         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 488         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 489         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 490         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 491         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 492         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 493         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 496         { 0xFFFFFFFF }
 497 };
 498
 499 static const struct si_cac_config_reg cac_override_pitcairn[] =
 500 {
 501     { 0xFFFFFFFF }
 502 };
 503
 504 static const struct si_powertune_data powertune_data_pitcairn =
 505 {
 506         ((1 << 16) | 27027),
 507         5,
 508         0,
 509         6,
 510         100,
 511         {
 512                 51600000UL,
 513                 1800000UL,
 514                 7194395UL,
 515                 309631529UL,
 516                 -1270850L,
 517                 4513710L,
 518                 100
 519         },
 520         117830498UL,
 521         12,
 522         {
 523                 0,
 524                 0,
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0
 531         },
 532         true
 533 };
 534
 535 static const struct si_dte_data dte_data_pitcairn =
 536 {
 537         { 0, 0, 0, 0, 0 },
 538         { 0, 0, 0, 0, 0 },
 539         0,
 540         0,
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 547         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         0,
 550         false
 551 };
 552
 553 static const struct si_dte_data dte_data_curacao_xt =
 554 {
 555         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 556         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 557         5,
 558         45000,
 559         100,
 560         0xA,
 561         1,
 562         0,
 563         0x10,
 564         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 565         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 566         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 567         90,
 568         true
 569 };
 570
 571 static const struct si_dte_data dte_data_curacao_pro =
 572 {
 573         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 574         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 575         5,
 576         45000,
 577         100,
 578         0xA,
 579         1,
 580         0,
 581         0x10,
 582         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 583         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 584         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 585         90,
 586         true
 587 };
 588
 589 static const struct si_dte_data dte_data_neptune_xt =
 590 {
 591         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 592         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 593         5,
 594         45000,
 595         100,
 596         0xA,
 597         1,
 598         0,
 599         0x10,
 600         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 601         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 602         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 603         90,
 604         true
 605 };
 606
 607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 608 {
 609         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 610         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 611         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 612         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 613         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 614         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 615         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 616         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 617         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 618         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 619         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 620         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 621         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 622         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 623         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 624         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 625         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 626         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 627         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 628         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 629         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 630         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 631         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 632         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 633         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 634         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 635         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 636         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 637         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 638         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 639         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 640         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 641         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 642         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 643         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 644         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 645         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 646         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 647         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 648         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 649         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 650         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 651         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 652         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 669         { 0xFFFFFFFF }
 670 };
 671
 672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 673 {
 674         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 675         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 676         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 677         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 678         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 679         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 680         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 681         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 682         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 683         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 684         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 685         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 686         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 687         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 688         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 689         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 690         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 691         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 692         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 693         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 694         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 695         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 696         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 697         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 698         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 699         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 700         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 701         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 702         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 703         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 704         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 705         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 706         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 707         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 708         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 709         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 710         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 711         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 712         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 713         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 714         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 715         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 716         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 717         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 734         { 0xFFFFFFFF }
 735 };
 736
 737 static const struct si_cac_config_reg cac_weights_heathrow[] =
 738 {
 739         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 740         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 741         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 743         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 745         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 746         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 747         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 748         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 749         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 750         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 752         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 753         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 754         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 755         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 756         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 757         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 758         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 759         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 760         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 761         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 762         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 763         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 764         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 765         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 766         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 767         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 768         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 769         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 770         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 771         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 772         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 773         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 774         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 775         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 776         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 777         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 778         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 779         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 780         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 781         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 782         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 799         { 0xFFFFFFFF }
 800 };
 801
 802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 803 {
 804         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 805         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 806         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 808         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 810         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 811         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 812         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 813         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 814         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 815         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 817         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 818         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 819         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 820         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 821         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 822         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 823         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 824         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 825         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 826         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 827         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 828         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 829         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 830         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 831         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 832         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 833         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 834         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 835         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 836         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 837         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 838         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 839         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 840         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 841         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 842         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 843         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 844         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 845         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 846         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 847         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 864         { 0xFFFFFFFF }
 865 };
 866
 867 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 868 {
 869         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 870         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 871         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 873         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 875         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 876         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 877         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 878         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 879         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 880         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 882         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 883         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 884         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 885         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 886         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 887         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 888         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 889         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 890         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 891         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 892         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 893         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 894         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 895         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 896         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 897         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 898         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 899         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 900         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 901         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 902         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 903         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 904         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 905         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 906         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 907         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 908         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 909         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 910         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 911         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 912         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 929         { 0xFFFFFFFF }
 930 };
 931
 932 static const struct si_cac_config_reg lcac_cape_verde[] =
 933 {
 934         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 935         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 936         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 937         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 938         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 939         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 940         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 941         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 942         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 943         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 944         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 947         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 948         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 949         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 950         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 951         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 952         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 953         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 954         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 959         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 962         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 963         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 964         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 965         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 966         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 967         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 968         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 969         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 970         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 971         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 972         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 973         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 974         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 975         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 976         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 979         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 980         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0xFFFFFFFF }
 989 };
 990
 991 static const struct si_cac_config_reg cac_override_cape_verde[] =
 992 {
 993     { 0xFFFFFFFF }
 994 };
 995
 996 static const struct si_powertune_data powertune_data_cape_verde =
 997 {
 998         ((1 << 16) | 0x6993),
 999         5,
1000         0,
1001         7,
1002         105,
1003         {
1004                 0UL,
1005                 0UL,
1006                 7194395UL,
1007                 309631529UL,
1008                 -1270850L,
1009                 4513710L,
1010                 100
1011         },
1012         117830498UL,
1013         12,
1014         {
1015                 0,
1016                 0,
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0
1023         },
1024         true
1025 };
1026
1027 static const struct si_dte_data dte_data_cape_verde =
1028 {
1029         { 0, 0, 0, 0, 0 },
1030         { 0, 0, 0, 0, 0 },
1031         0,
1032         0,
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         0,
1042         false
1043 };
1044
1045 static const struct si_dte_data dte_data_venus_xtx =
1046 {
1047         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1049         5,
1050         55000,
1051         0x69,
1052         0xA,
1053         1,
1054         0,
1055         0x3,
1056         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         90,
1060         true
1061 };
1062
1063 static const struct si_dte_data dte_data_venus_xt =
1064 {
1065         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1067         5,
1068         55000,
1069         0x69,
1070         0xA,
1071         1,
1072         0,
1073         0x3,
1074         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         90,
1078         true
1079 };
1080
1081 static const struct si_dte_data dte_data_venus_pro =
1082 {
1083         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1085         5,
1086         55000,
1087         0x69,
1088         0xA,
1089         1,
1090         0,
1091         0x3,
1092         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         90,
1096         true
1097 };
1098
1099 struct si_cac_config_reg cac_weights_oland[] =
1100 {
1101         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1102         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1103         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1104         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1105         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1106         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1107         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1108         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1110         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1111         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1112         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1113         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1114         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1115         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1116         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1117         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1118         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1119         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1120         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1121         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1122         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1123         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1124         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1125         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1126         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1127         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1128         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1130         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1131         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1132         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1133         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1134         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1135         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1136         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1137         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1138         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1139         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1141         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1142         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1161         { 0xFFFFFFFF }
1162 };
1163
1164 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1165 {
1166         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1167         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1168         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1169         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1170         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1171         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1172         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1173         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1175         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1176         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1177         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1178         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1179         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1180         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1181         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1182         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1183         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1184         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1185         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1186         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1187         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1188         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1189         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1190         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1191         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1192         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1193         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1194         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1195         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1196         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1197         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1199         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1200         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1201         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1202         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1204         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1206         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1207         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1213         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1226         { 0xFFFFFFFF }
1227 };
1228
1229 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1230 {
1231         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1232         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1233         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1235         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1238         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1240         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1241         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1242         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1244         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1245         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1246         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1247         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1248         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1249         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1250         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1251         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1252         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1253         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1254         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1255         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1256         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1257         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1258         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1259         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1260         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1261         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1262         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1264         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1265         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1266         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1267         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1269         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1271         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1272         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1278         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1291         { 0xFFFFFFFF }
1292 };
1293
1294 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1295 {
1296         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1297         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1298         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1300         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1303         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1305         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1306         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1307         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1309         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1310         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1311         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1312         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1313         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1314         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1315         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1316         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1317         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1318         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1319         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1320         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1321         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1322         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1323         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1324         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1325         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1326         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1327         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1329         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1330         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1331         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1332         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1334         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1336         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1337         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1343         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1356         { 0xFFFFFFFF }
1357 };
1358
1359 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1360 {
1361         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1362         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1363         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1365         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1368         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1370         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1371         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1372         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1374         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1375         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1376         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1377         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1378         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1379         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1380         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1381         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1382         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1383         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1384         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1385         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1386         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1387         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1388         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1389         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1391         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1392         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1394         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1395         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1396         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1397         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1399         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1401         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1402         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1408         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1421         { 0xFFFFFFFF }
1422 };
1423
1424 static const struct si_cac_config_reg lcac_oland[] =
1425 {
1426         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1437         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0xFFFFFFFF }
1469 };
1470
1471 static const struct si_cac_config_reg lcac_mars_pro[] =
1472 {
1473         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1474         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1478         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1484         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1502         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0xFFFFFFFF }
1516 };
1517
1518 static const struct si_cac_config_reg cac_override_oland[] =
1519 {
1520         { 0xFFFFFFFF }
1521 };
1522
1523 static const struct si_powertune_data powertune_data_oland =
1524 {
1525         ((1 << 16) | 0x6993),
1526         5,
1527         0,
1528         7,
1529         105,
1530         {
1531                 0UL,
1532                 0UL,
1533                 7194395UL,
1534                 309631529UL,
1535                 -1270850L,
1536                 4513710L,
1537                 100
1538         },
1539         117830498UL,
1540         12,
1541         {
1542                 0,
1543                 0,
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0
1550         },
1551         true
1552 };
1553
1554 static const struct si_powertune_data powertune_data_mars_pro =
1555 {
1556         ((1 << 16) | 0x6993),
1557         5,
1558         0,
1559         7,
1560         105,
1561         {
1562                 0UL,
1563                 0UL,
1564                 7194395UL,
1565                 309631529UL,
1566                 -1270850L,
1567                 4513710L,
1568                 100
1569         },
1570         117830498UL,
1571         12,
1572         {
1573                 0,
1574                 0,
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0
1581         },
1582         true
1583 };
1584
1585 static const struct si_dte_data dte_data_oland =
1586 {
1587         { 0, 0, 0, 0, 0 },
1588         { 0, 0, 0, 0, 0 },
1589         0,
1590         0,
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         0,
1600         false
1601 };
1602
1603 static const struct si_dte_data dte_data_mars_pro =
1604 {
1605         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1607         5,
1608         55000,
1609         105,
1610         0xA,
1611         1,
1612         0,
1613         0x10,
1614         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1617         90,
1618         true
1619 };
1620
1621 static const struct si_dte_data dte_data_sun_xt =
1622 {
1623         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1625         5,
1626         55000,
1627         105,
1628         0xA,
1629         1,
1630         0,
1631         0x10,
1632         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1635         90,
1636         true
1637 };
1638
1639
1640 static const struct si_cac_config_reg cac_weights_hainan[] =
1641 {
1642         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1643         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1644         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1645         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1646         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1647         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1648         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1649         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1652         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1653         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1654         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1655         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1656         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1657         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1660         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1661         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1662         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1663         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1664         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1665         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1666         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1668         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1669         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1673         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1677         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1678         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1679         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1680         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1681         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1682         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1684         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1685         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1702         { 0xFFFFFFFF }
1703 };
1704
1705 static const struct si_powertune_data powertune_data_hainan =
1706 {
1707         ((1 << 16) | 0x6993),
1708         5,
1709         0,
1710         9,
1711         105,
1712         {
1713                 0UL,
1714                 0UL,
1715                 7194395UL,
1716                 309631529UL,
1717                 -1270850L,
1718                 4513710L,
1719                 100
1720         },
1721         117830498UL,
1722         12,
1723         {
1724                 0,
1725                 0,
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0
1732         },
1733         true
1734 };
1735
1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1740
1741 extern int si_mc_load_microcode(struct radeon_device *rdev);
1742
1743 static int si_populate_voltage_value(struct radeon_device *rdev,
1744                                      const struct atom_voltage_table *table,
1745                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1746 static int si_get_std_voltage_value(struct radeon_device *rdev,
1747                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1748                                     u16 *std_voltage);
1749 static int si_write_smc_soft_register(struct radeon_device *rdev,
1750                                       u16 reg_offset, u32 value);
1751 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1752                                          struct rv7xx_pl *pl,
1753                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1754 static int si_calculate_sclk_params(struct radeon_device *rdev,
1755                                     u32 engine_clock,
1756                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1757
1758 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1759 {
1760         struct si_power_info *pi = rdev->pm.dpm.priv;
1761
1762         return pi;
1763 }
1764
1765 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1766                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1767 {
1768         s64 kt, kv, leakage_w, i_leakage, vddc;
1769         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1770         s64 tmp;
1771
1772         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1773         vddc = div64_s64(drm_int2fixp(v), 1000);
1774         temperature = div64_s64(drm_int2fixp(t), 1000);
1775
1776         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1777         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1778         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1779         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1780         t_ref = drm_int2fixp(coeff->t_ref);
1781
1782         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1783         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1784         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1785         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1786
1787         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1788
1789         *leakage = drm_fixp2int(leakage_w * 1000);
1790 }
1791
1792 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1793                                              const struct ni_leakage_coeffients *coeff,
1794                                              u16 v,
1795                                              s32 t,
1796                                              u32 i_leakage,
1797                                              u32 *leakage)
1798 {
1799         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1800 }
1801
1802 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1803                                                const u32 fixed_kt, u16 v,
1804                                                u32 ileakage, u32 *leakage)
1805 {
1806         s64 kt, kv, leakage_w, i_leakage, vddc;
1807
1808         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1809         vddc = div64_s64(drm_int2fixp(v), 1000);
1810
1811         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1812         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1813                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1814
1815         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1816
1817         *leakage = drm_fixp2int(leakage_w * 1000);
1818 }
1819
1820 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1821                                        const struct ni_leakage_coeffients *coeff,
1822                                        const u32 fixed_kt,
1823                                        u16 v,
1824                                        u32 i_leakage,
1825                                        u32 *leakage)
1826 {
1827         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1828 }
1829
1830
1831 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1832                                    struct si_dte_data *dte_data)
1833 {
1834         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1835         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1836         u32 k = dte_data->k;
1837         u32 t_max = dte_data->max_t;
1838         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1839         u32 t_0 = dte_data->t0;
1840         u32 i;
1841
1842         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1843                 dte_data->tdep_count = 3;
1844
1845                 for (i = 0; i < k; i++) {
1846                         dte_data->r[i] =
1847                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1848                                 (p_limit2  * (u32)100);
1849                 }
1850
1851                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1852
1853                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1854                         dte_data->tdep_r[i] = dte_data->r[4];
1855                 }
1856         } else {
1857                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1858         }
1859 }
1860
1861 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1862 {
1863         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1864         struct si_power_info *si_pi = si_get_pi(rdev);
1865         bool update_dte_from_pl2 = false;
1866
1867         if (rdev->family == CHIP_TAHITI) {
1868                 si_pi->cac_weights = cac_weights_tahiti;
1869                 si_pi->lcac_config = lcac_tahiti;
1870                 si_pi->cac_override = cac_override_tahiti;
1871                 si_pi->powertune_data = &powertune_data_tahiti;
1872                 si_pi->dte_data = dte_data_tahiti;
1873
1874                 switch (rdev->pdev->device) {
1875                 case 0x6798:
1876                         si_pi->dte_data.enable_dte_by_default = true;
1877                         break;
1878                 case 0x6799:
1879                         si_pi->dte_data = dte_data_new_zealand;
1880                         break;
1881                 case 0x6790:
1882                 case 0x6791:
1883                 case 0x6792:
1884                 case 0x679E:
1885                         si_pi->dte_data = dte_data_aruba_pro;
1886                         update_dte_from_pl2 = true;
1887                         break;
1888                 case 0x679B:
1889                         si_pi->dte_data = dte_data_malta;
1890                         update_dte_from_pl2 = true;
1891                         break;
1892                 case 0x679A:
1893                         si_pi->dte_data = dte_data_tahiti_pro;
1894                         update_dte_from_pl2 = true;
1895                         break;
1896                 default:
1897                         if (si_pi->dte_data.enable_dte_by_default == true)
1898                                 DRM_ERROR("DTE is not enabled!\n");
1899                         break;
1900                 }
1901         } else if (rdev->family == CHIP_PITCAIRN) {
1902                 switch (rdev->pdev->device) {
1903                 case 0x6810:
1904                 case 0x6818:
1905                         si_pi->cac_weights = cac_weights_pitcairn;
1906                         si_pi->lcac_config = lcac_pitcairn;
1907                         si_pi->cac_override = cac_override_pitcairn;
1908                         si_pi->powertune_data = &powertune_data_pitcairn;
1909                         si_pi->dte_data = dte_data_curacao_xt;
1910                         update_dte_from_pl2 = true;
1911                         break;
1912                 case 0x6819:
1913                 case 0x6811:
1914                         si_pi->cac_weights = cac_weights_pitcairn;
1915                         si_pi->lcac_config = lcac_pitcairn;
1916                         si_pi->cac_override = cac_override_pitcairn;
1917                         si_pi->powertune_data = &powertune_data_pitcairn;
1918                         si_pi->dte_data = dte_data_curacao_pro;
1919                         update_dte_from_pl2 = true;
1920                         break;
1921                 case 0x6800:
1922                 case 0x6806:
1923                         si_pi->cac_weights = cac_weights_pitcairn;
1924                         si_pi->lcac_config = lcac_pitcairn;
1925                         si_pi->cac_override = cac_override_pitcairn;
1926                         si_pi->powertune_data = &powertune_data_pitcairn;
1927                         si_pi->dte_data = dte_data_neptune_xt;
1928                         update_dte_from_pl2 = true;
1929                         break;
1930                 default:
1931                         si_pi->cac_weights = cac_weights_pitcairn;
1932                         si_pi->lcac_config = lcac_pitcairn;
1933                         si_pi->cac_override = cac_override_pitcairn;
1934                         si_pi->powertune_data = &powertune_data_pitcairn;
1935                         si_pi->dte_data = dte_data_pitcairn;
1936                         break;
1937                 }
1938         } else if (rdev->family == CHIP_VERDE) {
1939                 si_pi->lcac_config = lcac_cape_verde;
1940                 si_pi->cac_override = cac_override_cape_verde;
1941                 si_pi->powertune_data = &powertune_data_cape_verde;
1942
1943                 switch (rdev->pdev->device) {
1944                 case 0x683B:
1945                 case 0x683F:
1946                 case 0x6829:
1947                 case 0x6835:
1948                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1949                         si_pi->dte_data = dte_data_cape_verde;
1950                         break;
1951                 case 0x682C:
1952                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1953                         si_pi->dte_data = dte_data_sun_xt;
1954                         break;
1955                 case 0x6825:
1956                 case 0x6827:
1957                         si_pi->cac_weights = cac_weights_heathrow;
1958                         si_pi->dte_data = dte_data_cape_verde;
1959                         break;
1960                 case 0x6824:
1961                 case 0x682D:
1962                         si_pi->cac_weights = cac_weights_chelsea_xt;
1963                         si_pi->dte_data = dte_data_cape_verde;
1964                         break;
1965                 case 0x682F:
1966                         si_pi->cac_weights = cac_weights_chelsea_pro;
1967                         si_pi->dte_data = dte_data_cape_verde;
1968                         break;
1969                 case 0x6820:
1970                         si_pi->cac_weights = cac_weights_heathrow;
1971                         si_pi->dte_data = dte_data_venus_xtx;
1972                         break;
1973                 case 0x6821:
1974                         si_pi->cac_weights = cac_weights_heathrow;
1975                         si_pi->dte_data = dte_data_venus_xt;
1976                         break;
1977                 case 0x6823:
1978                 case 0x682B:
1979                 case 0x6822:
1980                 case 0x682A:
1981                         si_pi->cac_weights = cac_weights_chelsea_pro;
1982                         si_pi->dte_data = dte_data_venus_pro;
1983                         break;
1984                 default:
1985                         si_pi->cac_weights = cac_weights_cape_verde;
1986                         si_pi->dte_data = dte_data_cape_verde;
1987                         break;
1988                 }
1989         } else if (rdev->family == CHIP_OLAND) {
1990                 switch (rdev->pdev->device) {
1991                 case 0x6601:
1992                 case 0x6621:
1993                 case 0x6603:
1994                 case 0x6605:
1995                         si_pi->cac_weights = cac_weights_mars_pro;
1996                         si_pi->lcac_config = lcac_mars_pro;
1997                         si_pi->cac_override = cac_override_oland;
1998                         si_pi->powertune_data = &powertune_data_mars_pro;
1999                         si_pi->dte_data = dte_data_mars_pro;
2000                         update_dte_from_pl2 = true;
2001                         break;
2002                 case 0x6600:
2003                 case 0x6606:
2004                 case 0x6620:
2005                 case 0x6604:
2006                         si_pi->cac_weights = cac_weights_mars_xt;
2007                         si_pi->lcac_config = lcac_mars_pro;
2008                         si_pi->cac_override = cac_override_oland;
2009                         si_pi->powertune_data = &powertune_data_mars_pro;
2010                         si_pi->dte_data = dte_data_mars_pro;
2011                         update_dte_from_pl2 = true;
2012                         break;
2013                 case 0x6611:
2014                 case 0x6613:
2015                 case 0x6608:
2016                         si_pi->cac_weights = cac_weights_oland_pro;
2017                         si_pi->lcac_config = lcac_mars_pro;
2018                         si_pi->cac_override = cac_override_oland;
2019                         si_pi->powertune_data = &powertune_data_mars_pro;
2020                         si_pi->dte_data = dte_data_mars_pro;
2021                         update_dte_from_pl2 = true;
2022                         break;
2023                 case 0x6610:
2024                         si_pi->cac_weights = cac_weights_oland_xt;
2025                         si_pi->lcac_config = lcac_mars_pro;
2026                         si_pi->cac_override = cac_override_oland;
2027                         si_pi->powertune_data = &powertune_data_mars_pro;
2028                         si_pi->dte_data = dte_data_mars_pro;
2029                         update_dte_from_pl2 = true;
2030                         break;
2031                 default:
2032                         si_pi->cac_weights = cac_weights_oland;
2033                         si_pi->lcac_config = lcac_oland;
2034                         si_pi->cac_override = cac_override_oland;
2035                         si_pi->powertune_data = &powertune_data_oland;
2036                         si_pi->dte_data = dte_data_oland;
2037                         break;
2038                 }
2039         } else if (rdev->family == CHIP_HAINAN) {
2040                 si_pi->cac_weights = cac_weights_hainan;
2041                 si_pi->lcac_config = lcac_oland;
2042                 si_pi->cac_override = cac_override_oland;
2043                 si_pi->powertune_data = &powertune_data_hainan;
2044                 si_pi->dte_data = dte_data_sun_xt;
2045                 update_dte_from_pl2 = true;
2046         } else {
2047                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2048                 return;
2049         }
2050
2051         ni_pi->enable_power_containment = false;
2052         ni_pi->enable_cac = false;
2053         ni_pi->enable_sq_ramping = false;
2054         si_pi->enable_dte = false;
2055
2056         if (si_pi->powertune_data->enable_powertune_by_default) {
2057                 ni_pi->enable_power_containment= true;
2058                 ni_pi->enable_cac = true;
2059                 if (si_pi->dte_data.enable_dte_by_default) {
2060                         si_pi->enable_dte = true;
2061                         if (update_dte_from_pl2)
2062                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2063
2064                 }
2065                 ni_pi->enable_sq_ramping = true;
2066         }
2067
2068         ni_pi->driver_calculate_cac_leakage = true;
2069         ni_pi->cac_configuration_required = true;
2070
2071         if (ni_pi->cac_configuration_required) {
2072                 ni_pi->support_cac_long_term_average = true;
2073                 si_pi->dyn_powertune_data.l2_lta_window_size =
2074                         si_pi->powertune_data->l2_lta_window_size_default;
2075                 si_pi->dyn_powertune_data.lts_truncate =
2076                         si_pi->powertune_data->lts_truncate_default;
2077         } else {
2078                 ni_pi->support_cac_long_term_average = false;
2079                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2080                 si_pi->dyn_powertune_data.lts_truncate = 0;
2081         }
2082
2083         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2084 }
2085
2086 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2087 {
2088         return 1;
2089 }
2090
2091 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2092 {
2093         u32 xclk;
2094         u32 wintime;
2095         u32 cac_window;
2096         u32 cac_window_size;
2097
2098         xclk = radeon_get_xclk(rdev);
2099
2100         if (xclk == 0)
2101                 return 0;
2102
2103         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2104         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2105
2106         wintime = (cac_window_size * 100) / xclk;
2107
2108         return wintime;
2109 }
2110
2111 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2112 {
2113         return power_in_watts;
2114 }
2115
2116 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2117                                             bool adjust_polarity,
2118                                             u32 tdp_adjustment,
2119                                             u32 *tdp_limit,
2120                                             u32 *near_tdp_limit)
2121 {
2122         u32 adjustment_delta, max_tdp_limit;
2123
2124         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2125                 return -EINVAL;
2126
2127         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2128
2129         if (adjust_polarity) {
2130                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2131                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2132         } else {
2133                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2134                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2135                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2136                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2137                 else
2138                         *near_tdp_limit = 0;
2139         }
2140
2141         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2142                 return -EINVAL;
2143         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2144                 return -EINVAL;
2145
2146         return 0;
2147 }
2148
2149 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2150                                       struct radeon_ps *radeon_state)
2151 {
2152         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2153         struct si_power_info *si_pi = si_get_pi(rdev);
2154
2155         if (ni_pi->enable_power_containment) {
2156                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2157                 PP_SIslands_PAPMParameters *papm_parm;
2158                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2159                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2160                 u32 tdp_limit;
2161                 u32 near_tdp_limit;
2162                 int ret;
2163
2164                 if (scaling_factor == 0)
2165                         return -EINVAL;
2166
2167                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2168
2169                 ret = si_calculate_adjusted_tdp_limits(rdev,
2170                                                        false, /* ??? */
2171                                                        rdev->pm.dpm.tdp_adjustment,
2172                                                        &tdp_limit,
2173                                                        &near_tdp_limit);
2174                 if (ret)
2175                         return ret;
2176
2177                 smc_table->dpm2Params.TDPLimit =
2178                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2179                 smc_table->dpm2Params.NearTDPLimit =
2180                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2181                 smc_table->dpm2Params.SafePowerLimit =
2182                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2183
2184                 ret = si_copy_bytes_to_smc(rdev,
2185                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2186                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2187                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2188                                            sizeof(u32) * 3,
2189                                            si_pi->sram_end);
2190                 if (ret)
2191                         return ret;
2192
2193                 if (si_pi->enable_ppm) {
2194                         papm_parm = &si_pi->papm_parm;
2195                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2196                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2197                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2198                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2199                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2200                         papm_parm->PlatformPowerLimit = 0xffffffff;
2201                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2202
2203                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2204                                                    (u8 *)papm_parm,
2205                                                    sizeof(PP_SIslands_PAPMParameters),
2206                                                    si_pi->sram_end);
2207                         if (ret)
2208                                 return ret;
2209                 }
2210         }
2211         return 0;
2212 }
2213
2214 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2215                                         struct radeon_ps *radeon_state)
2216 {
2217         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2218         struct si_power_info *si_pi = si_get_pi(rdev);
2219
2220         if (ni_pi->enable_power_containment) {
2221                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2222                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2223                 int ret;
2224
2225                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2226
2227                 smc_table->dpm2Params.NearTDPLimit =
2228                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2229                 smc_table->dpm2Params.SafePowerLimit =
2230                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2231
2232                 ret = si_copy_bytes_to_smc(rdev,
2233                                            (si_pi->state_table_start +
2234                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2235                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2236                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2237                                            sizeof(u32) * 2,
2238                                            si_pi->sram_end);
2239                 if (ret)
2240                         return ret;
2241         }
2242
2243         return 0;
2244 }
2245
2246 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2247                                                const u16 prev_std_vddc,
2248                                                const u16 curr_std_vddc)
2249 {
2250         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2251         u64 prev_vddc = (u64)prev_std_vddc;
2252         u64 curr_vddc = (u64)curr_std_vddc;
2253         u64 pwr_efficiency_ratio, n, d;
2254
2255         if ((prev_vddc == 0) || (curr_vddc == 0))
2256                 return 0;
2257
2258         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2259         d = prev_vddc * prev_vddc;
2260         pwr_efficiency_ratio = div64_u64(n, d);
2261
2262         if (pwr_efficiency_ratio > (u64)0xFFFF)
2263                 return 0;
2264
2265         return (u16)pwr_efficiency_ratio;
2266 }
2267
2268 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2269                                             struct radeon_ps *radeon_state)
2270 {
2271         struct si_power_info *si_pi = si_get_pi(rdev);
2272
2273         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2274             radeon_state->vclk && radeon_state->dclk)
2275                 return true;
2276
2277         return false;
2278 }
2279
2280 static int si_populate_power_containment_values(struct radeon_device *rdev,
2281                                                 struct radeon_ps *radeon_state,
2282                                                 SISLANDS_SMC_SWSTATE *smc_state)
2283 {
2284         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2285         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2286         struct ni_ps *state = ni_get_ps(radeon_state);
2287         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2288         u32 prev_sclk;
2289         u32 max_sclk;
2290         u32 min_sclk;
2291         u16 prev_std_vddc;
2292         u16 curr_std_vddc;
2293         int i;
2294         u16 pwr_efficiency_ratio;
2295         u8 max_ps_percent;
2296         bool disable_uvd_power_tune;
2297         int ret;
2298
2299         if (ni_pi->enable_power_containment == false)
2300                 return 0;
2301
2302         if (state->performance_level_count == 0)
2303                 return -EINVAL;
2304
2305         if (smc_state->levelCount != state->performance_level_count)
2306                 return -EINVAL;
2307
2308         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2309
2310         smc_state->levels[0].dpm2.MaxPS = 0;
2311         smc_state->levels[0].dpm2.NearTDPDec = 0;
2312         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2313         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2314         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2315
2316         for (i = 1; i < state->performance_level_count; i++) {
2317                 prev_sclk = state->performance_levels[i-1].sclk;
2318                 max_sclk  = state->performance_levels[i].sclk;
2319                 if (i == 1)
2320                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2321                 else
2322                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2323
2324                 if (prev_sclk > max_sclk)
2325                         return -EINVAL;
2326
2327                 if ((max_ps_percent == 0) ||
2328                     (prev_sclk == max_sclk) ||
2329                     disable_uvd_power_tune) {
2330                         min_sclk = max_sclk;
2331                 } else if (i == 1) {
2332                         min_sclk = prev_sclk;
2333                 } else {
2334                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2335                 }
2336
2337                 if (min_sclk < state->performance_levels[0].sclk)
2338                         min_sclk = state->performance_levels[0].sclk;
2339
2340                 if (min_sclk == 0)
2341                         return -EINVAL;
2342
2343                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2344                                                 state->performance_levels[i-1].vddc, &vddc);
2345                 if (ret)
2346                         return ret;
2347
2348                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2349                 if (ret)
2350                         return ret;
2351
2352                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2353                                                 state->performance_levels[i].vddc, &vddc);
2354                 if (ret)
2355                         return ret;
2356
2357                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2358                 if (ret)
2359                         return ret;
2360
2361                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2362                                                                            prev_std_vddc, curr_std_vddc);
2363
2364                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2365                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2366                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2367                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2368                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2369         }
2370
2371         return 0;
2372 }
2373
2374 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2375                                          struct radeon_ps *radeon_state,
2376                                          SISLANDS_SMC_SWSTATE *smc_state)
2377 {
2378         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2379         struct ni_ps *state = ni_get_ps(radeon_state);
2380         u32 sq_power_throttle, sq_power_throttle2;
2381         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2382         int i;
2383
2384         if (state->performance_level_count == 0)
2385                 return -EINVAL;
2386
2387         if (smc_state->levelCount != state->performance_level_count)
2388                 return -EINVAL;
2389
2390         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2391                 return -EINVAL;
2392
2393         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2394                 enable_sq_ramping = false;
2395
2396         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2397                 enable_sq_ramping = false;
2398
2399         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2400                 enable_sq_ramping = false;
2401
2402         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2403                 enable_sq_ramping = false;
2404
2405         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2406                 enable_sq_ramping = false;
2407
2408         for (i = 0; i < state->performance_level_count; i++) {
2409                 sq_power_throttle = 0;
2410                 sq_power_throttle2 = 0;
2411
2412                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2413                     enable_sq_ramping) {
2414                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2415                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2416                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2417                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2418                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2419                 } else {
2420                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2421                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2422                 }
2423
2424                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2425                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2426         }
2427
2428         return 0;
2429 }
2430
2431 static int si_enable_power_containment(struct radeon_device *rdev,
2432                                        struct radeon_ps *radeon_new_state,
2433                                        bool enable)
2434 {
2435         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2436         PPSMC_Result smc_result;
2437         int ret = 0;
2438
2439         if (ni_pi->enable_power_containment) {
2440                 if (enable) {
2441                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2442                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2443                                 if (smc_result != PPSMC_Result_OK) {
2444                                         ret = -EINVAL;
2445                                         ni_pi->pc_enabled = false;
2446                                 } else {
2447                                         ni_pi->pc_enabled = true;
2448                                 }
2449                         }
2450                 } else {
2451                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2452                         if (smc_result != PPSMC_Result_OK)
2453                                 ret = -EINVAL;
2454                         ni_pi->pc_enabled = false;
2455                 }
2456         }
2457
2458         return ret;
2459 }
2460
2461 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2462 {
2463         struct si_power_info *si_pi = si_get_pi(rdev);
2464         int ret = 0;
2465         struct si_dte_data *dte_data = &si_pi->dte_data;
2466         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2467         u32 table_size;
2468         u8 tdep_count;
2469         u32 i;
2470
2471         if (dte_data == NULL)
2472                 si_pi->enable_dte = false;
2473
2474         if (si_pi->enable_dte == false)
2475                 return 0;
2476
2477         if (dte_data->k <= 0)
2478                 return -EINVAL;
2479
2480         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2481         if (dte_tables == NULL) {
2482                 si_pi->enable_dte = false;
2483                 return -ENOMEM;
2484         }
2485
2486         table_size = dte_data->k;
2487
2488         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2489                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2490
2491         tdep_count = dte_data->tdep_count;
2492         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2493                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2494
2495         dte_tables->K = cpu_to_be32(table_size);
2496         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2497         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2498         dte_tables->WindowSize = dte_data->window_size;
2499         dte_tables->temp_select = dte_data->temp_select;
2500         dte_tables->DTE_mode = dte_data->dte_mode;
2501         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2502
2503         if (tdep_count > 0)
2504                 table_size--;
2505
2506         for (i = 0; i < table_size; i++) {
2507                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2508                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2509         }
2510
2511         dte_tables->Tdep_count = tdep_count;
2512
2513         for (i = 0; i < (u32)tdep_count; i++) {
2514                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2515                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2516                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2517         }
2518
2519         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2520                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2521         kfree(dte_tables);
2522
2523         return ret;
2524 }
2525
2526 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2527                                           u16 *max, u16 *min)
2528 {
2529         struct si_power_info *si_pi = si_get_pi(rdev);
2530         struct radeon_cac_leakage_table *table =
2531                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2532         u32 i;
2533         u32 v0_loadline;
2534
2535
2536         if (table == NULL)
2537                 return -EINVAL;
2538
2539         *max = 0;
2540         *min = 0xFFFF;
2541
2542         for (i = 0; i < table->count; i++) {
2543                 if (table->entries[i].vddc > *max)
2544                         *max = table->entries[i].vddc;
2545                 if (table->entries[i].vddc < *min)
2546                         *min = table->entries[i].vddc;
2547         }
2548
2549         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2550                 return -EINVAL;
2551
2552         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2553
2554         if (v0_loadline > 0xFFFFUL)
2555                 return -EINVAL;
2556
2557         *min = (u16)v0_loadline;
2558
2559         if ((*min > *max) || (*max == 0) || (*min == 0))
2560                 return -EINVAL;
2561
2562         return 0;
2563 }
2564
2565 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2566 {
2567         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2568                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2569 }
2570
2571 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2572                                      PP_SIslands_CacConfig *cac_tables,
2573                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2574                                      u16 t0, u16 t_step)
2575 {
2576         struct si_power_info *si_pi = si_get_pi(rdev);
2577         u32 leakage;
2578         unsigned int i, j;
2579         s32 t;
2580         u32 smc_leakage;
2581         u32 scaling_factor;
2582         u16 voltage;
2583
2584         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2585
2586         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2587                 t = (1000 * (i * t_step + t0));
2588
2589                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2590                         voltage = vddc_max - (vddc_step * j);
2591
2592                         si_calculate_leakage_for_v_and_t(rdev,
2593                                                          &si_pi->powertune_data->leakage_coefficients,
2594                                                          voltage,
2595                                                          t,
2596                                                          si_pi->dyn_powertune_data.cac_leakage,
2597                                                          &leakage);
2598
2599                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2600
2601                         if (smc_leakage > 0xFFFF)
2602                                 smc_leakage = 0xFFFF;
2603
2604                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2605                                 cpu_to_be16((u16)smc_leakage);
2606                 }
2607         }
2608         return 0;
2609 }
2610
2611 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2612                                             PP_SIslands_CacConfig *cac_tables,
2613                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2614 {
2615         struct si_power_info *si_pi = si_get_pi(rdev);
2616         u32 leakage;
2617         unsigned int i, j;
2618         u32 smc_leakage;
2619         u32 scaling_factor;
2620         u16 voltage;
2621
2622         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2623
2624         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2625                 voltage = vddc_max - (vddc_step * j);
2626
2627                 si_calculate_leakage_for_v(rdev,
2628                                            &si_pi->powertune_data->leakage_coefficients,
2629                                            si_pi->powertune_data->fixed_kt,
2630                                            voltage,
2631                                            si_pi->dyn_powertune_data.cac_leakage,
2632                                            &leakage);
2633
2634                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2635
2636                 if (smc_leakage > 0xFFFF)
2637                         smc_leakage = 0xFFFF;
2638
2639                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2640                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2641                                 cpu_to_be16((u16)smc_leakage);
2642         }
2643         return 0;
2644 }
2645
2646 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2647 {
2648         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2649         struct si_power_info *si_pi = si_get_pi(rdev);
2650         PP_SIslands_CacConfig *cac_tables = NULL;
2651         u16 vddc_max, vddc_min, vddc_step;
2652         u16 t0, t_step;
2653         u32 load_line_slope, reg;
2654         int ret = 0;
2655         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2656
2657         if (ni_pi->enable_cac == false)
2658                 return 0;
2659
2660         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2661         if (!cac_tables)
2662                 return -ENOMEM;
2663
2664         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2665         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2666         WREG32(CG_CAC_CTRL, reg);
2667
2668         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2669         si_pi->dyn_powertune_data.dc_pwr_value =
2670                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2671         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2672         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2673
2674         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2675
2676         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2677         if (ret)
2678                 goto done_free;
2679
2680         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2681         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2682         t_step = 4;
2683         t0 = 60;
2684
2685         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2686                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2687                                                 vddc_max, vddc_min, vddc_step,
2688                                                 t0, t_step);
2689         else
2690                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2691                                                        vddc_max, vddc_min, vddc_step);
2692         if (ret)
2693                 goto done_free;
2694
2695         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2696
2697         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2698         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2699         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2700         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2701         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2702         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2703         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2704         cac_tables->calculation_repeats = cpu_to_be32(2);
2705         cac_tables->dc_cac = cpu_to_be32(0);
2706         cac_tables->log2_PG_LKG_SCALE = 12;
2707         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2708         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2709         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2710
2711         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2712                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2713
2714         if (ret)
2715                 goto done_free;
2716
2717         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2718
2719 done_free:
2720         if (ret) {
2721                 ni_pi->enable_cac = false;
2722                 ni_pi->enable_power_containment = false;
2723         }
2724
2725         kfree(cac_tables);
2726
2727         return 0;
2728 }
2729
2730 static int si_program_cac_config_registers(struct radeon_device *rdev,
2731                                            const struct si_cac_config_reg *cac_config_regs)
2732 {
2733         const struct si_cac_config_reg *config_regs = cac_config_regs;
2734         u32 data = 0, offset;
2735
2736         if (!config_regs)
2737                 return -EINVAL;
2738
2739         while (config_regs->offset != 0xFFFFFFFF) {
2740                 switch (config_regs->type) {
2741                 case SISLANDS_CACCONFIG_CGIND:
2742                         offset = SMC_CG_IND_START + config_regs->offset;
2743                         if (offset < SMC_CG_IND_END)
2744                                 data = RREG32_SMC(offset);
2745                         break;
2746                 default:
2747                         data = RREG32(config_regs->offset << 2);
2748                         break;
2749                 }
2750
2751                 data &= ~config_regs->mask;
2752                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2753
2754                 switch (config_regs->type) {
2755                 case SISLANDS_CACCONFIG_CGIND:
2756                         offset = SMC_CG_IND_START + config_regs->offset;
2757                         if (offset < SMC_CG_IND_END)
2758                                 WREG32_SMC(offset, data);
2759                         break;
2760                 default:
2761                         WREG32(config_regs->offset << 2, data);
2762                         break;
2763                 }
2764                 config_regs++;
2765         }
2766         return 0;
2767 }
2768
2769 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2770 {
2771         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2772         struct si_power_info *si_pi = si_get_pi(rdev);
2773         int ret;
2774
2775         if ((ni_pi->enable_cac == false) ||
2776             (ni_pi->cac_configuration_required == false))
2777                 return 0;
2778
2779         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2780         if (ret)
2781                 return ret;
2782         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2783         if (ret)
2784                 return ret;
2785         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2786         if (ret)
2787                 return ret;
2788
2789         return 0;
2790 }
2791
2792 static int si_enable_smc_cac(struct radeon_device *rdev,
2793                              struct radeon_ps *radeon_new_state,
2794                              bool enable)
2795 {
2796         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2797         struct si_power_info *si_pi = si_get_pi(rdev);
2798         PPSMC_Result smc_result;
2799         int ret = 0;
2800
2801         if (ni_pi->enable_cac) {
2802                 if (enable) {
2803                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2804                                 if (ni_pi->support_cac_long_term_average) {
2805                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2806                                         if (smc_result != PPSMC_Result_OK)
2807                                                 ni_pi->support_cac_long_term_average = false;
2808                                 }
2809
2810                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2811                                 if (smc_result != PPSMC_Result_OK) {
2812                                         ret = -EINVAL;
2813                                         ni_pi->cac_enabled = false;
2814                                 } else {
2815                                         ni_pi->cac_enabled = true;
2816                                 }
2817
2818                                 if (si_pi->enable_dte) {
2819                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2820                                         if (smc_result != PPSMC_Result_OK)
2821                                                 ret = -EINVAL;
2822                                 }
2823                         }
2824                 } else if (ni_pi->cac_enabled) {
2825                         if (si_pi->enable_dte)
2826                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2827
2828                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2829
2830                         ni_pi->cac_enabled = false;
2831
2832                         if (ni_pi->support_cac_long_term_average)
2833                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2834                 }
2835         }
2836         return ret;
2837 }
2838
2839 static int si_init_smc_spll_table(struct radeon_device *rdev)
2840 {
2841         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2842         struct si_power_info *si_pi = si_get_pi(rdev);
2843         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2844         SISLANDS_SMC_SCLK_VALUE sclk_params;
2845         u32 fb_div, p_div;
2846         u32 clk_s, clk_v;
2847         u32 sclk = 0;
2848         int ret = 0;
2849         u32 tmp;
2850         int i;
2851
2852         if (si_pi->spll_table_start == 0)
2853                 return -EINVAL;
2854
2855         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2856         if (spll_table == NULL)
2857                 return -ENOMEM;
2858
2859         for (i = 0; i < 256; i++) {
2860                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2861                 if (ret)
2862                         break;
2863
2864                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2865                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2866                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2867                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2868
2869                 fb_div &= ~0x00001FFF;
2870                 fb_div >>= 1;
2871                 clk_v >>= 6;
2872
2873                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2874                         ret = -EINVAL;
2875                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2876                         ret = -EINVAL;
2877                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2878                         ret = -EINVAL;
2879                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2880                         ret = -EINVAL;
2881
2882                 if (ret)
2883                         break;
2884
2885                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2886                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2887                 spll_table->freq[i] = cpu_to_be32(tmp);
2888
2889                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2890                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2891                 spll_table->ss[i] = cpu_to_be32(tmp);
2892
2893                 sclk += 512;
2894         }
2895
2896
2897         if (!ret)
2898                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2899                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2900                                            si_pi->sram_end);
2901
2902         if (ret)
2903                 ni_pi->enable_power_containment = false;
2904
2905         kfree(spll_table);
2906
2907         return ret;
2908 }
2909
2910 struct si_dpm_quirk {
2911         u32 chip_vendor;
2912         u32 chip_device;
2913         u32 subsys_vendor;
2914         u32 subsys_device;
2915         u32 max_sclk;
2916         u32 max_mclk;
2917 };
2918
2919 /* cards with dpm stability problems */
2920 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2921         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2922         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2923         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2924         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2925         { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2926         { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2927         { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2928         { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2929         { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
2930         { 0, 0, 0, 0 },
2931 };
2932
2933 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2934                                         struct radeon_ps *rps)
2935 {
2936         struct ni_ps *ps = ni_get_ps(rps);
2937         struct radeon_clock_and_voltage_limits *max_limits;
2938         bool disable_mclk_switching = false;
2939         bool disable_sclk_switching = false;
2940         u32 mclk, sclk;
2941         u16 vddc, vddci;
2942         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2943         u32 max_sclk = 0, max_mclk = 0;
2944         int i;
2945         struct si_dpm_quirk *p = si_dpm_quirk_list;
2946
2947         /* limit all SI kickers */
2948         if (rdev->family == CHIP_PITCAIRN) {
2949                 if ((rdev->pdev->revision == 0x81) ||
2950                     (rdev->pdev->device == 0x6810) ||
2951                     (rdev->pdev->device == 0x6811) ||
2952                     (rdev->pdev->device == 0x6816) ||
2953                     (rdev->pdev->device == 0x6817) ||
2954                     (rdev->pdev->device == 0x6806))
2955                         max_mclk = 120000;
2956         } else if (rdev->family == CHIP_VERDE) {
2957                 if ((rdev->pdev->revision == 0x81) ||
2958                     (rdev->pdev->revision == 0x83) ||
2959                     (rdev->pdev->revision == 0x87) ||
2960                     (rdev->pdev->device == 0x6820) ||
2961                     (rdev->pdev->device == 0x6821) ||
2962                     (rdev->pdev->device == 0x6822) ||
2963                     (rdev->pdev->device == 0x6823) ||
2964                     (rdev->pdev->device == 0x682A) ||
2965                     (rdev->pdev->device == 0x682B)) {
2966                         max_sclk = 75000;
2967                         max_mclk = 80000;
2968                 }
2969         } else if (rdev->family == CHIP_OLAND) {
2970                 if ((rdev->pdev->revision == 0xC7) ||
2971                     (rdev->pdev->revision == 0x80) ||
2972                     (rdev->pdev->revision == 0x81) ||
2973                     (rdev->pdev->revision == 0x83) ||
2974                     (rdev->pdev->device == 0x6604) ||
2975                     (rdev->pdev->device == 0x6605)) {
2976                         max_sclk = 75000;
2977                         max_mclk = 80000;
2978                 }
2979         } else if (rdev->family == CHIP_HAINAN) {
2980                 if ((rdev->pdev->revision == 0x81) ||
2981                     (rdev->pdev->revision == 0x83) ||
2982                     (rdev->pdev->revision == 0xC3) ||
2983                     (rdev->pdev->device == 0x6664) ||
2984                     (rdev->pdev->device == 0x6665) ||
2985                     (rdev->pdev->device == 0x6667)) {
2986                         max_sclk = 75000;
2987                         max_mclk = 80000;
2988                 }
2989         }
2990         /* Apply dpm quirks */
2991         while (p && p->chip_device != 0) {
2992                 if (rdev->pdev->vendor == p->chip_vendor &&
2993                     rdev->pdev->device == p->chip_device &&
2994                     rdev->pdev->subsystem_vendor == p->subsys_vendor &&
2995                     rdev->pdev->subsystem_device == p->subsys_device) {
2996                         max_sclk = p->max_sclk;
2997                         max_mclk = p->max_mclk;
2998                         break;
2999                 }
3000                 ++p;
3001         }
3002
3003         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3004             ni_dpm_vblank_too_short(rdev))
3005                 disable_mclk_switching = true;
3006
3007         if (rps->vclk || rps->dclk) {
3008                 disable_mclk_switching = true;
3009                 disable_sclk_switching = true;
3010         }
3011
3012         if (rdev->pm.dpm.ac_power)
3013                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3014         else
3015                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3016
3017         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3018                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3019                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3020         }
3021         if (rdev->pm.dpm.ac_power == false) {
3022                 for (i = 0; i < ps->performance_level_count; i++) {
3023                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3024                                 ps->performance_levels[i].mclk = max_limits->mclk;
3025                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3026                                 ps->performance_levels[i].sclk = max_limits->sclk;
3027                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3028                                 ps->performance_levels[i].vddc = max_limits->vddc;
3029                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3030                                 ps->performance_levels[i].vddci = max_limits->vddci;
3031                 }
3032         }
3033
3034         /* limit clocks to max supported clocks based on voltage dependency tables */
3035         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3036                                                         &max_sclk_vddc);
3037         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3038                                                         &max_mclk_vddci);
3039         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3040                                                         &max_mclk_vddc);
3041
3042         for (i = 0; i < ps->performance_level_count; i++) {
3043                 if (max_sclk_vddc) {
3044                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3045                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3046                 }
3047                 if (max_mclk_vddci) {
3048                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3049                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3050                 }
3051                 if (max_mclk_vddc) {
3052                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3053                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3054                 }
3055                 if (max_mclk) {
3056                         if (ps->performance_levels[i].mclk > max_mclk)
3057                                 ps->performance_levels[i].mclk = max_mclk;
3058                 }
3059                 if (max_sclk) {
3060                         if (ps->performance_levels[i].sclk > max_sclk)
3061                                 ps->performance_levels[i].sclk = max_sclk;
3062                 }
3063         }
3064
3065         /* XXX validate the min clocks required for display */
3066
3067         if (disable_mclk_switching) {
3068                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3069                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3070         } else {
3071                 mclk = ps->performance_levels[0].mclk;
3072                 vddci = ps->performance_levels[0].vddci;
3073         }
3074
3075         if (disable_sclk_switching) {
3076                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3077                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3078         } else {
3079                 sclk = ps->performance_levels[0].sclk;
3080                 vddc = ps->performance_levels[0].vddc;
3081         }
3082
3083         /* adjusted low state */
3084         ps->performance_levels[0].sclk = sclk;
3085         ps->performance_levels[0].mclk = mclk;
3086         ps->performance_levels[0].vddc = vddc;
3087         ps->performance_levels[0].vddci = vddci;
3088
3089         if (disable_sclk_switching) {
3090                 sclk = ps->performance_levels[0].sclk;
3091                 for (i = 1; i < ps->performance_level_count; i++) {
3092                         if (sclk < ps->performance_levels[i].sclk)
3093                                 sclk = ps->performance_levels[i].sclk;
3094                 }
3095                 for (i = 0; i < ps->performance_level_count; i++) {
3096                         ps->performance_levels[i].sclk = sclk;
3097                         ps->performance_levels[i].vddc = vddc;
3098                 }
3099         } else {
3100                 for (i = 1; i < ps->performance_level_count; i++) {
3101                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3102                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3103                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3104                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3105                 }
3106         }
3107
3108         if (disable_mclk_switching) {
3109                 mclk = ps->performance_levels[0].mclk;
3110                 for (i = 1; i < ps->performance_level_count; i++) {
3111                         if (mclk < ps->performance_levels[i].mclk)
3112                                 mclk = ps->performance_levels[i].mclk;
3113                 }
3114                 for (i = 0; i < ps->performance_level_count; i++) {
3115                         ps->performance_levels[i].mclk = mclk;
3116                         ps->performance_levels[i].vddci = vddci;
3117                 }
3118         } else {
3119                 for (i = 1; i < ps->performance_level_count; i++) {
3120                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3121                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3122                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3123                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3124                 }
3125         }
3126
3127         for (i = 0; i < ps->performance_level_count; i++)
3128                 btc_adjust_clock_combinations(rdev, max_limits,
3129                                               &ps->performance_levels[i]);
3130
3131         for (i = 0; i < ps->performance_level_count; i++) {
3132                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3133                                                    ps->performance_levels[i].sclk,
3134                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3135                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3136                                                    ps->performance_levels[i].mclk,
3137                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3138                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3139                                                    ps->performance_levels[i].mclk,
3140                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3141                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3142                                                    rdev->clock.current_dispclk,
3143                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3144         }
3145
3146         for (i = 0; i < ps->performance_level_count; i++) {
3147                 btc_apply_voltage_delta_rules(rdev,
3148                                               max_limits->vddc, max_limits->vddci,
3149                                               &ps->performance_levels[i].vddc,
3150                                               &ps->performance_levels[i].vddci);
3151         }
3152
3153         ps->dc_compatible = true;
3154         for (i = 0; i < ps->performance_level_count; i++) {
3155                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3156                         ps->dc_compatible = false;
3157         }
3158
3159 }
3160
3161 #if 0
3162 static int si_read_smc_soft_register(struct radeon_device *rdev,
3163                                      u16 reg_offset, u32 *value)
3164 {
3165         struct si_power_info *si_pi = si_get_pi(rdev);
3166
3167         return si_read_smc_sram_dword(rdev,
3168                                       si_pi->soft_regs_start + reg_offset, value,
3169                                       si_pi->sram_end);
3170 }
3171 #endif
3172
3173 static int si_write_smc_soft_register(struct radeon_device *rdev,
3174                                       u16 reg_offset, u32 value)
3175 {
3176         struct si_power_info *si_pi = si_get_pi(rdev);
3177
3178         return si_write_smc_sram_dword(rdev,
3179                                        si_pi->soft_regs_start + reg_offset,
3180                                        value, si_pi->sram_end);
3181 }
3182
3183 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3184 {
3185         bool ret = false;
3186         u32 tmp, width, row, column, bank, density;
3187         bool is_memory_gddr5, is_special;
3188
3189         tmp = RREG32(MC_SEQ_MISC0);
3190         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3191         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3192                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3193
3194         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3195         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3196
3197         tmp = RREG32(MC_ARB_RAMCFG);
3198         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3199         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3200         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3201
3202         density = (1 << (row + column - 20 + bank)) * width;
3203
3204         if ((rdev->pdev->device == 0x6819) &&
3205             is_memory_gddr5 && is_special && (density == 0x400))
3206                 ret = true;
3207
3208         return ret;
3209 }
3210
3211 static void si_get_leakage_vddc(struct radeon_device *rdev)
3212 {
3213         struct si_power_info *si_pi = si_get_pi(rdev);
3214         u16 vddc, count = 0;
3215         int i, ret;
3216
3217         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3218                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3219
3220                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3221                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3222                         si_pi->leakage_voltage.entries[count].leakage_index =
3223                                 SISLANDS_LEAKAGE_INDEX0 + i;
3224                         count++;
3225                 }
3226         }
3227         si_pi->leakage_voltage.count = count;
3228 }
3229
3230 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3231                                                      u32 index, u16 *leakage_voltage)
3232 {
3233         struct si_power_info *si_pi = si_get_pi(rdev);
3234         int i;
3235
3236         if (leakage_voltage == NULL)
3237                 return -EINVAL;
3238
3239         if ((index & 0xff00) != 0xff00)
3240                 return -EINVAL;
3241
3242         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3243                 return -EINVAL;
3244
3245         if (index < SISLANDS_LEAKAGE_INDEX0)
3246                 return -EINVAL;
3247
3248         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3249                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3250                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3251                         return 0;
3252                 }
3253         }
3254         return -EAGAIN;
3255 }
3256
3257 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3258 {
3259         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3260         bool want_thermal_protection;
3261         enum radeon_dpm_event_src dpm_event_src;
3262
3263         switch (sources) {
3264         case 0:
3265         default:
3266                 want_thermal_protection = false;
3267                 break;
3268         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3269                 want_thermal_protection = true;
3270                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3271                 break;
3272         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3273                 want_thermal_protection = true;
3274                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3275                 break;
3276         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3277               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3278                 want_thermal_protection = true;
3279                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3280                 break;
3281         }
3282
3283         if (want_thermal_protection) {
3284                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3285                 if (pi->thermal_protection)
3286                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3287         } else {
3288                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3289         }
3290 }
3291
3292 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3293                                            enum radeon_dpm_auto_throttle_src source,
3294                                            bool enable)
3295 {
3296         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3297
3298         if (enable) {
3299                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3300                         pi->active_auto_throttle_sources |= 1 << source;
3301                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3302                 }
3303         } else {
3304                 if (pi->active_auto_throttle_sources & (1 << source)) {
3305                         pi->active_auto_throttle_sources &= ~(1 << source);
3306                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3307                 }
3308         }
3309 }
3310
3311 static void si_start_dpm(struct radeon_device *rdev)
3312 {
3313         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3314 }
3315
3316 static void si_stop_dpm(struct radeon_device *rdev)
3317 {
3318         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3319 }
3320
3321 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3322 {
3323         if (enable)
3324                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3325         else
3326                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3327
3328 }
3329
3330 #if 0
3331 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3332                                                u32 thermal_level)
3333 {
3334         PPSMC_Result ret;
3335
3336         if (thermal_level == 0) {
3337                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3338                 if (ret == PPSMC_Result_OK)
3339                         return 0;
3340                 else
3341                         return -EINVAL;
3342         }
3343         return 0;
3344 }
3345
3346 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3347 {
3348         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3349 }
3350 #endif
3351
3352 #if 0
3353 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3354 {
3355         if (ac_power)
3356                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3357                         0 : -EINVAL;
3358
3359         return 0;
3360 }
3361 #endif
3362
3363 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3364                                                       PPSMC_Msg msg, u32 parameter)
3365 {
3366         WREG32(SMC_SCRATCH0, parameter);
3367         return si_send_msg_to_smc(rdev, msg);
3368 }
3369
3370 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3371 {
3372         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3373                 return -EINVAL;
3374
3375         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3376                 0 : -EINVAL;
3377 }
3378
3379 int si_dpm_force_performance_level(struct radeon_device *rdev,
3380                                    enum radeon_dpm_forced_level level)
3381 {
3382         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3383         struct ni_ps *ps = ni_get_ps(rps);
3384         u32 levels = ps->performance_level_count;
3385
3386         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3387                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3388                         return -EINVAL;
3389
3390                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3391                         return -EINVAL;
3392         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3393                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3394                         return -EINVAL;
3395
3396                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3397                         return -EINVAL;
3398         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3399                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3400                         return -EINVAL;
3401
3402                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3403                         return -EINVAL;
3404         }
3405
3406         rdev->pm.dpm.forced_level = level;
3407
3408         return 0;
3409 }
3410
3411 static int si_set_boot_state(struct radeon_device *rdev)
3412 {
3413         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3414                 0 : -EINVAL;
3415 }
3416
3417 static int si_set_sw_state(struct radeon_device *rdev)
3418 {
3419         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3420                 0 : -EINVAL;
3421 }
3422
3423 static int si_halt_smc(struct radeon_device *rdev)
3424 {
3425         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3426                 return -EINVAL;
3427
3428         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3429                 0 : -EINVAL;
3430 }
3431
3432 static int si_resume_smc(struct radeon_device *rdev)
3433 {
3434         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3435                 return -EINVAL;
3436
3437         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3438                 0 : -EINVAL;
3439 }
3440
3441 static void si_dpm_start_smc(struct radeon_device *rdev)
3442 {
3443         si_program_jump_on_start(rdev);
3444         si_start_smc(rdev);
3445         si_start_smc_clock(rdev);
3446 }
3447
3448 static void si_dpm_stop_smc(struct radeon_device *rdev)
3449 {
3450         si_reset_smc(rdev);
3451         si_stop_smc_clock(rdev);
3452 }
3453
3454 static int si_process_firmware_header(struct radeon_device *rdev)
3455 {
3456         struct si_power_info *si_pi = si_get_pi(rdev);
3457         u32 tmp;
3458         int ret;
3459
3460         ret = si_read_smc_sram_dword(rdev,
3461                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3462                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3463                                      &tmp, si_pi->sram_end);
3464         if (ret)
3465                 return ret;
3466
3467         si_pi->state_table_start = tmp;
3468
3469         ret = si_read_smc_sram_dword(rdev,
3470                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3471                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3472                                      &tmp, si_pi->sram_end);
3473         if (ret)
3474                 return ret;
3475
3476         si_pi->soft_regs_start = tmp;
3477
3478         ret = si_read_smc_sram_dword(rdev,
3479                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3480                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3481                                      &tmp, si_pi->sram_end);
3482         if (ret)
3483                 return ret;
3484
3485         si_pi->mc_reg_table_start = tmp;
3486
3487         ret = si_read_smc_sram_dword(rdev,
3488                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3489                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3490                                      &tmp, si_pi->sram_end);
3491         if (ret)
3492                 return ret;
3493
3494         si_pi->arb_table_start = tmp;
3495
3496         ret = si_read_smc_sram_dword(rdev,
3497                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3498                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3499                                      &tmp, si_pi->sram_end);
3500         if (ret)
3501                 return ret;
3502
3503         si_pi->cac_table_start = tmp;
3504
3505         ret = si_read_smc_sram_dword(rdev,
3506                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3507                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3508                                      &tmp, si_pi->sram_end);
3509         if (ret)
3510                 return ret;
3511
3512         si_pi->dte_table_start = tmp;
3513
3514         ret = si_read_smc_sram_dword(rdev,
3515                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3516                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3517                                      &tmp, si_pi->sram_end);
3518         if (ret)
3519                 return ret;
3520
3521         si_pi->spll_table_start = tmp;
3522
3523         ret = si_read_smc_sram_dword(rdev,
3524                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3525                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3526                                      &tmp, si_pi->sram_end);
3527         if (ret)
3528                 return ret;
3529
3530         si_pi->papm_cfg_table_start = tmp;
3531
3532         return ret;
3533 }
3534
3535 static void si_read_clock_registers(struct radeon_device *rdev)
3536 {
3537         struct si_power_info *si_pi = si_get_pi(rdev);
3538
3539         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3540         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3541         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3542         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3543         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3544         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3545         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3546         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3547         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3548         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3549         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3550         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3551         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3552         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3553         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3554 }
3555
3556 static void si_enable_thermal_protection(struct radeon_device *rdev,
3557                                           bool enable)
3558 {
3559         if (enable)
3560                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3561         else
3562                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3563 }
3564
3565 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3566 {
3567         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3568 }
3569
3570 #if 0
3571 static int si_enter_ulp_state(struct radeon_device *rdev)
3572 {
3573         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3574
3575         udelay(25000);
3576
3577         return 0;
3578 }
3579
3580 static int si_exit_ulp_state(struct radeon_device *rdev)
3581 {
3582         int i;
3583
3584         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3585
3586         udelay(7000);
3587
3588         for (i = 0; i < rdev->usec_timeout; i++) {
3589                 if (RREG32(SMC_RESP_0) == 1)
3590                         break;
3591                 udelay(1000);
3592         }
3593
3594         return 0;
3595 }
3596 #endif
3597
3598 static int si_notify_smc_display_change(struct radeon_device *rdev,
3599                                      bool has_display)
3600 {
3601         PPSMC_Msg msg = has_display ?
3602                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3603
3604         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3605                 0 : -EINVAL;
3606 }
3607
3608 static void si_program_response_times(struct radeon_device *rdev)
3609 {
3610         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3611         u32 vddc_dly, acpi_dly, vbi_dly;
3612         u32 reference_clock;
3613
3614         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3615
3616         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3617         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3618
3619         if (voltage_response_time == 0)
3620                 voltage_response_time = 1000;
3621
3622         acpi_delay_time = 15000;
3623         vbi_time_out = 100000;
3624
3625         reference_clock = radeon_get_xclk(rdev);
3626
3627         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3628         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3629         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3630
3631         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3632         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3633         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3634         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3635 }
3636
3637 static void si_program_ds_registers(struct radeon_device *rdev)
3638 {
3639         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3640         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3641
3642         if (eg_pi->sclk_deep_sleep) {
3643                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3644                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3645                          ~AUTOSCALE_ON_SS_CLEAR);
3646         }
3647 }
3648
3649 static void si_program_display_gap(struct radeon_device *rdev)
3650 {
3651         u32 tmp, pipe;
3652         int i;
3653
3654         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3655         if (rdev->pm.dpm.new_active_crtc_count > 0)
3656                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3657         else
3658                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3659
3660         if (rdev->pm.dpm.new_active_crtc_count > 1)
3661                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3662         else
3663                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3664
3665         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3666
3667         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3668         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3669
3670         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3671             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3672                 /* find the first active crtc */
3673                 for (i = 0; i < rdev->num_crtc; i++) {
3674                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3675                                 break;
3676                 }
3677                 if (i == rdev->num_crtc)
3678                         pipe = 0;
3679                 else
3680                         pipe = i;
3681
3682                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3683                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3684                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3685         }
3686
3687         /* Setting this to false forces the performance state to low if the crtcs are disabled.
3688          * This can be a problem on PowerXpress systems or if you want to use the card
3689          * for offscreen rendering or compute if there are no crtcs enabled.
3690          */
3691         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3692 }
3693
3694 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3695 {
3696         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3697
3698         if (enable) {
3699                 if (pi->sclk_ss)
3700                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3701         } else {
3702                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3703                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3704         }
3705 }
3706
3707 static void si_setup_bsp(struct radeon_device *rdev)
3708 {
3709         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3710         u32 xclk = radeon_get_xclk(rdev);
3711
3712         r600_calculate_u_and_p(pi->asi,
3713                                xclk,
3714                                16,
3715                                &pi->bsp,
3716                                &pi->bsu);
3717
3718         r600_calculate_u_and_p(pi->pasi,
3719                                xclk,
3720                                16,
3721                                &pi->pbsp,
3722                                &pi->pbsu);
3723
3724
3725         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3726         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3727
3728         WREG32(CG_BSP, pi->dsp);
3729 }
3730
3731 static void si_program_git(struct radeon_device *rdev)
3732 {
3733         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3734 }
3735
3736 static void si_program_tp(struct radeon_device *rdev)
3737 {
3738         int i;
3739         enum r600_td td = R600_TD_DFLT;
3740
3741         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3742                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3743
3744         if (td == R600_TD_AUTO)
3745                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3746         else
3747                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3748
3749         if (td == R600_TD_UP)
3750                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3751
3752         if (td == R600_TD_DOWN)
3753                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3754 }
3755
3756 static void si_program_tpp(struct radeon_device *rdev)
3757 {
3758         WREG32(CG_TPC, R600_TPC_DFLT);
3759 }
3760
3761 static void si_program_sstp(struct radeon_device *rdev)
3762 {
3763         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3764 }
3765
3766 static void si_enable_display_gap(struct radeon_device *rdev)
3767 {
3768         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3769
3770         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3771         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3772                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3773
3774         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3775         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3776                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3777         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3778 }
3779
3780 static void si_program_vc(struct radeon_device *rdev)
3781 {
3782         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3783
3784         WREG32(CG_FTV, pi->vrc);
3785 }
3786
3787 static void si_clear_vc(struct radeon_device *rdev)
3788 {
3789         WREG32(CG_FTV, 0);
3790 }
3791
3792 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3793 {
3794         u8 mc_para_index;
3795
3796         if (memory_clock < 10000)
3797                 mc_para_index = 0;
3798         else if (memory_clock >= 80000)
3799                 mc_para_index = 0x0f;
3800         else
3801                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3802         return mc_para_index;
3803 }
3804
3805 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3806 {
3807         u8 mc_para_index;
3808
3809         if (strobe_mode) {
3810                 if (memory_clock < 12500)
3811                         mc_para_index = 0x00;
3812                 else if (memory_clock > 47500)
3813                         mc_para_index = 0x0f;
3814                 else
3815                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3816         } else {
3817                 if (memory_clock < 65000)
3818                         mc_para_index = 0x00;
3819                 else if (memory_clock > 135000)
3820                         mc_para_index = 0x0f;
3821                 else
3822                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3823         }
3824         return mc_para_index;
3825 }
3826
3827 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3828 {
3829         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3830         bool strobe_mode = false;
3831         u8 result = 0;
3832
3833         if (mclk <= pi->mclk_strobe_mode_threshold)
3834                 strobe_mode = true;
3835
3836         if (pi->mem_gddr5)
3837                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3838         else
3839                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3840
3841         if (strobe_mode)
3842                 result |= SISLANDS_SMC_STROBE_ENABLE;
3843
3844         return result;
3845 }
3846
3847 static int si_upload_firmware(struct radeon_device *rdev)
3848 {
3849         struct si_power_info *si_pi = si_get_pi(rdev);
3850         int ret;
3851
3852         si_reset_smc(rdev);
3853         si_stop_smc_clock(rdev);
3854
3855         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3856
3857         return ret;
3858 }
3859
3860 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3861                                               const struct atom_voltage_table *table,
3862                                               const struct radeon_phase_shedding_limits_table *limits)
3863 {
3864         u32 data, num_bits, num_levels;
3865
3866         if ((table == NULL) || (limits == NULL))
3867                 return false;
3868
3869         data = table->mask_low;
3870
3871         num_bits = hweight32(data);
3872
3873         if (num_bits == 0)
3874                 return false;
3875
3876         num_levels = (1 << num_bits);
3877
3878         if (table->count != num_levels)
3879                 return false;
3880
3881         if (limits->count != (num_levels - 1))
3882                 return false;
3883
3884         return true;
3885 }
3886
3887 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3888                                               u32 max_voltage_steps,
3889                                               struct atom_voltage_table *voltage_table)
3890 {
3891         unsigned int i, diff;
3892
3893         if (voltage_table->count <= max_voltage_steps)
3894                 return;
3895
3896         diff = voltage_table->count - max_voltage_steps;
3897
3898         for (i= 0; i < max_voltage_steps; i++)
3899                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3900
3901         voltage_table->count = max_voltage_steps;
3902 }
3903
3904 static int si_construct_voltage_tables(struct radeon_device *rdev)
3905 {
3906         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3907         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3908         struct si_power_info *si_pi = si_get_pi(rdev);
3909         int ret;
3910
3911         ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3912                                             VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3913         if (ret)
3914                 return ret;
3915
3916         if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3917                 si_trim_voltage_table_to_fit_state_table(rdev,
3918                                                          SISLANDS_MAX_NO_VREG_STEPS,
3919                                                          &eg_pi->vddc_voltage_table);
3920
3921         if (eg_pi->vddci_control) {
3922                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3923                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3924                 if (ret)
3925                         return ret;
3926
3927                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3928                         si_trim_voltage_table_to_fit_state_table(rdev,
3929                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3930                                                                  &eg_pi->vddci_voltage_table);
3931         }
3932
3933         if (pi->mvdd_control) {
3934                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3935                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3936
3937                 if (ret) {
3938                         pi->mvdd_control = false;
3939                         return ret;
3940                 }
3941
3942                 if (si_pi->mvdd_voltage_table.count == 0) {
3943                         pi->mvdd_control = false;
3944                         return -EINVAL;
3945                 }
3946
3947                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3948                         si_trim_voltage_table_to_fit_state_table(rdev,
3949                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3950                                                                  &si_pi->mvdd_voltage_table);
3951         }
3952
3953         if (si_pi->vddc_phase_shed_control) {
3954                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3955                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3956                 if (ret)
3957                         si_pi->vddc_phase_shed_control = false;
3958
3959                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3960                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3961                         si_pi->vddc_phase_shed_control = false;
3962         }
3963
3964         return 0;
3965 }
3966
3967 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3968                                           const struct atom_voltage_table *voltage_table,
3969                                           SISLANDS_SMC_STATETABLE *table)
3970 {
3971         unsigned int i;
3972
3973         for (i = 0; i < voltage_table->count; i++)
3974                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3975 }
3976
3977 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3978                                           SISLANDS_SMC_STATETABLE *table)
3979 {
3980         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3981         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3982         struct si_power_info *si_pi = si_get_pi(rdev);
3983         u8 i;
3984
3985         if (eg_pi->vddc_voltage_table.count) {
3986                 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3987                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3988                         cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3989
3990                 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3991                         if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3992                                 table->maxVDDCIndexInPPTable = i;
3993                                 break;
3994                         }
3995                 }
3996         }
3997
3998         if (eg_pi->vddci_voltage_table.count) {
3999                 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4000
4001                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4002                         cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4003         }
4004
4005
4006         if (si_pi->mvdd_voltage_table.count) {
4007                 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4008
4009                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4010                         cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4011         }
4012
4013         if (si_pi->vddc_phase_shed_control) {
4014                 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4015                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4016                         si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4017
4018                         table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4019                                 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4020
4021                         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4022                                                    (u32)si_pi->vddc_phase_shed_table.phase_delay);
4023                 } else {
4024                         si_pi->vddc_phase_shed_control = false;
4025                 }
4026         }
4027
4028         return 0;
4029 }
4030
4031 static int si_populate_voltage_value(struct radeon_device *rdev,
4032                                      const struct atom_voltage_table *table,
4033                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4034 {
4035         unsigned int i;
4036
4037         for (i = 0; i < table->count; i++) {
4038                 if (value <= table->entries[i].value) {
4039                         voltage->index = (u8)i;
4040                         voltage->value = cpu_to_be16(table->entries[i].value);
4041                         break;
4042                 }
4043         }
4044
4045         if (i >= table->count)
4046                 return -EINVAL;
4047
4048         return 0;
4049 }
4050
4051 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4052                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4053 {
4054         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4055         struct si_power_info *si_pi = si_get_pi(rdev);
4056
4057         if (pi->mvdd_control) {
4058                 if (mclk <= pi->mvdd_split_frequency)
4059                         voltage->index = 0;
4060                 else
4061                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4062
4063                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4064         }
4065         return 0;
4066 }
4067
4068 static int si_get_std_voltage_value(struct radeon_device *rdev,
4069                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4070                                     u16 *std_voltage)
4071 {
4072         u16 v_index;
4073         bool voltage_found = false;
4074         *std_voltage = be16_to_cpu(voltage->value);
4075
4076         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4077                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4078                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4079                                 return -EINVAL;
4080
4081                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4082                                 if (be16_to_cpu(voltage->value) ==
4083                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4084                                         voltage_found = true;
4085                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4086                                                 *std_voltage =
4087                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4088                                         else
4089                                                 *std_voltage =
4090                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4091                                         break;
4092                                 }
4093                         }
4094
4095                         if (!voltage_found) {
4096                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4097                                         if (be16_to_cpu(voltage->value) <=
4098                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4099                                                 voltage_found = true;
4100                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4101                                                         *std_voltage =
4102                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4103                                                 else
4104                                                         *std_voltage =
4105                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4106                                                 break;
4107                                         }
4108                                 }
4109                         }
4110                 } else {
4111                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4112                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4113                 }
4114         }
4115
4116         return 0;
4117 }
4118
4119 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4120                                          u16 value, u8 index,
4121                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4122 {
4123         voltage->index = index;
4124         voltage->value = cpu_to_be16(value);
4125
4126         return 0;
4127 }
4128
4129 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4130                                             const struct radeon_phase_shedding_limits_table *limits,
4131                                             u16 voltage, u32 sclk, u32 mclk,
4132                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4133 {
4134         unsigned int i;
4135
4136         for (i = 0; i < limits->count; i++) {
4137                 if ((voltage <= limits->entries[i].voltage) &&
4138                     (sclk <= limits->entries[i].sclk) &&
4139                     (mclk <= limits->entries[i].mclk))
4140                         break;
4141         }
4142
4143         smc_voltage->phase_settings = (u8)i;
4144
4145         return 0;
4146 }
4147
4148 static int si_init_arb_table_index(struct radeon_device *rdev)
4149 {
4150         struct si_power_info *si_pi = si_get_pi(rdev);
4151         u32 tmp;
4152         int ret;
4153
4154         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4155         if (ret)
4156                 return ret;
4157
4158         tmp &= 0x00FFFFFF;
4159         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4160
4161         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4162 }
4163
4164 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4165 {
4166         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4167 }
4168
4169 static int si_reset_to_default(struct radeon_device *rdev)
4170 {
4171         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4172                 0 : -EINVAL;
4173 }
4174
4175 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4176 {
4177         struct si_power_info *si_pi = si_get_pi(rdev);
4178         u32 tmp;
4179         int ret;
4180
4181         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4182                                      &tmp, si_pi->sram_end);
4183         if (ret)
4184                 return ret;
4185
4186         tmp = (tmp >> 24) & 0xff;
4187
4188         if (tmp == MC_CG_ARB_FREQ_F0)
4189                 return 0;
4190
4191         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4192 }
4193
4194 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4195                                             u32 engine_clock)
4196 {
4197         u32 dram_rows;
4198         u32 dram_refresh_rate;
4199         u32 mc_arb_rfsh_rate;
4200         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4201
4202         if (tmp >= 4)
4203                 dram_rows = 16384;
4204         else
4205                 dram_rows = 1 << (tmp + 10);
4206
4207         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4208         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4209
4210         return mc_arb_rfsh_rate;
4211 }
4212
4213 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4214                                                 struct rv7xx_pl *pl,
4215                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4216 {
4217         u32 dram_timing;
4218         u32 dram_timing2;
4219         u32 burst_time;
4220
4221         arb_regs->mc_arb_rfsh_rate =
4222                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4223
4224         radeon_atom_set_engine_dram_timings(rdev,
4225                                             pl->sclk,
4226                                             pl->mclk);
4227
4228         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4229         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4230         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4231
4232         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4233         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4234         arb_regs->mc_arb_burst_time = (u8)burst_time;
4235
4236         return 0;
4237 }
4238
4239 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4240                                                   struct radeon_ps *radeon_state,
4241                                                   unsigned int first_arb_set)
4242 {
4243         struct si_power_info *si_pi = si_get_pi(rdev);
4244         struct ni_ps *state = ni_get_ps(radeon_state);
4245         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4246         int i, ret = 0;
4247
4248         for (i = 0; i < state->performance_level_count; i++) {
4249                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4250                 if (ret)
4251                         break;
4252                 ret = si_copy_bytes_to_smc(rdev,
4253                                            si_pi->arb_table_start +
4254                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4255                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4256                                            (u8 *)&arb_regs,
4257                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4258                                            si_pi->sram_end);
4259                 if (ret)
4260                         break;
4261         }
4262
4263         return ret;
4264 }
4265
4266 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4267                                                struct radeon_ps *radeon_new_state)
4268 {
4269         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4270                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4271 }
4272
4273 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4274                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4275 {
4276         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4277         struct si_power_info *si_pi = si_get_pi(rdev);
4278
4279         if (pi->mvdd_control)
4280                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4281                                                  si_pi->mvdd_bootup_value, voltage);
4282
4283         return 0;
4284 }
4285
4286 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4287                                          struct radeon_ps *radeon_initial_state,
4288                                          SISLANDS_SMC_STATETABLE *table)
4289 {
4290         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4291         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4292         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4293         struct si_power_info *si_pi = si_get_pi(rdev);
4294         u32 reg;
4295         int ret;
4296
4297         table->initialState.levels[0].mclk.vDLL_CNTL =
4298                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4299         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4300                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4301         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4302                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4303         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4304                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4305         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4306                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4307         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4308                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4309         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4310                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4311         table->initialState.levels[0].mclk.vMPLL_SS =
4312                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4313         table->initialState.levels[0].mclk.vMPLL_SS2 =
4314                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4315
4316         table->initialState.levels[0].mclk.mclk_value =
4317                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4318
4319         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4320                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4321         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4322                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4323         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4324                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4325         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4326                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4327         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4328                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4329         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4330                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4331
4332         table->initialState.levels[0].sclk.sclk_value =
4333                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4334
4335         table->initialState.levels[0].arbRefreshState =
4336                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4337
4338         table->initialState.levels[0].ACIndex = 0;
4339
4340         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4341                                         initial_state->performance_levels[0].vddc,
4342                                         &table->initialState.levels[0].vddc);
4343
4344         if (!ret) {
4345                 u16 std_vddc;
4346
4347                 ret = si_get_std_voltage_value(rdev,
4348                                                &table->initialState.levels[0].vddc,
4349                                                &std_vddc);
4350                 if (!ret)
4351                         si_populate_std_voltage_value(rdev, std_vddc,
4352                                                       table->initialState.levels[0].vddc.index,
4353                                                       &table->initialState.levels[0].std_vddc);
4354         }
4355
4356         if (eg_pi->vddci_control)
4357                 si_populate_voltage_value(rdev,
4358                                           &eg_pi->vddci_voltage_table,
4359                                           initial_state->performance_levels[0].vddci,
4360                                           &table->initialState.levels[0].vddci);
4361
4362         if (si_pi->vddc_phase_shed_control)
4363                 si_populate_phase_shedding_value(rdev,
4364                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4365                                                  initial_state->performance_levels[0].vddc,
4366                                                  initial_state->performance_levels[0].sclk,
4367                                                  initial_state->performance_levels[0].mclk,
4368                                                  &table->initialState.levels[0].vddc);
4369
4370         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4371
4372         reg = CG_R(0xffff) | CG_L(0);
4373         table->initialState.levels[0].aT = cpu_to_be32(reg);
4374
4375         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4376
4377         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4378
4379         if (pi->mem_gddr5) {
4380                 table->initialState.levels[0].strobeMode =
4381                         si_get_strobe_mode_settings(rdev,
4382                                                     initial_state->performance_levels[0].mclk);
4383
4384                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4385                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4386                 else
4387                         table->initialState.levels[0].mcFlags =  0;
4388         }
4389
4390         table->initialState.levelCount = 1;
4391
4392         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4393
4394         table->initialState.levels[0].dpm2.MaxPS = 0;
4395         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4396         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4397         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4398         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4399
4400         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4401         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4402
4403         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4404         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4405
4406         return 0;
4407 }
4408
4409 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4410                                       SISLANDS_SMC_STATETABLE *table)
4411 {
4412         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4413         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4414         struct si_power_info *si_pi = si_get_pi(rdev);
4415         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4416         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4417         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4418         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4419         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4420         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4421         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4422         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4423         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4424         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4425         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4426         u32 reg;
4427         int ret;
4428
4429         table->ACPIState = table->initialState;
4430
4431         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4432
4433         if (pi->acpi_vddc) {
4434                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4435                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4436                 if (!ret) {
4437                         u16 std_vddc;
4438
4439                         ret = si_get_std_voltage_value(rdev,
4440                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4441                         if (!ret)
4442                                 si_populate_std_voltage_value(rdev, std_vddc,
4443                                                               table->ACPIState.levels[0].vddc.index,
4444                                                               &table->ACPIState.levels[0].std_vddc);
4445                 }
4446                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4447
4448                 if (si_pi->vddc_phase_shed_control) {
4449                         si_populate_phase_shedding_value(rdev,
4450                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4451                                                          pi->acpi_vddc,
4452                                                          0,
4453                                                          0,
4454                                                          &table->ACPIState.levels[0].vddc);
4455                 }
4456         } else {
4457                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4458                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4459                 if (!ret) {
4460                         u16 std_vddc;
4461
4462                         ret = si_get_std_voltage_value(rdev,
4463                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4464
4465                         if (!ret)
4466                                 si_populate_std_voltage_value(rdev, std_vddc,
4467                                                               table->ACPIState.levels[0].vddc.index,
4468                                                               &table->ACPIState.levels[0].std_vddc);
4469                 }
4470                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4471                                                                                     si_pi->sys_pcie_mask,
4472                                                                                     si_pi->boot_pcie_gen,
4473                                                                                     RADEON_PCIE_GEN1);
4474
4475                 if (si_pi->vddc_phase_shed_control)
4476                         si_populate_phase_shedding_value(rdev,
4477                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4478                                                          pi->min_vddc_in_table,
4479                                                          0,
4480                                                          0,
4481                                                          &table->ACPIState.levels[0].vddc);
4482         }
4483
4484         if (pi->acpi_vddc) {
4485                 if (eg_pi->acpi_vddci)
4486                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4487                                                   eg_pi->acpi_vddci,
4488                                                   &table->ACPIState.levels[0].vddci);
4489         }
4490
4491         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4492         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4493
4494         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4495
4496         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4497         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4498
4499         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4500                 cpu_to_be32(dll_cntl);
4501         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4502                 cpu_to_be32(mclk_pwrmgt_cntl);
4503         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4504                 cpu_to_be32(mpll_ad_func_cntl);
4505         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4506                 cpu_to_be32(mpll_dq_func_cntl);
4507         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4508                 cpu_to_be32(mpll_func_cntl);
4509         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4510                 cpu_to_be32(mpll_func_cntl_1);
4511         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4512                 cpu_to_be32(mpll_func_cntl_2);
4513         table->ACPIState.levels[0].mclk.vMPLL_SS =
4514                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4515         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4516                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4517
4518         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4519                 cpu_to_be32(spll_func_cntl);
4520         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4521                 cpu_to_be32(spll_func_cntl_2);
4522         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4523                 cpu_to_be32(spll_func_cntl_3);
4524         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4525                 cpu_to_be32(spll_func_cntl_4);
4526
4527         table->ACPIState.levels[0].mclk.mclk_value = 0;
4528         table->ACPIState.levels[0].sclk.sclk_value = 0;
4529
4530         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4531
4532         if (eg_pi->dynamic_ac_timing)
4533                 table->ACPIState.levels[0].ACIndex = 0;
4534
4535         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4536         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4537         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4538         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4539         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4540
4541         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4542         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4543
4544         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4545         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4546
4547         return 0;
4548 }
4549
4550 static int si_populate_ulv_state(struct radeon_device *rdev,
4551                                  SISLANDS_SMC_SWSTATE *state)
4552 {
4553         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4554         struct si_power_info *si_pi = si_get_pi(rdev);
4555         struct si_ulv_param *ulv = &si_pi->ulv;
4556         u32 sclk_in_sr = 1350; /* ??? */
4557         int ret;
4558
4559         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4560                                             &state->levels[0]);
4561         if (!ret) {
4562                 if (eg_pi->sclk_deep_sleep) {
4563                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4564                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4565                         else
4566                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4567                 }
4568                 if (ulv->one_pcie_lane_in_ulv)
4569                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4570                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4571                 state->levels[0].ACIndex = 1;
4572                 state->levels[0].std_vddc = state->levels[0].vddc;
4573                 state->levelCount = 1;
4574
4575                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4576         }
4577
4578         return ret;
4579 }
4580
4581 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4582 {
4583         struct si_power_info *si_pi = si_get_pi(rdev);
4584         struct si_ulv_param *ulv = &si_pi->ulv;
4585         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4586         int ret;
4587
4588         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4589                                                    &arb_regs);
4590         if (ret)
4591                 return ret;
4592
4593         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4594                                    ulv->volt_change_delay);
4595
4596         ret = si_copy_bytes_to_smc(rdev,
4597                                    si_pi->arb_table_start +
4598                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4599                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4600                                    (u8 *)&arb_regs,
4601                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4602                                    si_pi->sram_end);
4603
4604         return ret;
4605 }
4606
4607 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4608 {
4609         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4610
4611         pi->mvdd_split_frequency = 30000;
4612 }
4613
4614 static int si_init_smc_table(struct radeon_device *rdev)
4615 {
4616         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4617         struct si_power_info *si_pi = si_get_pi(rdev);
4618         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4619         const struct si_ulv_param *ulv = &si_pi->ulv;
4620         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4621         int ret;
4622         u32 lane_width;
4623         u32 vr_hot_gpio;
4624
4625         si_populate_smc_voltage_tables(rdev, table);
4626
4627         switch (rdev->pm.int_thermal_type) {
4628         case THERMAL_TYPE_SI:
4629         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4630                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4631                 break;
4632         case THERMAL_TYPE_NONE:
4633                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4634                 break;
4635         default:
4636                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4637                 break;
4638         }
4639
4640         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4641                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4642
4643         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4644                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4645                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4646         }
4647
4648         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4649                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4650
4651         if (pi->mem_gddr5)
4652                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4653
4654         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4655                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4656
4657         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4658                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4659                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4660                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4661                                            vr_hot_gpio);
4662         }
4663
4664         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4665         if (ret)
4666                 return ret;
4667
4668         ret = si_populate_smc_acpi_state(rdev, table);
4669         if (ret)
4670                 return ret;
4671
4672         table->driverState = table->initialState;
4673
4674         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4675                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4676         if (ret)
4677                 return ret;
4678
4679         if (ulv->supported && ulv->pl.vddc) {
4680                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4681                 if (ret)
4682                         return ret;
4683
4684                 ret = si_program_ulv_memory_timing_parameters(rdev);
4685                 if (ret)
4686                         return ret;
4687
4688                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4689                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4690
4691                 lane_width = radeon_get_pcie_lanes(rdev);
4692                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4693         } else {
4694                 table->ULVState = table->initialState;
4695         }
4696
4697         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4698                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4699                                     si_pi->sram_end);
4700 }
4701
4702 static int si_calculate_sclk_params(struct radeon_device *rdev,
4703                                     u32 engine_clock,
4704                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4705 {
4706         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4707         struct si_power_info *si_pi = si_get_pi(rdev);
4708         struct atom_clock_dividers dividers;
4709         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4710         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4711         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4712         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4713         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4714         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4715         u64 tmp;
4716         u32 reference_clock = rdev->clock.spll.reference_freq;
4717         u32 reference_divider;
4718         u32 fbdiv;
4719         int ret;
4720
4721         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4722                                              engine_clock, false, &dividers);
4723         if (ret)
4724                 return ret;
4725
4726         reference_divider = 1 + dividers.ref_div;
4727
4728         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4729         do_div(tmp, reference_clock);
4730         fbdiv = (u32) tmp;
4731
4732         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4733         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4734         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4735
4736         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4737         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4738
4739         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4740         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4741         spll_func_cntl_3 |= SPLL_DITHEN;
4742
4743         if (pi->sclk_ss) {
4744                 struct radeon_atom_ss ss;
4745                 u32 vco_freq = engine_clock * dividers.post_div;
4746
4747                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4748                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4749                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4750                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4751
4752                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4753                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4754                         cg_spll_spread_spectrum |= SSEN;
4755
4756                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4757                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4758                 }
4759         }
4760
4761         sclk->sclk_value = engine_clock;
4762         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4763         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4764         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4765         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4766         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4767         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4768
4769         return 0;
4770 }
4771
4772 static int si_populate_sclk_value(struct radeon_device *rdev,
4773                                   u32 engine_clock,
4774                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4775 {
4776         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4777         int ret;
4778
4779         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4780         if (!ret) {
4781                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4782                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4783                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4784                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4785                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4786                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4787                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4788         }
4789
4790         return ret;
4791 }
4792
4793 static int si_populate_mclk_value(struct radeon_device *rdev,
4794                                   u32 engine_clock,
4795                                   u32 memory_clock,
4796                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4797                                   bool strobe_mode,
4798                                   bool dll_state_on)
4799 {
4800         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4801         struct si_power_info *si_pi = si_get_pi(rdev);
4802         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4803         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4804         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4805         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4806         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4807         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4808         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4809         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4810         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4811         struct atom_mpll_param mpll_param;
4812         int ret;
4813
4814         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4815         if (ret)
4816                 return ret;
4817
4818         mpll_func_cntl &= ~BWCTRL_MASK;
4819         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4820
4821         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4822         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4823                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4824
4825         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4826         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4827
4828         if (pi->mem_gddr5) {
4829                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4830                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4831                         YCLK_POST_DIV(mpll_param.post_div);
4832         }
4833
4834         if (pi->mclk_ss) {
4835                 struct radeon_atom_ss ss;
4836                 u32 freq_nom;
4837                 u32 tmp;
4838                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4839
4840                 if (pi->mem_gddr5)
4841                         freq_nom = memory_clock * 4;
4842                 else
4843                         freq_nom = memory_clock * 2;
4844
4845                 tmp = freq_nom / reference_clock;
4846                 tmp = tmp * tmp;
4847                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4848                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4849                         u32 clks = reference_clock * 5 / ss.rate;
4850                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4851
4852                         mpll_ss1 &= ~CLKV_MASK;
4853                         mpll_ss1 |= CLKV(clkv);
4854
4855                         mpll_ss2 &= ~CLKS_MASK;
4856                         mpll_ss2 |= CLKS(clks);
4857                 }
4858         }
4859
4860         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4861         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4862
4863         if (dll_state_on)
4864                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4865         else
4866                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4867
4868         mclk->mclk_value = cpu_to_be32(memory_clock);
4869         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4870         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4871         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4872         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4873         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4874         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4875         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4876         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4877         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4878
4879         return 0;
4880 }
4881
4882 static void si_populate_smc_sp(struct radeon_device *rdev,
4883                                struct radeon_ps *radeon_state,
4884                                SISLANDS_SMC_SWSTATE *smc_state)
4885 {
4886         struct ni_ps *ps = ni_get_ps(radeon_state);
4887         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4888         int i;
4889
4890         for (i = 0; i < ps->performance_level_count - 1; i++)
4891                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4892
4893         smc_state->levels[ps->performance_level_count - 1].bSP =
4894                 cpu_to_be32(pi->psp);
4895 }
4896
4897 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4898                                          struct rv7xx_pl *pl,
4899                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4900 {
4901         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4902         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4903         struct si_power_info *si_pi = si_get_pi(rdev);
4904         int ret;
4905         bool dll_state_on;
4906         u16 std_vddc;
4907         bool gmc_pg = false;
4908
4909         if (eg_pi->pcie_performance_request &&
4910             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4911                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4912         else
4913                 level->gen2PCIE = (u8)pl->pcie_gen;
4914
4915         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4916         if (ret)
4917                 return ret;
4918
4919         level->mcFlags =  0;
4920
4921         if (pi->mclk_stutter_mode_threshold &&
4922             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4923             !eg_pi->uvd_enabled &&
4924             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4925             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4926                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4927
4928                 if (gmc_pg)
4929                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4930         }
4931
4932         if (pi->mem_gddr5) {
4933                 if (pl->mclk > pi->mclk_edc_enable_threshold)
4934                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4935
4936                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4937                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4938
4939                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4940
4941                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4942                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4943                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4944                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4945                         else
4946                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4947                 } else {
4948                         dll_state_on = false;
4949                 }
4950         } else {
4951                 level->strobeMode = si_get_strobe_mode_settings(rdev,
4952                                                                 pl->mclk);
4953
4954                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4955         }
4956
4957         ret = si_populate_mclk_value(rdev,
4958                                      pl->sclk,
4959                                      pl->mclk,
4960                                      &level->mclk,
4961                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4962         if (ret)
4963                 return ret;
4964
4965         ret = si_populate_voltage_value(rdev,
4966                                         &eg_pi->vddc_voltage_table,
4967                                         pl->vddc, &level->vddc);
4968         if (ret)
4969                 return ret;
4970
4971
4972         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4973         if (ret)
4974                 return ret;
4975
4976         ret = si_populate_std_voltage_value(rdev, std_vddc,
4977                                             level->vddc.index, &level->std_vddc);
4978         if (ret)
4979                 return ret;
4980
4981         if (eg_pi->vddci_control) {
4982                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4983                                                 pl->vddci, &level->vddci);
4984                 if (ret)
4985                         return ret;
4986         }
4987
4988         if (si_pi->vddc_phase_shed_control) {
4989                 ret = si_populate_phase_shedding_value(rdev,
4990                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4991                                                        pl->vddc,
4992                                                        pl->sclk,
4993                                                        pl->mclk,
4994                                                        &level->vddc);
4995                 if (ret)
4996                         return ret;
4997         }
4998
4999         level->MaxPoweredUpCU = si_pi->max_cu;
5000
5001         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5002
5003         return ret;
5004 }
5005
5006 static int si_populate_smc_t(struct radeon_device *rdev,
5007                              struct radeon_ps *radeon_state,
5008                              SISLANDS_SMC_SWSTATE *smc_state)
5009 {
5010         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5011         struct ni_ps *state = ni_get_ps(radeon_state);
5012         u32 a_t;
5013         u32 t_l, t_h;
5014         u32 high_bsp;
5015         int i, ret;
5016
5017         if (state->performance_level_count >= 9)
5018                 return -EINVAL;
5019
5020         if (state->performance_level_count < 2) {
5021                 a_t = CG_R(0xffff) | CG_L(0);
5022                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5023                 return 0;
5024         }
5025
5026         smc_state->levels[0].aT = cpu_to_be32(0);
5027
5028         for (i = 0; i <= state->performance_level_count - 2; i++) {
5029                 ret = r600_calculate_at(
5030                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5031                         100 * R600_AH_DFLT,
5032                         state->performance_levels[i + 1].sclk,
5033                         state->performance_levels[i].sclk,
5034                         &t_l,
5035                         &t_h);
5036
5037                 if (ret) {
5038                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5039                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5040                 }
5041
5042                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5043                 a_t |= CG_R(t_l * pi->bsp / 20000);
5044                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5045
5046                 high_bsp = (i == state->performance_level_count - 2) ?
5047                         pi->pbsp : pi->bsp;
5048                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5049                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5050         }
5051
5052         return 0;
5053 }
5054
5055 static int si_disable_ulv(struct radeon_device *rdev)
5056 {
5057         struct si_power_info *si_pi = si_get_pi(rdev);
5058         struct si_ulv_param *ulv = &si_pi->ulv;
5059
5060         if (ulv->supported)
5061                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5062                         0 : -EINVAL;
5063
5064         return 0;
5065 }
5066
5067 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5068                                        struct radeon_ps *radeon_state)
5069 {
5070         const struct si_power_info *si_pi = si_get_pi(rdev);
5071         const struct si_ulv_param *ulv = &si_pi->ulv;
5072         const struct ni_ps *state = ni_get_ps(radeon_state);
5073         int i;
5074
5075         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5076                 return false;
5077
5078         /* XXX validate against display requirements! */
5079
5080         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5081                 if (rdev->clock.current_dispclk <=
5082                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5083                         if (ulv->pl.vddc <
5084                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5085                                 return false;
5086                 }
5087         }
5088
5089         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5090                 return false;
5091
5092         return true;
5093 }
5094
5095 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5096                                                        struct radeon_ps *radeon_new_state)
5097 {
5098         const struct si_power_info *si_pi = si_get_pi(rdev);
5099         const struct si_ulv_param *ulv = &si_pi->ulv;
5100
5101         if (ulv->supported) {
5102                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5103                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5104                                 0 : -EINVAL;
5105         }
5106         return 0;
5107 }
5108
5109 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5110                                          struct radeon_ps *radeon_state,
5111                                          SISLANDS_SMC_SWSTATE *smc_state)
5112 {
5113         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5114         struct ni_power_info *ni_pi = ni_get_pi(rdev);
5115         struct si_power_info *si_pi = si_get_pi(rdev);
5116         struct ni_ps *state = ni_get_ps(radeon_state);
5117         int i, ret;
5118         u32 threshold;
5119         u32 sclk_in_sr = 1350; /* ??? */
5120
5121         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5122                 return -EINVAL;
5123
5124         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5125
5126         if (radeon_state->vclk && radeon_state->dclk) {
5127                 eg_pi->uvd_enabled = true;
5128                 if (eg_pi->smu_uvd_hs)
5129                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5130         } else {
5131                 eg_pi->uvd_enabled = false;
5132         }
5133
5134         if (state->dc_compatible)
5135                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5136
5137         smc_state->levelCount = 0;
5138         for (i = 0; i < state->performance_level_count; i++) {
5139                 if (eg_pi->sclk_deep_sleep) {
5140                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5141                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5142                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5143                                 else
5144                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5145                         }
5146                 }
5147
5148                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5149                                                     &smc_state->levels[i]);
5150                 smc_state->levels[i].arbRefreshState =
5151                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5152
5153                 if (ret)
5154                         return ret;
5155
5156                 if (ni_pi->enable_power_containment)
5157                         smc_state->levels[i].displayWatermark =
5158                                 (state->performance_levels[i].sclk < threshold) ?
5159                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5160                 else
5161                         smc_state->levels[i].displayWatermark = (i < 2) ?
5162                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5163
5164                 if (eg_pi->dynamic_ac_timing)
5165                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5166                 else
5167                         smc_state->levels[i].ACIndex = 0;
5168
5169                 smc_state->levelCount++;
5170         }
5171
5172         si_write_smc_soft_register(rdev,
5173                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5174                                    threshold / 512);
5175
5176         si_populate_smc_sp(rdev, radeon_state, smc_state);
5177
5178         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5179         if (ret)
5180                 ni_pi->enable_power_containment = false;
5181
5182         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5183         if (ret)
5184                 ni_pi->enable_sq_ramping = false;
5185
5186         return si_populate_smc_t(rdev, radeon_state, smc_state);
5187 }
5188
5189 static int si_upload_sw_state(struct radeon_device *rdev,
5190                               struct radeon_ps *radeon_new_state)
5191 {
5192         struct si_power_info *si_pi = si_get_pi(rdev);
5193         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5194         int ret;
5195         u32 address = si_pi->state_table_start +
5196                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5197         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5198                 ((new_state->performance_level_count - 1) *
5199                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5200         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5201
5202         memset(smc_state, 0, state_size);
5203
5204         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5205         if (ret)
5206                 return ret;
5207
5208         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5209                                    state_size, si_pi->sram_end);
5210
5211         return ret;
5212 }
5213
5214 static int si_upload_ulv_state(struct radeon_device *rdev)
5215 {
5216         struct si_power_info *si_pi = si_get_pi(rdev);
5217         struct si_ulv_param *ulv = &si_pi->ulv;
5218         int ret = 0;
5219
5220         if (ulv->supported && ulv->pl.vddc) {
5221                 u32 address = si_pi->state_table_start +
5222                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5223                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5224                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5225
5226                 memset(smc_state, 0, state_size);
5227
5228                 ret = si_populate_ulv_state(rdev, smc_state);
5229                 if (!ret)
5230                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5231                                                    state_size, si_pi->sram_end);
5232         }
5233
5234         return ret;
5235 }
5236
5237 static int si_upload_smc_data(struct radeon_device *rdev)
5238 {
5239         struct radeon_crtc *radeon_crtc = NULL;
5240         int i;
5241
5242         if (rdev->pm.dpm.new_active_crtc_count == 0)
5243                 return 0;
5244
5245         for (i = 0; i < rdev->num_crtc; i++) {
5246                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5247                         radeon_crtc = rdev->mode_info.crtcs[i];
5248                         break;
5249                 }
5250         }
5251
5252         if (radeon_crtc == NULL)
5253                 return 0;
5254
5255         if (radeon_crtc->line_time <= 0)
5256                 return 0;
5257
5258         if (si_write_smc_soft_register(rdev,
5259                                        SI_SMC_SOFT_REGISTER_crtc_index,
5260                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5261                 return 0;
5262
5263         if (si_write_smc_soft_register(rdev,
5264                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5265                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5266                 return 0;
5267
5268         if (si_write_smc_soft_register(rdev,
5269                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5270                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5271                 return 0;
5272
5273         return 0;
5274 }
5275
5276 static int si_set_mc_special_registers(struct radeon_device *rdev,
5277                                        struct si_mc_reg_table *table)
5278 {
5279         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5280         u8 i, j, k;
5281         u32 temp_reg;
5282
5283         for (i = 0, j = table->last; i < table->last; i++) {
5284                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5285                         return -EINVAL;
5286                 switch (table->mc_reg_address[i].s1 << 2) {
5287                 case MC_SEQ_MISC1:
5288                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5289                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5290                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5291                         for (k = 0; k < table->num_entries; k++)
5292                                 table->mc_reg_table_entry[k].mc_data[j] =
5293                                         ((temp_reg & 0xffff0000)) |
5294                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5295                         j++;
5296                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5297                                 return -EINVAL;
5298
5299                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5300                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5301                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5302                         for (k = 0; k < table->num_entries; k++) {
5303                                 table->mc_reg_table_entry[k].mc_data[j] =
5304                                         (temp_reg & 0xffff0000) |
5305                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5306                                 if (!pi->mem_gddr5)
5307                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5308                         }
5309                         j++;
5310                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5311                                 return -EINVAL;
5312
5313                         if (!pi->mem_gddr5) {
5314                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5315                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5316                                 for (k = 0; k < table->num_entries; k++)
5317                                         table->mc_reg_table_entry[k].mc_data[j] =
5318                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5319                                 j++;
5320                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5321                                         return -EINVAL;
5322                         }
5323                         break;
5324                 case MC_SEQ_RESERVE_M:
5325                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5326                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5327                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5328                         for(k = 0; k < table->num_entries; k++)
5329                                 table->mc_reg_table_entry[k].mc_data[j] =
5330                                         (temp_reg & 0xffff0000) |
5331                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5332                         j++;
5333                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5334                                 return -EINVAL;
5335                         break;
5336                 default:
5337                         break;
5338                 }
5339         }
5340
5341         table->last = j;
5342
5343         return 0;
5344 }
5345
5346 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5347 {
5348         bool result = true;
5349
5350         switch (in_reg) {
5351         case  MC_SEQ_RAS_TIMING >> 2:
5352                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5353                 break;
5354         case MC_SEQ_CAS_TIMING >> 2:
5355                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5356                 break;
5357         case MC_SEQ_MISC_TIMING >> 2:
5358                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5359                 break;
5360         case MC_SEQ_MISC_TIMING2 >> 2:
5361                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5362                 break;
5363         case MC_SEQ_RD_CTL_D0 >> 2:
5364                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5365                 break;
5366         case MC_SEQ_RD_CTL_D1 >> 2:
5367                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5368                 break;
5369         case MC_SEQ_WR_CTL_D0 >> 2:
5370                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5371                 break;
5372         case MC_SEQ_WR_CTL_D1 >> 2:
5373                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5374                 break;
5375         case MC_PMG_CMD_EMRS >> 2:
5376                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5377                 break;
5378         case MC_PMG_CMD_MRS >> 2:
5379                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5380                 break;
5381         case MC_PMG_CMD_MRS1 >> 2:
5382                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5383                 break;
5384         case MC_SEQ_PMG_TIMING >> 2:
5385                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5386                 break;
5387         case MC_PMG_CMD_MRS2 >> 2:
5388                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5389                 break;
5390         case MC_SEQ_WR_CTL_2 >> 2:
5391                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5392                 break;
5393         default:
5394                 result = false;
5395                 break;
5396         }
5397
5398         return result;
5399 }
5400
5401 static void si_set_valid_flag(struct si_mc_reg_table *table)
5402 {
5403         u8 i, j;
5404
5405         for (i = 0; i < table->last; i++) {
5406                 for (j = 1; j < table->num_entries; j++) {
5407                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5408                                 table->valid_flag |= 1 << i;
5409                                 break;
5410                         }
5411                 }
5412         }
5413 }
5414
5415 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5416 {
5417         u32 i;
5418         u16 address;
5419
5420         for (i = 0; i < table->last; i++)
5421                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5422                         address : table->mc_reg_address[i].s1;
5423
5424 }
5425
5426 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5427                                       struct si_mc_reg_table *si_table)
5428 {
5429         u8 i, j;
5430
5431         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5432                 return -EINVAL;
5433         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5434                 return -EINVAL;
5435
5436         for (i = 0; i < table->last; i++)
5437                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5438         si_table->last = table->last;
5439
5440         for (i = 0; i < table->num_entries; i++) {
5441                 si_table->mc_reg_table_entry[i].mclk_max =
5442                         table->mc_reg_table_entry[i].mclk_max;
5443                 for (j = 0; j < table->last; j++) {
5444                         si_table->mc_reg_table_entry[i].mc_data[j] =
5445                                 table->mc_reg_table_entry[i].mc_data[j];
5446                 }
5447         }
5448         si_table->num_entries = table->num_entries;
5449
5450         return 0;
5451 }
5452
5453 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5454 {
5455         struct si_power_info *si_pi = si_get_pi(rdev);
5456         struct atom_mc_reg_table *table;
5457         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5458         u8 module_index = rv770_get_memory_module_index(rdev);
5459         int ret;
5460
5461         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5462         if (!table)
5463                 return -ENOMEM;
5464
5465         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5466         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5467         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5468         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5469         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5470         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5471         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5472         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5473         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5474         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5475         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5476         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5477         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5478         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5479
5480         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5481         if (ret)
5482                 goto init_mc_done;
5483
5484         ret = si_copy_vbios_mc_reg_table(table, si_table);
5485         if (ret)
5486                 goto init_mc_done;
5487
5488         si_set_s0_mc_reg_index(si_table);
5489
5490         ret = si_set_mc_special_registers(rdev, si_table);
5491         if (ret)
5492                 goto init_mc_done;
5493
5494         si_set_valid_flag(si_table);
5495
5496 init_mc_done:
5497         kfree(table);
5498
5499         return ret;
5500
5501 }
5502
5503 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5504                                          SMC_SIslands_MCRegisters *mc_reg_table)
5505 {
5506         struct si_power_info *si_pi = si_get_pi(rdev);
5507         u32 i, j;
5508
5509         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5510                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5511                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5512                                 break;
5513                         mc_reg_table->address[i].s0 =
5514                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5515                         mc_reg_table->address[i].s1 =
5516                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5517                         i++;
5518                 }
5519         }
5520         mc_reg_table->last = (u8)i;
5521 }
5522
5523 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5524                                     SMC_SIslands_MCRegisterSet *data,
5525                                     u32 num_entries, u32 valid_flag)
5526 {
5527         u32 i, j;
5528
5529         for(i = 0, j = 0; j < num_entries; j++) {
5530                 if (valid_flag & (1 << j)) {
5531                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5532                         i++;
5533                 }
5534         }
5535 }
5536
5537 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5538                                                  struct rv7xx_pl *pl,
5539                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5540 {
5541         struct si_power_info *si_pi = si_get_pi(rdev);
5542         u32 i = 0;
5543
5544         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5545                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5546                         break;
5547         }
5548
5549         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5550                 --i;
5551
5552         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5553                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5554                                 si_pi->mc_reg_table.valid_flag);
5555 }
5556
5557 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5558                                            struct radeon_ps *radeon_state,
5559                                            SMC_SIslands_MCRegisters *mc_reg_table)
5560 {
5561         struct ni_ps *state = ni_get_ps(radeon_state);
5562         int i;
5563
5564         for (i = 0; i < state->performance_level_count; i++) {
5565                 si_convert_mc_reg_table_entry_to_smc(rdev,
5566                                                      &state->performance_levels[i],
5567                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5568         }
5569 }
5570
5571 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5572                                     struct radeon_ps *radeon_boot_state)
5573 {
5574         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5575         struct si_power_info *si_pi = si_get_pi(rdev);
5576         struct si_ulv_param *ulv = &si_pi->ulv;
5577         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5578
5579         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5580
5581         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5582
5583         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5584
5585         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5586                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5587
5588         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5589                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5590                                 si_pi->mc_reg_table.last,
5591                                 si_pi->mc_reg_table.valid_flag);
5592
5593         if (ulv->supported && ulv->pl.vddc != 0)
5594                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5595                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5596         else
5597                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5598                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5599                                         si_pi->mc_reg_table.last,
5600                                         si_pi->mc_reg_table.valid_flag);
5601
5602         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5603
5604         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5605                                     (u8 *)smc_mc_reg_table,
5606                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5607 }
5608
5609 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5610                                   struct radeon_ps *radeon_new_state)
5611 {
5612         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5613         struct si_power_info *si_pi = si_get_pi(rdev);
5614         u32 address = si_pi->mc_reg_table_start +
5615                 offsetof(SMC_SIslands_MCRegisters,
5616                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5617         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5618
5619         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5620
5621         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5622
5623
5624         return si_copy_bytes_to_smc(rdev, address,
5625                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5626                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5627                                     si_pi->sram_end);
5628
5629 }
5630
5631 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5632 {
5633         if (enable)
5634                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5635         else
5636                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5637 }
5638
5639 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5640                                                       struct radeon_ps *radeon_state)
5641 {
5642         struct ni_ps *state = ni_get_ps(radeon_state);
5643         int i;
5644         u16 pcie_speed, max_speed = 0;
5645
5646         for (i = 0; i < state->performance_level_count; i++) {
5647                 pcie_speed = state->performance_levels[i].pcie_gen;
5648                 if (max_speed < pcie_speed)
5649                         max_speed = pcie_speed;
5650         }
5651         return max_speed;
5652 }
5653
5654 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5655 {
5656         u32 speed_cntl;
5657
5658         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5659         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5660
5661         return (u16)speed_cntl;
5662 }
5663
5664 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5665                                                              struct radeon_ps *radeon_new_state,
5666                                                              struct radeon_ps *radeon_current_state)
5667 {
5668         struct si_power_info *si_pi = si_get_pi(rdev);
5669         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5670         enum radeon_pcie_gen current_link_speed;
5671
5672         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5673                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5674         else
5675                 current_link_speed = si_pi->force_pcie_gen;
5676
5677         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5678         si_pi->pspp_notify_required = false;
5679         if (target_link_speed > current_link_speed) {
5680                 switch (target_link_speed) {
5681 #if defined(CONFIG_ACPI)
5682                 case RADEON_PCIE_GEN3:
5683                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5684                                 break;
5685                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5686                         if (current_link_speed == RADEON_PCIE_GEN2)
5687                                 break;
5688                 case RADEON_PCIE_GEN2:
5689                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5690                                 break;
5691 #endif
5692                 default:
5693                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5694                         break;
5695                 }
5696         } else {
5697                 if (target_link_speed < current_link_speed)
5698                         si_pi->pspp_notify_required = true;
5699         }
5700 }
5701
5702 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5703                                                            struct radeon_ps *radeon_new_state,
5704                                                            struct radeon_ps *radeon_current_state)
5705 {
5706         struct si_power_info *si_pi = si_get_pi(rdev);
5707         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5708         u8 request;
5709
5710         if (si_pi->pspp_notify_required) {
5711                 if (target_link_speed == RADEON_PCIE_GEN3)
5712                         request = PCIE_PERF_REQ_PECI_GEN3;
5713                 else if (target_link_speed == RADEON_PCIE_GEN2)
5714                         request = PCIE_PERF_REQ_PECI_GEN2;
5715                 else
5716                         request = PCIE_PERF_REQ_PECI_GEN1;
5717
5718                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5719                     (si_get_current_pcie_speed(rdev) > 0))
5720                         return;
5721
5722 #if defined(CONFIG_ACPI)
5723                 radeon_acpi_pcie_performance_request(rdev, request, false);
5724 #endif
5725         }
5726 }
5727
5728 #if 0
5729 static int si_ds_request(struct radeon_device *rdev,
5730                          bool ds_status_on, u32 count_write)
5731 {
5732         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5733
5734         if (eg_pi->sclk_deep_sleep) {
5735                 if (ds_status_on)
5736                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5737                                 PPSMC_Result_OK) ?
5738                                 0 : -EINVAL;
5739                 else
5740                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5741                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5742         }
5743         return 0;
5744 }
5745 #endif
5746
5747 static void si_set_max_cu_value(struct radeon_device *rdev)
5748 {
5749         struct si_power_info *si_pi = si_get_pi(rdev);
5750
5751         if (rdev->family == CHIP_VERDE) {
5752                 switch (rdev->pdev->device) {
5753                 case 0x6820:
5754                 case 0x6825:
5755                 case 0x6821:
5756                 case 0x6823:
5757                 case 0x6827:
5758                         si_pi->max_cu = 10;
5759                         break;
5760                 case 0x682D:
5761                 case 0x6824:
5762                 case 0x682F:
5763                 case 0x6826:
5764                         si_pi->max_cu = 8;
5765                         break;
5766                 case 0x6828:
5767                 case 0x6830:
5768                 case 0x6831:
5769                 case 0x6838:
5770                 case 0x6839:
5771                 case 0x683D:
5772                         si_pi->max_cu = 10;
5773                         break;
5774                 case 0x683B:
5775                 case 0x683F:
5776                 case 0x6829:
5777                         si_pi->max_cu = 8;
5778                         break;
5779                 default:
5780                         si_pi->max_cu = 0;
5781                         break;
5782                 }
5783         } else {
5784                 si_pi->max_cu = 0;
5785         }
5786 }
5787
5788 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5789                                                              struct radeon_clock_voltage_dependency_table *table)
5790 {
5791         u32 i;
5792         int j;
5793         u16 leakage_voltage;
5794
5795         if (table) {
5796                 for (i = 0; i < table->count; i++) {
5797                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5798                                                                           table->entries[i].v,
5799                                                                           &leakage_voltage)) {
5800                         case 0:
5801                                 table->entries[i].v = leakage_voltage;
5802                                 break;
5803                         case -EAGAIN:
5804                                 return -EINVAL;
5805                         case -EINVAL:
5806                         default:
5807                                 break;
5808                         }
5809                 }
5810
5811                 for (j = (table->count - 2); j >= 0; j--) {
5812                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5813                                 table->entries[j].v : table->entries[j + 1].v;
5814                 }
5815         }
5816         return 0;
5817 }
5818
5819 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5820 {
5821         int ret = 0;
5822
5823         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5824                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5825         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5826                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5827         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5828                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5829         return ret;
5830 }
5831
5832 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5833                                           struct radeon_ps *radeon_new_state,
5834                                           struct radeon_ps *radeon_current_state)
5835 {
5836         u32 lane_width;
5837         u32 new_lane_width =
5838                 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5839         u32 current_lane_width =
5840                 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5841
5842         if (new_lane_width != current_lane_width) {
5843                 radeon_set_pcie_lanes(rdev, new_lane_width);
5844                 lane_width = radeon_get_pcie_lanes(rdev);
5845                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5846         }
5847 }
5848
5849 void si_dpm_setup_asic(struct radeon_device *rdev)
5850 {
5851         int r;
5852
5853         r = si_mc_load_microcode(rdev);
5854         if (r)
5855                 DRM_ERROR("Failed to load MC firmware!\n");
5856         rv770_get_memory_type(rdev);
5857         si_read_clock_registers(rdev);
5858         si_enable_acpi_power_management(rdev);
5859 }
5860
5861 static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5862                                         int min_temp, int max_temp)
5863 {
5864         int low_temp = 0 * 1000;
5865         int high_temp = 255 * 1000;
5866
5867         if (low_temp < min_temp)
5868                 low_temp = min_temp;
5869         if (high_temp > max_temp)
5870                 high_temp = max_temp;
5871         if (high_temp < low_temp) {
5872                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5873                 return -EINVAL;
5874         }
5875
5876         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5877         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5878         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5879
5880         rdev->pm.dpm.thermal.min_temp = low_temp;
5881         rdev->pm.dpm.thermal.max_temp = high_temp;
5882
5883         return 0;
5884 }
5885
5886 int si_dpm_enable(struct radeon_device *rdev)
5887 {
5888         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5889         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5890         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5891         int ret;
5892
5893         if (si_is_smc_running(rdev))
5894                 return -EINVAL;
5895         if (pi->voltage_control)
5896                 si_enable_voltage_control(rdev, true);
5897         if (pi->mvdd_control)
5898                 si_get_mvdd_configuration(rdev);
5899         if (pi->voltage_control) {
5900                 ret = si_construct_voltage_tables(rdev);
5901                 if (ret) {
5902                         DRM_ERROR("si_construct_voltage_tables failed\n");
5903                         return ret;
5904                 }
5905         }
5906         if (eg_pi->dynamic_ac_timing) {
5907                 ret = si_initialize_mc_reg_table(rdev);
5908                 if (ret)
5909                         eg_pi->dynamic_ac_timing = false;
5910         }
5911         if (pi->dynamic_ss)
5912                 si_enable_spread_spectrum(rdev, true);
5913         if (pi->thermal_protection)
5914                 si_enable_thermal_protection(rdev, true);
5915         si_setup_bsp(rdev);
5916         si_program_git(rdev);
5917         si_program_tp(rdev);
5918         si_program_tpp(rdev);
5919         si_program_sstp(rdev);
5920         si_enable_display_gap(rdev);
5921         si_program_vc(rdev);
5922         ret = si_upload_firmware(rdev);
5923         if (ret) {
5924                 DRM_ERROR("si_upload_firmware failed\n");
5925                 return ret;
5926         }
5927         ret = si_process_firmware_header(rdev);
5928         if (ret) {
5929                 DRM_ERROR("si_process_firmware_header failed\n");
5930                 return ret;
5931         }
5932         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5933         if (ret) {
5934                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5935                 return ret;
5936         }
5937         ret = si_init_smc_table(rdev);
5938         if (ret) {
5939                 DRM_ERROR("si_init_smc_table failed\n");
5940                 return ret;
5941         }
5942         ret = si_init_smc_spll_table(rdev);
5943         if (ret) {
5944                 DRM_ERROR("si_init_smc_spll_table failed\n");
5945                 return ret;
5946         }
5947         ret = si_init_arb_table_index(rdev);
5948         if (ret) {
5949                 DRM_ERROR("si_init_arb_table_index failed\n");
5950                 return ret;
5951         }
5952         if (eg_pi->dynamic_ac_timing) {
5953                 ret = si_populate_mc_reg_table(rdev, boot_ps);
5954                 if (ret) {
5955                         DRM_ERROR("si_populate_mc_reg_table failed\n");
5956                         return ret;
5957                 }
5958         }
5959         ret = si_initialize_smc_cac_tables(rdev);
5960         if (ret) {
5961                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5962                 return ret;
5963         }
5964         ret = si_initialize_hardware_cac_manager(rdev);
5965         if (ret) {
5966                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5967                 return ret;
5968         }
5969         ret = si_initialize_smc_dte_tables(rdev);
5970         if (ret) {
5971                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5972                 return ret;
5973         }
5974         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5975         if (ret) {
5976                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5977                 return ret;
5978         }
5979         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5980         if (ret) {
5981                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5982                 return ret;
5983         }
5984         si_program_response_times(rdev);
5985         si_program_ds_registers(rdev);
5986         si_dpm_start_smc(rdev);
5987         ret = si_notify_smc_display_change(rdev, false);
5988         if (ret) {
5989                 DRM_ERROR("si_notify_smc_display_change failed\n");
5990                 return ret;
5991         }
5992         si_enable_sclk_control(rdev, true);
5993         si_start_dpm(rdev);
5994
5995         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5996
5997         ni_update_current_ps(rdev, boot_ps);
5998
5999         return 0;
6000 }
6001
6002 int si_dpm_late_enable(struct radeon_device *rdev)
6003 {
6004         int ret;
6005
6006         if (rdev->irq.installed &&
6007             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
6008                 PPSMC_Result result;
6009
6010                 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6011                 if (ret)
6012                         return ret;
6013                 rdev->irq.dpm_thermal = true;
6014                 radeon_irq_set(rdev);
6015                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
6016
6017                 if (result != PPSMC_Result_OK)
6018                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6019         }
6020
6021         return 0;
6022 }
6023
6024 void si_dpm_disable(struct radeon_device *rdev)
6025 {
6026         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6027         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6028
6029         if (!si_is_smc_running(rdev))
6030                 return;
6031         si_disable_ulv(rdev);
6032         si_clear_vc(rdev);
6033         if (pi->thermal_protection)
6034                 si_enable_thermal_protection(rdev, false);
6035         si_enable_power_containment(rdev, boot_ps, false);
6036         si_enable_smc_cac(rdev, boot_ps, false);
6037         si_enable_spread_spectrum(rdev, false);
6038         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6039         si_stop_dpm(rdev);
6040         si_reset_to_default(rdev);
6041         si_dpm_stop_smc(rdev);
6042         si_force_switch_to_arb_f0(rdev);
6043
6044         ni_update_current_ps(rdev, boot_ps);
6045 }
6046
6047 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6048 {
6049         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6050         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6051         struct radeon_ps *new_ps = &requested_ps;
6052
6053         ni_update_requested_ps(rdev, new_ps);
6054
6055         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6056
6057         return 0;
6058 }
6059
6060 static int si_power_control_set_level(struct radeon_device *rdev)
6061 {
6062         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6063         int ret;
6064
6065         ret = si_restrict_performance_levels_before_switch(rdev);
6066         if (ret)
6067                 return ret;
6068         ret = si_halt_smc(rdev);
6069         if (ret)
6070                 return ret;
6071         ret = si_populate_smc_tdp_limits(rdev, new_ps);
6072         if (ret)
6073                 return ret;
6074         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6075         if (ret)
6076                 return ret;
6077         ret = si_resume_smc(rdev);
6078         if (ret)
6079                 return ret;
6080         ret = si_set_sw_state(rdev);
6081         if (ret)
6082                 return ret;
6083         return 0;
6084 }
6085
6086 int si_dpm_set_power_state(struct radeon_device *rdev)
6087 {
6088         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6089         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6090         struct radeon_ps *old_ps = &eg_pi->current_rps;
6091         int ret;
6092
6093         ret = si_disable_ulv(rdev);
6094         if (ret) {
6095                 DRM_ERROR("si_disable_ulv failed\n");
6096                 return ret;
6097         }
6098         ret = si_restrict_performance_levels_before_switch(rdev);
6099         if (ret) {
6100                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6101                 return ret;
6102         }
6103         if (eg_pi->pcie_performance_request)
6104                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6105         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6106         ret = si_enable_power_containment(rdev, new_ps, false);
6107         if (ret) {
6108                 DRM_ERROR("si_enable_power_containment failed\n");
6109                 return ret;
6110         }
6111         ret = si_enable_smc_cac(rdev, new_ps, false);
6112         if (ret) {
6113                 DRM_ERROR("si_enable_smc_cac failed\n");
6114                 return ret;
6115         }
6116         ret = si_halt_smc(rdev);
6117         if (ret) {
6118                 DRM_ERROR("si_halt_smc failed\n");
6119                 return ret;
6120         }
6121         ret = si_upload_sw_state(rdev, new_ps);
6122         if (ret) {
6123                 DRM_ERROR("si_upload_sw_state failed\n");
6124                 return ret;
6125         }
6126         ret = si_upload_smc_data(rdev);
6127         if (ret) {
6128                 DRM_ERROR("si_upload_smc_data failed\n");
6129                 return ret;
6130         }
6131         ret = si_upload_ulv_state(rdev);
6132         if (ret) {
6133                 DRM_ERROR("si_upload_ulv_state failed\n");
6134                 return ret;
6135         }
6136         if (eg_pi->dynamic_ac_timing) {
6137                 ret = si_upload_mc_reg_table(rdev, new_ps);
6138                 if (ret) {
6139                         DRM_ERROR("si_upload_mc_reg_table failed\n");
6140                         return ret;
6141                 }
6142         }
6143         ret = si_program_memory_timing_parameters(rdev, new_ps);
6144         if (ret) {
6145                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6146                 return ret;
6147         }
6148         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6149
6150         ret = si_resume_smc(rdev);
6151         if (ret) {
6152                 DRM_ERROR("si_resume_smc failed\n");
6153                 return ret;
6154         }
6155         ret = si_set_sw_state(rdev);
6156         if (ret) {
6157                 DRM_ERROR("si_set_sw_state failed\n");
6158                 return ret;
6159         }
6160         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6161         if (eg_pi->pcie_performance_request)
6162                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6163         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6164         if (ret) {
6165                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6166                 return ret;
6167         }
6168         ret = si_enable_smc_cac(rdev, new_ps, true);
6169         if (ret) {
6170                 DRM_ERROR("si_enable_smc_cac failed\n");
6171                 return ret;
6172         }
6173         ret = si_enable_power_containment(rdev, new_ps, true);
6174         if (ret) {
6175                 DRM_ERROR("si_enable_power_containment failed\n");
6176                 return ret;
6177         }
6178
6179         ret = si_power_control_set_level(rdev);
6180         if (ret) {
6181                 DRM_ERROR("si_power_control_set_level failed\n");
6182                 return ret;
6183         }
6184
6185         return 0;
6186 }
6187
6188 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6189 {
6190         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6191         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6192
6193         ni_update_current_ps(rdev, new_ps);
6194 }
6195
6196
6197 void si_dpm_reset_asic(struct radeon_device *rdev)
6198 {
6199         si_restrict_performance_levels_before_switch(rdev);
6200         si_disable_ulv(rdev);
6201         si_set_boot_state(rdev);
6202 }
6203
6204 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6205 {
6206         si_program_display_gap(rdev);
6207 }
6208
6209 union power_info {
6210         struct _ATOM_POWERPLAY_INFO info;
6211         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6212         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6213         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6214         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6215         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6216 };
6217
6218 union pplib_clock_info {
6219         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6220         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6221         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6222         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6223         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6224 };
6225
6226 union pplib_power_state {
6227         struct _ATOM_PPLIB_STATE v1;
6228         struct _ATOM_PPLIB_STATE_V2 v2;
6229 };
6230
6231 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6232                                           struct radeon_ps *rps,
6233                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6234                                           u8 table_rev)
6235 {
6236         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6237         rps->class = le16_to_cpu(non_clock_info->usClassification);
6238         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6239
6240         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6241                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6242                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6243         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6244                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6245                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6246         } else {
6247                 rps->vclk = 0;
6248                 rps->dclk = 0;
6249         }
6250
6251         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6252                 rdev->pm.dpm.boot_ps = rps;
6253         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6254                 rdev->pm.dpm.uvd_ps = rps;
6255 }
6256
6257 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6258                                       struct radeon_ps *rps, int index,
6259                                       union pplib_clock_info *clock_info)
6260 {
6261         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6262         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6263         struct si_power_info *si_pi = si_get_pi(rdev);
6264         struct ni_ps *ps = ni_get_ps(rps);
6265         u16 leakage_voltage;
6266         struct rv7xx_pl *pl = &ps->performance_levels[index];
6267         int ret;
6268
6269         ps->performance_level_count = index + 1;
6270
6271         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6272         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6273         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6274         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6275
6276         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6277         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6278         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6279         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6280                                                  si_pi->sys_pcie_mask,
6281                                                  si_pi->boot_pcie_gen,
6282                                                  clock_info->si.ucPCIEGen);
6283
6284         /* patch up vddc if necessary */
6285         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6286                                                         &leakage_voltage);
6287         if (ret == 0)
6288                 pl->vddc = leakage_voltage;
6289
6290         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6291                 pi->acpi_vddc = pl->vddc;
6292                 eg_pi->acpi_vddci = pl->vddci;
6293                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6294         }
6295
6296         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6297             index == 0) {
6298                 /* XXX disable for A0 tahiti */
6299                 si_pi->ulv.supported = false;
6300                 si_pi->ulv.pl = *pl;
6301                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6302                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6303                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6304                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6305         }
6306
6307         if (pi->min_vddc_in_table > pl->vddc)
6308                 pi->min_vddc_in_table = pl->vddc;
6309
6310         if (pi->max_vddc_in_table < pl->vddc)
6311                 pi->max_vddc_in_table = pl->vddc;
6312
6313         /* patch up boot state */
6314         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6315                 u16 vddc, vddci, mvdd;
6316                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6317                 pl->mclk = rdev->clock.default_mclk;
6318                 pl->sclk = rdev->clock.default_sclk;
6319                 pl->vddc = vddc;
6320                 pl->vddci = vddci;
6321                 si_pi->mvdd_bootup_value = mvdd;
6322         }
6323
6324         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6325             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6326                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6327                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6328                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6329                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6330         }
6331 }
6332
6333 static int si_parse_power_table(struct radeon_device *rdev)
6334 {
6335         struct radeon_mode_info *mode_info = &rdev->mode_info;
6336         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6337         union pplib_power_state *power_state;
6338         int i, j, k, non_clock_array_index, clock_array_index;
6339         union pplib_clock_info *clock_info;
6340         struct _StateArray *state_array;
6341         struct _ClockInfoArray *clock_info_array;
6342         struct _NonClockInfoArray *non_clock_info_array;
6343         union power_info *power_info;
6344         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6345         u16 data_offset;
6346         u8 frev, crev;
6347         u8 *power_state_offset;
6348         struct ni_ps *ps;
6349
6350         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6351                                    &frev, &crev, &data_offset))
6352                 return -EINVAL;
6353         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6354
6355         state_array = (struct _StateArray *)
6356                 (mode_info->atom_context->bios + data_offset +
6357                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6358         clock_info_array = (struct _ClockInfoArray *)
6359                 (mode_info->atom_context->bios + data_offset +
6360                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6361         non_clock_info_array = (struct _NonClockInfoArray *)
6362                 (mode_info->atom_context->bios + data_offset +
6363                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6364
6365         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6366                                   state_array->ucNumEntries, GFP_KERNEL);
6367         if (!rdev->pm.dpm.ps)
6368                 return -ENOMEM;
6369         power_state_offset = (u8 *)state_array->states;
6370         for (i = 0; i < state_array->ucNumEntries; i++) {
6371                 u8 *idx;
6372                 power_state = (union pplib_power_state *)power_state_offset;
6373                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6374                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6375                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6376                 if (!rdev->pm.power_state[i].clock_info)
6377                         return -EINVAL;
6378                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6379                 if (ps == NULL) {
6380                         kfree(rdev->pm.dpm.ps);
6381                         return -ENOMEM;
6382                 }
6383                 rdev->pm.dpm.ps[i].ps_priv = ps;
6384                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6385                                               non_clock_info,
6386                                               non_clock_info_array->ucEntrySize);
6387                 k = 0;
6388                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6389                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6390                         clock_array_index = idx[j];
6391                         if (clock_array_index >= clock_info_array->ucNumEntries)
6392                                 continue;
6393                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6394                                 break;
6395                         clock_info = (union pplib_clock_info *)
6396                                 ((u8 *)&clock_info_array->clockInfo[0] +
6397                                  (clock_array_index * clock_info_array->ucEntrySize));
6398                         si_parse_pplib_clock_info(rdev,
6399                                                   &rdev->pm.dpm.ps[i], k,
6400                                                   clock_info);
6401                         k++;
6402                 }
6403                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6404         }
6405         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6406         return 0;
6407 }
6408
6409 int si_dpm_init(struct radeon_device *rdev)
6410 {
6411         struct rv7xx_power_info *pi;
6412         struct evergreen_power_info *eg_pi;
6413         struct ni_power_info *ni_pi;
6414         struct si_power_info *si_pi;
6415         struct atom_clock_dividers dividers;
6416         int ret;
6417         u32 mask;
6418
6419         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6420         if (si_pi == NULL)
6421                 return -ENOMEM;
6422         rdev->pm.dpm.priv = si_pi;
6423         ni_pi = &si_pi->ni;
6424         eg_pi = &ni_pi->eg;
6425         pi = &eg_pi->rv7xx;
6426
6427         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6428         if (ret)
6429                 si_pi->sys_pcie_mask = 0;
6430         else
6431                 si_pi->sys_pcie_mask = mask;
6432         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6433         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6434
6435         si_set_max_cu_value(rdev);
6436
6437         rv770_get_max_vddc(rdev);
6438         si_get_leakage_vddc(rdev);
6439         si_patch_dependency_tables_based_on_leakage(rdev);
6440
6441         pi->acpi_vddc = 0;
6442         eg_pi->acpi_vddci = 0;
6443         pi->min_vddc_in_table = 0;
6444         pi->max_vddc_in_table = 0;
6445
6446         ret = r600_get_platform_caps(rdev);
6447         if (ret)
6448                 return ret;
6449
6450         ret = si_parse_power_table(rdev);
6451         if (ret)
6452                 return ret;
6453         ret = r600_parse_extended_power_table(rdev);
6454         if (ret)
6455                 return ret;
6456
6457         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6458                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6459         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6460                 r600_free_extended_power_table(rdev);
6461                 return -ENOMEM;
6462         }
6463         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6464         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6465         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6466         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6467         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6468         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6469         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6470         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6471         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6472
6473         if (rdev->pm.dpm.voltage_response_time == 0)
6474                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6475         if (rdev->pm.dpm.backbias_response_time == 0)
6476                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6477
6478         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6479                                              0, false, &dividers);
6480         if (ret)
6481                 pi->ref_div = dividers.ref_div + 1;
6482         else
6483                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6484
6485         eg_pi->smu_uvd_hs = false;
6486
6487         pi->mclk_strobe_mode_threshold = 40000;
6488         if (si_is_special_1gb_platform(rdev))
6489                 pi->mclk_stutter_mode_threshold = 0;
6490         else
6491                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6492         pi->mclk_edc_enable_threshold = 40000;
6493         eg_pi->mclk_edc_wr_enable_threshold = 40000;
6494
6495         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6496
6497         pi->voltage_control =
6498                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6499
6500         pi->mvdd_control =
6501                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6502
6503         eg_pi->vddci_control =
6504                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6505
6506         si_pi->vddc_phase_shed_control =
6507                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6508
6509         rv770_get_engine_memory_ss(rdev);
6510
6511         pi->asi = RV770_ASI_DFLT;
6512         pi->pasi = CYPRESS_HASI_DFLT;
6513         pi->vrc = SISLANDS_VRC_DFLT;
6514
6515         pi->gfx_clock_gating = true;
6516
6517         eg_pi->sclk_deep_sleep = true;
6518         si_pi->sclk_deep_sleep_above_low = false;
6519
6520         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6521                 pi->thermal_protection = true;
6522         else
6523                 pi->thermal_protection = false;
6524
6525         eg_pi->dynamic_ac_timing = true;
6526
6527         eg_pi->light_sleep = true;
6528 #if defined(CONFIG_ACPI)
6529         eg_pi->pcie_performance_request =
6530                 radeon_acpi_is_pcie_performance_request_supported(rdev);
6531 #else
6532         eg_pi->pcie_performance_request = false;
6533 #endif
6534
6535         si_pi->sram_end = SMC_RAM_END;
6536
6537         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6538         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6539         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6540         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6541         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6542         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6543         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6544
6545         si_initialize_powertune_defaults(rdev);
6546
6547         /* make sure dc limits are valid */
6548         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6549             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6550                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6551                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6552
6553         return 0;
6554 }
6555
6556 void si_dpm_fini(struct radeon_device *rdev)
6557 {
6558         int i;
6559
6560         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6561                 kfree(rdev->pm.dpm.ps[i].ps_priv);
6562         }
6563         kfree(rdev->pm.dpm.ps);
6564         kfree(rdev->pm.dpm.priv);
6565         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6566         r600_free_extended_power_table(rdev);
6567 }
6568
6569 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6570                                                     struct seq_file *m)
6571 {
6572         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6573         struct radeon_ps *rps = &eg_pi->current_rps;
6574         struct ni_ps *ps = ni_get_ps(rps);
6575         struct rv7xx_pl *pl;
6576         u32 current_index =
6577                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6578                 CURRENT_STATE_INDEX_SHIFT;
6579
6580         if (current_index >= ps->performance_level_count) {
6581                 seq_printf(m, "invalid dpm profile %d\n", current_index);
6582         } else {
6583                 pl = &ps->performance_levels[current_index];
6584                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6585                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6586                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6587         }
6588 }