drivers/gpu/drm/radeon/radeon_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33
  34 #include <drm/drm.h>
  35
  36 #include "radeon.h"
  37 #include "radeon_ucode.h"
  38 #include "r600d.h"
  39
  40 /* 1 second timeout */
  41 #define UVD_IDLE_TIMEOUT_MS     1000
  42
  43 /* Firmware Names */
  44 #define FIRMWARE_R600           "/*(DEBLOBBED)*/"
  45 #define FIRMWARE_RS780          "/*(DEBLOBBED)*/"
  46 #define FIRMWARE_RV770          "/*(DEBLOBBED)*/"
  47 #define FIRMWARE_RV710          "/*(DEBLOBBED)*/"
  48 #define FIRMWARE_CYPRESS        "/*(DEBLOBBED)*/"
  49 #define FIRMWARE_SUMO           "/*(DEBLOBBED)*/"
  50 #define FIRMWARE_TAHITI         "/*(DEBLOBBED)*/"
  51 #define FIRMWARE_BONAIRE_LEGACY "/*(DEBLOBBED)*/"
  52 #define FIRMWARE_BONAIRE        "/*(DEBLOBBED)*/"
  53
  54 /*(DEBLOBBED)*/
  55
  56 static void radeon_uvd_idle_work_handler(struct work_struct *work);
  57
  58 int radeon_uvd_init(struct radeon_device *rdev)
  59 {
  60         unsigned long bo_size;
  61         const char *fw_name = NULL, *legacy_fw_name = NULL;
  62         int i, r;
  63
  64         INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
  65
  66         switch (rdev->family) {
  67         case CHIP_RV610:
  68         case CHIP_RV630:
  69         case CHIP_RV670:
  70         case CHIP_RV620:
  71         case CHIP_RV635:
  72                 legacy_fw_name = FIRMWARE_R600;
  73                 break;
  74
  75         case CHIP_RS780:
  76         case CHIP_RS880:
  77                 legacy_fw_name = FIRMWARE_RS780;
  78                 break;
  79
  80         case CHIP_RV770:
  81                 legacy_fw_name = FIRMWARE_RV770;
  82                 break;
  83
  84         case CHIP_RV710:
  85         case CHIP_RV730:
  86         case CHIP_RV740:
  87                 legacy_fw_name = FIRMWARE_RV710;
  88                 break;
  89
  90         case CHIP_CYPRESS:
  91         case CHIP_HEMLOCK:
  92         case CHIP_JUNIPER:
  93         case CHIP_REDWOOD:
  94         case CHIP_CEDAR:
  95                 legacy_fw_name = FIRMWARE_CYPRESS;
  96                 break;
  97
  98         case CHIP_SUMO:
  99         case CHIP_SUMO2:
 100         case CHIP_PALM:
 101         case CHIP_CAYMAN:
 102         case CHIP_BARTS:
 103         case CHIP_TURKS:
 104         case CHIP_CAICOS:
 105                 legacy_fw_name = FIRMWARE_SUMO;
 106                 break;
 107
 108         case CHIP_TAHITI:
 109         case CHIP_VERDE:
 110         case CHIP_PITCAIRN:
 111         case CHIP_ARUBA:
 112         case CHIP_OLAND:
 113                 legacy_fw_name = FIRMWARE_TAHITI;
 114                 break;
 115
 116         case CHIP_BONAIRE:
 117         case CHIP_KABINI:
 118         case CHIP_KAVERI:
 119         case CHIP_HAWAII:
 120         case CHIP_MULLINS:
 121                 legacy_fw_name = FIRMWARE_BONAIRE_LEGACY;
 122                 fw_name = FIRMWARE_BONAIRE;
 123                 break;
 124
 125         default:
 126                 return -EINVAL;
 127         }
 128
 129         rdev->uvd.fw_header_present = false;
 130         rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES;
 131         if (fw_name) {
 132                 /* Let's try to load the newer firmware first */
 133                 r = reject_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
 134                 if (r) {
 135                         dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 136                                 fw_name);
 137                 } else {
 138                         struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data;
 139                         unsigned version_major, version_minor, family_id;
 140
 141                         r = radeon_ucode_validate(rdev->uvd_fw);
 142                         if (r)
 143                                 return r;
 144
 145                         rdev->uvd.fw_header_present = true;
 146
 147                         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 148                         version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 149                         version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 150                         DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 151                                  version_major, version_minor, family_id);
 152
 153                         /*
 154                          * Limit the number of UVD handles depending on
 155                          * microcode major and minor versions.
 156                          */
 157                         if ((version_major >= 0x01) && (version_minor >= 0x37))
 158                                 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES;
 159                 }
 160         }
 161
 162         /*
 163          * In case there is only legacy firmware, or we encounter an error
 164          * while loading the new firmware, we fall back to loading the legacy
 165          * firmware now.
 166          */
 167         if (!fw_name || r) {
 168                 r = reject_firmware(&rdev->uvd_fw, legacy_fw_name, rdev->dev);
 169                 if (r) {
 170                         dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 171                                 legacy_fw_name);
 172                         return r;
 173                 }
 174         }
 175
 176         bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
 177                   RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
 178                   RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles;
 179         r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
 180                              RADEON_GEM_DOMAIN_VRAM, 0, NULL,
 181                              NULL, &rdev->uvd.vcpu_bo);
 182         if (r) {
 183                 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
 184                 return r;
 185         }
 186
 187         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 188         if (r) {
 189                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 190                 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
 191                 return r;
 192         }
 193
 194         r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
 195                           &rdev->uvd.gpu_addr);
 196         if (r) {
 197                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 198                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 199                 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
 200                 return r;
 201         }
 202
 203         r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 204         if (r) {
 205                 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
 206                 return r;
 207         }
 208
 209         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 210
 211         for (i = 0; i < rdev->uvd.max_handles; ++i) {
 212                 atomic_set(&rdev->uvd.handles[i], 0);
 213                 rdev->uvd.filp[i] = NULL;
 214                 rdev->uvd.img_size[i] = 0;
 215         }
 216
 217         return 0;
 218 }
 219
 220 void radeon_uvd_fini(struct radeon_device *rdev)
 221 {
 222         int r;
 223
 224         if (rdev->uvd.vcpu_bo == NULL)
 225                 return;
 226
 227         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 228         if (!r) {
 229                 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 230                 radeon_bo_unpin(rdev->uvd.vcpu_bo);
 231                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 232         }
 233
 234         radeon_bo_unref(&rdev->uvd.vcpu_bo);
 235
 236         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
 237
 238         release_firmware(rdev->uvd_fw);
 239 }
 240
 241 int radeon_uvd_suspend(struct radeon_device *rdev)
 242 {
 243         int i, r;
 244
 245         if (rdev->uvd.vcpu_bo == NULL)
 246                 return 0;
 247
 248         for (i = 0; i < rdev->uvd.max_handles; ++i) {
 249                 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 250                 if (handle != 0) {
 251                         struct radeon_fence *fence;
 252
 253                         radeon_uvd_note_usage(rdev);
 254
 255                         r = radeon_uvd_get_destroy_msg(rdev,
 256                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 257                         if (r) {
 258                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 259                                 continue;
 260                         }
 261
 262                         radeon_fence_wait(fence, false);
 263                         radeon_fence_unref(&fence);
 264
 265                         rdev->uvd.filp[i] = NULL;
 266                         atomic_set(&rdev->uvd.handles[i], 0);
 267                 }
 268         }
 269
 270         return 0;
 271 }
 272
 273 int radeon_uvd_resume(struct radeon_device *rdev)
 274 {
 275         unsigned size;
 276         void *ptr;
 277
 278         if (rdev->uvd.vcpu_bo == NULL)
 279                 return -EINVAL;
 280
 281         memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 282
 283         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 284         size -= rdev->uvd_fw->size;
 285
 286         ptr = rdev->uvd.cpu_addr;
 287         ptr += rdev->uvd_fw->size;
 288
 289         memset(ptr, 0, size);
 290
 291         return 0;
 292 }
 293
 294 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
 295                                        uint32_t allowed_domains)
 296 {
 297         int i;
 298
 299         for (i = 0; i < rbo->placement.num_placement; ++i) {
 300                 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 301                 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 302         }
 303
 304         /* If it must be in VRAM it must be in the first segment as well */
 305         if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)
 306                 return;
 307
 308         /* abort if we already have more than one placement */
 309         if (rbo->placement.num_placement > 1)
 310                 return;
 311
 312         /* add another 256MB segment */
 313         rbo->placements[1] = rbo->placements[0];
 314         rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
 315         rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
 316         rbo->placement.num_placement++;
 317         rbo->placement.num_busy_placement++;
 318 }
 319
 320 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 321 {
 322         int i, r;
 323         for (i = 0; i < rdev->uvd.max_handles; ++i) {
 324                 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 325                 if (handle != 0 && rdev->uvd.filp[i] == filp) {
 326                         struct radeon_fence *fence;
 327
 328                         radeon_uvd_note_usage(rdev);
 329
 330                         r = radeon_uvd_get_destroy_msg(rdev,
 331                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 332                         if (r) {
 333                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 334                                 continue;
 335                         }
 336
 337                         radeon_fence_wait(fence, false);
 338                         radeon_fence_unref(&fence);
 339
 340                         rdev->uvd.filp[i] = NULL;
 341                         atomic_set(&rdev->uvd.handles[i], 0);
 342                 }
 343         }
 344 }
 345
 346 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 347 {
 348         unsigned stream_type = msg[4];
 349         unsigned width = msg[6];
 350         unsigned height = msg[7];
 351         unsigned dpb_size = msg[9];
 352         unsigned pitch = msg[28];
 353
 354         unsigned width_in_mb = width / 16;
 355         unsigned height_in_mb = ALIGN(height / 16, 2);
 356
 357         unsigned image_size, tmp, min_dpb_size;
 358
 359         image_size = width * height;
 360         image_size += image_size / 2;
 361         image_size = ALIGN(image_size, 1024);
 362
 363         switch (stream_type) {
 364         case 0: /* H264 */
 365
 366                 /* reference picture buffer */
 367                 min_dpb_size = image_size * 17;
 368
 369                 /* macroblock context buffer */
 370                 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 371
 372                 /* IT surface buffer */
 373                 min_dpb_size += width_in_mb * height_in_mb * 32;
 374                 break;
 375
 376         case 1: /* VC1 */
 377
 378                 /* reference picture buffer */
 379                 min_dpb_size = image_size * 3;
 380
 381                 /* CONTEXT_BUFFER */
 382                 min_dpb_size += width_in_mb * height_in_mb * 128;
 383
 384                 /* IT surface buffer */
 385                 min_dpb_size += width_in_mb * 64;
 386
 387                 /* DB surface buffer */
 388                 min_dpb_size += width_in_mb * 128;
 389
 390                 /* BP */
 391                 tmp = max(width_in_mb, height_in_mb);
 392                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 393                 break;
 394
 395         case 3: /* MPEG2 */
 396
 397                 /* reference picture buffer */
 398                 min_dpb_size = image_size * 3;
 399                 break;
 400
 401         case 4: /* MPEG4 */
 402
 403                 /* reference picture buffer */
 404                 min_dpb_size = image_size * 3;
 405
 406                 /* CM */
 407                 min_dpb_size += width_in_mb * height_in_mb * 64;
 408
 409                 /* IT surface buffer */
 410                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 411                 break;
 412
 413         default:
 414                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 415                 return -EINVAL;
 416         }
 417
 418         if (width > pitch) {
 419                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 420                 return -EINVAL;
 421         }
 422
 423         if (dpb_size < min_dpb_size) {
 424                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 425                           dpb_size, min_dpb_size);
 426                 return -EINVAL;
 427         }
 428
 429         buf_sizes[0x1] = dpb_size;
 430         buf_sizes[0x2] = image_size;
 431         return 0;
 432 }
 433
 434 static int radeon_uvd_validate_codec(struct radeon_cs_parser *p,
 435                                      unsigned stream_type)
 436 {
 437         switch (stream_type) {
 438         case 0: /* H264 */
 439         case 1: /* VC1 */
 440                 /* always supported */
 441                 return 0;
 442
 443         case 3: /* MPEG2 */
 444         case 4: /* MPEG4 */
 445                 /* only since UVD 3 */
 446                 if (p->rdev->family >= CHIP_PALM)
 447                         return 0;
 448
 449                 /* fall through */
 450         default:
 451                 DRM_ERROR("UVD codec not supported by hardware %d!\n",
 452                           stream_type);
 453                 return -EINVAL;
 454         }
 455 }
 456
 457 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
 458                              unsigned offset, unsigned buf_sizes[])
 459 {
 460         int32_t *msg, msg_type, handle;
 461         unsigned img_size = 0;
 462         struct dma_fence *f;
 463         void *ptr;
 464
 465         int i, r;
 466
 467         if (offset & 0x3F) {
 468                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 469                 return -EINVAL;
 470         }
 471
 472         f = dma_resv_get_excl(bo->tbo.base.resv);
 473         if (f) {
 474                 r = radeon_fence_wait((struct radeon_fence *)f, false);
 475                 if (r) {
 476                         DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
 477                         return r;
 478                 }
 479         }
 480
 481         r = radeon_bo_kmap(bo, &ptr);
 482         if (r) {
 483                 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
 484                 return r;
 485         }
 486
 487         msg = ptr + offset;
 488
 489         msg_type = msg[1];
 490         handle = msg[2];
 491
 492         if (handle == 0) {
 493                 DRM_ERROR("Invalid UVD handle!\n");
 494                 return -EINVAL;
 495         }
 496
 497         switch (msg_type) {
 498         case 0:
 499                 /* it's a create msg, calc image size (width * height) */
 500                 img_size = msg[7] * msg[8];
 501
 502                 r = radeon_uvd_validate_codec(p, msg[4]);
 503                 radeon_bo_kunmap(bo);
 504                 if (r)
 505                         return r;
 506
 507                 /* try to alloc a new handle */
 508                 for (i = 0; i < p->rdev->uvd.max_handles; ++i) {
 509                         if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
 510                                 DRM_ERROR("Handle 0x%x already in use!\n", handle);
 511                                 return -EINVAL;
 512                         }
 513
 514                         if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
 515                                 p->rdev->uvd.filp[i] = p->filp;
 516                                 p->rdev->uvd.img_size[i] = img_size;
 517                                 return 0;
 518                         }
 519                 }
 520
 521                 DRM_ERROR("No more free UVD handles!\n");
 522                 return -EINVAL;
 523
 524         case 1:
 525                 /* it's a decode msg, validate codec and calc buffer sizes */
 526                 r = radeon_uvd_validate_codec(p, msg[4]);
 527                 if (!r)
 528                         r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
 529                 radeon_bo_kunmap(bo);
 530                 if (r)
 531                         return r;
 532
 533                 /* validate the handle */
 534                 for (i = 0; i < p->rdev->uvd.max_handles; ++i) {
 535                         if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
 536                                 if (p->rdev->uvd.filp[i] != p->filp) {
 537                                         DRM_ERROR("UVD handle collision detected!\n");
 538                                         return -EINVAL;
 539                                 }
 540                                 return 0;
 541                         }
 542                 }
 543
 544                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
 545                 return -ENOENT;
 546
 547         case 2:
 548                 /* it's a destroy msg, free the handle */
 549                 for (i = 0; i < p->rdev->uvd.max_handles; ++i)
 550                         atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
 551                 radeon_bo_kunmap(bo);
 552                 return 0;
 553
 554         default:
 555
 556                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 557                 return -EINVAL;
 558         }
 559
 560         BUG();
 561         return -EINVAL;
 562 }
 563
 564 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
 565                                int data0, int data1,
 566                                unsigned buf_sizes[], bool *has_msg_cmd)
 567 {
 568         struct radeon_cs_chunk *relocs_chunk;
 569         struct radeon_bo_list *reloc;
 570         unsigned idx, cmd, offset;
 571         uint64_t start, end;
 572         int r;
 573
 574         relocs_chunk = p->chunk_relocs;
 575         offset = radeon_get_ib_value(p, data0);
 576         idx = radeon_get_ib_value(p, data1);
 577         if (idx >= relocs_chunk->length_dw) {
 578                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 579                           idx, relocs_chunk->length_dw);
 580                 return -EINVAL;
 581         }
 582
 583         reloc = &p->relocs[(idx / 4)];
 584         start = reloc->gpu_offset;
 585         end = start + radeon_bo_size(reloc->robj);
 586         start += offset;
 587
 588         p->ib.ptr[data0] = start & 0xFFFFFFFF;
 589         p->ib.ptr[data1] = start >> 32;
 590
 591         cmd = radeon_get_ib_value(p, p->idx) >> 1;
 592
 593         if (cmd < 0x4) {
 594                 if (end <= start) {
 595                         DRM_ERROR("invalid reloc offset %X!\n", offset);
 596                         return -EINVAL;
 597                 }
 598                 if ((end - start) < buf_sizes[cmd]) {
 599                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 600                                   (unsigned)(end - start), buf_sizes[cmd]);
 601                         return -EINVAL;
 602                 }
 603
 604         } else if (cmd != 0x100) {
 605                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 606                 return -EINVAL;
 607         }
 608
 609         if ((start >> 28) != ((end - 1) >> 28)) {
 610                 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 611                           start, end);
 612                 return -EINVAL;
 613         }
 614
 615         /* TODO: is this still necessary on NI+ ? */
 616         if ((cmd == 0 || cmd == 0x3) &&
 617             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
 618                 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 619                           start, end);
 620                 return -EINVAL;
 621         }
 622
 623         if (cmd == 0) {
 624                 if (*has_msg_cmd) {
 625                         DRM_ERROR("More than one message in a UVD-IB!\n");
 626                         return -EINVAL;
 627                 }
 628                 *has_msg_cmd = true;
 629                 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
 630                 if (r)
 631                         return r;
 632         } else if (!*has_msg_cmd) {
 633                 DRM_ERROR("Message needed before other commands are send!\n");
 634                 return -EINVAL;
 635         }
 636
 637         return 0;
 638 }
 639
 640 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
 641                              struct radeon_cs_packet *pkt,
 642                              int *data0, int *data1,
 643                              unsigned buf_sizes[],
 644                              bool *has_msg_cmd)
 645 {
 646         int i, r;
 647
 648         p->idx++;
 649         for (i = 0; i <= pkt->count; ++i) {
 650                 switch (pkt->reg + i*4) {
 651                 case UVD_GPCOM_VCPU_DATA0:
 652                         *data0 = p->idx;
 653                         break;
 654                 case UVD_GPCOM_VCPU_DATA1:
 655                         *data1 = p->idx;
 656                         break;
 657                 case UVD_GPCOM_VCPU_CMD:
 658                         r = radeon_uvd_cs_reloc(p, *data0, *data1,
 659                                                 buf_sizes, has_msg_cmd);
 660                         if (r)
 661                                 return r;
 662                         break;
 663                 case UVD_ENGINE_CNTL:
 664                 case UVD_NO_OP:
 665                         break;
 666                 default:
 667                         DRM_ERROR("Invalid reg 0x%X!\n",
 668                                   pkt->reg + i*4);
 669                         return -EINVAL;
 670                 }
 671                 p->idx++;
 672         }
 673         return 0;
 674 }
 675
 676 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
 677 {
 678         struct radeon_cs_packet pkt;
 679         int r, data0 = 0, data1 = 0;
 680
 681         /* does the IB has a msg command */
 682         bool has_msg_cmd = false;
 683
 684         /* minimum buffer sizes */
 685         unsigned buf_sizes[] = {
 686                 [0x00000000]    =       2048,
 687                 [0x00000001]    =       32 * 1024 * 1024,
 688                 [0x00000002]    =       2048 * 1152 * 3,
 689                 [0x00000003]    =       2048,
 690         };
 691
 692         if (p->chunk_ib->length_dw % 16) {
 693                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 694                           p->chunk_ib->length_dw);
 695                 return -EINVAL;
 696         }
 697
 698         if (p->chunk_relocs == NULL) {
 699                 DRM_ERROR("No relocation chunk !\n");
 700                 return -EINVAL;
 701         }
 702
 703
 704         do {
 705                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
 706                 if (r)
 707                         return r;
 708                 switch (pkt.type) {
 709                 case RADEON_PACKET_TYPE0:
 710                         r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
 711                                               buf_sizes, &has_msg_cmd);
 712                         if (r)
 713                                 return r;
 714                         break;
 715                 case RADEON_PACKET_TYPE2:
 716                         p->idx += pkt.count + 2;
 717                         break;
 718                 default:
 719                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 720                         return -EINVAL;
 721                 }
 722         } while (p->idx < p->chunk_ib->length_dw);
 723
 724         if (!has_msg_cmd) {
 725                 DRM_ERROR("UVD-IBs need a msg command!\n");
 726                 return -EINVAL;
 727         }
 728
 729         return 0;
 730 }
 731
 732 static int radeon_uvd_send_msg(struct radeon_device *rdev,
 733                                int ring, uint64_t addr,
 734                                struct radeon_fence **fence)
 735 {
 736         struct radeon_ib ib;
 737         int i, r;
 738
 739         r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
 740         if (r)
 741                 return r;
 742
 743         ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
 744         ib.ptr[1] = addr;
 745         ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
 746         ib.ptr[3] = addr >> 32;
 747         ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
 748         ib.ptr[5] = 0;
 749         for (i = 6; i < 16; i += 2) {
 750                 ib.ptr[i] = PACKET0(UVD_NO_OP, 0);
 751                 ib.ptr[i+1] = 0;
 752         }
 753         ib.length_dw = 16;
 754
 755         r = radeon_ib_schedule(rdev, &ib, NULL, false);
 756
 757         if (fence)
 758                 *fence = radeon_fence_ref(ib.fence);
 759
 760         radeon_ib_free(rdev, &ib);
 761         return r;
 762 }
 763
 764 /*
 765  * multiple fence commands without any stream commands in between can
 766  * crash the vcpu so just try to emmit a dummy create/destroy msg to
 767  * avoid this
 768  */
 769 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 770                               uint32_t handle, struct radeon_fence **fence)
 771 {
 772         /* we use the last page of the vcpu bo for the UVD message */
 773         uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
 774                 RADEON_GPU_PAGE_SIZE;
 775
 776         uint32_t *msg = rdev->uvd.cpu_addr + offs;
 777         uint64_t addr = rdev->uvd.gpu_addr + offs;
 778
 779         int r, i;
 780
 781         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
 782         if (r)
 783                 return r;
 784
 785         /* stitch together an UVD create msg */
 786         msg[0] = cpu_to_le32(0x00000de4);
 787         msg[1] = cpu_to_le32(0x00000000);
 788         msg[2] = cpu_to_le32(handle);
 789         msg[3] = cpu_to_le32(0x00000000);
 790         msg[4] = cpu_to_le32(0x00000000);
 791         msg[5] = cpu_to_le32(0x00000000);
 792         msg[6] = cpu_to_le32(0x00000000);
 793         msg[7] = cpu_to_le32(0x00000780);
 794         msg[8] = cpu_to_le32(0x00000440);
 795         msg[9] = cpu_to_le32(0x00000000);
 796         msg[10] = cpu_to_le32(0x01b37000);
 797         for (i = 11; i < 1024; ++i)
 798                 msg[i] = cpu_to_le32(0x0);
 799
 800         r = radeon_uvd_send_msg(rdev, ring, addr, fence);
 801         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 802         return r;
 803 }
 804
 805 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 806                                uint32_t handle, struct radeon_fence **fence)
 807 {
 808         /* we use the last page of the vcpu bo for the UVD message */
 809         uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
 810                 RADEON_GPU_PAGE_SIZE;
 811
 812         uint32_t *msg = rdev->uvd.cpu_addr + offs;
 813         uint64_t addr = rdev->uvd.gpu_addr + offs;
 814
 815         int r, i;
 816
 817         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
 818         if (r)
 819                 return r;
 820
 821         /* stitch together an UVD destroy msg */
 822         msg[0] = cpu_to_le32(0x00000de4);
 823         msg[1] = cpu_to_le32(0x00000002);
 824         msg[2] = cpu_to_le32(handle);
 825         msg[3] = cpu_to_le32(0x00000000);
 826         for (i = 4; i < 1024; ++i)
 827                 msg[i] = cpu_to_le32(0x0);
 828
 829         r = radeon_uvd_send_msg(rdev, ring, addr, fence);
 830         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 831         return r;
 832 }
 833
 834 /**
 835  * radeon_uvd_count_handles - count number of open streams
 836  *
 837  * @rdev: radeon_device pointer
 838  * @sd: number of SD streams
 839  * @hd: number of HD streams
 840  *
 841  * Count the number of open SD/HD streams as a hint for power mangement
 842  */
 843 static void radeon_uvd_count_handles(struct radeon_device *rdev,
 844                                      unsigned *sd, unsigned *hd)
 845 {
 846         unsigned i;
 847
 848         *sd = 0;
 849         *hd = 0;
 850
 851         for (i = 0; i < rdev->uvd.max_handles; ++i) {
 852                 if (!atomic_read(&rdev->uvd.handles[i]))
 853                         continue;
 854
 855                 if (rdev->uvd.img_size[i] >= 720*576)
 856                         ++(*hd);
 857                 else
 858                         ++(*sd);
 859         }
 860 }
 861
 862 static void radeon_uvd_idle_work_handler(struct work_struct *work)
 863 {
 864         struct radeon_device *rdev =
 865                 container_of(work, struct radeon_device, uvd.idle_work.work);
 866
 867         if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
 868                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 869                         radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
 870                                                  &rdev->pm.dpm.hd);
 871                         radeon_dpm_enable_uvd(rdev, false);
 872                 } else {
 873                         radeon_set_uvd_clocks(rdev, 0, 0);
 874                 }
 875         } else {
 876                 schedule_delayed_work(&rdev->uvd.idle_work,
 877                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 878         }
 879 }
 880
 881 void radeon_uvd_note_usage(struct radeon_device *rdev)
 882 {
 883         bool streams_changed = false;
 884         bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
 885         set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
 886                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 887
 888         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 889                 unsigned hd = 0, sd = 0;
 890                 radeon_uvd_count_handles(rdev, &sd, &hd);
 891                 if ((rdev->pm.dpm.sd != sd) ||
 892                     (rdev->pm.dpm.hd != hd)) {
 893                         rdev->pm.dpm.sd = sd;
 894                         rdev->pm.dpm.hd = hd;
 895                         /* disable this for now */
 896                         /*streams_changed = true;*/
 897                 }
 898         }
 899
 900         if (set_clocks || streams_changed) {
 901                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 902                         radeon_dpm_enable_uvd(rdev, true);
 903                 } else {
 904                         radeon_set_uvd_clocks(rdev, 53300, 40000);
 905                 }
 906         }
 907 }
 908
 909 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
 910                                               unsigned target_freq,
 911                                               unsigned pd_min,
 912                                               unsigned pd_even)
 913 {
 914         unsigned post_div = vco_freq / target_freq;
 915
 916         /* adjust to post divider minimum value */
 917         if (post_div < pd_min)
 918                 post_div = pd_min;
 919
 920         /* we alway need a frequency less than or equal the target */
 921         if ((vco_freq / post_div) > target_freq)
 922                 post_div += 1;
 923
 924         /* post dividers above a certain value must be even */
 925         if (post_div > pd_even && post_div % 2)
 926                 post_div += 1;
 927
 928         return post_div;
 929 }
 930
 931 /**
 932  * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 933  *
 934  * @rdev: radeon_device pointer
 935  * @vclk: wanted VCLK
 936  * @dclk: wanted DCLK
 937  * @vco_min: minimum VCO frequency
 938  * @vco_max: maximum VCO frequency
 939  * @fb_factor: factor to multiply vco freq with
 940  * @fb_mask: limit and bitmask for feedback divider
 941  * @pd_min: post divider minimum
 942  * @pd_max: post divider maximum
 943  * @pd_even: post divider must be even above this value
 944  * @optimal_fb_div: resulting feedback divider
 945  * @optimal_vclk_div: resulting vclk post divider
 946  * @optimal_dclk_div: resulting dclk post divider
 947  *
 948  * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 949  * Returns zero on success -EINVAL on error.
 950  */
 951 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
 952                                   unsigned vclk, unsigned dclk,
 953                                   unsigned vco_min, unsigned vco_max,
 954                                   unsigned fb_factor, unsigned fb_mask,
 955                                   unsigned pd_min, unsigned pd_max,
 956                                   unsigned pd_even,
 957                                   unsigned *optimal_fb_div,
 958                                   unsigned *optimal_vclk_div,
 959                                   unsigned *optimal_dclk_div)
 960 {
 961         unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 962
 963         /* start off with something large */
 964         unsigned optimal_score = ~0;
 965
 966         /* loop through vco from low to high */
 967         vco_min = max(max(vco_min, vclk), dclk);
 968         for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 969
 970                 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
 971                 unsigned vclk_div, dclk_div, score;
 972
 973                 do_div(fb_div, ref_freq);
 974
 975                 /* fb div out of range ? */
 976                 if (fb_div > fb_mask)
 977                         break; /* it can oly get worse */
 978
 979                 fb_div &= fb_mask;
 980
 981                 /* calc vclk divider with current vco freq */
 982                 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
 983                                                          pd_min, pd_even);
 984                 if (vclk_div > pd_max)
 985                         break; /* vco is too big, it has to stop */
 986
 987                 /* calc dclk divider with current vco freq */
 988                 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
 989                                                          pd_min, pd_even);
 990                 if (dclk_div > pd_max)
 991                         break; /* vco is too big, it has to stop */
 992
 993                 /* calc score with current vco freq */
 994                 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 995
 996                 /* determine if this vco setting is better than current optimal settings */
 997                 if (score < optimal_score) {
 998                         *optimal_fb_div = fb_div;
 999                         *optimal_vclk_div = vclk_div;
1000                         *optimal_dclk_div = dclk_div;
1001                         optimal_score = score;
1002                         if (optimal_score == 0)
1003                                 break; /* it can't get better than this */
1004                 }
1005         }
1006
1007         /* did we found a valid setup ? */
1008         if (optimal_score == ~0)
1009                 return -EINVAL;
1010
1011         return 0;
1012 }
1013
1014 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1015                                 unsigned cg_upll_func_cntl)
1016 {
1017         unsigned i;
1018
1019         /* make sure UPLL_CTLREQ is deasserted */
1020         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
1021
1022         mdelay(10);
1023
1024         /* assert UPLL_CTLREQ */
1025         WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
1026
1027         /* wait for CTLACK and CTLACK2 to get asserted */
1028         for (i = 0; i < 100; ++i) {
1029                 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
1030                 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
1031                         break;
1032                 mdelay(10);
1033         }
1034
1035         /* deassert UPLL_CTLREQ */
1036         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
1037
1038         if (i == 100) {
1039                 DRM_ERROR("Timeout setting UVD clocks!\n");
1040                 return -ETIMEDOUT;
1041         }
1042
1043         return 0;
1044 }